Program flashing method and device, vehicle and storage medium

Abstract

The application discloses a program flashing method and device, a vehicle and a storage medium, wherein the program flashing method comprises the following steps: acquiring current version data; sending the current version data to an upper computer, so that the upper computer determines whether the current version data is consistent with preloaded latest version data, wherein the upper computer is provided with a plurality of output ports, and each output port is provided with an output port identifier; in response to the current version data being inconsistent with the latest version data, receiving program data to be written from the upper computer via a receiving port; checking the output port identifier and the receiving port identifier to obtain a checking result; and in response to the checking result indicating that the output port identifier is consistent with the receiving port identifier, performing a writing operation on the program data to be written. The application solves the technical problem of low accuracy in the prior art when a program is flashed by means of manually loading a data packet.

Description

Technical Field

[0001] This invention relates to the field of new energy vehicle controller software technology, and more specifically, to a method, apparatus, vehicle, and storage medium for flashing a program. Background Technology

[0002] The battery system is a key component of electric vehicles, and its safety, reliability, and maintainability are crucial, determining the performance of the electric vehicle. When faced with high power demands, the electric vehicle's battery management system typically employs a three-level serial-parallel architecture, consisting of a main control ECU (Electronic Control Unit), multiple slave control ECUs, and multiple sampling units.

[0003] Human error is unpredictable during program flashing. When updating and downloading the master control program, a slave ECU data packet may be loaded due to a human error. At this time, the slave data packet will automatically be encoded with the ID number of the master control ECU. When the master control ECU receives the data packet, it will determine that the ID number is consistent and then flash the slave data packet into the master controller. Thus, the data in the slave data packet will run in the master control ECU. At this time, whether the error is found in the middle of the flashing process or after the flashing is completed, an error flashing prompt will be generated. Subsequently, it is necessary to re-flash or re-disassemble the device if it fails to run, which increases the labor cost.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This invention provides a method, apparatus, vehicle, and storage medium for flashing programs, thereby at least solving the technical problem of low accuracy when flashing programs by manually loading data packets in the prior art.

[0006] According to one embodiment of the present invention, a method for flashing a program is provided, comprising: acquiring current version data, wherein the current version data includes: a first version identifier of a main processor and a second version identifier of a slave processor; sending the current version data to a host computer so that the host computer determines whether the current version data is consistent with the latest version data that has been loaded, wherein the host computer is provided with multiple output ports, each output port being provided with an output port identifier; in response to the inconsistency between the current version data and the latest version data, receiving program data to be written from the host computer via a receiving port, wherein the receiving port is provided with a receiving port identifier, and the program data to be written includes at least one of the following: first program data to be written to the main processor and second program data to be written to the slave processor; verifying the output port identifier and the receiving port identifier to obtain a verification result; and in response to the verification result indicating that the output port identifier and the receiving port identifier are consistent, performing a write operation on the program data to be written.

[0007] Optionally, the program flashing method further includes: the latest version data includes: the third version identifier of the main processor, the fourth version identifier of the slave processor, and in response to the first version identifier being different from the third version identifier and the second version identifier being the same as the fourth version identifier, receiving the first program data from the host computer via the receiving port.

[0008] Optionally, the program flashing method further includes: in response to the first version identifier being the same as the third version identifier and the second version identifier being different from the fourth version identifier, receiving second program data from the host computer via the receiving port.

[0009] Optionally, the program flashing method further includes: in response to the fact that the first version identifier is different from the third version identifier and the second version identifier is different from the fourth version identifier, receiving the first program data and the second program data from the host computer via the receiving port.

[0010] Optionally, the program writing method further includes: the output port includes a first output port and a second output port; the receiving port identifier of the receiving port is obtained; the first output port identifier carried by the program data to be written output through the first output port is obtained; in response to the first output port identifier being the same as the receiving port identifier, the program data to be written output by the first output port is determined to be the first program data.

[0011] Optionally, the program writing method further includes: in response to the first output port identifier being different from the receiving port identifier, obtaining the second output port identifier carried by the program data to be written output through the second output port; in response to the second output port identifier being the same as the receiving port identifier, determining that the program data to be written output by the second output port is the first program data.

[0012] Optionally, the program flashing method further includes: the main processor storing first preset key data, the slave processor storing second preset key data, receiving first current key data and second current key data from the host computer; when performing the write operation on the program data to be written, stopping the writing of the first program data to the main processor in response to the first current key data being different from the first preset key data; and / or stopping the writing of the second program data to the slave processor in response to the second current key data being different from the second preset key data.

[0013] According to one embodiment of the present invention, a program writing device is also provided, comprising: an acquisition module for acquiring current version data, wherein the current version data includes: a first version identifier of a main processor and a second version identifier of a slave processor; a sending module for sending the current version data to a host computer so that the host computer determines whether the current version data is consistent with the latest version data that has been loaded, wherein the host computer is provided with multiple output ports, each output port being provided with an output port identifier; a first receiving module for receiving program data to be written from the host computer via a receiving port in response to the inconsistency between the current version data and the latest version data, wherein the receiving port is provided with a receiving port identifier, and the program data to be written includes at least one of the following: first program data to be written to the main processor and second program data to be written to the slave processor; a verification module for verifying the output port identifier and the receiving port identifier to obtain a verification result; and a writing module for performing a writing operation on the program data to be written in response to the verification result indicating that the output port identifier and the receiving port identifier are consistent.

[0014] According to one embodiment of the present invention, a vehicle is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to execute the flashing method of the program in any of the above claims.

[0015] According to one embodiment of the present invention, a non-volatile storage medium is also provided, wherein a computer program is stored in the non-volatile storage medium, and the computer program is configured to execute the flashing method of the program in any of the above-mentioned embodiments when running.

[0016] In this embodiment of the invention, the current version data is obtained, which includes a first version identifier of the main processor and a second version identifier of the slave processor. The current version data is sent to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is provided with multiple output ports, each of which is provided with an output port identifier. In response to the inconsistency between the current version data and the latest version data, the host computer receives the program data to be written from the host computer via a receiving port, which is provided with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor and second program data to be written to the slave processor. This achieves the purpose of verifying the output port identifier and the receiving port identifier and obtaining a verification result. This achieves the technical effect of performing a write operation on the program data to be written in response to the verification result indicating that the output port identifier and the receiving port identifier are consistent. This solves the technical problem of low accuracy when writing programs by manually loading data packets in the prior art. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a flowchart of a program flashing method according to one embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the vehicle battery management system flashing architecture according to one embodiment of the present invention;

[0020] Figure 3 This is a structural block diagram of a program writing device according to one embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] According to an embodiment of the present invention, an embodiment of a program flashing method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system containing at least one set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0024] This method embodiment can also be executed in an electronic device, similar control device, or vehicle-mounted terminal that includes a memory and a processor. Taking a vehicle-mounted terminal as an example, the vehicle-mounted terminal may include one or more processors and a memory for storing data. Optionally, the vehicle-mounted terminal may also include a communication device for communication functions and a display device. Those skilled in the art will understand that the above structural description is merely illustrative and does not limit the structure of the vehicle-mounted terminal. For example, the vehicle-mounted terminal may include more or fewer components than those described above, or have a different configuration than those described above.

[0025] A processor may include one or more processing units. For example, a processor may include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processing (DSP) chip, a microcontroller unit (MCU), a field-programmable gate array (FPGA), a neural network processing unit (NPU), a tensor processing unit (TPU), or an artificial intelligence (AI) processor. Different processing units may be independent components or integrated into one or more processors. In some instances, electronic devices may also include one or more processors.

[0026] The memory can be used to store computer programs, such as the computer program corresponding to the program flashing method in the embodiments of the present invention. The processor implements the program flashing method by running the computer program stored in the memory. The memory may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to the electronic device via a grid. Examples of such grids include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0027] The communication device is used to receive or transmit data via a grid. Specific examples of the aforementioned grid may include a wireless grid provided by the mobile terminal's communication provider. In one example, the communication device includes a network interface controller (NIC), which can connect to other grid devices via a base station to communicate with the Internet. In another example, the communication device may be a radio frequency (RF) module used for wireless communication with the Internet. In some embodiments of this solution, the communication device is used to connect to mobile devices such as mobile phones and tablets, enabling the mobile device to send commands to the vehicle-mounted terminal.

[0028] The display device can be a touchscreen liquid crystal display (LCD) or a touch display (also referred to as a "touchscreen" or "touch screen"). This LCD allows the user to interact with the user interface of the in-vehicle terminal. In some embodiments, the in-vehicle terminal has a graphical user interface (GUI), allowing the user to interact with the GUI through finger contact and / or gestures on a touch-sensitive surface. This human-machine interaction function may include a vehicle gear shifting function. Executable instructions for performing these human-machine interaction functions are configured / stored in one or more processor-executable computer program products or readable storage media.

[0029] Figure 1 This is a flowchart of a program flashing method according to one embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0030] Step S102: Obtain the current version data, which includes: the first version identifier of the main processor and the second version identifier of the slave processor.

[0031] Optionally, the execution subject in this embodiment is the main processor. It should be noted that other electronic devices or processors can also serve as the execution subject, and no further limitations are imposed here.

[0032] In the technical solution provided by step S102 of the present invention, the main processor first obtains its own version data and the version data of the slave processor, wherein the version data of the main processor includes a first version identifier of the main processor and the version data of the slave processor includes a second version identifier of the slave processor.

[0033] Specifically, the host computer sends a flash request to the main processor. After receiving the request, the main processor forwards the handshake message to the slave processor. After receiving the message, the slave processor sends its current second version identifier to the main processor and then jumps to the bootstrap layer. The main processor receives the second version identifier from the slave processor.

[0034] Step S104: Send the current version data to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer has multiple output ports, and each output port is assigned an output port identifier.

[0035] In the technical solution provided by step S104 of the present invention, the main processor sends version data with a first version identifier and a second version identifier to the host computer. After receiving the version data, the host computer should compare the currently received version data with the version data of the already loaded data packet to determine whether they are consistent.

[0036] Specifically, the main processor simultaneously sends its first version identifier and the slave processor's second version identifier to the host computer. The host computer has multiple output ports, each with its own identifier. After collecting the first and second version identifiers, the host computer waits for the user to load and import the respective data packets to be flashed from the main controller and slave processor at the corresponding locations on the host computer. Once the user loads and imports these data packets, the host computer parses and obtains the version identifiers of the two new data packets. It then compares the version identifier of the newly loaded main processor data packet with the current first version identifier of the main processor, and simultaneously compares the version identifier of the newly loaded slave processor data packet with the current second version identifier of the slave processor to determine if they match.

[0037] Optionally, multiple slave processors may exist during the program flashing process. When multiple slave processors exist (i.e., the number of slave processors is greater than or equal to two), the host computer still only transmits two data packets. The master processor determines the slave processor's number and sends data packets to their respective slave processors. The host computer uniformly sets the program flashing address number for both the master and slave processors, and then increments the slave processor's address number by the address number of the master processor based on the number of slave processors. The slave processor's address number is configured and stored at the factory to facilitate receiving and sending data corresponding to their respective address numbers. Generally, the slave processor's address number starts from F4.

[0038] For example, the host computer sets the address numbers for the main processor and slave processors to be flashed uniformly (e.g., F3 for the main processor and F1 for the slave processor). Then the main processor will reassign the address numbers of the slave processors. If the host computer interface is configured with 3 slave processors, then F3 will be fixed as the address number of the main processor, and the address numbers of the slave processors will be F4, F5, and F6 respectively.

[0039] Optionally, the host computer typically refers to a computer or software used to control and manage the operation of the slave computer. Through a communication interface with the slave computer, the host computer can obtain the slave computer's operating status, control its operations, and process the data transmitted by the slave computer. The host computer can provide monitoring, debugging, and control functions for the slave computer, enabling it to operate more efficiently. It is worth noting that the host computer used in this application only needs to be able to exchange data with the main processor; no further limitations are imposed.

[0040] It is worth noting that, such as Figure 2 As shown, in addition to local flashing via a host computer, remote program flashing can also be achieved in this application. The specific implementation method is as follows: The information required for flashing the main processor and slave processors—the Hex file, the number of slave processors, and the key data of the main processor and slave processors—is uploaded to the T-Box (Remote Information Processing Control Unit) webpage, and a scheduled send is clicked. Since the T-Box module has a 4G communication module that supports webpage upload, the Hex file can be parsed when the processor is powered on, and the data is sent remotely in pages. During remote flashing, the T-Box module parses and reads the version identifiers of two new hex file data packets. If the T-Box compares the program data and finds that the program data of one of the processors does not need to be updated, the T-Box module does not parse the data packet corresponding to that processor and does not send the relevant program data of the data packet corresponding to that processor. If the T-Box module compares the program data and finds that the program data of one of the processors needs to be updated, the T-Box module sends the program data corresponding to the processor that needs to be updated to the main processor via the 4G communication module, and the main processor then executes the subsequent program flashing process.

[0041] Step S106: In response to the inconsistency between the current version data and the latest version data, receive the program data to be written from the host computer via the receiving port. The receiving port is equipped with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor, and second program data to be written to the slave processor.

[0042] In the technical solution provided by step S106 of the present invention, when the host computer compares the version identifiers of the two parsed data packets with the version identifiers of the corresponding processors, if the version identifier of the main processor is inconsistent with the version identifier of the corresponding newly loaded data packet and the version identifier of the slave processor is also inconsistent with the version identifier of the corresponding newly loaded data packet, it is determined that the data packets in both the main processor and the slave processor need to be updated. Therefore, the main processor receives the program data to be written from the host computer through the receiving port. The program data to be written includes at least one of the following: first program data to be written to the main processor and second program data to be written to the slave processor.

[0043] Step S108: Verify the output port identifier with the receiving port identifier to obtain the verification result.

[0044] In the technical solution provided by step S108 of the present invention, when the host computer sends the program data to be written to the main processor through the output port, the output port identifier carried by the output port of the host computer and the receiving port identifier of the main processor should be verified by the transmission interface to obtain the final verification result.

[0045] Optionally, the transmission interface verification is set up internally by the main processor. When the host computer sends the program data to be written through multiple output ports, the main processor will verify the port identifier of its own receiving port and the output port identifier carried by the program data to be written transmitted through multiple output ports to determine the output port for transmitting the first program data, thereby further reducing the risk of errors in manually loading data packets.

[0046] Step S110: In response to the verification result indicating that the output port identifier and the receiving port identifier are consistent, the write operation is performed on the program data to be written.

[0047] In the technical solution provided by step S110 of the present invention, when the verification result obtained by the main processor is that the port identifier of a certain output port of the host computer is consistent with the port identifier of its own receiving port, the program data to be written transmitted by the output port is determined to be the first program data of the main processor, that is, it indicates that the verification result of the main processor's transmission interface verification is correct, and the program data to be written of the transmission channel can be written to the main processor to complete the update of the main processor's program data.

[0048] Steps S102 to S110 above, as follows: Figure 2As shown, in this embodiment of the invention, the current version data is obtained, which includes: a first version identifier of the main processor and a second version identifier of the slave processor. The current version data is sent to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is provided with multiple output ports, each of which is provided with an output port identifier. In response to the inconsistency between the current version data and the latest version data, the host computer receives the program data to be written from the host computer via the receiving port. The receiving port is provided with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor and second program data to be written to the slave processor. This achieves the purpose of verifying the output port identifier and the receiving port identifier and obtaining the verification result. When the verification result indicates that the output port identifier and the receiving port identifier are consistent, the technical effect of performing the writing operation on the program data to be written is achieved. This can solve the technical problem of low accuracy when writing programs by manually loading data packets in the prior art.

[0049] It is worth noting that existing technologies generally use single-data packet flashing. This means that when all processors have flashing and update requirements, one processor can only be flashed before another. The time for erasing and flashing Flash address data is multiplied, which increases the time cost and reduces the efficiency of the flashing process.

[0050] In this application, because the chip message receiving and sending interrupt mechanism of the processor is triggered, the data can be processed before the preset period, so that execution will start after the data is sent. In addition, since the main processor and the slave processor are two independent processor systems, synchronous writing with millisecond error can be achieved. It is worth noting that synchronous writing greatly reduces the writing time of all processor programs, achieving the technical effect of saving manual time and reducing human error rate in batch writing projects.

[0051] The method described in this embodiment will now be described in further detail.

[0052] As an optional implementation, the latest version data includes: a third version identifier of the main processor, a fourth version identifier of the slave processor, and in response to the inconsistency between the current version data and the latest version data, receiving the program data to be written from the host computer via the receiving port includes: in response to the first version identifier being different from the third version identifier and the second version identifier being the same as the fourth version identifier, receiving the first program data from the host computer via the receiving port.

[0053] In this embodiment, the host computer checks whether the current version data and the latest version data are consistent through the version identifier of the version data. When the check result is that the first version identifier of the current main processor is inconsistent with the third version identifier of the latest version data of the main processor, and the second version identifier of the current slave processor is consistent with the fourth version identifier of the latest version data of the slave processor, it is determined that the data packet of the current main processor needs to be updated, while the data packet of the slave processor does not need to be updated. Therefore, the main processor only needs to receive the program to be written from the main processor through the receiving port and write the program to be written into its own storage area.

[0054] As an optional implementation, in response to the inconsistency between the current version data and the latest version data, receiving the program data to be written from the host computer via the receiving port includes: in response to the first version identifier being the same as the third version identifier and the second version identifier being different from the fourth version identifier, receiving the second program data from the host computer via the receiving port.

[0055] In this embodiment, the host computer checks whether the current version data and the latest version data are consistent through the version identifier of the version data. When the check result is that the first version identifier of the current main processor is consistent with the third version identifier of the latest version data of the main processor, and the second version identifier of the current slave processor is inconsistent with the fourth version identifier of the latest version data of the slave processor, it is determined that the data packet of the current slave processor needs to be updated, while the data packet of the main processor does not need to be updated. Therefore, the main processor only needs to receive the program to be written from the slave processor through the receiving port, and then send the program to be written from the slave processor to the slave processor, and the slave processor can write the program to be written into its own storage area.

[0056] As an optional implementation, in response to the inconsistency between the current version data and the latest version data, receiving the program data to be written from the host computer via the receiving port includes: in response to the first version identifier being different from the third version identifier and the second version identifier being different from the fourth version identifier, receiving the first program data and the second program data from the host computer via the receiving port.

[0057] In this embodiment, the host computer checks whether the current version data and the latest version data are consistent through the version identifier of the version data. When the check result is that the first version identifier of the current main processor is inconsistent with the third version identifier of the latest version data of the main processor, and the second version identifier of the current slave processor is also inconsistent with the fourth version identifier of the latest version data of the slave processor, it is determined that the data packets of the current main processor and the slave processor need to be updated. Therefore, the main processor needs to receive the first program data to be written to the main processor and the second program data to be written to the slave processor through the receiving port. After receiving the first program data and the second program data, the main processor sends the second program data to be written to the slave processor to the slave processor, and the slave processor writes the second program data to its own storage area.

[0058] As an optional implementation, the output port includes a first output port and a second output port. The output port identifier is verified with the receiving port identifier to obtain the verification result, which includes: obtaining the receiving port identifier of the receiving port; obtaining the first output port identifier carried by the program data to be written output through the first output port; and determining that the program data to be written output by the first output port is the first program data in response to the first output port identifier being the same as the receiving port identifier.

[0059] In this embodiment, the host computer has two output ports, namely the first output port and the second output port. The main processor verifies the port identifiers of multiple output ports and the port identifier of its own receiving port to obtain the verification result. The verification results include the following steps: the main processor first obtains the receiving port identifier of its own receiving port, and then obtains the first output port identifier carried by the program data to be written output through the first output port. The receiving port identifier and the first output port identifier carried by the program data to be written are verified. When the verification result is that the first output port identifier is the same as the receiving port identifier, the main processor determines that the program data to be written output by the first output port at this time is the first program data corresponding to the main processor.

[0060] Specifically, the port verification program set up inside the main processor can further verify the data packets loaded and transmitted manually, minimizing the risk of human error and achieving the technical effect of improving the accuracy of the program flashing process.

[0061] As an optional implementation, the method further includes: in response to the first output port identifier being different from the receiving port identifier, obtaining the second output port identifier carried in the program data to be written output through the second output port; and in response to the second output port identifier being the same as the receiving port identifier, determining that the program data to be written output by the second output port is the first program data.

[0062] In this embodiment, the host computer has two output ports, namely the first output port and the second output port. The main processor verifies the port identifiers of multiple output ports and the port identifier of its own receiving port to obtain the verification result. The verification process also includes the following steps: The main processor verifies the receiving port identifier and the first output port identifier carried by the program data to be written. When the verification result is that the first output port identifier is different from the receiving port identifier, the main processor determines that the program data to be written output by the first output port is not the first program data corresponding to the main processor. At this time, the main processor should also obtain the second output port identifier carried by the program data to be written output through the second output port, and verify the receiving port identifier and the second output port identifier carried by the program data to be written. When the verification result is that the second output port identifier is the same as the receiving port identifier, the main processor determines that the program data to be written output by the second output port is the first program data corresponding to the main processor.

[0063] Optionally, when the host computer transmits the program data to be written, due to manual loading errors, it is easy for the program data transmitted by the two transmission ports to be incorrect. That is, the first program data is loaded into the second transmission port for transmission, while the second program data is loaded into the first transmission port for transmission. Therefore, when it is found that the transmission port identifier carried by the program to be written in the first transmission port is different from the port identifier of the main processor receiving port, it can be determined by verifying whether the transmission port identifier carried by the program to be written in the second transmission port is consistent with the port identifier of the main processor receiving port.

[0064] As an optional implementation, the main processor stores a first preset key data, and the slave processor stores a second preset key data. The method further includes: receiving first current key data and second current key data from a host computer; when performing a write operation on the program data to be written, stopping the writing of the first program data to the main processor in response to the first current key data being different from the first preset key data; and / or, stopping the writing of the second program data to the slave processor in response to the second current key data being different from the second preset key data.

[0065] In this embodiment, the above-mentioned program flashing method further includes: during the program flashing process, the main processor receives first current key data and second current key data from the host computer. When the received first current key data is different from the first preset key data stored by the main processor, it is determined that a data verification error has occurred, and the writing of the first program data to the main processor should be stopped immediately. At the same time, when the main processor receives the first current key data and the second current key data, it also forwards the received second current key data to the slave processor. After receiving the second current key data, the slave processor verifies the second current key data with the second preset key data stored by the slave processor. If the received second current key data is different from the second preset key data, it is determined that a data verification error has occurred, and the slave processor stops writing the second program data to the slave processor.

[0066] Optionally, after performing internal key data verification, the main processor should wait for the key data verification results from the slave processors to be transmitted back to the main processor. Then, it aggregates its own key data verification results with those of the slave processors and sends them to the host computer. This process continues until all programs are successfully flashed, at which point the main processor aggregates the success results and displays them to the host computer. It's worth noting that if a processor's key data verification result is incorrect or the flashing process fails, the host computer will display a message indicating that a particular processor failed to flash after the process is complete. This allows the host computer to notify the user which processor experienced the flashing error. Afterward, the host computer will retransmit the program to flash the faulty processor until all processors are successfully flashed.

[0067] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or grid device, etc.) to execute the methods of the various embodiments of the present invention.

[0068] This embodiment also provides a program writing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0069] Figure 3 This is a structural block diagram of a program writing device 300 according to one embodiment of the present invention, as shown below. Figure 3 As shown, the device includes: an acquisition module 301, a transmission module 302, a first receiving module 303, a verification module 304, and a writing module 305.

[0070] The acquisition module 301 is used to acquire the current version data, wherein the current version data includes: the first version identifier of the main processor and the second version identifier of the slave processor;

[0071] The sending module 302 is used to send the current version data to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is equipped with multiple output ports, and each output port is equipped with an output port identifier.

[0072] The first receiving module 303 is used to receive program data to be written from the host computer via a receiving port in response to the inconsistency between the current version data and the latest version data. The receiving port is equipped with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor, and second program data to be written to the slave processor.

[0073] The verification module 304 is used to verify the output port identifier against the receiving port identifier and obtain the verification result.

[0074] The write module 305 is used to perform a write operation on the program data to be written in response to the verification result indicating that the output port identifier and the receiving port identifier are consistent.

[0075] Optionally, the first receiving module 303 includes: a first receiving unit, configured to receive first program data from the host computer via a receiving port in response to the first version identifier being different from the third version identifier and the second version identifier being the same as the fourth version identifier.

[0076] Optionally, the first receiving module 303 includes: a second receiving unit, configured to receive second program data from the host computer via a receiving port in response to the first version identifier being the same as the third version identifier and the second version identifier being different from the fourth version identifier.

[0077] Optionally, the first receiving module 303 includes: a third receiving unit, configured to receive first program data and second program data from the host computer via a receiving port in response to the first version identifier being different from the third version identifier and the second version identifier being different from the fourth version identifier.

[0078] Optionally, the verification module 304 includes: a first acquisition unit, used to acquire the receiver port identifier of the receiving port; a second acquisition unit, used to acquire the first output port identifier carried by the program data to be written output through the first output port; and a first determination unit, used to determine that the program data to be written output by the first output port is the first program data in response to the first output port identifier being the same as the receiver port identifier.

[0079] Optionally, the verification module 304 further includes: a third acquisition unit, configured to acquire the second output port identifier carried in the program data to be written output through the second output port in response to the first output port identifier being different from the receiving port identifier; and a second determination unit, configured to determine that the program data to be written output by the second output port is the first program data in response to the second output port identifier being the same as the receiving port identifier.

[0080] Optionally, the program writing device 300 further includes: a second receiving module for receiving first current key data and second current key data from a host computer; a stop module for stopping the writing of first program data to the main processor in response to the first current key data being different from the first preset key data when performing a write operation on the program data to be written; and / or stopping the writing of second program data to the slave processor in response to the second current key data being different from the second preset key data.

[0081] Embodiments of the present invention also provide a vehicle, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the above-described program flashing method.

[0082] Optionally, in this embodiment, the vehicle may be configured to store a computer program for performing the following steps:

[0083] Step S102: Obtain the current version data, wherein the current version data includes: the first version identifier of the main processor and the second version identifier of the slave processor;

[0084] Step S104: Send the current version data to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is equipped with multiple output ports, and each output port is equipped with an output port identifier.

[0085] Step S106: In response to the inconsistency between the current version data and the latest version data, receive the program data to be written from the host computer via the receiving port. The receiving port is set with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor, and second program data to be written to the slave processor.

[0086] Step S108: Verify the output port identifier with the receiving port identifier to obtain the verification result;

[0087] Step S110: In response to the verification result indicating that the output port identifier and the receiving port identifier are consistent, the write operation is performed on the program data to be written.

[0088] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0089] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0090] In the embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0091] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0093] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or grid device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0094] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for flashing a program, characterized in that, include: Obtain the current version data, wherein the current version data includes: a first version identifier of the main processor and a second version identifier of the slave processor; The current version data is sent to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is provided with multiple output ports, each of which is provided with an output port identifier. The multiple output ports include a first output port and a second output port. In response to the inconsistency between the current version data and the latest version data, program data to be written is received from the host computer via the receiving port, wherein the receiving port is provided with a receiving port identifier, and the program data to be written includes at least one of the following: first program data to be written to the main processor, and second program data to be written to the slave processor. The output port identifier is verified against the receiving port identifier to obtain the verification result; In response to the verification result indicating that the output port identifier matches the receiving port identifier, a write operation is performed on the program data to be written. The verification process involves comparing the output port identifier with the receiving port identifier to obtain the following verification results: Obtain the receiver port identifier of the receiving port; Obtain the first output port identifier carried in the program data to be written that is output through the first output port; In response to the fact that the first output port identifier is the same as the receiving port identifier, the program data to be written output by the first output port is determined to be the first program data; In response to the fact that the first output port identifier is different from the receiving port identifier, the second output port identifier carried by the program data to be written output through the second output port is obtained; In response to the fact that the second output port identifier is the same as the receiving port identifier, the program data to be written output by the second output port is determined to be the first program data.

2. The program flashing method according to claim 1, characterized in that, The latest version data includes: the third version identifier of the main processor, and the fourth version identifier of the slave processor. In response to a discrepancy between the current version data and the latest version data, the program data to be written received from the host computer via the receiving port includes: In response to the first version identifier being different from the third version identifier and the second version identifier being the same as the fourth version identifier, the first program data from the host computer is received via the receiving port.

3. The program flashing method according to claim 2, characterized in that, In response to the inconsistency between the current version data and the latest version data, receiving the program data to be written from the host computer via the receiving port includes: In response to the first version identifier being the same as the third version identifier and the second version identifier being different from the fourth version identifier, the second program data from the host computer is received via the receiving port.

4. The program flashing method according to claim 2, characterized in that, In response to the inconsistency between the current version data and the latest version data, receiving the program data to be written from the host computer via the receiving port includes: In response to the fact that the first version identifier is different from the third version identifier and the second version identifier is different from the fourth version identifier, the first program data and the second program data from the host computer are received via the receiving port.

5. The program flashing method according to claim 1, characterized in that, The main processor stores a first preset key data, the slave processor stores a second preset key data, and the method further includes: Receive the first current key data and the second current key data from the host computer; When performing the write operation on the program data to be written, in response to the first current key data being different from the first preset key data, the writing of the first program data to the main processor is stopped; and / or, in response to the second current key data being different from the second preset key data, the writing of the second program data to the slave processor is stopped.

6. A program flashing / writing device, characterized in that, include: The acquisition module is used to acquire current version data, wherein the current version data includes: a first version identifier of the main processor and a second version identifier of the slave processor; The sending module is used to send the current version data to the host computer so that the host computer can determine whether the current version data is consistent with the latest version data that has been loaded. The host computer is provided with multiple output ports, each output port is provided with an output port identifier, and the multiple output ports include a first output port and a second output port. The first receiving module is configured to receive program data to be written from the host computer via a receiving port in response to the inconsistency between the current version data and the latest version data. The receiving port is provided with a receiving port identifier. The program data to be written includes at least one of the following: first program data to be written to the main processor, and second program data to be written to the slave processor. The verification module is used to verify the output port identifier against the receiving port identifier to obtain the verification result; The writing module is configured to perform a writing operation on the program data to be written in response to the verification result indicating that the output port identifier and the receiving port identifier are consistent. The verification module is further configured to: Obtain the receiver port identifier of the receiving port; Obtain the first output port identifier carried in the program data to be written that is output through the first output port; In response to the fact that the first output port identifier is the same as the receiving port identifier, the program data to be written output by the first output port is determined to be the first program data; In response to the fact that the first output port identifier is different from the receiving port identifier, the second output port identifier carried by the program data to be written output through the second output port is obtained; In response to the fact that the second output port identifier is the same as the receiving port identifier, the program data to be written output by the second output port is determined to be the first program data.

7. A vehicle comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the flashing method of the program as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the flashing method of the program as described in any one of claims 1 to 5 when run on a computer or processor.

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