A synchronous read-write method, a storage device and a readable storage medium
By alternately generating write and read requests, and combining write and read registers, the problem of large area occupied by dual data ports is solved, synchronous read and write of memory is realized, and the number of data ports of memory chip is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YUSUR TECH CO LTD
- Filing Date
- 2023-11-30
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, static random access memory with dual data ports occupies a large area of the memory chip. How can we reduce the number of data ports of static random access memory while implementing a FIFO queue for synchronous read and write?
By alternately generating the first write request and the second write request, as well as the first read request and the second read request, and utilizing the write register and the read register, simulated synchronous read and write operations on the memory are achieved, while concurrent requests are handled with the help of the conflict register.
While reducing the number of data ports in the memory chip, synchronous read and write functions of the memory were achieved, reducing the overall area of the memory chip.
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Figure CN117632258B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and more specifically, to a synchronous read / write method, a storage device, and a readable storage medium. Background Technology
[0002] Static Random-Access Memory (SRAM) is a type of storage device. If an SRAM has two data ports, a synchronous FIFO can be implemented when one data port is being read from and the other is being written to. A FIFO (First In First Out) queue is a type of first-in-first-out queue, including synchronous FIFOs and asynchronous FIFOs. Synchronous FIFOs use the same clock for both reading and writing.
[0003] In the synchronous read and write process of memory chips, a synchronous FIFO queue is usually implemented using dual-port SRAM. The synchronous FIFO generally serves as a buffer for interactive data. When data is written in bursts (i.e., data is written too quickly and the interval is long), by setting a FIFO of a certain depth, it can temporarily store the data, prevent data loss, and make the subsequent processing flow smooth.
[0004] However, compared to static random access memory with a single data port, static random access memory with two data ports occupies more area of the digital circuitry in the memory chip, which is not conducive to reducing the overall area of the memory chip.
[0005] Therefore, how to reduce the amount of data in the static random access memory while enabling memory chips to implement FIFO queues for synchronous read and write is a key issue that needs to be considered in the process of improving memory chips. Summary of the Invention
[0006] This application provides a synchronous read / write method, a storage device, and a readable storage medium, which can achieve synchronous read / write of the memory while reducing the number of data ports in the memory on the chip.
[0007] Firstly, a synchronous read / write method is provided, including:
[0008] The system alternately generates a first write request and a second write request, and alternately generates a first read request and a second read request. The first write request and the first read request are both directed to the memory, the second write request is directed to the write register, and the second write request is directed to the read register. The data queue stored in the memory is a first-in-first-out queue.
[0009] When the first write request or the first read request occurs, determine whether the first write request and the first read request are concurrent. If not:
[0010] In response to the first write request, the write data of the first write request is written into the memory, and the write data of the second write request that has been written into the write register is written into the memory;
[0011] In response to the first read request, the current read data and the next read data in the first-in-first-out queue stored in the memory are read out to the same data port of the memory, and the next read data is written into the read register;
[0012] In response to the second read request, the next read data is read from the read register;
[0013] In response to the second write request, the write data of the second write request is written into the write register.
[0014] In one possible embodiment, the synchronous read / write method further includes: if the first write request and the first read request are concurrent, in response to the first write request, writing the write data of the first write request into a conflict register; and in response to the first read request, reading the current read data and the next read data in the first-in-first-out queue stored in the memory from the data port to the same data port of the memory, and writing the next read data into a read register; and after reading the current read data and the next read data in the first-in-first-out queue stored in the memory from the data port to the same data port of the memory, writing the write data of the first write request already written into the conflict register into the memory, and writing the write data of the second write request already written into the write register into the memory.
[0015] In one possible embodiment, the first-in-first-out queue includes a first sub-queue and a second sub-queue;
[0016] The step of responding to the first write request by writing the write data of the first write request into the memory, and writing the write data of the second write request already written in the write register into the memory, includes:
[0017] Write the write data of the first write request into the first sub-queue;
[0018] Write the write data of the second write request, which has already been written to the write register, into the second queue; and...
[0019] The step of writing the write data of the first write request already written to the conflict register into the memory, and writing the write data of the second write request already written to the write register into the memory, includes:
[0020] Write the write data of the first write request that has been written to the conflict register into the first sub-queue;
[0021] Write the write data of the second write request that has been written to the write register into the second queue.
[0022] In one possible embodiment, the step of responding to the first read request by reading the current read data and the next read data in the first-in-first-out queue stored in the memory from the data port to the same data port of the memory includes: responding to the first read request by reading the prior data in the first sub-queue as the next read data to the same data port of the memory; and reading the prior data in the second sub-queue as the current read data to the same data port of the memory.
[0023] In one possible embodiment, the alternating generation of the first write request and the second write request includes:
[0024] Determine the write request count status.
[0025] The second write request is generated when the count status of the write request indicates the odd number of times;
[0026] The first write request is generated when the count status of the write request indicates an even number of times.
[0027] In one possible embodiment, the alternating generation of the first read request and the second read request includes:
[0028] Determine the count status of read requests.
[0029] The first read request is generated when the count status of the read request indicates an odd number of read requests;
[0030] The second read request is generated when the count status of the read request indicates an even number of reads.
[0031] In one possible embodiment, the method further includes: when the read register is in an empty state and the memory is in an in-store state, responding to the first read request or the second read request, reading the currently read data in the first-in-first-out queue into the data port.
[0032] In one possible embodiment, when the read register, the memory, and the conflict register are all in an empty state, and the write register is in an in-store state, the data in the write register is read out in response to the first read request or the second read request.
[0033] Secondly, this application also provides a storage device, including: a read / write controller, a memory, a write register, a read register, and an instruction port, wherein the memory includes a data port; and the data queue stored in the memory is a first-in-first-out queue.
[0034] The read / write controller is configured to: alternately generate the first write request and the second write request, and alternately generate the first read request and the second read request;
[0035] The instruction port is used to: obtain the first write request, the second write request, the first read request, and the second read request from the read / write controller, and send the first write request and the first read request to the memory, send the second write request to the write register, and send the second write request to the read register;
[0036] The write register is used to: respond to the second write request and write the write data of the second write request;
[0037] The instruction port is also used to: determine whether the first write request and the first read request are concurrent; if not:
[0038] The memory is used to: respond to the first write request, write the write data of the first write request into the memory, and write the write data of the second write request that has been written into the write register;
[0039] The memory is also used to: in response to the first read request, read the current read data and the next read data from the first-in-first-out queue stored in the memory to the data port of the memory;
[0040] The read register is used to: write the next read data into the read register;
[0041] The read register is also used to: in response to the second read request, read the next read data from the read register.
[0042] In one possible embodiment, the storage device further includes a conflict register.
[0043] If the instruction port determines that the first write request and the first read request are concurrent:
[0044] The conflict register is used to: respond to the first write request and write the write data of the first write request;
[0045] In response to the first read request, after the memory reads the current read data and the next read data from the first-in-first-out queue from the data port to the same data port of the memory, the memory is further configured to: write the write data of the first write request in the conflict register, and write the write data of the second write request that has been written in the write register into the memory.
[0046] Thirdly, this application also provides a readable storage medium storing a program for a synchronous read / write method, wherein when the program for the synchronous read / write method is executed by a processor, the steps of the synchronous read / write method described above are implemented.
[0047] By employing the aforementioned synchronous read / write method, and utilizing write registers and read registers, and by alternately generating the first write request and the second write request, as well as the first read request and the second read request, read requests and write requests can be generated simultaneously within each unit time period, thus achieving simulated synchronous read / write of the memory. Therefore, the synchronous read / write method provided in this application can achieve synchronous read / write of the memory while reducing the number of data ports in the chip. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. By reading the detailed description of the embodiments below, the advantages and benefits of the solutions will become clear to those skilled in the art. The accompanying drawings are only for illustrating preferred embodiments and are not intended to limit this application. In the accompanying drawings:
[0049] Figure 1 A partial flowchart of a synchronous read / write method provided in an embodiment of this application is shown.
[0050] Figure 2 A partial flowchart of a synchronous read / write method provided in an embodiment of this application is shown.
[0051] Figure 3 The diagram illustrates the data flow in a synchronous read / write method provided in an embodiment of this application.
[0052] Figure 4 The illustration shows a flowchart of a synchronous read / write method provided in an embodiment of this application, illustrating the alternating generation of a first write request and a second write request.
[0053] Figure 5 The illustration shows a flowchart of a synchronous read / write method provided in an embodiment of this application, illustrating the alternating generation of a first request and a second read request.
[0054] Figure 6 A structural block diagram of a storage device provided in an embodiment of this application is shown.
[0055] Figure label:
[0056] S101: Alternately generate the first write request and the second write request, and alternately generate the first read request and the second read request;
[0057] S102: When the first write request or the first read request is generated, determine whether the first write request and the first read request are concurrent. If not, perform at least one of the following steps:
[0058] S104: In response to the second write request, write the write data of the second write request into the write register;
[0059] S105: In response to the first read request, read the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory, and write the next read data into the read register;
[0060] S103: In response to the first write request, write the write data of the first write request into the memory, and write the write data of the second write request that has been written into the write register into the memory;
[0061] S106: In response to the second read request, read the next read data from the read register;
[0062] S201: In response to the first write request, write the write data of the first write request into the conflict register;
[0063] S202: In response to the first read request, read the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory, and write the next read data into the read register;
[0064] S203: After reading the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory, the write data of the first write request that has been written to the conflict register is written to the first-in-first-out queue, and the write data of the second write request that has been written to the write register is written to the memory.
[0065] S401: Check the write request count status.
[0066] S402: When the count state of the write request indicates the odd number of times, the second write request is generated;
[0067] S403: When the count state of the write request indicates an even number of times, the first write request is generated;
[0068] S501: Determine the count status of read requests.
[0069] S502: When the count state of the read request indicates the odd number of times, the first read request is generated;
[0070] S503: When the count status of the read request indicates an even number of times, the second read request is generated;
[0071] 600: Storage device; 601: Read / write controller; 602: Memory; 603: Write register; 604: Read register; 605: Instruction port; 606: Conflict register; 607: Data port. Detailed Implementation
[0072] The technical solutions in this application will now be described with reference to the accompanying drawings.
[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0074] In related technologies, chips include a memory with a single data port and multiple internal registers. Because the memory has only one data port, synchronous read / write operations cannot be implemented, thus preventing the implementation of synchronous FIFO functionality. To address this issue, this application utilizes multiple internal registers within the chip (i.e., the storage device) to provide a synchronous read / write method, referencing... Figure 1 The synchronous read / write method includes:
[0075] Step S101: Alternately generate a first write request and a second write request, and alternately generate a first read request and a second read request. The first write request and the first read request are both directed to the memory, the second write request is directed to the write register, and the second write request is directed to the read register. The data queue stored in the memory is a first-in-first-out queue.
[0076] Step S102: When the first write request or the first read request is generated, determine whether the first write request and the first read request are concurrent. If not, execute at least one of the following steps S103, S104, S105 and S106.
[0077] Step S104: In response to the second write request, write the write data of the second write request into the write register.
[0078] Step S105: In response to the first read request, read the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory, and write the next read data into the read register; and,
[0079] Step S103: In response to the first write request, write the write data of the first write request into the memory, and write the write data of the second write request that has been written into the write register into the memory.
[0080] Step S106: In response to the second read request, read the next read data from the read register.
[0081] Based on the above technical solution, by using write registers and read registers, and by alternately generating the first write request and the second write request, as well as alternately generating the first read request and the second read request, simulated synchronous read and write of the memory of a single data port is realized.
[0082] Specifically, firstly, within the first unit time period, a second write request and a first read request can be concurrently initiated. In response to the second write request, the write data is written to the write register. Simultaneously, in response to the first read request, the current read data and the next read data from the first-in-first-out queue stored in the memory are read out to the same data port of the memory, and the next read data is written to the read register. That is, within the first unit time period, the memory data port is not used when responding to the second write request, but it is used when responding to the first read request. This achieves simulated synchronous read and write operations on the memory within the first unit time period. It should be clarified that after the current read data is read out to the memory data port, it will continue to be read out to the chip's data port; similarly, after the next read data is read from the read register, it will continue to be read out to the chip's data port. It should be understood that the memory can be based on SRAM. The storage device includes memory, a write register, and a read register. Read and write requests can be obtained from the instruction port of the storage device. Furthermore, read data is read from the data port of the storage device, and write data is written from the data port of the storage device.
[0083] Then, within the second unit time period, a first write request and a second read request can be generated simultaneously. In response to the second read request, the next read data is read from the read register. Simultaneously, in response to the first write request, the write data of the first request is written into the memory, and the write data of the first request already written into the write register is written into the memory. That is, within the second unit time period, the memory's data port is used in response to the first write request, but not in response to the second read request. Thus, simulated synchronous read and write operations on the memory are achieved within the second unit time period.
[0084] Then, within the third time unit, the concurrent second write request and first read request can be responded to in the same way as within the first time unit, thereby realizing simulated synchronous read and write to the memory within the third time unit.
[0085] In summary, this cyclical approach allows for the simultaneous generation of read and write requests within each time unit, achieving simulated synchronous read and write operations on the memory. Therefore, the synchronous read / write method provided in this application can reduce the number of data ports in the chip while simultaneously enabling synchronous read and write operations on the memory.
[0086] It should be clarified that if only a second write request or a second read request is generated within the same unit time period, then in response to the second write request, the write data of the second write request is written into the write register; in response to the second read request, the next read data is read from the read register.
[0087] In one possible embodiment, reference Figure 2 If the first write request and the first read request occur concurrently, then the following steps S201, S202 and S203 are executed:
[0088] Step S201: In response to the first write request, write the write data of the first write request into the conflict register;
[0089] Step S202: In response to the first read request, read the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory, and write the next read data into the read register;
[0090] Step S203: After reading the current read data and the next read data from the first-in-first-out queue stored in the memory to the same data port of the memory,
[0091] Write the write data of the first write request that has been written to the conflict register into the first-in-first-out data queue, and write the write data of the second write request that has been written to the write register into the memory.
[0092] This can be understood as follows: during the first time period mentioned above, only the second write request was generated, and the first read request was not generated. This resulted in the first write request and the first read request occurring concurrently during the second time period. In this case, a conflict register can be used to simulate synchronous read and write operations on the memory.
[0093] Specifically, in the first step, in response to the first read request, the current read data and the next read data stored in the first-in-first-out (FIFO) queue of the memory are read from the data port of the memory. Simultaneously, in response to the first write request, the write data of the first write request is written to the conflict register. Then, in the second step, the next read data is written to the read register. Simultaneously, the write data is written from the conflict register to the FIFO data queue, and the write data of the second write request already written to the write register is written to the memory. In this way, simulated synchronous read and write operations on the memory are achieved.
[0094] Then, in the next time unit, if the second write request and the second read request occur concurrently, the second write request is responded to and the data is written into the write register. At the same time, the second read request is responded to and the next read data is read from the read register.
[0095] Alternatively, if a second write request is generated but a second read request is not generated, the second write request is responded to and the data is written to the write register; while the next read data still exists in the read register, waiting for the second read request to be generated again.
[0096] Alternatively, if no second write request is generated, but a second read request is generated, the second read request is responded to, and the next read data is read from the read register; while the write register waits for the second write request to be generated again.
[0097] In summary, by using a conflict register and the method provided in this application, the problem of concurrent first read and first write requests can also be solved. Thus, regardless of whether the first and second write requests, or the first and second read requests, are generated alternately in a regular manner, simulated synchronous read and write operations on a single data port memory can be achieved.
[0098] It should be clarified that the memory has only one data port, but its bit width is twice that of a memory with two data ports. This memory allows the write data of the first write request and the write data of the second write request already written to the write register to be written into the memory simultaneously. Similarly, the currently read data and the next read data can be read from the data port simultaneously.
[0099] In one specific implementation, refer to Figure 3 The first-in-first-out queue includes a first sub-queue and a second sub-queue; the step of responding to the first write request, writing the write data of the first write request into the memory, and writing the write data of the second write request that has been written into the write register into the memory includes: writing the write data of the first write request into the first sub-queue; and writing the write data of the second write request that has been written into the write register into the second queue.
[0100] Furthermore, the step of writing the write data of the first write request already written in the conflict register to the memory, and writing the write data of the second write request already written in the write register to the memory, includes: writing the write data of the first write request already written in the conflict register to the first sub-queue; and writing the write data of the second write request already written in the write register to the second queue.
[0101] This method facilitates storing the write data of the first write request into the first sub-queue and the write data of the second write request into the second sub-queue, according to the order in which the first and second write requests are generated. This prepares the system for responding to the first and second read requests. Specifically:
[0102] The step of responding to the first read request by reading the current read data and the next read data in the first-in-first-out queue stored in the memory to the same data port of the memory includes: responding to the first read request by reading the prior data in the first sub-queue as the next read data to the same data port of the memory; and reading the prior data in the second sub-queue as the current read data to the same data port of the memory.
[0103] Here, "earlier data" in the first sub-queue refers to data that was written to the first sub-queue earlier, and "earlier data" in the second sub-queue refers to data that was written to the second sub-queue earlier.
[0104] In summary, by distinguishing between the first and second sub-queues, and mapping the first write request to the first sub-queue and the second write request to the second sub-queue, it is easier to differentiate between the currently read data and the next data to be read during the first read request. This ensures that data is written to and read from memory according to a first-in, first-out (FIFO) mechanism.
[0105] In one possible embodiment, reference Figure 4 The alternating generation of the first write request and the second write request includes:
[0106] Step S401: Determine the write request count status.
[0107] Step S402: When the count state of the write request indicates the odd number of times, the second write request is generated; that is, the second write request is generated when the count state indicates the odd number of times.
[0108] Step S403: The first write request is generated when the count state of the write request indicates an even number of times. That is, the first write request is generated when the count state indicates an even number of times.
[0109] In other words, when a write request is generated, a first write request is generated first, followed by a second write request, and then the first and second write requests are generated alternately. Furthermore, the order in which the write request is generated is determined to identify whether the current write request is the first or second write request.
[0110] Based on the above description, this application provides an embodiment in which: the first write request can be determined as the second write request, the second write request as the first write request, the third write request as the second write request, and so on. In this way, the data in the second sub-queue corresponding to the second write request should be read out as the current read data, and the data in the first sub-queue corresponding to the first write request should be read out as the next read data.
[0111] In one possible embodiment, reference Figure 5 The alternating generation of the first read request and the second read request further includes:
[0112] Step S501: Determine the count status of the read request.
[0113] Step S502: The first read request is generated when the count state of the read request indicates the odd number of times; that is, the first read request is generated when the count state indicates the odd number of times.
[0114] Step S503: When the count state of the read request indicates an even number of times, the second read request is generated. That is, the second read request is generated when the count state indicates an even number of times.
[0115] In other words, a first read request is generated first, followed by a second read request, and then the first and second read requests are generated alternately. Furthermore, by determining which read request it is, we can determine whether the current write request is the first or second read request, thus identifying whether each read request is for memory or for a register.
[0116] It should be clarified here that when the first read request is generated, a first write request or a second write request may be generated simultaneously; this application does not limit this. Furthermore, the first second write request is generated before the first first read request, so that the first read request can read data from the write register, memory, or read register.
[0117] In one possible implementation, when the read register is in an empty state and the memory is in an in-store state, the current read data in the first-in-first-out queue is read into the data port in response to the second read request.
[0118] In other words, for special cases where the read register is empty (i.e., not storing the next read data) but the memory stores the current read data, even though the second read request is directed to the read register, the current read data in the first-in-first-out queue can still be read into the data port to respond to the second read request.
[0119] In another possible implementation, when the read register, the memory, and the conflict register are all in an empty state, and the write register is in an active state,
[0120] In response to the first read request or the second read request, the data in the write register is read out.
[0121] In other words, for special cases that may occur: when the read register, the memory, and the conflict register are all in an empty state, that is, when the read register, the memory, and the conflict register do not store data, but the write register stores the write data of the second write instruction, the data in the write register can still be read out to respond to the first read request or the second read request.
[0122] This application also protects a storage device that can achieve synchronous read and write operations using the synchronous read / write method described above. In one possible example, the storage device can be a chip.
[0123] refer to Figure 6The storage device 600 includes a read / write controller 601, a memory 602, a write register 603, a read register 604, and an instruction port 605 (which can be implemented as an instruction port, for example). The storage device 600 may also include a first data port 607, and the memory includes a second data port. The storage data queue in the memory is a first-in-first-out queue.
[0124] The read / write controller 601 is used to: alternately generate the first write request and the second write request, and alternately generate the first read request and the second read request;
[0125] The instruction port 605 is used to: obtain the first write request, the second write request, the first read request, and the second read request from the read / write controller, and send the first write request and the first read request to the memory, send the second write request to the write register, and send the second write request to the read register;
[0126] The write register 603 is used to: respond to the second write request and write the write data of the second write request;
[0127] The instruction port 605 is also used to: determine whether the first write request and the first read request are concurrent; if not:
[0128] The memory 602 is used to: respond to the first write request, write the write data of the first write request into the memory, and write the write data of the second write request that has been written into the write register;
[0129] The memory 602 is further configured to: in response to the first read request, read the currently read data and the next read data from the first-in-first-out queue stored in the memory to the data port of the memory.
[0130] The read register 604 is used to write the next read data;
[0131] The read register 604 is further configured to: in response to the second read request, read the next read data from the read register. The next read data will then be read into the first data port 607.
[0132] Based on the above technical solution, the read / write controller alternately generates the first write request and the second write request, as well as the first read request and the second read request. With the help of the write register and the read register, it realizes the simulated synchronous read and write of the memory with a single data port, so that the storage device can realize synchronous read and write.
[0133] Specifically, firstly, within the first unit time period, a second write request and a first read request can be concurrently initiated. In response to the second write request, the write data is written to the register. Simultaneously, in response to the first read request, the current read data and the next read data from the first-in-first-out queue stored in the memory are read out to the memory's data port, and the next read data is written to the read register. That is, within the first unit time period, the memory's data port is not used when responding to the second write request, but it is used when responding to the first read request. This achieves simulated synchronous read and write operations on the memory within the first unit time period, meaning the storage device can perform synchronous read and write operations. Of course, after the currently read data is read out to the memory's data port, it will continue to be read to the first data port 607.
[0134] Then, within the second unit time period, a first write request and a second read request can be generated simultaneously. In response to the second read request, the next read data is read from the read register. Simultaneously, in response to the first write request, the write data of the first request is written into the memory, and the write data of the first request already written into the write register is written into the memory. That is, within the second unit time period, the memory's data port is used when responding to the first write request, but not when responding to the second read request. In this way, simulated synchronous read and write operations on the memory are achieved within the second unit time period, meaning the storage device can perform synchronous read and write operations.
[0135] Then, within the third time unit, the second write request and the first read request can be responded to in the same way as in the first time unit, thereby realizing simulated synchronous read and write to the memory within the third time unit, that is, realizing synchronous read and write to the storage device.
[0136] In summary, this cyclical approach allows for the simultaneous generation of read and write requests within each time unit, achieving synchronous read and write operations on the storage device. Therefore, the synchronous read / write method provided in this application enables synchronous read and write operations on the storage device while reducing the number of data ports in the memory.
[0137] In one possible embodiment, the storage device further includes a conflict register 606, which is used if the instruction port determines that the first write request and the first read request are concurrent:
[0138] The conflict register is used to: respond to the first write request and write the write data of the first write request;
[0139] In response to the first read request, the memory reads the current read data and the next read data from the first-in-first-out queue to the memory's data port.
[0140] The memory is also used to: write the write data of the first write request in the conflict register, and write the write data of the second write request that has been written in the write register into the memory.
[0141] This can be understood as follows: During the first unit time period, the read / write controller only generated the second write request and did not generate the first read request. This resulted in the first write request and the first read request occurring concurrently during the second unit time period. In this case, a conflict register can be used to simulate synchronous read and write operations on the memory.
[0142] Specifically, in the first step, in response to the first read request, the current read data and the next read data stored in the first-in-first-out (FIFO) queue of the memory are read out to the data port of the memory. Simultaneously, in response to the first write request, the write data of the first write request is written into the conflict register. Then, in the second step, the next read data is written into the read register. At the same time, the write data is written from the conflict register into the FIFO data queue, and the write data of the second write request already written into the write register is written into the memory. In this way, the storage device can achieve synchronous read and write operations.
[0143] Then, in the next time unit, if the second write request and the second read request occur concurrently, the second write request is responded to and the data is written into the write register. At the same time, the second read request is responded to and the next read data is read from the read register.
[0144] Alternatively, if a second write request is generated but a second read request is not generated, the second write request is responded to and the data is written to the write register; while the next read data still exists in the read register, waiting for the second read request to be generated again.
[0145] Alternatively, if no second write request is generated, but a second read request is generated, the second read request is responded to, and the next read data is read from the read register; while the write register waits for the second write request to be generated again.
[0146] In summary, the problem of concurrent first read and first write requests can be solved by using a conflict register. Thus, regardless of whether the first and second write requests, or the first and second read requests, occur alternately, simulated synchronous read and write operations can be performed on a single data port memory, meaning the memory device can achieve synchronous read and write operations.
[0147] It should be clarified that the memory has only one data port, but its bit width is twice that of a memory with two data ports. This memory allows the write data of the first write request and the write data of the second write request already written to the write register to be written into the memory simultaneously. Similarly, the currently read data and the next read data can be read out to the same data port of the memory simultaneously.
[0148] In one specific implementation, the memory includes a first storage area and a second storage area. The first storage area is used to store a first sub-queue, and the second storage area is used to store a second sub-queue. Both the first sub-queue and the second sub-queue are first-in-first-out queues.
[0149] Specifically, the memory is used to: write the write data of the first write request into the first sub-queue; write the write data of the first write request that has been written into the conflict register into the first sub-queue; and write the write data of the second write request that has been written into the write register into the second queue.
[0150] This method facilitates storing the write data of the first write request into the first sub-queue and the write data of the second write request into the second sub-queue, according to the order in which the first and second write requests are generated. This prepares the memory for responding to the first and second read requests. Specifically:
[0151] In one example, the memory has a data port for: in response to the first request, reading prior data in the first sub-queue as the next read data to the memory data port, and reading prior data in the second sub-queue as the current read data to the memory data port.
[0152] It can also be understood as:
[0153] The step of responding to the first read request by reading the current read data and the next read data from the first-in-first-out queue stored in the memory to the data port of the memory includes: responding to the first read request by reading the prior data in the first sub-queue as the next read data to the data port of the memory; and reading the prior data in the second sub-queue as the current read data to the data port of the memory.
[0154] Here, "earlier data" in the first sub-queue refers to data written to the first sub-queue earlier, and "earlier data" in the second sub-queue refers to data written to the second sub-queue earlier. In summary, by distinguishing between the first and second sub-queues, and mapping the first write request to the first sub-queue and the second write request to the second sub-queue, it is easier to distinguish between the currently read data and the next data to be read during the first read request. This ensures that data is written to and read from memory according to a first-in, first-out (FIFO) mechanism.
[0155] In one possible embodiment, the read / write controller may include a first counter device.
[0156] The first counter is used to determine the count status of write requests.
[0157] The read / write controller generates the second write request when the count status of the write request indicates an odd number of times.
[0158] The read / write controller generates the first write request when the count status of the write request indicates an even number of times.
[0159] In other words, when a write request is generated, a first write request is generated first, followed by a second write request, and then the first and second write requests are generated alternately. Furthermore, by determining which write request it is the first or second, it can be determined whether each write request is directed to memory or to a register.
[0160] Based on the above description, this application provides an embodiment in which: the first write request can be determined as the second write request, the second write request as the first write request, the third write request as the second write request, and so on. In this way, the data in the second sub-queue corresponding to the second write request should be read out as the current read data, and the data in the first sub-queue corresponding to the first write request should be read out as the next read data.
[0161] In one possible embodiment, the read / write controller may include a second counter device, and further includes:
[0162] The second counter is used to determine the count status of read requests. The read / write controller obtains the count status of read requests.
[0163] The read / write controller generates the first read request when the count status of the read request indicates an odd number of reads;
[0164] The read / write controller generates the second read request when the count status of the read request indicates an even number of reads.
[0165] In other words, the read / write controller first generates a first read request, then a second read request, and so on, alternating between the first and second read requests. Furthermore, by determining which read request it is, it can be determined whether the current write request is the first or second read request, thus indicating whether each read request is for memory or for a register.
[0166] It should be clarified here that when the read / write controller generates the first read request, it may simultaneously generate the first write request or the second write request; this application does not limit this. Furthermore, the first second write request is generated before the first first read request, so that the first read request can read data from the write register, memory, or read register.
[0167] In one possible implementation, when the read register is in an empty state and the memory is in an in-store state, the memory is also used to respond to the second read request by reading the currently read data in the first-in-first-out queue into the data port.
[0168] In other words, for special cases where the read register is empty (i.e., not storing the next read data) but the memory stores the current read data, even though the second read request is directed to the read register, the current read data in the first-in-first-out queue can still be read into the data port to respond to the second read request.
[0169] In another possible implementation, when the read register, the memory, and the conflict register are all in an empty state, and the write register is in an active state,
[0170] The write register is also used to read the data in the write register in response to the first read request or the second read request.
[0171] In other words, for special cases that may occur: when the read register, the memory, and the conflict register are all in an empty state, that is, when the read register, the memory, and the conflict register do not store data, but the write register stores the write data of the second write instruction, the data in the write register can still be read out to respond to the first read request or the second read request.
[0172] This application also provides a program storing a synchronous read / write method on the readable storage medium, wherein when the program of the synchronous read / write method is executed by a processor, it implements the steps of the synchronous read / write method described above.
[0173] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.
[0174] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.
[0175] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A synchronous read / write method, characterized in that, include: The system alternately generates a first write request and a second write request, and alternately generates a first read request and a second read request. The first write request and the first read request are both directed to the memory, the second write request is directed to the write register, and the second write request is directed to the read register. The data queue stored in the memory is a first-in-first-out queue. When the first write request or the first read request is generated, determine whether the first write request and the first read request are concurrent. If not, execute the following time-period cycle. Within the first time unit, the second write request and the first read request are executed concurrently: In response to the second write request, the write data of the second write request is written into the register. At the same time, in response to the first read request, the current read data and the next read data in the first-in-first-out queue stored in the memory are read out to the same data port of the memory, and the next read data is written into the read register. Within the second time unit, the first write request and the second read request are executed concurrently: In response to the second read request, the next read data is read from the read register; at the same time, in response to the first write request, the write data of the first write request is written into the memory, and the write data of the second write request that has been written into the write register is written into the memory. Repeat the operations of the first and second time periods described above to achieve continuous synchronous read and write; If the first write request and the first read request occur concurrently, respond to the first write request by writing the write data of the first write request into the conflict register; In response to the first read request, the current read data and the next read data in the first-in-first-out queue stored in the memory are read from the data port to the same data port of the memory, and the next read data is written into the read register; Furthermore, after reading the current read data and the next read data from the first-in-first-out queue stored in the memory from the data port to the same data port of the memory, the write data of the first write request that has been written to the conflict register is written to the memory, and the write data of the second write request that has been written to the write register is written to the memory.
2. The synchronous read / write method according to claim 1, characterized in that, The first-in-first-out queue includes a first sub-queue and a second sub-queue; The step of responding to the first write request by writing the write data of the first write request into the memory, and writing the write data of the second write request already written in the write register into the memory, includes: Write the write data of the first write request into the first sub-queue; Write the write data of the second write request, which has already been written to the write register, into the second sub-queue; and... The step of writing the write data of the first write request already written to the conflict register into the memory, and writing the write data of the second write request already written to the write register into the memory, includes: Write the write data of the first write request that has been written to the conflict register into the first sub-queue; Write the write data of the second write request, which has already been written to the write register, into the second sub-queue.
3. The synchronous read / write method according to claim 2, characterized in that, The step of responding to the first read request by reading the current read data and the next read data from the first-in-first-out queue stored in the memory from the data port to the same data port of the memory includes: In response to the first read request, the prior data in the first sub-queue is read as the next read data and sent to the same data port of the memory; and, The prior data in the second sub-queue is read out as the current read data to the same data port of the memory.
4. The synchronous read / write method according to claim 1, characterized in that, The alternating generation of the first write request and the second write request includes: Determine the write request count status. The second write request is generated when the count status of the write request indicates the odd number of times; The first write request is generated when the count status of the write request indicates an even number of times.
5. The synchronous read / write method according to claim 1, characterized in that, The alternating generation of the first read request and the second read request includes: Determine the count status of read requests. The first read request is generated when the count status of the read request indicates an odd number of read requests; The second read request is generated when the count status of the read request indicates an even number of reads.
6. The synchronous read / write method according to claim 1, characterized in that, The method further includes: when the read register is in an empty state and the memory is in a stored state. In response to the first read request or the second read request, the currently read data in the first-in-first-out queue is read into the data port.
7. The synchronous read / write method according to claim 1, characterized in that, When the read register, the memory, and the conflict register are all in an empty state, and the write register is in a stored state, In response to the first read request or the second read request, the data in the write register is read out.
8. A storage device, characterized in that, include: The system includes a read / write controller, a memory, a write register, a read register, and an instruction port. The memory includes a data port. The data queue stored in the memory is a first-in-first-out (FIFO) queue. The read / write controller is used to: alternately generate a first write request and a second write request, and alternately generate a first read request and a second read request; and to cyclically control each component to perform operations according to the following unit time period to achieve simulated synchronous read / write; The instruction port is used to: obtain the first write request, the second write request, the first read request, and the second read request from the read / write controller, and send the first write request and the first read request to the memory, send the second write request to the write register, and send the second write request to the read register; The write register is used to: respond to the second write request and write the write data of the second write request; The instruction port is also used to: determine whether the first write request and the first read request are concurrent; if not: Within the first time unit, control the concurrent execution of the second write request and the first read request: The write register is used to: respond to the second write request and write the write data of the second write request; the memory is also used to: respond to the first read request and read the current read data and the next read data from the first-in-first-out queue stored in the memory to the data port of the memory; the read register is used to: write the next read data; Within the second time unit, control the concurrent execution of the first write request and the second read request: The read register is further configured to: in response to the second read request, read the next read data from the read register; the memory is further configured to: in response to the first write request, write the write data of the first write request into the memory, and write the write data of the second write request that has been written into the write register; Repeat the operations for the first and second time units as described above; The storage device further includes a conflict register. If the instruction port determines that the first write request and the first read request are concurrent, the conflict register is used to: respond to the first write request and write the write data of the first write request. In response to the first read request, after the memory reads the current read data and the next read data from the first-in-first-out queue from the data port to the same data port of the memory, the memory is further configured to: write the write data of the first write request in the conflict register, and write the write data of the second write request that has been written in the write register into the memory.
9. A readable storage medium, characterized in that, The readable storage medium stores a program for a synchronous read / write method. When the program for the synchronous read / write method is executed by a processor, it implements the steps of the synchronous read / write method as described in any one of claims 1-7.