A heterogeneous hardware emulation method and system

Abstract

The present application relates to the technical field of chip verification, in particular to a heterogeneous hardware simulation method and system, which interconnects microprocessors and FPGA chips, wherein the compilation speed of the microprocessors is greater than that of the FPGA and the simulation performance is lower than that of the FPGA chip, the chip design is divided by a system compiler to multiple microprocessors and FPGA chips, wherein the autonomous design module D to be debugged and corrected in the chip design is divided to the microprocessors, and the physical interconnection link is allocated to the divided microprocessors and FPGA, and the executable files are generated after being compiled respectively to perform cooperative simulation, since the compilation speed of the microprocessor where the autonomous design module is located is greater than that of the FPGA chip, and meanwhile the mature design module in the FPGA chip has high simulation performance, the iteration speed of the microprocessor and the simulation performance of the FPGA are combined.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a heterogeneous hardware simulation method and system. Background Technology

[0002] Chip design, also known as integrated circuit design (IC design), refers to the design process targeting integrated circuits and very large-scale integrated circuits. Chip design typically uses hardware description languages, such as Verilog, System Verilog, and VHDL, which are text-based languages ​​used to describe the structure and behavior of digital system hardware. After the chip design is completed, it enters the tape-out stage. Fatal problems in the chip design can lead to tape-out failure, which is very costly. To reduce the risk of tape-out failure, the chip design needs to be thoroughly verified before tape-out to identify problems in a timely manner and make adjustments to ensure a smooth tape-out process.

[0003] Digital chip logic function verification includes software simulation and hardware simulation. The hardware emulator architecture includes a Field Programmable Gate Array (FPGA) and a microprocessor. In hardware simulation, FPGA compilation is time-consuming and has a low iteration speed, but offers good simulation performance. Microprocessors, on the other hand, have a high iteration speed but relatively poor simulation performance. Currently, there is no hardware emulator that can balance simulation performance and iteration speed. Therefore, effectively allocating IC design tasks to FPGAs and microprocessors to fully leverage the advantages of each hardware emulator has become a pressing technical problem. Summary of the Invention

[0004] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0005] In a first aspect, embodiments of the present invention provide a heterogeneous hardware simulation method, the method comprising:

[0006] S200, acquire an interconnected hardware emulator Emu and K memories. The Emu includes N microprocessors and M FPGA chips. The compilation speed of the microprocessors is greater than that of the FPGA chips, but the simulation performance is lower than that of the FPGA chips. There are L physical interconnect links between the N microprocessors, M FPGA chips and K memories, where K≥0, N≥1, M≥1 and L≥1.

[0007] S400, Obtain the chip design DUT, which includes the self-designed module D to be debugged and corrected.

[0008] S600, the system compiler processes the DUT to obtain n Class I executable files corresponding to n microprocessors in Emu and m Class II executable files corresponding to m FPGA chips, where 0 < n ≤ N and 0 < m ≤ M; including:

[0009] S620 divides the DUT into n microprocessors and m FPGA chips, where D is divided into microprocessors, resulting in a first type of design module of n microprocessors and a second type of design module of m FPGA chips; where 0 < n ≤ N and 0 < m ≤ M.

[0010] S640 allocates physical interconnection links for the transmission signals between n first-class design modules and m second-class design modules, resulting in signal transmission configuration modules for n first-class design modules and m second-class design modules.

[0011] S660 compiles and generates a first-class executable file for the microprocessor based on each first-class design module and its signal transmission configuration module, resulting in n first-class executable files; it also compiles and generates a second-class executable file for the FPGA chip based on each second-class design module and its signal transmission configuration module, resulting in m second-class executable files.

[0012] The S800 stores n first-class executable files into n microprocessors and m second-class executable files into m FPGA chips. It controls the n microprocessors and m FPGA chips to perform collaborative simulation and debugging through the first-class and second-class executable files.

[0013] Secondly, embodiments of the present invention provide a heterogeneous hardware simulation system. The system includes an interconnected hardware emulator (Emu), K memories, and a system compiler. The Emu includes N microprocessors and M FPGA chips. The compilation speed of the microprocessors is greater than that of the FPGA chips, but their simulation performance is lower. The N microprocessors, M FPGA chips, and K memories are interconnected by L physical interconnect links, where K ≥ 0, N ≥ 1, M ≥ 1, and L ≥ 1. The system compiler includes a partitioner, a router, n microprocessor compilers, and m FPGA chip compilers, where 0 < n ≤ N and 0 < m ≤ M.

[0014] A partitioner is used to partition a chip design unit (DUT) into n microprocessors and m FPGA chips, wherein the DUT includes a custom design module D to be debugged and corrected. D is partitioned into microprocessors to obtain a first type of design module of n microprocessors and a second type of design module of m FPGA chips.

[0015] A router is used to allocate physical interconnect links for the transmission signals between n first-class design modules and m second-class design modules, resulting in signal transmission configuration modules for the n first-class design modules and the m second-class design modules.

[0016] A microprocessor compiler is used to compile and generate a first-class executable file for a microprocessor based on a first-class design module and its signal transmission configuration module.

[0017] An FPGA chip compiler is used to compile and generate a second-type executable file for an FPGA chip based on the second-type design module and its signal transmission configuration module.

[0018] The server is used to store n first-class executable files into n microprocessors and m second-class executable files into m FPGA chips. The first-class and second-class executable files are used to control the n microprocessors and m FPGA chips to perform collaborative simulation and debugging.

[0019] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the heterogeneous hardware simulation method and system provided by the present invention can achieve considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0020] This invention provides a heterogeneous hardware simulation method and system. It constructs a heterogeneous system by interconnecting microprocessors and FPGA chips. A system compiler assigns the chip design to multiple microprocessors and FPGA chips. The self-designed module D, which requires debugging and correction, is assigned to the microprocessors. After compiling and generating executable files, co-simulation is performed. Compared to using only FPGAs or microprocessors as hardware simulators, this invention enables simulation iteration speed equivalent to that of a microprocessor, and merges simulation performance close to that of an FPGA. Therefore, this invention combines the advantages of microprocessor iteration speed and FPGA simulation performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart of a heterogeneous hardware simulation method provided in an embodiment of the present invention;

[0023] Figure 2This is a block diagram of a system compiler in a heterogeneous hardware simulation system provided in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Hardware simulators consist of FPGAs (Field Programmable Gate Arrays) and microprocessors. FPGAs do not rely on software to simulate circuit behavior; instead, they directly execute simulation tasks, resulting in superior simulation performance. During compilation, placement and routing is a crucial step, determining the physical arrangement and electrical connections of logic circuits on the FPGA. However, the extensive optimization and constraint settings required during placement and routing lead to significant time consumption, consequently resulting in long FPGA compilation times and slow iteration speeds. If bugs are found in the chip design during simulation, each bug fix necessitates recompiling the modified chip design on the FPGA, further increasing compilation time, slowing iteration speed, and reducing debug usability. Microprocessors do not require placement and routing and have a fast iteration speed through direct compilation. However, their simulation performance is lower than that of FPGAs. To combine the advantages of simulation performance and iteration speed during IC design simulation and debugging, this invention combines FPGAs and microprocessors. The self-designed modules that require key debugging and correction in the chip design are assigned to the microprocessor, while the mature design modules are mainly assigned to the FPGA. Then, each FPGA and microprocessor is compiled separately to generate corresponding executable files. The executable files are used to control the FPGA and microprocessor to perform joint simulation. When the self-designed modules need debugging, the chip design corresponding to the modified parts is recompiled, resulting in a significant improvement in compilation speed compared to FPGAs. At the same time, in subsequent simulations, the mature design modules can fully utilize the simulation performance advantages of FPGAs, thus combining the advantages of simulation performance and iteration speed.

[0026] Please see Figure 1 The diagram illustrates a flowchart of a heterogeneous hardware simulation method provided by an embodiment of the present invention, the method comprising the following steps:

[0027] S200, acquire an interconnected hardware emulator Emu and K memories. The Emu includes N microprocessors and M FPGA chips. The compilation speed of the microprocessors is greater than that of the FPGA chips, but the simulation performance is lower than that of the FPGA chips. The N microprocessors, M FPGA chips and K memories include L physical interconnect links, where K≥0, N≥1, M≥1 and L≥1.

[0028] Optionally, the microprocessor is a Boolean processor or a multi-core processor. Microprocessors in the prior art capable of hardware simulation and with compilation speeds exceeding those of FPGAs all fall within the scope of this invention. Preferably, the microprocessor is a Boolean processor. It should be noted that a Boolean processor is a microprocessor specifically designed for handling Boolean operations, including AND, OR, and NOT operations. During the compilation process to generate an executable file, a Boolean processor does not require placement and routing, resulting in faster compilation speeds than FPGAs and higher ease of debugging.

[0029] The memory is used to support memory in debugging or simulating chip design. Optionally, the memory is random access memory (RAM). Further, the memory is dynamic random access memory (DRAM) or static random access memory (SRAM).

[0030] The network comprises N microprocessors, M FPGA chips, and K memories, which are interconnected by multiple physical interconnect links, each forming an interconnect channel. The interconnect structure includes a u-th memory that simultaneously connects f1 microprocessors and f2 FPGA chips, where f1 and f2 are both greater than or equal to 0.

[0031] S400, Obtain the chip design DUT (Design Under Test), which includes a user-designed module D to be debugged and corrected. The chip design DUT is the RTL code of the chip design, including the user-designed module D and a mature design module P. The user-designed module D is a user-defined module that requires focused debugging and is specified by the user. The mature design P is a circuit module that has been repeatedly verified and does not require extensive modification or adjustment, such as an IP core or a mature circuit module from a previous generation that has been repeatedly verified.

[0032] In S600, the system compiler processes the DUT to obtain n Class I executable files corresponding to the n microprocessors in the Emu and m Class II executable files corresponding to the m FPGA chips, where 0 < n ≤ N and 0 < m ≤ M. The executable files are binary code.

[0033] Furthermore, the steps by which the system compiler processes the DUT include:

[0034] S620 divides the DUT into n microprocessors and m FPGA chips, where D is assigned to a microprocessor, resulting in a first type of design module with n microprocessors and a second type of design module with m FPGA chips.

[0035] For ease of description, FPGA chips and microprocessors will be collectively referred to as hardware emulators, and will not be further specified below.

[0036] It should be noted that chip design DUTs are generally quite large, while the hardware resources of a single hardware emulator are limited. A single hardware emulator cannot accommodate the entire chip design. Therefore, the chip design DUT needs to be divided into n+m design modules, and each design module is used to implement the design on the corresponding hardware emulator.

[0037] Among them, the self-designed module D requires intensive debugging and correction, necessitating multiple recompilations. Therefore, module D is allocated to the microprocessor, which accelerates compilation during simulation, thereby improving simulation efficiency. Furthermore, when D needs recompilation, the microprocessor also speeds up the recompilation process, enhancing overall simulation efficiency. Meanwhile, the mature design modules, other than the self-designed module, do not require intensive debugging and correction and are more focused on simulation, avoiding multiple recompilations. Therefore, the mature design modules are primarily allocated to the FPGA, where their simulation performance is better.

[0038] Optionally, the partitioning steps include: marking the self-designed module D as a first-class label and the mature design module P as a second-class label, assigning the chip design with the first-class label to the microprocessor, and assigning the chip design with the second-class label to the FPGA.

[0039] S640 allocates physical interconnect links for the transmission signals between n first-class design modules and m second-class design modules, resulting in signal transmission configuration modules for the n first-class design modules and the m second-class design modules. A routing algorithm can allocate physical interconnect links for data transmission and communication between the various hardware simulators; all existing routing algorithms fall within the scope of this invention. It should be noted that the signal transmission configuration module stores the mapping relationship between the transmission signals and physical interconnect links in the corresponding first-class design modules.

[0040] The S660 compiles and generates n executable files for the microprocessor based on each first-type design module and its signal transmission configuration module; it also compiles and generates m executable files for the FPGA chip based on each second-type design module and its signal transmission configuration module. It should be noted that the executable files are binary files.

[0041] The S800 stores n first-class executable files into n microprocessors and m second-class executable files into m FPGA chips. It controls the n microprocessors and m FPGA chips to perform collaborative simulation and debugging through the first-class and second-class executable files.

[0042] Regarding hardware simulation iteration speed, this invention addresses this by allocating the self-designed modules to a microprocessor. When debugging and modifying these modules, only the microprocessor needs to be recompiled, resulting in an overall system iteration speed equal to the microprocessor's iteration speed. If the entire DUT is allocated to an FPGA, the system iteration speed equals the FPGA's iteration speed. Since the microprocessor's iteration speed is greater than the FPGA's, this invention improves the overall system iteration speed. For example, for a design module, the compilation time on an FPGA is 26 hours, while on a microprocessor it's 6 hours. If the entire DUT is allocated to the FPGA, the system compilation time is 26 hours; with this invention, the compilation time is only 6 hours, thus improving the iteration speed compared to allocating the entire DUT to the FPGA.

[0043] For hardware simulation performance, the proportion of parts that require frequent modifications is low. The more mature designs that require more modifications are implemented in FPGAs. FPGA simulation performance is higher than that of microprocessors, so the simulation performance of the entire system is close to that of FPGAs.

[0044] Therefore, by dividing the self-designed modules into the microprocessor and the mature designs into the FPGA, this invention enables the simulation iteration speed to be equivalent to that of the microprocessor, compared to using only the FPGA or microprocessor as a hardware simulator, and integrates the simulation performance to be close to that of the FPGA. Thus, this invention combines the advantages of the iteration speed of the microprocessor and the simulation performance of the FPGA.

[0045] As a preferred embodiment, S600 further includes: S630, optimizing the number of physical interconnect links between the various microprocessors.

[0046] Furthermore, the S630 includes the following steps:

[0047] S632, respectively obtain the first type of design module B assigned to the j-th microprocessor. j and the second type of design module F assigned to the i-th FPGA chip i B j Including the submodule D of D j Where j ranges from 1 to n, and i ranges from 1 to m. When partitioning modules, the partitioner prioritizes assigning D to the same microprocessor; when a microprocessor cannot accommodate the entire D, the partitioner divides D into multiple sub-modules and assigns them to multiple microprocessors. j Design module B of type I, assigned to the j-th microprocessor j .

[0048] S634, obtain F i Middle and D j Connecting Q elements cell = {cell1, cell2, ..., cell...} q ,…,cell Q}, cell q For F i Middle and D j The q-th element across the chip, where q ranges from 1 to Q. It should be noted that the element can be a sequential unit, such as a register, flip-flop, or latch, or a combinational logic unit, such as a gated clock.

[0049] S636, obtain the relationship between each element in the cell and D. j Number of connections Sum1 i and each component in F i The number of connections within Sum2 i , where cell q With D j Number of connections Sum1 i,q cell q In F i The number of connections within Sum2 i,q .

[0050] S638, when Sum1 i,q Greater than Sum2 i,q At that time, the cell q Reassigned to B j Inside. (The cell is placed inside.) q Reassigned to B, which has a larger number of connections. jInternally, it can reduce the number of cross-chip connections between FPGA and microprocessor, transforming inter-chip connections into intra-chip connections, shortening signal transmission paths, reducing latency on transmission paths, and further reducing failure rates and improving system reliability by reducing inter-chip connections.

[0051] As a preferred embodiment, when the number of physical interconnect links in the microprocessor or FPGA chip is less than the number of transmission signal lines, the corresponding physical interconnect links are multiplexed by a multiplexer. The method further includes: S300, configuring multiplexers for the ports of the microprocessor and FPGA chip respectively.

[0052] Optionally, each port is configured with a time-division multiplexer or a frequency-division multiplexer. Other multiplexers in the prior art fall within the scope of protection of this invention. It should be noted that ports at both ends of the same interconnection channel are configured with the same type of time-division multiplexer, while ports on different interconnection channels can be configured with different types of multiplexers as needed. Preferably, the multiplexer is a time-division multiplexer (TDM), which is used to transmit multiple signals via one interconnection channel.

[0053] In a preferred embodiment, S640 further includes: allocating time slot resources for the transmission signals between n first-type design modules and m second-type design modules; inserting a multiplexer into each physical interconnection link according to the time slot resources; and obtaining signal transmission configuration modules for the n first-type design modules and the m second-type design modules. Allocating physical interconnection links for each transmission signal through a routing algorithm clarifies the physical interconnection link corresponding to each transmission signal, and the allocation of time slot resources clarifies the time slot allocation rules among multiple transmission signals that need to be transmitted on the same physical interconnection link. Optionally, the allocated time slot resources are time-division multiplexing ratios. Preferably, the time-division multiplexing ratio k of the time-division multiplexer is such that k input signals are combined into one output signal for transmission.

[0054] In a preferred embodiment, the method further includes:

[0055] S700: Obtain k memories that are respectively connected to n microprocessors and m FPGA chips. Package the n microprocessors, m FPGA chips, and k memories through chip-to-chip integration, where 0 ≤ k ≤ K. This chip-to-chip integration packaging method can reduce the interconnection latency between microprocessors, FPGAs, and memories, thereby improving the performance of the heterogeneous simulation system provided by this invention.

[0056] As a preferred embodiment, the S700 is packaged in any of the following ways: interconnecting n microprocessors, m FPGA chips and k memories through a PCB; interconnecting n microprocessors, m FPGA chips and k memories through a silicon interposer; or interconnecting n microprocessors, m FPGA chips and k memories through vias in a silicon substrate.

[0057] As a preferred embodiment, the heterogeneous simulation system provided by the present invention may not be packaged as a whole. In this case, the n microprocessors, m FPGA chips and k memories are interconnected through PCB boards or physical connections, where 0≤k≤K.

[0058] Based on the same inventive concept as the above-described method embodiments, this invention also provides a heterogeneous hardware simulation system. The system includes an interconnected hardware emulator (Emu), K memories, a system compiler, and a server. The Emu includes N microprocessors and M FPGA chips. The compilation speed of the microprocessors is greater than that of the FPGA chips, but their simulation performance is lower. The N microprocessors, M FPGA chips, and K memories are interconnected by L physical interconnect links, where K≥0, N≥1, M≥1, and L≥1. The system compiler includes a partitioner, a router, n microprocessor compilers, and m FPGA chip compilers, as shown below. Figure 2 As shown, 0 < n ≤ N and 0 < m ≤ M; where:

[0059] A partitioner is used to partition a chip design unit (DUT) into n microprocessors and m FPGA chips, wherein the DUT includes a custom design module D to be debugged and corrected. D is partitioned into microprocessors to obtain a first type of design module of n microprocessors and a second type of design module of m FPGA chips.

[0060] A router is used to allocate physical interconnect links for the transmission signals between n first-class design modules and m second-class design modules, resulting in signal transmission configuration modules for the n first-class design modules and the m second-class design modules.

[0061] A microprocessor compiler is used to compile first-class design modules and their signal transmission configuration modules into first-class executable files for the microprocessor.

[0062] An FPGA chip compiler is used to compile second-type design modules and their signal transmission configuration modules into second-type executable files for FPGA chips.

[0063] The server stores n Class I executable files into n microprocessors and m Class II executable files into m FPGA chips. It then uses these executable files to control the n microprocessors and m FPGA chips for collaborative simulation and debugging. It should be noted that the server includes emulator runtime software to support the correct operation of the entire hardware simulation system.

[0064] In a preferred embodiment, the router is used to allocate physical interconnect links and time slot resources for transmission signals between n first-class design modules and m second-class design modules, and the system compiler further includes a multiplexer inserter for inserting time slot resources allocated according to each physical interconnect link into the multiplexer.

[0065] It should be noted that the inventive concept of this system embodiment is the same as that of the above method embodiment, and the technical features with the same name are the same, which will not be repeated here.

[0066] This heterogeneous hardware simulation system assigns self-designed modules to microprocessors and mature designs to FPGAs for simulation, thus combining the iteration speed of microprocessors with the simulation performance advantages of FPGAs.

[0067] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A heterogeneous hardware simulation method, characterized in that, The method includes: S200, acquire an interconnected hardware emulator Emu and K memories. The Emu includes N microprocessors and M FPGA chips. The compilation speed of the microprocessors is greater than that of the FPGA chips, but the simulation performance is lower than that of the FPGA chips. There are L physical interconnect links between the N microprocessors, M FPGA chips and K memories, where K≥0, N≥1, M≥1, and L≥1. S400, Obtain the chip design DUT, the DUT including the self-designed module D to be debugged and corrected; S600, the system compiler processes the DUT to obtain n Class I executable files corresponding to n microprocessors in Emu and m Class II executable files corresponding to m FPGA chips, where 0 < n ≤ N and 0 < m ≤ M; including: S620 divides the DUT into n microprocessors and m FPGA chips, where D is divided into microprocessors, resulting in a first type of design module of n microprocessors and a second type of design module of m FPGA chips. S640 allocates physical interconnection links for the transmission signals between n first-class design modules and m second-class design modules, resulting in signal transmission configuration modules for n first-class design modules and m second-class design modules; S660 compiles and generates a first-class executable file for the microprocessor based on each first-class design module and its signal transmission configuration module, resulting in n first-class executable files; and compiles and generates a second-class executable file for the FPGA chip based on each second-class design module and its signal transmission configuration module, resulting in m second-class executable files. The S800 stores n first-class executable files into n microprocessors and m second-class executable files into m FPGA chips. It controls the n microprocessors and m FPGA chips to perform collaborative simulation and debugging through the first-class and second-class executable files.

2. The method according to claim 1, characterized in that, The method further includes: The S300 provides separate multiplexers for the ports of the microprocessor and FPGA chip.

3. The method according to claim 1, characterized in that, in: S640 further includes: allocating time slot resources for the transmission signals between n first-class design modules and m second-class design modules, inserting a multiplexer into each physical interconnection link according to the time slot resources, and obtaining a signal transmission configuration module for n first-class design modules and a signal transmission configuration module for m second-class design modules.

4. The method according to claim 3, characterized in that, The multiplexer is a time-division multiplexer, and the time slot resource is the time-division multiplexing ratio.

5. The method according to claim 1, characterized in that, The microprocessor is a Boolean processor.

6. The method according to claim 1, characterized in that, The method further includes: S700: Obtain k memories that are respectively connected to n microprocessors and m FPGA chips, and package the n microprocessors, m FPGA chips and k memories through chip integration, where 0≤k≤K.

7. The method according to claim 6, characterized in that, The S700 is packaged using any of the following methods: n microprocessors, m FPGA chips, and k memories are interconnected via a PCB; n microprocessors, m FPGA chips, and k memories are interconnected through a silicon interposer; n microprocessors, m FPGA chips, and k memories are interconnected through vias in a silicon substrate.

8. The method according to claim 1, characterized in that, The n microprocessors, m FPGA chips, and k memory are interconnected via PCB boards or physical wiring, where 0 ≤ k ≤ K.

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