Multi-clock domain accurate stall and resume circuit and method for large scale fpga platforms

Abstract

The application discloses a kind of multi-clock domain accurate pause and recovery circuit and method for large-scale FPGA platform, the circuit of the present application includes digital clock management module, global gate clock, trigger time stamp counter, gate clock control logic, control and state register, N gate clock and its frequency divider controller and user logic module, global clock signal gclk after passing through digital clock management module one way input trigger time stamp counter, another way input global gate clock after again input to user logic module and N gate clock;Global gate clock is connected with gate clock control logic, and gate clock control logic is used to control the enable state of global gate clock based on control and state register.This application aims at the technical problem of synchronous breakpoint triggering and accurate on-site recovery under the condition of existing multi-FPGA complex, realizes the accurate pause and recovery of all clocks of multiple FPGA at the same time.

Description

Technical Field

[0001] This invention relates to the field of clock sampling technology for large-scale FPGA verification, specifically to a multi-clock domain precise pause and recovery circuit and method for large-scale FPGA platforms. Background Technology

[0002] FPGA simulation verification is a crucial method for large-scale chip verification. Using an FPGA simulation verification platform for system function verification and fault diagnosis can assist in the rapid location and repair of faults during the system verification phase, enabling the early detection and elimination of deep-seated design flaws in the chip. Furthermore, it allows for the observation and recording of data transmission status between various functional components within the system. This is essential for understanding the functional and performance characteristics of the entire system, conducting system analysis and optimization design, and providing a user-friendly interface and experience.

[0003] With the continuous improvement of high-performance chip performance, hundreds of billions or even more transistors, equivalent to tens of billions of gates, can be implemented in a single chip package. For large-scale chip verification tasks with tens of billions of gates, it is often necessary to divide a large-capacity chip design and run it on multiple FPGAs. The FPGA simulation verification platform interconnects multiple large-capacity FPGAs through specific connection relationships. The user's large-capacity chip uses a logic block mapping method to distribute and map the hardware logic behavior onto the FPGA array. Through distributed parallel collaborative simulation of multiple FPGAs, the actual behavior of the whole chip or whole machine is simulated, and functional simulation and performance statistical analysis are carried out. On the other hand, large-scale FPGA prototype verification systems include multiple nodes, each containing multiple clock signal domains. Sampling signals across clock domains is prone to metastability, data omissions, and other problems, leading to data acquisition errors. Furthermore, because the time scales of sampling in different clock domains are different, the final recovered cross-clock domain signals often deviate from the actual system operation.

[0004] Therefore, how to achieve precise pause and recovery of signals across clock domains, ensure the synchronization and accuracy of sampling, breakpoint triggering and recovery, and waveform recovery, and achieve precise pause and recovery of all clocks of multiple FPGAs at the same moment is a key problem that needs to be solved in large-scale FPGA verification. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a multi-clock domain precise pause and recovery circuit and method for large-scale FPGA platforms, which addresses the above-mentioned problems in the existing multi-FPGA complex conditions. The present invention aims to solve the problem of synchronous breakpoint triggering and precise field recovery technology, and realize the precise pause and recovery of all clocks of multiple FPGAs at the same time.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform includes a digital clock management module, a global gated clock, a trigger timestamp counter, gated clock control logic, a control and status register, N gated clocks and their frequency dividers, and a user logic module. The global clock signal gclk, synchronized across multiple FPGAs, enters the multi-clock domain precise pause and recovery circuit of each FPGA. After passing through the digital clock management module, it is split into two paths: one path inputs the trigger timestamp counter to generate a timestamp trig_cnt for global synchronization triggering and recovery; the other path inputs the global gated clock and then to the user logic module and the N gated clocks. The enable terminal en of the global gated clock is connected to the gated clock control logic, which controls the enable state of the global gated clock based on the register value in the control and status register.

[0008] Optionally, the registers in the control and status register include a breakpoint trigger timestamp register `trig_ts`, a breakpoint recovery timestamp register `rec_ts`, and a debug status register `trig_st`. The gated clock control logic controls the enable state of the global gated clock based on the register values ​​in the control and status register, including: when the debug status register `trig_st` is set to the breakpoint trigger state, the gated clock control logic starts the breakpoint trigger clock comparator to compare the values ​​of the breakpoint trigger timestamp register `trig_ts` and the timestamp `trig_cnt`. If... If the two are equal, the gated clock control logic sends an enable signal st to turn off the global gated clock. When the debug status register trig_st is set to the end of the breakpoint debugging state and enter the breakpoint recovery state, the gated clock control logic starts the breakpoint recovery clock comparator to compare the values ​​of the breakpoint recovery timestamp register rec_ts and the timestamp trig_cnt. If the two are equal, the gated clock control logic turns off the enable signal st to turn on the global gated clock, so that the global gated clock is reopened, the timestamp continues to count from the pause time, and the FPGA resumes operation from the breakpoint.

[0009] Optionally, the N gated clocks and their frequency divider controllers include N gated clocks and N frequency divider controllers. The N gated clocks are respectively denoted as the first gated clock, the second gated clock, ..., the Nth gated clock, and the N frequency divider controllers are respectively denoted as the first frequency divider controller, the second frequency divider controller, ..., the Nth frequency divider controller. The enable signal ce generated by any i-th frequency divider controller... i Output to the i-th gated clock, so that the i-th gated clock is activated according to the enable signal ce. i And the global clock signal gclk generates the frequency-divided clock clk. i .

[0010] Optionally, the i-th frequency divider controller generates an enable signal ce. i The counter cnt outputs an enable signal ce every M clock cycles for counting. i , where M is the specified number of cycles.

[0011] Optionally, the counter cnt-based counting outputs an enable signal ce every M clock cycles. i The steps include: Step S101, initializing the counter cnt; Step S102, based on the counting of the counter cnt, outputting the enable signal ce in a cycle every M clock cycles. i When 1 ≤ cnt ≤ N, output enable signal ce. i =1; When N+1≤cnt≤M, output enable signal ce i =0; Step S103, when cnt>M, cnt=cnt%M, go to step S102, where "%" is the modulo operator.

[0012] Optionally, the i-th gated clock is determined according to the enable signal ce. i And the global clock signal gclk generates the frequency-divided clock clk. i Includes: when the enable signal ce i When the value is 1, the i-th gated clock is turned on, and the output clock clk is turned on. i The signal value is the same as the global clock signal gclk; when the enable signal ce... i When the value is 0, the i-th gate clock is turned off, and the output clock clk is turned off. i The signal value is 0.

[0013] Optionally, the N gated clocks are latch- / register-based gated clocks, and the enable signal ce is first enabled on the falling edge of the global clock signal gclk for any i-th gated clock. i The delay enable signal ce_r is obtained by registering one clock cycle, and then the delay enable signal ce_r and the global clock signal gclk are ANDed to generate the output clock clk. i .

[0014] Furthermore, the present invention also provides an FPGA platform, including a clock synchronization module and multiple FPGAs. The clock synchronization module is used to generate a global clock signal gclk. Each FPGA is provided with the aforementioned multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms. The clock synchronization module is connected to the multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms in each FPGA.

[0015] Furthermore, this invention also provides an application method for multi-clock domain precise pause and recovery circuits in large-scale FPGA platforms, including:

[0016] S201, determine the clock domain and its required clock signal in each FPGA respectively;

[0017] S202, for each FPGA, determine and set the enable state of N frequency divider controllers according to the clock signals required by each clock domain in the FPGA, so that the output clock of the N frequency divider controllers is consistent with the clock signal required by the FPGA;

[0018] S203 outputs a global clock signal gclk through the clock synchronization module that is connected to all FPGAs. This global clock signal gclk is then used by the multi-clock domain precision pause and recovery circuits in each FPGA to generate the clock signals required by each clock domain.

[0019] Optionally, step S203 further includes, when it is necessary to shut down the clock signals for multiple clock domains of each FPGA to achieve a pause, controlling the clock synchronization module commonly connected to each FPGA to stop outputting the global clock signal gclk, thereby synchronously shutting down the clock signals of all clock domains in all FPGAs; after the pause is achieved, when it is necessary to turn on the clock signals for multiple clock domains of each FPGA to achieve recovery, controlling the clock synchronization module commonly connected to each FPGA to resume outputting the global clock signal gclk, thereby synchronously restoring the clock signals of all clock domains in all FPGAs.

[0020] Compared with the prior art, the present invention has the following main advantages:

[0021] 1. This invention provides a multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms. It generates an enable signal through a frequency divider controller, which then periodically shuts down a portion of the global clock signal gclk, thereby generating clock signals for different domains. This is equivalent to the entire system having only a master clock. Therefore, shutting down the master clock simultaneously shuts down all the frequency divider clocks, simplifying the clock generation logic.

[0022] 2. This invention designs a complex multi-condition triggering mechanism through control and status registers and gated clock control logic, and uses a global clock and N frequency-division gated clock modules to achieve precise clock gating and recovery, enabling precise pause and recovery of cross-clock domain signals of multiple FPGAs at the same time, ensuring the synchronization and accuracy of sampling, breakpoint triggering and recovery, and waveform recovery. Attached Figure Description

[0023] Figure 1This is a schematic diagram of the structure of the multi-clock domain precise pause and recovery circuit in an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the gated clock circuit in an embodiment of the present invention. Detailed Implementation

[0025] like Figure 1 As shown, the large-scale FPGA platform in this embodiment is specifically an FPGA simulation and verification platform. The FPGA simulation and verification platform contains P FPGAs, each FPGA employing the same multi-clock domain precise pause and recovery circuit based on a gated clock. The P FPGAs are denoted as FPGA1, ..., FPGA2. k ,…,FPGA P 1 ≤ k ≤ P, where k and P are natural numbers. Let M be the frequency of the global master clock gclk, and let clk be the frequency of the i-th divided clock. i The frequencies are N, M>N, global master clock gclk and i-th divided clock clk. i The frequency division ratio is M / N, 1≤i≤N, where i, M, and N are all natural numbers. This embodiment of the multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform includes a Digital Clock Manager (DCM), a global gated clock, a trigger timestamp counter, gated clock control logic, a Control and State Register (CSR), N gated clocks and their frequency dividers, and a user logic module. The global clock signal gclk, synchronized across multiple FPGAs, enters the multi-clock domain precise pause and recovery circuit of each FPGA. After passing through the DCM, it is split into two paths: one path inputs the trigger timestamp counter to generate the timestamp trig_cnt for global synchronization triggering and recovery; the other path inputs the global gated clock and then to the user logic module and the N gated clocks. The enable terminal en of the global gated clock is connected to the gated clock control logic, which controls the enable state of the global gated clock based on the register value in the Control and State Register. To address the existing problems of synchronous breakpoint triggering and precise field recovery under complex conditions in multiple FPGAs, this embodiment adopts a global triggering synchronization network for the multi-clock domain precise pause and recovery circuit of a large-scale FPGA platform. At the same time, it designs a multi-condition complex triggering mechanism, utilizes precise clock gating and recovery technology and a dedicated interconnection network to trigger command broadcasting network, so as to achieve precise pause and recovery of all clocks of multiple FPGAs at the same time.

[0026] like Figure 1As shown, the registers in the control and status register include the breakpoint trigger timestamp register `trig_ts`, the breakpoint recovery timestamp register `rec_ts`, and the debug status register `trig_st`. The gated clock control logic controls the enable state of the global gated clock based on the register values ​​in the control and status register. This includes: when the debug status register `trig_st` is set to the breakpoint trigger state, the gated clock control logic starts the breakpoint trigger clock comparator to compare the values ​​of the breakpoint trigger timestamp register `trig_ts` and the timestamp `trig_cnt`. If the two... If the values ​​of the two are equal, the gated clock control logic sends an enable signal st to turn off the global gated clock. When the debug status register trig_st is set to the end of the breakpoint debugging state and enter the breakpoint recovery state, the gated clock control logic starts the breakpoint recovery clock comparator to compare the values ​​of the breakpoint recovery timestamp register rec_ts and the timestamp trig_cnt. If the two are equal, the gated clock control logic turns off the enable signal st to turn on the global gated clock, so that the global gated clock is reopened, the timestamp continues to count from the pause time, and the FPGA resumes operation from the breakpoint.

[0027] like Figure 1 As shown, the N gated clocks and their frequency dividers include N gated clocks and N frequency dividers. The N gated clocks are denoted as the first gated clock, the second gated clock, ..., the Nth gated clock, and the N frequency dividers are denoted as the first frequency divider, the second frequency divider, ..., the Nth frequency divider. The enable signal ce generated by any i-th frequency divider... i Output to the i-th gated clock, so that the i-th gated clock is activated according to the enable signal ce. i And the global clock signal gclk generates the frequency-divided clock clk. i .

[0028] In this embodiment, any i-th frequency divider controller generates an enable signal ce. i The counter cnt outputs an enable signal ce every M clock cycles for counting. i , where M is the specified number of cycles.

[0029] In this embodiment, the enable signal ce is output cyclically every M clock cycles based on the counter cnt. i The steps include: Step S101, initializing the counter cnt; Step S102, based on the counting of the counter cnt, outputting the enable signal ce in a cycle every M clock cycles. i When 1 ≤ cnt ≤ N, output enable signal ce. i =1; When N+1≤cnt≤M, output enable signal ce i=0; Step S103, when cnt>M, cnt=cnt%M, go to step S102, where "%" is the modulo operator.

[0030] In this embodiment, the i-th gated clock is based on the enable signal ce. i And the global clock signal gclk generates the frequency-divided clock clk. i Includes: when the enable signal ce i When the value is 1, the i-th gated clock is turned on, and the output clock clk is turned on. i The signal value is the same as the global clock signal gclk; when the enable signal ce... i When the value is 0, the i-th gate clock is turned off, and the output clock clk is turned off. i The signal value is 0.

[0031] like Figure 2 As shown, the N gated clocks are latch- / register-based gated clocks, and for any i-th gated clock, the enable signal ce is first enabled on the falling edge of the global clock signal gclk. i The delay enable signal ce_r is obtained by registering one clock cycle, and then the delay enable signal ce_r and the global clock signal gclk are ANDed to generate the output clock clk. i . Figure 2 In the diagram, the device on the left represents a register, where D is the input terminal used to input the enable signal ce (referring to the enable signal of any gated clock), and Q is the output terminal used to output the delay enable signal ce_r; the device on the right represents AND logic, used to perform AND operations, where "&" represents the AND operation.

[0032] like Figure 1 As shown, this embodiment also provides an FPGA platform, including a clock synchronization module and multiple FPGAs. The clock synchronization module is used to generate a global clock signal gclk. Each FPGA is equipped with the multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms described above. The clock synchronization module is connected to the multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms in each FPGA.

[0033] This embodiment also provides an application method for the aforementioned multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms, including:

[0034] S201, determine the clock domain and its required clock signal in each FPGA respectively;

[0035] S202, for each FPGA, determine and set the enable state of N frequency divider controllers according to the clock signals required by each clock domain in the FPGA, so that the output clock of the N frequency divider controllers is consistent with the clock signal required by the FPGA;

[0036] S203 outputs a global clock signal gclk through the clock synchronization module that is connected to all FPGAs. This global clock signal gclk is then used by the multi-clock domain precision pause and recovery circuits in each FPGA to generate the clock signals required by each clock domain.

[0037] In step S203 of this embodiment, when it is necessary to shut down the clock signals for multiple clock domains of each FPGA to achieve a pause, the clock synchronization module connected to each FPGA is controlled to stop outputting the global clock signal gclk, thereby synchronously shutting down the clock signals of all clock domains in all FPGAs. After the pause is achieved, when it is necessary to turn on the clock signals for multiple clock domains of each FPGA to achieve recovery, the clock synchronization module connected to each FPGA is controlled to resume outputting the global clock signal gclk, thereby synchronously restoring the clock signals of all clock domains in all FPGAs. This enables precise pause and recovery of cross-clock domain signals of multiple FPGAs at the same time, ensuring the synchronization and accuracy of sampling, breakpoint triggering and recovery, and waveform recovery.

[0038] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms, characterized in that, The system includes a digital clock management module, a global gated clock, a trigger timestamp counter, gated clock control logic, a control and status register, N gated clocks and their frequency dividers, and a user logic module. The global clock signal gclk, synchronized across multiple FPGAs, enters the multi-clock domain precise pause and recovery circuit of each FPGA. After passing through the digital clock management module, it is split into two paths: one path inputs the trigger timestamp counter to generate the timestamp trig_cnt for global synchronization triggering and recovery; the other path inputs the global gated clock and then to the user logic module and the N gated clocks. The enable terminal en of the global gated clock is connected to the gated clock control logic, which controls the enable state of the global gated clock based on the register values ​​in the control and status register. The registers in the control and status register include the breakpoint trigger timestamp register trig_ts, the breakpoint recovery timestamp register rec_ts, and the debug status register. The gated clock control logic, based on the register values ​​in the control and status registers, controls the enable state of the global gated clock, including: when the debug status register `trig_st` is set to the breakpoint trigger state, the gated clock control logic starts the breakpoint trigger clock comparator to compare the values ​​of the breakpoint trigger timestamp register `trig_ts` and the timestamp `trig_cnt`. If they are equal, the gated clock control logic issues an enable signal `st` to turn off the global gated clock; when the debug status register `trig_st` is set to the breakpoint recovery state after the breakpoint debugging state ends, the gated clock control logic starts the breakpoint recovery clock comparator to compare the values ​​of the breakpoint recovery timestamp register `rec_ts` and the timestamp `trig_cnt`. If they are equal, the gated clock control logic disables the enable signal `st` to turn on the global gated clock, so that the global gated clock is reopened, the timestamp continues counting from the pause time, and the FPGA resumes operation from the breakpoint.

2. The multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms according to claim 1, characterized in that, The N gated clocks and their frequency divider controllers include N gated clocks and N frequency divider controllers. The N gated clocks are denoted as the first gated clock, the second gated clock, ..., the Nth gated clock, and the N frequency divider controllers are denoted as the first frequency divider controller, the second frequency divider controller, ..., the Nth frequency divider controller. The enable signal ce generated by any i-th frequency divider controller... i Output to the i-th gated clock, so that the i-th gated clock is activated according to the enable signal ce. i And the global clock signal gclk generates the frequency-divided clock clk. i .

3. The multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms according to claim 2, characterized in that, The arbitrary i-th frequency divider controller generates an enable signal ce. i The counter cnt outputs an enable signal ce every M clock cycles for counting. i , where M is the specified number of cycles.

4. The multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms according to claim 3, characterized in that, The counter-based counting (cnt) outputs an enable signal (ce) cyclically every M clock cycles. i include: Step S101: Initialize counter cnt; Step S102: Based on the counter cnt, output enable signal ce every M clock cycles as one cycle. i When 1 ≤ cnt ≤ N, output enable signal ce. i =1; When N+1≤cnt≤M, output enable signal ce i =0; Step S103: When cnt > M, cnt = cnt%M, then proceed to step S102, where "%" is the modulo operator.

5. The multi-clock domain precise pause and recovery circuit for large-scale FPGA platforms according to claim 2, characterized in that, The i-th gated clock is based on the enable signal ce i And the global clock signal gclk generates the frequency-divided clock clk. i Includes: when the enable signal ce i When the value is 1, the i-th gated clock is turned on, and the output clock clk is turned on. i The signal value is the same as the global clock signal gclk; when the enable signal ce... i When the value is 0, the i-th gate clock is turned off, and the output clock clk is turned off. i The signal value is 0.

6. The multi-clock-domain precise pause and recovery circuit for large-scale FPGA platforms according to claim 5, characterized in that, The N gated clocks are latch / register-based gated clocks, and for any i-th gated clock, the enable signal ce is first enabled on the falling edge of the global clock signal gclk. i The delay enable signal ce_r is obtained by registering one clock cycle, and then the delay enable signal ce_r and the global clock signal gclk are ANDed to generate the output clock clk. i .

7. An FPGA platform, comprising a clock synchronization module and multiple FPGAs, wherein the clock synchronization module is used to generate a global clock signal gclk, and each FPGA is provided with a multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform as described in any one of claims 1 to 6, wherein the clock synchronization module is connected to the multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform in each FPGA respectively.

8. An application method for a multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform as described in any one of claims 1 to 6, characterized in that, include: S201, determine the clock domain in each FPGA and the required clock signal; S202, for each FPGA, determine and set the enable state of N frequency divider controllers according to the clock signals required by each clock domain in the FPGA, so that the output clock of the N frequency divider controllers is consistent with the clock signal required by the FPGA; S203 outputs a global clock signal gclk through the clock synchronization module that is connected to all FPGAs. This global clock signal gclk is then used by the multi-clock domain precision pause and recovery circuits in each FPGA to generate the clock signals required by each clock domain.

9. The application method of the multi-clock domain precise pause and recovery circuit for a large-scale FPGA platform according to claim 8, characterized in that, Step S203 further includes, when it is necessary to shut down the clock signals for multiple clock domains of each FPGA to achieve a pause, controlling the clock synchronization module that is commonly connected to each FPGA to stop outputting the global clock signal gclk, thereby synchronously shutting down the clock signals of all clock domains in all FPGAs; after the pause is achieved, when it is necessary to turn on the clock signals for multiple clock domains of each FPGA to achieve recovery, controlling the clock synchronization module that is commonly connected to each FPGA to resume outputting the global clock signal gclk, thereby synchronously restoring the clock signals of all clock domains in all FPGAs.

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