Clock generator and display device

Abstract

Disclosed is a clock generator and display device. The clock generator includes an oscillator configured to output a reference clock signal to a first line; an EMI reduction controller configured to generate an EMI reduction signal that cancels the reference clock signal and output the EMI reduction signal to a second line; and a driving clock generator configured to generate an operation clock signal based on the reference clock signal, the operation clock signal being one of the reference clock signal input through the first line and the EMI reduction signal input through the second line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0110036, filed on August 31, 2022, the entire contents of which are expressly incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to a clock generator, and more specifically, for example, but not limited to, a clock generator including an EMI reduction controller and a driving clock generator, and a display device including the clock generator. Background Technology

[0004] As display device performance improves, the amount of data to be processed increases. Display devices can operate at high speeds to process large amounts of data, thereby providing high-resolution, high-quality images.

[0005] To process data at high speed, a high-frequency clock signal must be generated, and specified operations must be performed based on the generated clock signal. However, the periodically generated high-frequency clock signal can cause electromagnetic interference (EMI). EMI can cause malfunctions in peripheral circuits and devices, therefore methods to reduce EMI from display devices are needed.

[0006] The description provided in the Background section should not be assumed to be prior art simply because it is mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention. Summary of the Invention

[0007] The inventors have recognized the foregoing requirements and other limitations associated with the prior art. Therefore, this disclosure relates to a clock generator and a display device including the clock generator, which substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0008] The purpose of this disclosure is to provide a clock generator capable of reducing the impact of EMI caused by high-frequency clock signals and a display device including the clock generator.

[0009] Other advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to those skilled in the art upon studying the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0010] To achieve these objectives and other advantages, and in accordance with the purposes of this disclosure, as implemented and broadly described herein, the clock generator includes: an oscillator configured to output a reference clock signal to a first line; an EMI reduction controller configured to generate an EMI reduction signal that cancels out the reference clock signal and output the EMI reduction signal to a second line; and a drive clock generator configured to generate an operating clock signal based on the reference clock signal, the operating clock signal being one of the reference clock signal input through the first line and the EMI reduction signal input through the second line.

[0011] The first line and the second line may each have a serrated structure, and the serrated structure of the first line and the serrated structure of the second line face each other and intersect.

[0012] The clock generator may also include a delay compensator configured to synchronize the phase of the reference clock signal and the EMI reduction signal.

[0013] The driving clock generator may include: multiple multiplexers connected in a tree structure to a first line and a second line, the multiple multiplexers being configured to output a reference clock signal applied to the first line; and multiple flip-flops connected to the multiple multiplexers respectively, the multiple flip-flops being configured to generate a driving clock signal based on the reference clock signal.

[0014] The EMI reduction signal may include an inverted OSC signal for canceling EMI via a reference clock signal and a ground signal for shielding the reference clock signal.

[0015] The EMI reduction controller may include: an inverter configured to invert a reference clock signal to generate an inverted OSC signal; and an output circuit configured to output a selected one of the inverted OSC signal and a ground signal.

[0016] The first and second lines can be configured to have a uniform distance between them.

[0017] The first line may include a first protrusion extending into a region adjacent to the second line, the second line may include a second protrusion extending into a region adjacent to the first line, and the first and second protrusions may be arranged alternately.

[0018] The first protrusion and the second protrusion can be arranged such that the distance between the end of each first protrusion and the end of a corresponding second protrusion is equal to or greater than the vertical distance between the end of each first protrusion and the second line.

[0019] The distance between the end of each first protrusion and the end of a corresponding second protrusion can be the distance between the center point of the end of each first protrusion and the center point of the end of a corresponding second protrusion.

[0020] Each first protrusion and each second protrusion can be formed into a ring shape.

[0021] In another aspect of this disclosure, the display device includes: a display panel; and a timing controller integration IC (TMIC) configured to convert an externally input image signal and supply image data to the display panel, wherein each of the TMICs includes: an oscillator configured to output a reference clock signal to a first line; an EMI reduction controller configured to generate an EMI reduction signal that cancels out the reference clock signal and output the EMI reduction signal to a second line; and a drive clock generator configured to generate an operating clock signal for supplying image data to the display panel based on the reference clock signal, the operating clock signal being one of the reference clock signal input through the first line and the EMI reduction signal input through the second line.

[0022] The display panel may include multiple pixels connected to data lines and gating lines, and the display device may also include a gating driver IC configured to supply gating signals to the gating lines.

[0023] The first and second lines can each have a serrated structure, with the serrated structures of the first and second lines facing each other and intersecting.

[0024] Each of the TMICs may also include a cascaded synchronization controller configured to synchronize the operating clock signal.

[0025] One of the TMICs can be set as the master TMIC, and the other TMICs in the TMIC can be set as slave TMICs, and the cascaded synchronization controller can be configured to synchronize the operating clock signal of the slave TMIC with the operating clock signal of the master TMIC.

[0026] One of the TMICs can be set as the master TMIC, and the master TMIC can generate control signals for controlling the gating driver IC based on the reference clock signal, and can apply control signals to the gating driver IC.

[0027] The TMIC may also include a delay compensator configured to synchronize the phase of the reference clock signal and the EMI reduction signal.

[0028] The EMI reduction signal may include an inverted OSC signal for canceling EMI via a reference clock signal and a ground signal for shielding the reference clock signal.

[0029] The first line and the second line can be configured to have a uniform distance between them. The first line can include a first protrusion extending into a region adjacent to the second line, and the second line can include a second protrusion extending into a region adjacent to the first line. The first protrusion and the second protrusion can be arranged alternately.

[0030] The first protrusion and the second protrusion can be arranged such that the distance between the end of each first protrusion and the end of a corresponding second protrusion is equal to or greater than the vertical distance between the end of each first protrusion and the second line.

[0031] The distance between the end of each first protrusion and the end of a corresponding second protrusion can be the distance between the center point of the end of each first protrusion and the center point of the end of a corresponding second protrusion.

[0032] Each first protrusion and each second protrusion can be formed into a ring shape.

[0033] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure.

[0034] According to embodiments of this disclosure, the impact of EMI caused by OSC signals can be reduced.

[0035] According to embodiments of this disclosure, the EMI reduction effect can be maximized due to the coupling effect between the two lines.

[0036] It should be understood that, in addition to the effects of this disclosure as described above, those skilled in the art will clearly understand other advantages and features of this disclosure from the foregoing description. Attached Figure Description

[0037] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0038] Figure 1 This is a view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0039] Figure 2 It is shown Figure 1 A view of the construction of the data driver IC TMIC;

[0040] Figure 3 and Figure 4 It is shown Figure 2The EMI reduction controller's construction and a view of the input and output signal relationship;

[0041] Figure 5 and Figure 6 It is shown Figure 2 The construction of the delay compensator and a view of the relationship between the input and output signals;

[0042] Figure 7 and Figure 8 It is shown Figure 2 A view showing the construction of the multiplexer and the relationship between its input and output signals;

[0043] Figure 9 This is a view illustrating the EMI cancellation principle using the arrangement of OSC signal lines and EMI reduction signal lines;

[0044] Figures 10 to 13 This is a view illustrating a design method for the first line L1 and the second line L2 according to a first embodiment of the present disclosure;

[0045] Figure 14 This is a view illustrating a radial pattern based on the shape of the protrusions formed on the line; and

[0046] Figure 15 , Figure 16 and Figure 17 This is a view illustrating a design method for the first line L1 and the second line L2 according to a second embodiment of the present disclosure.

[0047] Throughout the accompanying drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0048] The advantages, features, and implementation methods of this disclosure will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and can be implemented in various different forms. These embodiments are provided only to complete this disclosure and to fully inform those skilled in the art of its category. This disclosure is limited only by the category of the claims and their equivalents.

[0049] In the accompanying drawings used to explain exemplary embodiments of this disclosure, shapes, dimensions, areas, ratios, angles, and quantities are shown by way of example and are therefore not intended to limit the disclosure. Throughout the specification, the same reference numerals denote the same constituent elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted or briefly provided to avoid unnecessarily obscuring the subject matter. Unless used with terms such as “only,” the terms “comprising,” “including,” “having,” “containing,” “constituting,” “made of,” “formed by,” “composed of,” and “consisting of” as used herein do not exclude the presence or addition of other elements. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0050] In the explanation of the components, even if there is no explicit description, the components are interpreted as including the error range or tolerance range.

[0051] When describing positional relationships, for example, when using terms such as "on," "above," "above," "below," "next to," "below," "under," "near," "close to," "adjacent to," "on the side," "near" to describe the positional relationship between two components, one or more other components may be located between the two components unless they are used with terms such as "closely," "directly," or "tightly."

[0052] Spatially relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” etc., may be used in this document to describe the relationship between one element or feature and another element or feature as illustrated in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if an element in the figure is inverted, an element described as “below” or “below” other elements or features would be oriented as “above” other elements or features. Thus, the exemplary term “below” can include both lower and upper orientations. Similarly, the exemplary terms “above” or “above” can include both upper and lower orientations.

[0053] When describing temporal relationships, terms such as “after,” “following,” “next,” “following,” “before,” etc., can include situations where two events are not consecutive, unless explicitly stated that terms such as “immediately after,” “exactly,” or “directly” are used.

[0054] Although the terms "first," "second," "A," "B," "a," "b," etc., can be used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, the "first element" described below can be the "second element" within the technical concept of this disclosure.

[0055] Furthermore, when describing components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used herein. Each of these terms is not intended to define the nature, order, or sequence of the respective component, but only to distinguish the respective component from other components. In the description of a structural element or layer being “connected,” “joined,” “adheded,” or “joined” to another structural element or layer, it is generally understood that the other structural element or layer may be directly or indirectly “connected,” “joined,” “adheded,” or “joined” to that structural element or layer.

[0056] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, "at least one of the first, second, and third items" means a combination of all items drawn from two or more of the first, second, and third items, as well as the first, second, or third item.

[0057] As used herein, the term "device" can refer to a display device that includes a display panel and a driver for driving the display panel. Examples of display devices may include electroluminescent display devices, liquid crystal display devices, etc. Additionally, examples of devices may include laptops, televisions, computer monitors, automotive devices, wearable devices and automotive equipment devices, as well as assemblies of electronic devices (or equipment) or assemblies (or devices) that include EL, LCD, etc., as complete products or end products, such as mobile electronic devices like smartphones or tablets, but embodiments of this disclosure are not limited thereto.

[0058] For ease of description, the size and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the size and thickness of the components shown.

[0059] Features of the various aspects of this disclosure may be linked or combined with each other, either partially or entirely, and may interoperate with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. The aspects of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0060] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description of the present disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted where such descriptions might make the subject matter of the disclosure considerably unclear.

[0062] Figure 1 This is a view illustrating a display device according to an exemplary embodiment of the present disclosure. All components of each display device according to all embodiments of the present disclosure are operatively connected and configurable.

[0063] Reference Figure 1 The display device according to the exemplary embodiments of this disclosure can be implemented by an electroluminescent display device, a liquid crystal display device, etc., and includes a display panel PNL configured to display an image, data driver IC TMICs (e.g., IC TMIC1 to TMIC4), a gating driver IC GIC, and a system IC SIC. However, the embodiments of this disclosure are not limited to this. For example, the number of data driver IC TMICs can be n, where n is an integer greater than or equal to 1, and when n is greater than 1, one data driver IC TMIC is set as the master data driver IC TMIC, while the other data driver IC TMICs are set as slave data driver IC TMICs. The gating driver GIC and the data driver TMICs are disposed in the non-display area NA. However, the embodiments are not limited to this. For example, at least one of the gating driver GICs and the data driver TMICs can be disposed separately from the display panel PNL and connected to the display panel PNL. Alternatively, at least a portion of at least one of the gating driver GICs and the data driver TMICs can be disposed in the display area AA. In addition, although the gating driver GIC and the data driver TMIC are illustrated as being located on one side of the display panel PNL, at least one of the gating driver GIC and the data driver TMIC can be located on both sides of the display panel PNL.

[0064] The display panel PNL, data driver ICs TMIC1 to TMIC4, gating driver IC GIC, and system IC SIC can be disposed on a substrate (not shown). The substrate may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), or limonene copolymer, cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, and polystyrene (PS), but embodiments of this disclosure are not limited thereto.

[0065] The display panel PNL can be provided with multiple data lines DL and multiple gating lines GL. Pixels can be arranged in a matrix at the intersections of the signal lines GL and DL. Pixels forming the same horizontal line are connected to the same gating line GL, and pixels forming the same vertical line are connected to the same data line DL. Specifically, a pixel P receives gating signals from the gating driver GIC via the gating line GL, receives data signals from the data driver TMIC via the data line DL, and receives a high-potential driving voltage EVDD and a low-potential driving voltage EVSS from the power supply. Each pixel PIX can be implemented by a light-emitting unit including a light-emitting diode or a liquid crystal unit including a liquid crystal layer to display an image, but the embodiments disclosed herein are not limited to these.

[0066] The system IC SIC can provide image signals from external input and control signals (e.g., vertical synchronization signal Vsync and horizontal synchronization signal Hsync) to the data driver ICs TMIC1 to TMIC4.

[0067] Each of the data driver ICs TMIC1 to TMIC4 is implemented by a driver IC that combines the functions of a timing controller and a data driver. Therefore, the data driver ICs TMIC1 to TMIC4 can generate a data control signal DCS for controlling the supply of analog image signals to the display panel PNL based on control signals (e.g., vertical synchronization signal Vsync and horizontal synchronization signal Hsync) provided from the system IC SIC, and generate a gating control signal GCS for controlling the gating driver IC GIC. Here, the data control signal DCS may include a source start pulse SSP, a source sampling clock SSC, and a source output enable SOE. The gating control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, and a gate output enable GOE. However, the data control signal DCS and the gating control signal GCS according to embodiments of this disclosure are not limited thereto. The data driver ICs TMIC1 to TMIC4 convert the image data provided from the system IC SIC into data voltages as analog signals, and supply the data voltages to the data line DL based on the generated data control signals.

[0068] Each of the data driver ICs TMIC1 through TMIC4 includes an independently mounted oscillator to generate various control signals. Each of the data driver ICs TMIC1 through TMIC4 includes a clock generator configured to generate various necessary control signals using an oscillation signal generated by the oscillator mounted therein. To synchronize the operation of the data driver ICs TMIC1 through TMIC4, one of the data driver ICs, ICTMIC, is set as the master data driver IC, while the other data driver ICs are set as slave data driver ICs, ICTMICs. The master data driver IC can perform control to synchronize the slave data driver ICs and can apply strobe control signals to the gating driver IC GIC to control the operation of the gating driver IC GIC.

[0069] The gate driver IC (GIC) generates gate drive signals based on the gate control signals. The GIC sequentially supplies gate drive signals to the gate lines GL, driving one gate line GL per horizontal cycle. The gate drive signals select the horizontal line for the data voltage to be written and enable the pixel connected to the corresponding horizontal line GL. As previously described, the main data driver IC controls the operation of the GIC. In this document, as an example, the GIC can be implemented as an in-panel gate (GIP) type and can be directly disposed on the substrate of the display panel PNL. Alternatively, the GIC can be integrated and disposed on the display panel PNL, or each GIC can be implemented using a chip-on-film (COF) method where components are mounted on a film connected to the display panel PNL.

[0070] Figure 2 It is shown Figure 1 A view of the clock generator for each data driver IC TMIC. The display device includes multiple data driver IC TMICs, with one data driver IC TMIC designated as the master data driver IC TMIC and the others designated as slave data driver IC TMICs to synchronize the operation of data driver IC TMICs 1 through 4. The multiple data driver ICs 1 through 4 can be connected to each other in a cascaded manner for sequential operation of the units. Therefore, the first data driver IC TMIC 1 can be designated as the master data driver IC TMIC. The clock generators included in data driver ICs 1 through 4 are structurally identical; therefore, the construction of the master data driver IC TMIC_Master will be described representatively.

[0071] Reference Figure 2 The main data driver IC TMIC_Master includes an oscillator 110, a delay compensator 130, an EMI (electromagnetic interference) reduction controller 120, a drive clock generator 200, and a cascaded synchronization controller 140.

[0072] Oscillator 110 can output an oscillation clock (OSC) signal with a fixed frequency. The OSC signal is output as a high-frequency signal with a frequency of tens of MHz and is used as a reference clock when generating timing for driving the display device. The OSC signal is input to each of EMI reduction controller 120 and delay compensator 130.

[0073] The EMI reduction controller 120 outputs an EMI reduction signal capable of reducing the EMI of the OSC signal. The EMI reduction signal may include an inverted OSC signal and a ground signal; the inverted OSC signal is the inverse of the OSC signal. The EMI reduction controller 120 selectively supplies either the inverted OSC signal or the ground signal according to predetermined setting information.

[0074] The delay compensator 130 compensates for the phase delay of the OSC signal, causing the inverted OSC signal output from the EMI reduction controller 120 and the OSC signal output from the oscillator 110 to cancel each other out. The delay compensator 130 can synchronize the rise time of the OSC signal with the fall time of the inverted OSC signal, or synchronize the fall time of the OSC signal with the rise time of the inverted OSC signal, to maximize or increase the cancellation effect between the two signals, thereby maximizing or increasing the EMI reduction effect.

[0075] The drive clock generator 200 can generate operating timing for driving a data driver IC (TMIC) (e.g., at least one of a timing controller function and a data driver function). The drive clock generator 200 can use an OSC signal as a reference signal to generate the operating timing. To generate the operating timing, the drive clock generator 200 may include multiple flip-flops (FFs) and multiple multiplexers (MUXs) corresponding to the flip-flops. The OSC signal and an EMI reduction signal are input to the multiplexers (MUXs) corresponding to the flip-flops in the clock tree structure. Each multiplexer (MUX) is operated such that an OSC signal, as one of the EMI OSC signal and the EMI reduction signal, is supplied to a corresponding flip-flop (FF). Therefore, each multiplexer (MUX) can be implemented by, for example, a 2:1 multiplexer (MUX) configured to receive two signals and output one signal. The drive clock generator 200 can generate the operating timing based on the OSC signals selectively input to the multiplexers (MUXs). However, this disclosure is not limited to the above-described embodiments. Depending on the number of selection signals and input signals, the multiplexer MUX can be a 4:1 multiplexer MUX, an 8:1 multiplexer MUX, a 16:1 multiplexer MUX, etc.

[0076] The cascaded synchronization controller 140 provides the clock of the master data driver IC TMIC_Master to the slave data driver IC TMIC_SlaveN so that the operation timing of data drivers ICs TMIC1 to TMIC4 is synchronized.

[0077] Figure 3 and Figure 4 It is shown Figure 2This is a view showing the construction of the EMI reduction controller 120 and the relationship between its input and output signals. Depending on the predetermined settings, the EMI reduction controller 120 can use an inverted OSC signal or a ground signal as the EMI reduction signal.

[0078] Reference Figure 3 and Figure 4 The EMI reduction controller 120 may include an inverter 122 and an AND circuit 124.

[0079] Inverter 122 receives the OSC signal output from oscillator 110 and outputs an inverted OSC signal as the inverted signal of the OSC signal.

[0080] The AND circuit 124 receives the inverted OSC signal and the selection signal, and outputs the AND operation result OSC_B of these two signals. The selection signal is either a high-level signal or a low-level signal. The AND operation is an operation that outputs the sum of the two inputs. Therefore, when both inputs are high, a high-level signal is output. Thus, when the selection signal is input as a low-level signal to the AND circuit 124, a low-level signal (i.e., a ground signal) is output as the AND operation result OSC_B. When the selection signal is output as a high-level signal, the same high / low level state as the inverted OSC signal is output as the AND operation result OSC_B, thus outputting the same signal as the inverted OSC signal. Here, after the OSC signal is output from the oscillator 110, the inverted OSC signal, output as the AND operation result OSC_B, is output through the inverter 122 and the AND circuit 124. Therefore, the output signal OSC_B of the EMI reduction controller 120 has a predetermined time delay relative to the OSC signal output from the oscillator 110.

[0081] Figure 5 and Figure 6 It is shown Figure 2 The diagram shows the construction of the delay compensator 130 and the relationship between its input and output signals. The delay compensator 130 compensates for the phase delay of the OSC signal output from the oscillator 110, such that the OSC signal is canceled out by the delay of the EMI reduction signal OSC_B output from the EMI reduction controller 120.

[0082] Reference Figure 5 and Figure 6 The delay compensator 130 includes multiple inverters 132 and a register selector 134. The register selector 134 is configured to store the OSC signal delayed by the inverters 132 as signals Phase_0 to Phase_N, and output a delay-compensated OSC signal OSC_D as the selection of the OSC signal used for delay compensation.

[0083] Multiple inverters 132 generate a delayed OSC signal by receiving the OSC signal output from oscillator 110, inverting the OSC signal, and then inverting the inverted OSC signal again. The OSC signal is not delayed before being input to the inverters. However, the OSC signals output from the first and second inverters, as well as from the third and fourth inverters, are output with their phases delayed, even though these signals have the same magnitude. When multiple inverters are connected in series, the signal experiences a propagation delay at each stage, effectively increasing the overall delay. Therefore, as the number of inverters increases, the total signal delay also increases.

[0084] Register selector 134 stores OSC delay signals output from multiple inverters 132, selects a delay signal that is phase-synchronized with the EMI reduction signal OSC_B output from the EMI reduction controller 120, and outputs a delay-compensated OSC signal OSC_D. Register selector 134 can store the OSC signal before it is input to the inverter as a Phase_0 signal (the signal before delay), and store the OSC signal delayed once as a Phase_1 signal as a result of passing through the first and second inverters. It can store the OSC signal delayed twice as a result of passing through the third and fourth inverters as a Phase_2 signal. In this way, OSC signals delayed up to Phase_N can be stored. Therefore, EMI evaluation can be performed using delay signals from Phase_0 to Phase_N to confirm the optimal delay signal (i.e., a delay signal phase-synchronized with the EMI reduction signal OSC_B), and register selector 134 can output the corresponding phase delay signal as the delay-compensated OSC signal OSC_D.

[0085] When the EMI reduction signal OSC_B is an inverted OSC signal, the rising time of the delay compensation OSC signal OSC_D can be synchronized with the falling time of the inverted OSC signal, and the falling time of the delay compensation OSC signal OSC_D can also be synchronized with the rising time of the inverted OSC signal. Therefore, the EMI caused by the OSC signal OSC_D can be canceled by the EMI reduction signal OSC_B.

[0086] The delay-compensated OSC signal OSC_D and the EMI reduction signal OSC_B output from the EMI reduction controller 120 are supplied to signal lines arranged in parallel to each other and input to multiple multiplexers MUX in the clock tree structure that drive the clock generator 200. The multiple multiplexers MUX input the delay-compensated OSC signal OSC_D to the flip-flop FF; this delay-compensated OSC signal OSC_D is one of the EMI reduction signal OSC_B and the delay-compensated OSC signal OSC_D.

[0087] Figure 7 and Figure 8 It is shown Figure 2 This is a view of the construction of a multiplexer and the relationship between its input and output signals. The multiplexer MUX is a 2:1 multiplexer configured to receive two signals and output only one signal selected according to a selection signal. In this embodiment, the multiplexer MUX receives a delay compensation OSC signal OSC_D and an EMI reduction signal OSC_B, and outputs the delay compensation OSC signal OSC_D to the flip-flop FF according to the selection signal.

[0088] Reference Figure 7 and Figure 8 The multiplexer MUX may include a first AND circuit 212, a second AND circuit 214, an OR circuit 216, and an inverter 211. According to this embodiment, a high-level signal can be input as a selection signal for selecting the output of the multiplexer MUX. However, embodiments of this disclosure are not limited to this, and a low-level signal can also be input as a selection signal for selecting the output of the multiplexer MUX.

[0089] Inverter 211 is connected to the input of the second AND circuit 214 to invert the selection signal to be input to the second AND circuit 214, and inputs the inverted signal to the second AND circuit 214. Since a high-level signal is input as the selection signal according to this embodiment, the inverted low-level signal is input as the selection signal to the second AND circuit 214. However, if a low-level signal is input as the selection signal, inverter 211 can be connected to the input of the first AND circuit 212, inverting the selection signal to be input to the first AND circuit 212, and no inverter is provided at the input of the second AND circuit 214.

[0090] According to this embodiment, the first AND circuit 212 receives the delay compensation OSC signal OSC_D and a high-level signal as a selection signal, and outputs the AND operation result of these two signals as output signal ①. The AND operation is an operation that outputs the sum of two input signals. Therefore, when both input signals are in a high-level state, a high-level signal is output. Since the output signal ① of the first AND circuit 212 is the same as the high / low level state of the delay compensation OSC signal OSC_D, the output signal is the same as the delay compensation OSC signal OSC_D.

[0091] According to this embodiment, the second AND circuit 214 receives the EMI reduction signal OSC_B and a low-level signal as a selection signal, and outputs the AND operation result of these two signals as the output signal ②. Since the low-level signal as the selection signal is always input to the second AND circuit 214, the low-level signal is always output as the output signal ② of the second AND circuit 214.

[0092] According to this embodiment, the OR circuit 126 receives the output signal ① of the first AND circuit 212 and the output signal ② of the second AND circuit 214, and outputs the OR operation result of these two signals. The OR operation is an operation that outputs the derivation value of two inputs. Therefore, when both inputs are low, a low-level signal is output. Because the output signal ① of the first AND circuit 212 is the same as the delay compensation OSC signal OSC_D, and the output signal ② of the second AND circuit 214 is always low, the signal with the same high / low level state as the delay compensation OSC signal OSC_D is output as the output signal of the OR circuit 126, thereby outputting the same signal as the delay compensation OSC signal OSC_D.

[0093] Furthermore, when a low-level signal is input as a selection signal, the first AND circuit 212 receives the delay compensation OSC signal OSC_D and the low-level signal as the selection signal, and outputs the AND operation result of these two signals as the output signal ①. Since the AND operation is an operation that outputs the sum of two input signals, the low-level signal is output as the output signal ① of the first AND circuit 212.

[0094] The second AND circuit 214 receives the EMI reduction signal OSC_B and a high-level signal as a selection signal, and outputs the AND operation result of these two signals as the output signal ②. Since the AND operation is an operation that outputs the sum of two input signals, the EMI reduction signal OSC_B is always output as the output signal ② of the second AND circuit 214.

[0095] The OR circuit 126 receives the output signal ① of the first AND circuit 212 and the output signal ② of the second AND circuit 214, and outputs the OR operation result of these two signals. Because the output signal ① of the first AND circuit 212 is a low-level signal in the input of the OR circuit 126, and the output signal ② of the second AND circuit 214 is always the EMI reduction signal OSC_B, the signal with the same high / low level state as the EMI reduction signal OSC_B is output as the output signal of the OR circuit 126, thus outputting a signal identical to the EMI reduction signal OSC_B.

[0096] In the above configuration, when a high-level signal can be used as a selection signal input for selecting the output of the multiplexer MUX, the OSC signal can be applied together with the EMI reduction signal to the flip-flop FF of the driving clock generator 200 to reduce the EMI of the OSC signal, and only the OSC signal, which is one of the two signals, can be input to each flip-flop FF in the clock tree structure.

[0097] In the above configuration, the display device according to an exemplary embodiment of this disclosure can be configured to form an EMI reduction signal line in response to an OSC signal line providing an operating clock reference signal, and to selectively supply an inverted signal or a ground signal capable of reducing EMI generated in the OSC signal line to the EMI reduction signal line, thereby reducing the impact of EMI caused by the OSC signal. Here, the OSC signal line and the EMI reduction signal line can be modified to further improve the EMI reduction effect.

[0098] Figure 9 This is a view illustrating the EMI cancellation principle using OSC signal lines and EMI reduction signal lines.

[0099] When the first line L1, which applies the OSC signal OSC_D, and the second line, which applies the EMI reduction signal OSC_B, are placed adjacent to each other, EMI can be reduced through the coupling effect between the two lines L1 and L2. The coupling effect refers to the leakage of high-frequency signals from the two conductors through the parasitic capacitance formed between them. In other words, as the parasitic capacitance between the two conductors increases, EMI can be reduced.

[0100] The parasitic capacitance C formed between two conductors can be defined by the following equation 1.

[0101] [Formula 1]

[0102]

[0103] A: Area of ​​each metal plate, d: Distance between metal plates, ε: Dielectric constant between metals.

[0104] Referring to Equation 1, the parasitic capacitance C is directly proportional to the area A and dielectric constant ε of each conductor, and inversely proportional to the distance d between the conductors. Therefore, as the area A of each of the first line L1 and the second line L2 increases, the EMI reduction effect improves, and as the distance d between the two lines L1 and L2 decreases, the EMI reduction effect also improves. Here, it is preferable that the first line L1 and the second line L2 exhibit the same or substantially the same electrical signal characteristics and have low resistance. Considering the above issues, the optimized design values ​​of the first line L1 and the second line L2 can be achieved based on the design rules provided in the semiconductor manufacturing process.

[0105] like Figure 9 As shown, a first line L1, to which the OSC signal OSC_D is applied, has a length of Length_D, a width of Width D, and a thickness of Thickness_D. A second line L2, to which the EMI reduction signal OSC_B is applied, has a length of Length_B, a width of Width B, and a thickness of Thickness_B. A space (Space) exists between the first line L1 and the second line L2. The area of ​​the first line L1 is the product of its length of Length_D and its width of Width D, and the area of ​​the second line L2 is the product of its length of Length_B and its width of Width B. The distance between the first line L1 and the second line L2 is the space (Space). The EMI reduction effect increases as the area of ​​each of the first line L1 and the second line L2 increases, and the EMI reduction effect also increases as the distance between the two lines L1 and L2 decreases.

[0106] Figures 10 to 13 This is a view illustrating a design method for the first line L1 and the second line L2 according to a first embodiment of the present disclosure.

[0107] The first line L1 and the second line L2, which are adjacent to each other, can be formed in a sawtooth structure with protrusions that are alternately formed on the adjacent lines to maximize the EMI reduction effect due to coupling while having the same or substantially the same resistance characteristics. As an example, the protrusions can be formed on adjacent lines without overlapping or at least partially overlapping. When protrusions are formed on adjacent lines, the area of ​​each line increases, thereby increasing the parasitic capacitance. The planar shape of each protrusion in the direction parallel to the direction from the first line L1 to the second line L2 can be a quadrilateral, a rounded quadrilateral, a semicircle, a trapezoid, a triangle, etc., but the shape of the protrusion is not limited to these. Here, when the protrusions of adjacent lines are arranged side by side, the coupling effect can be improved due to the reduced distance between the lines, but the electrical stability (e.g., electrostatic discharge ESD) may be reduced. When the protrusions of adjacent lines are arranged alternately, the EMI cancellation and shielding effects can be improved due to the coupling effect in the diagonal direction, while the distance between the two conductors remains consistent.

[0108] Figure 10 An example is shown where quadrilateral protrusions with a planar quadrilateral shape are alternately formed in the relative regions of the first line L1 and the second line L2.

[0109] Reference Figure 10(a) can be designed such that the perpendicular distance A between the end of a protrusion formed on the first line L1 and the second line L2 is equal to the distance B between the end of a protrusion formed on the first line L1 and the end of a corresponding protrusion formed on the second line L2 (A = B). Here, the distance B between the end of a protrusion formed on the first line L1 and the end of a corresponding protrusion formed on the second line L2 can be defined as the distance between the center points of the protrusion ends.

[0110] Reference Figure 10 (b) The distance B between the end of a protrusion formed on the first line L1 and the end of the corresponding protrusion formed on the second line L2 can be designed to be equal to or greater than the vertical distance A between the end of the protrusion formed on the first line L1 and the second line L2 (A≤B). When the opposing protrusions are arranged alternately according to design requirements, the EMI cancellation and shielding effect can be improved due to the coupling effect in the diagonal direction, while uniformly maintaining the distance between the first line L1 and the second line L2.

[0111] Figure 11 , Figure 12 and Figure 13 Various protrusion patterns are illustrated, designed such that the distance B between the end of a protrusion formed on the first line L1 and the end of a corresponding protrusion formed on the second line L2 is equal to or greater than the vertical distance A (A≤B) between the end of the protrusion formed on the first line L1 and the second line L2. Figure 10 Similarly, regardless of the shape of the protrusion, the distance B between the end of a protrusion formed on the first line L1 and the end of the corresponding protrusion formed on the second line L2 can be defined as the distance between the center points of the ends of the protrusions.

[0112] Figure 11 This is a view showing a variation of quadrilateral protrusions that alternately form on adjacent lines.

[0113] Figure 11 (a) illustrates a conical pattern in which the width of each quadrilateral protrusion gradually increases from the end of the quadrilateral protrusion to the line with the quadrilateral protrusion. Figure 11 (b) illustrates a pattern with rounded ends to a planar shape of quadrilateral protrusions. Figure 11 (c) illustrates an inclined pattern, wherein each quadrilateral protrusion formed on the first line L1 and the corresponding quadrilateral protrusion formed on the second line L2 are inclined to face each other. Alternatively, the quadrilateral protrusions formed on the first line L1 and the quadrilateral protrusions formed on the second line L2 may be formed to be inclined in different directions.

[0114] Figure 12This is a view illustrating a structure in which semi-circular protrusions of a semi-circular planar shape are alternately formed on adjacent lines. As an example, the protrusions can be formed on adjacent lines without overlapping or at least partially overlapping. Various variations of the semi-circular protrusions are possible, as long as the design requirement is met that the distance B between the end of a protrusion formed on the first line L1 and the end of the corresponding protrusion formed on the second line L2 is equal to or greater than the vertical distance A (A≤B) between the end of the protrusion formed on the first line L1 and the second line L2.

[0115] Figure 13 This is a view illustrating a structure in which triangular protrusions alternately form on adjacent lines. Figure 13 (a) illustrates each isosceles triangle pattern with a planar shape of triangle and where the two sides of the triangle are the same. Figure 13 (b) shows a right-angled triangle pattern. When protrusions with right-angled triangle patterns are formed, the hypotenuse of each triangle formed on the first line L1 and the hypotenuse of the corresponding triangle formed on the second line L2 are inclined in the same or different directions. Figure 13 (c) illustrates a strip pattern, wherein each protrusion has a triangular vertex at its end. The strip protrusions formed on the first line L1 and the strip protrusions formed on the second line L2 can be formed to be inclined in the same or different directions.

[0116] As described above, when protrusions are alternately formed on adjacent lines (e.g., the first line L1 and the second line L2), the area of ​​each line can be increased, thereby increasing the parasitic capacitance and improving the EMI cancellation and shielding effect due to the coupling effect in the diagonal direction, while maintaining the same distance.

[0117] Furthermore, when a protrusion is formed on the line, antenna characteristics are obtained in which the electromagnetic waves generated from the line have a specific radiation pattern. When an electrical signal is applied to the conductor, antenna characteristics are obtained in which electromagnetic waves are radiated and have a specific radiation pattern depending on their shape.

[0118] Figure 14 This is a view illustrating a radial pattern that depends on the shape of the protrusions formed on the line.

[0119] like Figure 14 As shown in (a), when point protrusions are formed on lines (e.g., first line L1 and second line L2) such that the planar shape of each protrusion can be a quadrilateral in a direction parallel to the direction from the first line L1 to the second line L2, isotropic characteristics that radiate uniform electromagnetic energy in all directions can be obtained, as in the first embodiment.

[0120] On the other hand, such as Figure 14As shown in (b), when the planar shape of each protrusion formed on the line can be an annular protrusion in a direction parallel to the direction from the first line L1 to the second line L2, a directional characteristic of electromagnetic energy concentration in a specific direction can be obtained. Therefore, the antenna directivity of the two lines can be used to improve the EMI cancellation effect. That is, when annular protrusions are alternately formed on the first line L1 and the second line L2, the antenna directivity of the lines overlaps with each other, thereby obtaining an EMI cancellation effect. Here, when the annular protrusions are arranged such that the distance B between the end of an annular protrusion formed on the first line L1 and the end of the corresponding annular protrusion formed on the second line L2 is equal to or greater than the vertical distance A between the end of an annular protrusion formed on the first line L1 and the second line L2 (A≤B), a coupling effect can be obtained simultaneously due to the increase in line area, and an antenna directivity effect can be obtained due to the annular shape of the protrusion, thereby further improving the EMI cancellation effect. In addition, with Figure 10 Similarly, regardless of the shape of the protrusion, the distance B between the end of a protrusion formed on the first line L1 and the end of the corresponding protrusion formed on the second line L2 can be defined as the distance between the center points of the protrusion ends. Furthermore, this method can also be applied to what will be described below. Figures 15 to 17 The implementation method.

[0121] Figures 15 to 17 This is a view illustrating a design method for the first line L1 and the second line L2 according to a second embodiment of the present disclosure. According to the second embodiment, the annular protrusions can be alternately arranged on the first line L1 and the second line L2, such that the antenna directivity of the lines overlaps, thereby improving the EMI cancellation effect.

[0122] Figures 15 to 17 Various annular protrusion patterns are illustrated, which are designed such that the distance B between the end of an annular protrusion formed on the first line L1 and the end of a corresponding annular protrusion formed on the second line L2 is equal to or greater than the vertical distance A between the end of an annular protrusion formed on the first line L1 and the second line L2 (A≤B).

[0123] Figure 15 (a) illustrates a conical pattern in which the width of each quadrilateral ring protrusion gradually increases from the end of the quadrilateral ring protrusion to the line with the quadrilateral protrusion. Figure 15 (b) shows a pattern of annular protrusions in which the ends of the quadrilateral annular protrusions are rounded. Figure 15(c) shows an inclined annular pattern, wherein each quadrilateral annular protrusion formed on the first line L1 and the corresponding quadrilateral annular protrusion formed on the second line L2 are inclined to face each other. The quadrilateral annular protrusions formed on the first line L1 and the quadrilateral annular protrusions formed on the second line L2 can be formed to be inclined in the same or different directions.

[0124] Figure 16 This is a view illustrating a structure in which semi-circular annular protrusions are alternately formed on adjacent lines. Various modifications can be made to the semi-circular annular protrusions, as long as the design requirement is met that the distance B between the end of an annular protrusion formed on the first line L1 and the end of the corresponding annular protrusion formed on the second line L2 is equal to or greater than the vertical distance A (A≤B) between the end of an annular protrusion formed on the first line L1 and the second line L2.

[0125] Figure 17 This is a view illustrating a structure in which triangular ring-shaped protrusions alternately form on adjacent lines. Figure 17 (a) illustrates an isosceles triangular annular protrusion pattern in a top view, where both the inner and outer surfaces are triangular and the two sides of the triangle are equal. Figure 17 (b) shows a right-angled triangular ring pattern. When forming ring protrusions, each with a right-angled triangular pattern, the hypotenuse of each triangle formed on the first line L1 and the hypotenuse of the corresponding triangle formed on the second line L2 may be inclined in the same or different directions. Figure 17 (c) illustrates a strip-shaped annular pattern, wherein each annular protrusion has a triangular vertex at its end. The strip-shaped annular protrusions formed on the first line L1 and the strip-shaped annular protrusions formed on the second line L2 can be formed to be inclined in the same or different directions.

[0126] As described above, when annular protrusions are alternately formed on adjacent lines (e.g., the first line L1 and the second line L2 according to the second embodiment, but not limited thereto, for example, any two lines with OSC signal OSC_D applied and lines with EMI reduction signal OSC_B applied respectively), a coupling effect can be obtained due to the increase in line area, and the EMI cancellation effect can be improved by utilizing the antenna directivity characteristics of the lines.

[0127] It is evident from the above description that the exemplary embodiments of this disclosure have the following effects.

[0128] The advantage of the exemplary embodiments of this disclosure is that an EMI reduction signal line is formed in response to the OSC signal line providing the reference signal for the operating clock, and an inverted signal or ground signal capable of reducing or minimizing EMI generated in the OSC signal line is selectively supplied to the EMI reduction signal line, thereby reducing the impact of EMI caused by the OSC signal.

[0129] The advantage of the exemplary embodiments of this disclosure is that the OSC signal line and the EMI reduction signal line are arranged parallel to each other, and protrusions are alternately formed on the OSC signal line and the EMI reduction signal line, thereby maximizing the EMI reduction effect due to the coupling effect between the two lines.

[0130] The effects of this disclosure are not limited to those described above, and the disclosure has a wider range of effects.

[0131] Those skilled in the art should understand that various modifications and substitutions can be made based on the above description without departing from the technical concept of this disclosure.

Claims

1. A clock generator, the clock generator comprising: An oscillator configured to output a reference clock signal to a first line; An electromagnetic interference (EMI) reduction controller is configured to generate an EMI reduction signal that cancels out the reference clock signal and output the EMI reduction signal to a second line. as well as A driving clock generator is configured to generate an operating clock signal based on the reference clock signal, the operating clock signal being one of the reference clock signal input via the first line and the EMI reduction signal input via the second line. The EMI reduction signal includes an inverted oscillating clock (OSC) signal for canceling EMI caused by the reference clock signal and a ground signal for shielding the reference clock signal.

2. The clock generator according to claim 1, wherein, The first line and the second line each have a serrated structure, and the serrated structures of the first line and the second line face each other and are intersected.

3. The clock generator of claim 1, further comprising a delay compensator configured to synchronize the phase of the reference clock signal with the phase of the EMI reduction signal.

4. The clock generator according to claim 1, wherein, The driving clock generator includes: Multiple multiplexers, connected in a tree structure to the first line and the second line, are configured to output the reference clock signal applied to the first line; and Multiple triggers are connected to multiple multiplexers, and the multiple triggers are configured to generate a drive clock signal based on the reference clock signal.

5. The clock generator according to claim 1, wherein, The EMI reduction controller includes: An inverter configured to invert the reference clock signal to generate the inverted oscillating clock (OSC) signal; and An output circuit configured to output one of the inverted oscillating clock (OSC) signal and the ground signal.

6. The clock generator according to claim 1, wherein, The first line and the second line are configured to have a uniform distance between them.

7. The clock generator according to claim 1, wherein The first line includes a first protrusion extending into a region adjacent to the second line. The second line includes a second protrusion extending into a region adjacent to the first line, and The first protrusion and the second protrusion are arranged alternately.

8. The clock generator according to claim 7, wherein, The first protrusion and the second protrusion are arranged such that the distance between the end of each first protrusion and the end of a corresponding second protrusion is equal to or greater than the vertical distance between the end of each first protrusion and the second line.

9. The clock generator according to claim 8, wherein, The distance between the end of each first protrusion and the end of the corresponding second protrusion is the distance between the center point of the end of each first protrusion and the center point of the end of the corresponding second protrusion.

10. The clock generator according to claim 7, wherein, Each first protrusion and each second protrusion has a ring-shaped shape.

11. A display device, the display device comprising: Display panel; as well as The timing controller incorporates an IC TMIC, which is configured to convert externally input image signals and supply image data to the display panel. Each of the TMICs includes: An oscillator configured to output a reference clock signal to a first line; An electromagnetic interference (EMI) reduction controller is configured to generate an EMI reduction signal that cancels out the reference clock signal and output the EMI reduction signal to a second line; and A driving clock generator is configured to generate an operating clock signal for supplying image data to the display panel based on the reference clock signal, the operating clock signal being either the reference clock signal input through the first line or the EMI reduction signal input through the second line. The EMI reduction signal includes an inverted oscillating clock (OSC) signal for canceling EMI caused by the reference clock signal and a ground signal for shielding the reference clock signal.

12. The display device according to claim 11, wherein, The display panel includes multiple pixels connected to data lines and gate lines, and The display device also includes a gating driver IC configured to supply gating signals to the gating lines.

13. The display device according to claim 11, wherein, The first line and the second line each have a serrated structure, and the serrated structures of the first line and the second line face each other and are intersected.

14. The display device according to claim 11, wherein, Each of the TMICs further includes a cascaded synchronization controller configured to synchronize the operating clock signal.

15. The display device according to claim 14, wherein, One of the TMICs is set as the master TMIC, and the other TMICs in the TMIC are set as slave TMICs. The cascaded synchronization controller is configured to synchronize the operating clock signal of the slave TMIC with the operating clock signal of the master TMIC.

16. The display device according to claim 12, wherein One of the TMICs is set as the master TMIC, and The main TMIC generates a control signal for controlling the gating driver IC based on the reference clock signal, and applies the control signal to the gating driver IC.

17. The display device according to claim 11, wherein, The TMIC also includes a delay compensator configured to synchronize the phase of the reference clock signal with the phase of the EMI reduction signal.

18. The display device according to claim 11, wherein The first line and the second line are configured to have a uniform distance between them. The first line includes a first protrusion extending into a region adjacent to the second line. The second line includes a second protrusion extending into a region adjacent to the first line, and The first protrusion and the second protrusion are arranged alternately.

19. The display device according to claim 18, wherein, The first protrusion and the second protrusion are arranged such that the distance between the end of each first protrusion and the end of a corresponding second protrusion is equal to or greater than the vertical distance between the end of each first protrusion and the second line.

20. The display device according to claim 19, wherein, The distance between the end of each first protrusion and the end of the corresponding second protrusion is the distance between the center point of the end of each first protrusion and the center point of the end of the corresponding second protrusion.

21. The display device according to claim 18, wherein, Each first protrusion and each second protrusion has a ring-shaped shape.

Images