Semiconductor wafer and serial check circuit

Abstract

A semiconductor wafer and a sequence checking circuit, the semiconductor wafer includes a physical layer and a processing circuit. The physical layer includes at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is used to generate at least one test result signal according to a clock signal and at least one test data signal transmitted via the at least one signal transmission path, and the clock signal is not transmitted via the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is used to determine the operation state of the at least one signal transmission path according to the voltage level of the at least one test result signal. Through twice checking of the test data signal by the sequence checking circuit, the semiconductor wafer of the present disclosure can establish a data loopback pattern mechanism suitable for instruction / address physical layer in the case of the original matching timing of the clock signal and the test data signal disappearing, so as to improve the coverage of the design for testability.

Description

Technical Field

[0001] This disclosure relates to a semiconductor wafer, and more particularly to a semiconductor wafer containing a sequence checking circuit. Background Technology

[0002] In high-bandwidth memory specifications, the command / address PHY (CAPHY) is designed to have only a transmitting end and no receiving end. Therefore, in design for testability (DFT), the CAPHY lacks a data loopback pattern mechanism for testing, unlike the data quadword PHY (DQPHY). In view of this, it is necessary to improve the existing design to meet the requirements. Summary of the Invention

[0003] One embodiment of this disclosure is a semiconductor wafer. The semiconductor wafer includes a physical layer and a processing circuit. The physical layer includes at least one sequence check circuit and at least one signal transmission path, wherein the at least one sequence check circuit is used to generate at least one test result signal based on a clock signal and at least one test data signal transmitted via the at least one signal transmission path, and the clock signal has not been transmitted via the at least one signal transmission path. The processing circuit is electrically coupled to the physical layer and is used to determine the operating state of the at least one signal transmission path based on the voltage level of the at least one test result signal.

[0004] In some embodiments, the at least one sequence checking circuit is used to check a data sequence of the at least one test data signal twice based on multiple rising edges and multiple falling edges of the clock signal.

[0005] In some embodiments, the at least one sequence checking circuit includes: a first shift register circuit for checking the data sequence of the at least one test data signal according to the plurality of rising edges of the clock signal to output a first check result signal; a second shift register circuit for checking the data sequence of the at least one test data signal according to the plurality of falling edges of the clock signal to output a second check result signal; and an output logic gate for outputting the at least one test result signal according to the voltage level of the first check result signal and the voltage level of the second check result signal.

[0006] In some embodiments, the first shift register circuit includes: a plurality of first flip-flops connected in sequence for sequentially storing a plurality of data values ​​of the data sequence of the at least one test data signal according to the plurality of rising edges of the clock signal; a first logic gate for calculating a first calculated logic value based on the data values ​​stored by a first and a second of the plurality of first flip-flops at a first time; a second flip-flop for storing the first calculated logic value based on the plurality of rising edges of the clock signal; and a second logic gate for calculating a first verification logic value as the first check result signal based on the first calculated logic value and the data values ​​stored by a third of the plurality of first flip-flops at a second time after the first time.

[0007] In some embodiments, the second shift register circuit includes: a plurality of third flip-flops connected in sequence for sequentially storing a plurality of data values ​​of the data sequence of the at least one test data signal according to the plurality of falling edges of the clock signal; a third logic gate for calculating a second calculated logic value based on the data values ​​stored by a first and a second of the plurality of third flip-flops at a third time; a fourth flip-flop for storing the second calculated logic value based on the plurality of falling edges of the clock signal; and a fourth logic gate for calculating a second verification logic value as the second check result signal based on the second calculated logic value and the data values ​​stored by a third of the plurality of third flip-flops at a fourth time after the third time.

[0008] In some embodiments, the at least one sequence check circuit further includes: a first latch circuit coupled between the first shift register circuit and the output logic gate, and configured to selectively output the first check result signal to the output logic gate according to a control signal; and a second latch circuit coupled between the second shift register circuit and the output logic gate, and configured to selectively output the second check result signal to the output logic gate according to the control signal.

[0009] In some embodiments, when at least one of the first inspection result signal and the second inspection result signal has a first voltage level, the output logic gate outputs the at least one test result signal having the first voltage level, and the processing circuit determines that the at least one signal transmission path is operating normally based on the at least one test result signal having the first voltage level; wherein when both the first inspection result signal and the second inspection result signal have a second voltage level different from the first voltage level, the output logic gate outputs the at least one test result signal having the second voltage level, and the processing circuit determines that the at least one signal transmission path is not operating normally based on the at least one test result signal having the second voltage level.

[0010] In some embodiments, the processing circuit determines that the at least one signal transmission path is operating normally when at least one of the two check results generated by the at least one sequence check circuit is correct.

[0011] In some embodiments, the data sequence of the at least one test data signal is generated by at least one sequence generation circuit included in the processing circuit.

[0012] In some embodiments, the at least one sequence generation circuit is a pseudo-random binary sequence generator.

[0013] In some embodiments, the semiconductor wafer further includes a memory circuit for electrically coupling to the physical layer.

[0014] In some embodiments, the semiconductor wafer further includes an interposer layer, and the physical layer and the memory circuit are coupled to each other via the interposer layer.

[0015] Another embodiment of this case is a sequence check circuit. This sequence check circuit is used to check a test data signal transmitted via a signal transmission path through a physical layer, and includes a first shift register circuit, a second shift register circuit, and an output logic gate. The first shift register circuit performs a first check on a data sequence of the test data signal based on multiple rising edges of a clock signal, to output a first check result signal. The second shift register circuit performs a second check on the data sequence of the test data signal based on multiple falling edges of the clock signal, to output a second check result signal. The output logic gate outputs a test result signal based on the voltage levels of the first and second check result signals, wherein the test result signal indicates the operating state of the signal transmission path. The clock signal has not been transmitted via the at least one signal transmission path.

[0016] In some embodiments, the first shift register circuit includes: a plurality of first flip-flops connected in sequence for sequentially storing a plurality of data values ​​of the data sequence of the test data signal according to the plurality of rising edges of the clock signal; a first logic gate for calculating a first calculated logic value based on the data values ​​stored by a first and a second of the plurality of first flip-flops at a first time; a second flip-flop for storing the first calculated logic value based on the plurality of rising edges of the clock signal; and a second logic gate for calculating a first verification logic value as the first check result signal based on the first calculated logic value and the data values ​​stored by a third of the plurality of first flip-flops at a second time after the first time.

[0017] In some embodiments, the first logic gate and the second logic gate are each an XOR gate.

[0018] In some embodiments, the second shift register circuit includes: a plurality of third flip-flops connected in sequence for sequentially storing a plurality of data values ​​of the data sequence of the test data signal according to the plurality of falling edges of the clock signal; a third logic gate for calculating a second calculated logic value based on the data values ​​stored by a first and a second of the plurality of third flip-flops at a third time; a fourth flip-flop for storing the second calculated logic value based on the plurality of falling edges of the clock signal; and a fourth logic gate for calculating a second verification logic value as the second check result signal based on the second calculated logic value and the data values ​​stored by a third of the plurality of third flip-flops at a fourth time after the third time.

[0019] In some embodiments, the third logic gate and the fourth logic gate are each XOR gates.

[0020] In some embodiments, the sequence check circuit further includes: a first latch circuit coupled between the first shift register circuit and the output logic gate, and configured to selectively output the first check result signal to the output logic gate according to a control signal; and a second latch circuit coupled between the second shift register circuit and the output logic gate, and configured to selectively output the second check result signal to the output logic gate according to the control signal.

[0021] In some embodiments, the output logic gate is an AND gate.

[0022] In some embodiments, the signal transmission path includes a sub-logic circuit and an input / output circuit, the sub-logic circuit being used to receive at least a first data sequence to output a second data sequence, and the input / output circuit being used to receive the second data sequence to output a third data sequence; wherein the second data sequence or the third data sequence is used as the test data signal.

[0023] By using a sequence check circuit, the semiconductor wafer disclosed herein can establish a data feedback pattern mechanism applicable to the instruction / address entity layer when the timing of the clock signal and test data signal that was originally matched disappears, thereby improving the coverage of design-for-testability. Attached Figure Description

[0024] Figure 1 A block diagram illustrating a semiconductor wafer according to some embodiments of the present disclosure;

[0025] Figure 2A circuit diagram illustrating a sequence check circuit according to some embodiments of this disclosure;

[0026] Figure 3 A timing diagram illustrating multiple signals within a semiconductor wafer according to some embodiments of the present disclosure;

[0027] Figure 4 This is a circuit diagram of a sequence check circuit at a first time, illustrated according to some embodiments of the present disclosure;

[0028] Figure 5 A circuit diagram of a sequence check circuit at a second time, illustrated according to some embodiments of the present disclosure;

[0029] Figure 6A A block diagram illustrating a semiconductor wafer according to some embodiments of the present disclosure;

[0030] Figure 6B A block diagram illustrating a semiconductor wafer according to some embodiments of the present disclosure;

[0031] Figure 6C This is a block diagram illustrating a semiconductor wafer according to some embodiments of the present disclosure.

[0032] [Symbol Explanation]

[0033] 10: Processing Circuit

[0034] 11: Signal generation circuit

[0035] 20: Entity Layer

[0036] 21: Logic Circuits

[0037] 23: Input / output circuit

[0038] 25: Phase-locked loop circuit

[0039] 30: Memory Circuits

[0040] 40: Intermediary layer

[0041] 100, 200, 300: Semiconductor wafers

[0042] 110: Sequence Generation Circuit

[0043] 210: Sequence checking circuit

[0044] 212: Sub-logic circuits

[0045] SS: Reference Data Sequence

[0046] SP: First Data Sequence

[0047] CA_o: Second data sequence

[0048] CA_i: Third data sequence

[0049] CLR: Control signal

[0050] CK: Clock signal

[0051] XCK: Clock signal

[0052] ERR: Test result signal

[0053] ERR_r: First check result signal

[0054] ERR_f: Second check result signal

[0055] FF1: First Shifter

[0056] FF2: Second flip-flop

[0057] FF3: The Third Shifter

[0058] FF4: The Fourth Shifter

[0059] LG1: First Logic Gate

[0060] LG2: Second Logic Gate

[0061] LG3: Third Logic Gate

[0062] LG4: The Fourth Logic Gate

[0063] LG_o: Output logic gate

[0064] LH1: First latching circuit

[0065] LH2: Second latching circuit

[0066] SR1: First shift register circuit

[0067] SR2: Second shift register circuit

[0068] IVT: Reverse Door

[0069] T1, T2: Period

[0070] t1: First time

[0071] t2: Second time

[0072] (1)~(7): Numbering Detailed Implementation

[0073] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0074] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0075] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0076] For ease of explanation, the lowercase English indices 1 to n in the component symbols used in this specification and drawings are only for the convenience of referring to individual components, and are not intended to limit the number of the aforementioned components to a specific number. In this specification and drawings, if the index of a component symbol is not specified when it is used, it means that the component symbol refers to any unspecified component in the component group to which it belongs. For example, component symbol 11[1] refers to signal generation circuit 11[1], while component symbol 11 refers to any unspecified signal generation circuit in signal generation circuits 11[1] to 11[n].

[0077] Please see Figure 1 , Figure 1 This is a block diagram illustrating a semiconductor wafer 100 according to some embodiments of the present disclosure. In some embodiments, such as Figure 1 As shown, the semiconductor chip 100 includes a processing circuit 10 and a physical layer (PHY) 20. Specifically, the processing circuit 10 can be implemented using a system-on-a-chip (SoC), and the physical layer 20 can be implemented using a command / address physical layer (CAPHY).

[0078] First, the structure of the processing circuit 10 and the physical layer 20 will be described in detail. In some embodiments, the processing circuit 10 includes at least one signal generation circuit 11. For example, in... Figure 1 In one embodiment, the processing circuit 10 includes n signal generation circuits 11[1] to 11[n], where n is a positive integer greater than 1.

[0079] In some embodiments, n signal generation circuits 11[1] to 11[n] have the same structure, but this disclosure is not limited thereto. For the sake of simplicity, the structure of signal generation circuit 11[1] will be described in detail below using signal generation circuit 11[1] as an example. Figure 1 As shown, the signal generation circuit 11[1] includes multiple sequence generation circuits 110[1] to 110[4], but the present disclosure is not limited thereto. Specifically, each of the sequence generation circuits 110[1] to 110[4] is implemented by a pseudo-random binary sequence (PRBS) generator. The structure of the PRBS generator is well known to those skilled in the art to which the present disclosure pertains, and therefore will not be described in detail here.

[0080] In some embodiments, the physical layer 20 is electrically coupled to the processing circuit 10 and includes at least one logic circuit 21, at least one input / output (I / O) circuit 23, and a phase-locked loop (PLL) circuit 25. For example, in Figure 1 In this embodiment, the physical layer 20 includes n logic circuits 21[1] to 21[n] and n input / output circuits 23[1] to 23[n]. For example... Figure 1 As shown, multiple logic circuits 21[1] to 21[n] are electrically coupled to multiple input / output circuits 23[1] to 23[n], and are also electrically coupled to multiple signal generation circuits 11[1] to 11[n]. In addition, a phase-locked loop circuit 25 is coupled to multiple logic circuits 21[1] to 21[n].

[0081] In some embodiments, n logic circuits 21[1] to 21[n] have the same structure, but this disclosure is not limited thereto. For the sake of simplicity, the structure of logic circuit 21 will be described below using logic circuit 21[1] as an example. Figure 1 As shown, logic circuit 21[1] includes a sequence check circuit 210 and a sub-logic circuit 212, and the sub-logic circuit 212 is coupled to signal generation circuit 11[1]. Specifically, the sub-logic circuit 212 can be implemented by a parallel-to-serial conversion circuit. The structure of the parallel-to-serial conversion circuit is well known to those skilled in the art to which this disclosure pertains, and therefore will not be described in detail here. Corresponding to the sequence generation circuit 110 implemented by the PRBS generator, the sequence check circuit 210 can be implemented by a PRBS checker. The structure of the sequence check circuit 210 will be described in subsequent paragraphs. Figure 2 Detailed explanation.

[0082] In some embodiments, the n input / output circuits 23[1] to 23[n] also have the same structure, but this disclosure is not limited thereto. Specifically, each of the plurality of input / output circuits 23[1] to 23[n] includes a transmit path (not shown in the figure) and a receive path (not shown in the figure). The structure of the input / output circuits 23 is well known to those skilled in the art to which this disclosure pertains, and therefore will not be described in detail here.

[0083] Please see Figure 2 , Figure 2 This is a circuit diagram illustrating a sequence checking circuit 210 according to some embodiments of the present disclosure. In some embodiments, such as Figure 2 As shown, the sequence checking circuit 210 includes a first shift register circuit SR1, a second shift register circuit SR2, a first latch circuit LH1, a second latch circuit LH2, and an output logic gate LG_o. Specifically, the first latch circuit LH1 is coupled between an output terminal of the first shift register circuit SR1 and a first input terminal of the output logic gate LG_o, and the second latch circuit LH2 is coupled between an output terminal of the second shift register circuit SR2 and a second input terminal of the output logic gate LG_o.

[0084] In addition, although not shown in Figure 2 In this context, it should be understood that a data input terminal of the first shift register circuit SR1 and a data input terminal of the second shift register circuit SR2 are coupled to... Figure 1 The input / output circuit 23 in the circuit, a clock input terminal of the first shift register circuit SR1 and a clock input terminal of the second shift register circuit SR2 are coupled to the input / output circuit 23. Figure 1 The phase-locked loop circuit 25 in the middle, and one output terminal of the output logic gate LG_o is coupled to Figure 1 The processing circuit 10 in the middle.

[0085] In some embodiments, such as Figure 2 As shown, the first shift register circuit SR1 includes multiple first flip-flops FF1[1] to FF1[7], a first logic gate LG1, a second flip-flop FF2, and a second logic gate LG2. The multiple first flip-flops FF1[1] to FF1[7] are connected in sequence. The first logic gate LG1 is coupled to a data output terminal of the first flip-flop FF1[6], a data output terminal of the first flip-flop FF1[7], and a data input terminal of the second flip-flop FF2. The second logic gate LG2 is coupled to a data output terminal of the first flip-flop FF1[1] and a data output terminal of the second flip-flop FF2.

[0086] In some embodiments, such as Figure 2As shown, the second shift register circuit SR2 includes multiple third flip-flops FF3[1] to FF3[7], a third logic gate LG3, a fourth flip-flop FF4, and a fourth logic gate LG4. The multiple third flip-flops FF3[1] to FF3[7] are connected in sequence. The third logic gate LG3 is coupled to a data output terminal of the third flip-flop FF3[6], a data output terminal of the third flip-flop FF3[7], and a data input terminal of the fourth flip-flop FF4. The fourth logic gate LG4 is coupled to a data output terminal of the third flip-flop FF3[1] and a data output terminal of the fourth flip-flop FF4.

[0087] At Figure 2 In the embodiments described, the first logic gate LG1, the second logic gate LG2, the third logic gate LG3, and the fourth logic gate LG4 can each be implemented using an XOR gate, while the output logic gate LG_o can be implemented using an AND gate. However, this disclosure is not limited thereto. For example, in other embodiments, the first logic gate LG1 and the third logic gate LG3 can each be implemented using an XOR gate, the second logic gate LG2 and the fourth logic gate LG4 can each be implemented using a XNOR gate, and the output logic gate LG_o can be implemented using a NOR gate.

[0088] In some embodiments, the semiconductor chip 100 is used for electrical coupling to a memory circuit (not shown). Figure 1 (in the middle). In this way, the processing circuit 10 can send instruction signals and / or address signals to the memory circuit through the physical layer 20. In some embodiments, the processing circuit 10 tests the physical layer 20 before the semiconductor wafer 100 is packaged to prevent the memory circuit from receiving incorrect signals due to abnormal operation of the physical layer 20. The testing operation of the processing circuit 10 on the physical layer 20 will be described in detail below.

[0089] Please refer to it again. Figure 1In some embodiments, the sequence generation circuit 110 is used to generate a first data sequence SP based on a pre-set sub-value (or an initial value). For example, the sequence generation circuit 110[1] is used to generate the first data sequence SP[1] based on a first seed value, the sequence generation circuit 110[2] is used to generate the first data sequence SP[2] based on a second seed value, the sequence generation circuit 110[3] is used to generate the first data sequence SP[3] based on a third seed value, and the sequence generation circuit 110[4] is used to generate the first data sequence SP[4] based on a fourth seed value. It should be understood that the first seed value, the second seed value, the third seed value, and the fourth seed value may all be the same or all different, or they may be partially the same and partially different. Accordingly, the first data sequences SP[1] to SP[4] may all be the same or all different, or they may be partially the same and partially different.

[0090] In some embodiments, the first data sequence SP has multiple data values, and each data value can be either logic "1" or logic "0". In other words, the first data sequence SP can be composed of an arrangement of logic "1" and logic "0". It is worth noting that when the sequence generation circuit 110 outputs 2... M After -1 data value, the next output of the sequence generation circuit 110 is 2. M -1 data value will be combined with the previously output 2 M -1 data values ​​have the same permutation, where M is the order of the PRBS generator (e.g., 4, 7, 15, 23, 31, etc.). It should be understood that, given the seed value and the order of the PRBS generator, many data values ​​of the first data sequence SP are predictable.

[0091] Please see Figure 3 , Figure 3 This is a timing diagram of multiple signals within a semiconductor wafer 100 illustrated according to some embodiments of the present disclosure. In some embodiments, by setting a first seed value, a second seed value, a third seed value, and a fourth seed value, the signal generation circuit 11[1] is equivalent to outputting multiple data values ​​of a reference data sequence SS in parallel via multiple sequence generation circuits 110[1] to 110[4]. The first seven data values ​​in the reference data sequence SS (in Figure 3Taking numbers (1) to (7) as an example, with the triggering of a pulse in a clock signal CK, the data values ​​of numbers (1) to (4) in the reference data sequence SS are output in parallel through multiple sequence generation circuits 110[1] to 110[4]. Furthermore, with the triggering of the next pulse in the clock signal CK, the data values ​​of numbers (3) to (7) in the reference data sequence SS and the eighth data value not represented by a number are output in parallel through multiple sequence generation circuits 110[1] to 110[4]. In addition, it should be understood that the number of multiple first data sequences SP and the number of multiple sequence generation circuits 110 can be changed according to requirements and are not limited to... Figure 1 or Figure 3 Four of them. For example, in some embodiments, the signal generation circuit 11 includes at least one sequence generation circuit 110 and is used to generate at least one first data sequence SP.

[0092] In some embodiments, such as Figure 1 As shown, the phase-locked loop circuit 25 is used to generate another clock signal XCK based on the clock signal CK and transmit it to multiple logic circuits 21[1]~21[n]. For example... Figure 3 As shown, the clock signal CK has a period T1, while the clock signal XCK has another period T2, with period T1 being greater than period T2. In other words, the frequency of the clock signal XCK is higher than the frequency of the clock signal CK. In some embodiments, the frequency difference between the clock signal XCK and the clock signal CK corresponds to the number of times the first data sequence SP is generated. For example, Figure 1 The first data sequence SP has 4 elements, while Figure 3 The frequency of the clock signal XCK is four times the frequency of the clock signal CK, but this disclosure is not limited to this.

[0093] In some embodiments, sub-logic circuit 212 is used to receive at least a first data sequence SP to output a second data sequence CA_o. For example... Figure 1 As shown, the sub-logic circuit 212 is used to receive multiple first data sequences SP[1] to SP[4], and to convert the multiple parallel-input first data sequences SP[1] to SP[4] into a serially output second data sequence CA_o according to the clock signal XCK. In some embodiments, such as Figure 3 As shown, the order of multiple data values ​​in the second data sequence CA_o is essentially the same as the order of multiple data values ​​in the reference data sequence SS. The only difference between the second data sequence CA_o and the reference data sequence SS is the output frequency of the data values.

[0094] In some embodiments, the input / output circuit 23 is used to receive the second data sequence CA_o through the aforementioned transmit path, and to transmit the second data sequence CA_o as a third data sequence CA_i to the sequence checking circuit 210 through the aforementioned receive path. Note that the receive path of the input / output circuit 23 is typically turned off or disabled, and is only turned on or enabled during testing of the physical layer 20.

[0095] As explained above, when the sub-logic circuit 212 and the input / output circuit 23 operate normally, the order of the multiple data values ​​of the second data sequence CA_o and the order of the multiple data values ​​of the third data sequence CA_i will be substantially the same as the order of the multiple data values ​​of the reference data sequence SS. Furthermore, when at least one of the sub-logic circuit 212 and the input / output circuit 23 malfunctions, the order of the multiple data values ​​of the third data sequence CA_i may differ from the order of the multiple data values ​​of the reference data sequence SS.

[0096] It is worth noting that, such as Figure 1 As shown, the sequence checking circuit 210 of this disclosure can check the third data sequence CA_i transmitted via the sub-logic circuit 212 and the input / output circuit 23 to generate a test result signal ERR to the processing circuit 10. In this way, the processing circuit 10 can determine the operating status of the sub-logic circuit 212 and the input / output circuit 23 of the physical layer 20 based on the test result signal ERR.

[0097] Please refer to it again. Figure 2 The sequence checking circuit 210 is used to receive the third data sequence CA_i and the clock signal XCK. In some embodiments, the sub-logic circuit 212 and / or the input / output circuit 23 may be affected by process, voltage, and / or temperature, causing the timing of the clock signal XCK and the third data sequence CA_i to disappear from their original matching. It is worth noting that the sequence checking circuit 210 is used to perform two checks on the data sequence of the third data sequence CA_i based on multiple rising edges and multiple falling edges of the clock signal XCK through the first shift register circuit SR1 and the second shift register circuit SR2. In this way, the sequence checking circuit 210 of this disclosure can avoid incorrectly checking the data sequence of the third data sequence CA_i due to the disappearance of the timing of the clock signal XCK and the third data sequence CA_i.

[0098] Specifically, the first shift register circuit SR1 receives the third data sequence CA_i and the clock signal XCK, and checks the data sequence of the third data sequence CA_i based on multiple rising edges of the clock signal XCK (i.e., the first check), to output a first check result signal ERR_r. The second shift register circuit SR2 receives the third data sequence CA_i and another clock signal (not shown) that is inverted by the clock signal XCK, wherein the other clock signal can be generated by inverting the clock signal XCK via a NOT gate IVT. Accordingly, the second shift register circuit SR2 checks the data sequence of the third data sequence CA_i based on multiple falling edges of the clock signal XCK (i.e., the second check), to output a second check result signal ERR_f.

[0099] In some embodiments, the multiple first flip-flops FF1[1] to FF1[7] in the first shift register circuit SR1 are used to temporarily store multiple data values ​​of the data sequence of the third data sequence CA_i according to the multiple rising edges of the clock signal XCK. The following will use... Figure 4 The following is an example of an embodiment. Please refer to [link / reference]. Figure 4 , Figure 4 This is a circuit diagram of a sequence checking circuit 210 at a first time t1, as illustrated in some embodiments of this disclosure. For example... Figure 3 As shown, the first time t1 corresponds to one of the multiple rising edges of the clock signal XCK. At the first time t1, the multiple first flip-flops FF1[1] to FF1[7] each temporarily store one of the multiple data values ​​of the third data sequence CA_i. For example, as Figure 4 As shown, the first flip-flop FF1[1] temporarily stores logic "1", the first flip-flop FF1[2] temporarily stores logic "1", the first flip-flop FF1[3] temporarily stores logic "0", the first flip-flop FF1[4] temporarily stores logic "0", the first flip-flop FF1[5] temporarily stores logic "0", the first flip-flop FF1[6] temporarily stores logic "0", and the first flip-flop FF1[7] temporarily stores logic "0".

[0100] For example Figure 4 As shown, the first logic gate LG1 is used to calculate a first calculation logic value (i.e., logic "0") based on the data value (i.e., two logic "0") temporarily stored by the first flip-flop FF1[6] and the first flip-flop FF1[7] at the first time t1.

[0101] Furthermore, the second flip-flop FF2 is used to temporarily store the first calculated logic value of the first logic gate LG1 based on the multiple rising edges of the clock signal XCK. For example, at the first time t1, the second flip-flop FF2 temporarily stores the logic "1" calculated by the first logic gate LG1 before the first time t1, while the logic "0" calculated by the first logic gate LG1 at the first time t1 has not yet been stored by the second flip-flop FF2.

[0102] Please see Figure 5 , Figure 5 This is a circuit diagram of the sequence checking circuit 210 at a second time t2, as illustrated in some embodiments of this disclosure. For example... Figure 3 As shown, the second time t2 is after the first time t1 and corresponds to another of the multiple rising edges of the clock signal XCK. At the second time t2, the multiple first flip-flops FF1[1] to FF1[7] temporarily store the data values ​​received at their data input terminals (which are also one of the multiple data values ​​of the third data sequence CA_i). For example, as Figure 5 As shown, the first flip-flop FF1[1] temporarily stores the data value of the third data sequence CA_i at the second time t2 (i.e., as shown in the figure). Figure 3 The logic "0" shown is shown. The first flip-flop FF1[2] temporarily stores the logic "1" temporarily stored by the first flip-flop FF1[1] at the first time t1. The first flip-flop FF1[3] temporarily stores the logic "1" temporarily stored by the first flip-flop FF1[2] at the first time t1. The first flip-flop FF1[4] temporarily stores the logic "0" temporarily stored by the first flip-flop FF1[3] at the first time t1. The first flip-flop FF1[5] temporarily stores the logic "0" temporarily stored by the first flip-flop FF1[4] at the first time t1. The first flip-flop FF1[6] temporarily stores the logic "0" temporarily stored by the first flip-flop FF1[5] at the first time t1. The first flip-flop FF1[7] temporarily stores the logic "0" temporarily stored by the first flip-flop FF1[6] at the first time t1.

[0103] At the second time t2, the second flip-flop FF2 also temporarily stores the first calculated logic value (i.e., logic "0") calculated by the first logic gate LG1 at the first time t1. In addition, the second logic gate LG2 is used to calculate a first verification logic value (i.e. logic "0") as the first check result signal ERR_r based on the first calculated logic value and the data value (i.e. logic "0") temporarily stored by the first flip-flop FF1[1] at the second time t2.

[0104] In summary, the first logic gate LG1 calculates a first computational logic value based on the data value temporarily stored at a first time t1 of one of the plurality of first flip-flops FF1[1] to FF1[7] (e.g., first flip-flop FF1[6]) and another (e.g., first flip-flop FF1[7]). Then, the second logic gate LG2 calculates a first verification logic value based on the first computational logic value and the data value temporarily stored at a second time t2 of another of the plurality of first flip-flops FF1[1] to FF1[7] (e.g., first flip-flop FF1[1]).

[0105] It is worth noting that since the first check result signal ERR_r is logic "0" at the second time t2, the data value of the third data sequence CA_i at the second time t2 is as expected. It should be understood that if the first check result signal ERR_r is logic "1" at a certain time, then the data value of the third data sequence CA_i at that time is not as expected. Therefore, the first check result signal ERR_r output by the first shift register circuit SR1 can indicate whether the first check result of the third data sequence CA_i is normal.

[0106] In some embodiments, the first latching circuit LH1 is used to selectively output a first check result signal ERR_r to the output logic gate LG_o according to a control signal CLR. For example, as Figure 5 As shown, the first latch circuit LH1 outputs a first check result signal ERR_r based on the control signal CLR of the first voltage level (e.g., logic "0").

[0107] As explained above, the first shift register circuit SR1 is only meaningful for checking the third data sequence CA_i after at least the first seven data values ​​of the third data sequence CA_i have been input into it. Therefore, the sequence checking circuit 210 sets a buffer time through the control signal CLR to not output the check result, in order to avoid obtaining meaningless check results. For example, in Figure 4 In the embodiment, the second logic gate LG2 also calculates a first verification logic value (i.e., logic "0") as the first check result signal ERR_r based on the first calculation logic value calculated by the first logic gate LG1 before the first time t1 (i.e., logic "1" temporarily stored by the second flip-flop FF2) and the data value temporarily stored by the first flip-flop FF1[1] at the first time t1 (i.e., logic "1"). However, since the control signal CLR has a second voltage level (i.e., logic "1") different from the first voltage level at this time, the first latch circuit LH1 will not output the first check result signal ERR_r.

[0108] As mentioned above, the second shift register circuit SR2 is used to check the data sequence of the third data sequence CA_i based on multiple falling edges of the clock signal XCK. Otherwise, the operation of the second shift register circuit SR2 is similar to that of the first shift register circuit SR1. That is, the third logic gate LG3 calculates the second calculation logic value based on the data value temporarily stored at a third time (not shown) of one of the multiple third flip-flops FF3[1] to FF3[7] (e.g., the third flip-flop FF3[6]) and another (e.g., the third flip-flop FF3[7]). Then, the fourth logic gate LG4 calculates the second verification logic value as the second check result signal ERR_f based on the second calculation logic value and the data value temporarily stored at a fourth time (not shown) after the third time of another of the multiple third flip-flops FF3[1] to FF3[7] (e.g., the third flip-flop FF3[1]). The second check result signal ERR_f can be used to indicate whether the second check result of the third data sequence CA_i is normal. Furthermore, the second latch circuit LH2 is used to selectively output the second check result signal ERR_f generated by the second shift register circuit SR2 to the output logic gate LG_o according to the control signal CLR. The operation of the second latch circuit LH2 is similar to that of the first latch circuit LH1, so it will not be described in detail here.

[0109] In some embodiments, the output logic gate LG_o is used to output a test result signal ERR to the processing circuit 10 based on the voltage level of the first test result signal ERR_r and the voltage level of the second test result signal ERR_f.

[0110] Specifically, such as Figure 5 As shown, when at least one of the first check result signal ERR_r and the second check result signal ERR_f has a first voltage level (e.g., logic "0"), the output logic gate LG_o outputs a test result signal ERR with the first voltage level. The processing circuit 10 determines that the sub-logic circuit 212 and the input / output circuit 23 are operating normally based on the test result signal ERR with the first voltage level. In other words, when at least one of the two check results generated by the sequence check circuit 210 is correct (i.e., at least one of the first check result signal ERR_r and the second check result signal ERR_f has a first voltage level), the processing circuit 10 determines that the sub-logic circuit 212 and the input / output circuit 23 are operating normally.

[0111] When both the first check result signal ERR_r and the second check result signal ERR_f have a second voltage level (e.g., logic "1") different from the first voltage level, the output logic gate LG_o outputs a test result signal ERR with the second voltage level. The processing circuit 10 determines, based on the test result signal ERR with the second voltage level, that at least one of the sub-logic circuit 212 and the input / output circuit 23 is not operating correctly. In other words, when both check results generated by the sequence check circuit 210 are incorrect (i.e., both the first check result signal ERR_r and the second check result signal ERR_f have the second voltage level), the processing circuit 10 determines that at least one of the sub-logic circuit 212 and the input / output circuit 23 is not operating correctly. Therefore, the test result signal ERR can indicate the operating status of the sub-logic circuit 212 and the input / output circuit 23 used to transmit the third data sequence CA_i.

[0112] As described above, the sequence checking circuit 210 of this disclosure is used to check the test data signal (i.e., the third data sequence CA_i) transmitted via the signal transmission path (i.e., the sub-logic circuit 212 and the input / output circuit 23) of the physical layer 20, but this disclosure is not limited thereto. In other embodiments, the sequence checking circuit 210 can receive and check the second data sequence CA_o as a test data signal to test the operating status of the sub-logic circuit 212 (i.e., the signal transmission path) separately.

[0113] In the above embodiments, the sequence generation circuit 110 is implemented using a 7th-order PRBS generator, therefore the sequence checking circuit 210 is also implemented using a 7th-order PRBS checker. For example, the number of the plurality of first flip-flops FF1 in the first shift register circuit SR1 and the number of the plurality of third flip-flops FF3 in the second shift register circuit SR2 are both 7. However, this disclosure is not limited to this. When the order of the PRBS generator changes, the number of the plurality of first flip-flops FF1 and the number of the plurality of third flip-flops FF3 will change accordingly, and the data values ​​required for the calculation of the first logic gate LG1 and the third logic gate LG3 may also be obtained from different flip-flops. In addition, the buffer time may also be lengthened or shortened as the order of the PRBS generator changes.

[0114] At Figure 1In the embodiments, when the physical layer 20 is coupled to the memory circuit, multiple input / output circuits 23[1] to 23[n-1] can be used to transmit instruction signals and / or address signals to the memory circuit, while input / output circuit 23[n] can be used to transmit clock signals to the memory circuit. In known technologies, when testing multiple input / output circuits, a specific clock signal is generated by inputting a clock signal XCK to the input / output circuit (which may have a similar delay to the test data signal due to the influence of process, voltage, and / or temperature on the input / output circuit). The remaining input / output circuits used to transmit instruction signals and / or address signals are tested based on the test data signal and the specific clock signal. The test results of the remaining input / output circuits used to transmit instruction signals and / or address signals are then used to infer whether the input / output circuit used to transmit the clock signal is operating normally.

[0115] It is worth noting that this disclosure treats the input / output circuit 23[n] used to transmit the clock signal and the remaining input / output circuits 23[1] to 23[n-1] used to transmit the command signal and / or address signal equally. That is, this disclosure allows each signal transmission path of the physical layer 20 to transmit test data signals for testing, and does not allow the clock signal XCK to be transmitted via the signal transmission path (i.e., the sub-logic circuit 212 and the input / output circuit 23). Therefore, compared with the prior art, the physical layer 20 of this disclosure does not generate a specific clock signal, making the testing and implementation process simpler. In addition, by performing two checks on the test data signal through the sequence check circuit 210, this disclosure does not need to worry about misjudging that the test data signal has an abnormal data sequence because the timing of the test data signal and the clock signal XCK originally matched has disappeared.

[0116] In the above embodiments, please also refer to Figure 1 and Figure 6A The semiconductor chip 100 is electrically coupled to the packaged memory circuit 30 only after packaging, but this disclosure is not limited to this. For example, please refer to... Figure 6B , Figure 6B This is a block diagram illustrating a semiconductor wafer 200 according to some embodiments of the present disclosure. In some embodiments, such as Figure 6B As shown, the processing circuit 10 and the physical layer 20 can be packaged together with the memory circuit 30. In other words, the semiconductor wafer 200 may include the processing circuit 10, the physical layer 20, and the memory circuit 30. In some embodiments, such as Figure 6B As shown, physical layer 20 can be directly coupled to memory circuitry 30, but this disclosure is not limited thereto. For example, please refer to... Figure 6C , Figure 6CThis is a block diagram illustrating a semiconductor wafer 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor wafer 300 may further include an interposer 40, and the physical layer 20 and the memory circuitry 30 are indirectly coupled to each other via the interposer 40. Specifically, the memory circuitry 30 may be implemented using high bandwidth memory.

[0117] As can be seen from the above-described embodiments of this disclosure, by means of a sequence check circuit, the semiconductor wafer of this disclosure can establish a data feedback pattern mechanism suitable for the instruction / address entity layer when the timing of the clock signal and the test data signal that were originally matched disappears, thereby improving the coverage of the design for testability.

[0118] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A semiconductor wafer, characterized in that, Include: A physical layer includes at least one sequence check circuit and at least one signal transmission path, wherein the at least one sequence check circuit is configured to generate at least one test result signal based on a clock signal and at least one test data signal transmitted via the at least one signal transmission path, and the clock signal is not transmitted via the at least one signal transmission path; and A processing circuit, electrically coupled to the physical layer, is used to determine the operating state of the at least one signal transmission path based on the voltage level of the at least one test result signal.

2. The semiconductor wafer according to claim 1, characterized in that, The at least one sequence checking circuit is used to check a data sequence of the at least one test data signal twice based on multiple rising edges and multiple falling edges of the clock signal.

3. The semiconductor wafer according to claim 2, characterized in that, The at least one sequence check circuit includes: A first shift register circuit is used to check the data sequence of the at least one test data signal according to the plurality of rising edges of the clock signal, so as to output a first check result signal. A second shift register circuit is used to check the data sequence of the at least one test data signal according to the plurality of falling edges of the clock signal, so as to output a second check result signal; as well as An output logic gate is used to output the at least one test result signal based on the voltage level of the first test result signal and the voltage level of the second test result signal.

4. The semiconductor wafer according to claim 3, characterized in that, The first shift register circuit includes: A plurality of first flip-flops connected in sequence are used to temporarily store a plurality of data values ​​of the data sequence of the at least one test data signal in sequence according to the plurality of rising edges of the clock signal. A first logic gate is used to calculate a first calculation logic value based on the data values ​​temporarily stored in a first and a second of the plurality of first flip-flops at a first time. A second flip-flop is used to temporarily store the first calculated logic value based on the plurality of rising edges of the clock signal; as well as A second logic gate is used to calculate a first verification logic value as the first check result signal based on the first calculated logic value and the data value temporarily stored in a third party among the plurality of first flip-flops at a second time after the first time.

5. The semiconductor wafer according to claim 3, characterized in that, The second shift register circuit includes: A plurality of third flip-flops connected in sequence are used to temporarily store a plurality of data values ​​of the data sequence of the at least one test data signal in sequence according to the plurality of falling edges of the clock signal; A third logic gate is used to calculate a second calculation logic value based on the data values ​​temporarily stored in a first and a second of the plurality of third flip-flops at a third time. A fourth flip-flop is used to temporarily store the second calculated logic value based on the plurality of falling edges of the clock signal; as well as A fourth logic gate is used to calculate a second verification logic value as the second check result signal based on the second calculated logic value and the data value temporarily stored in a third of the plurality of third flip-flops at a fourth time after the third time.

6. The semiconductor wafer according to claim 3, characterized in that, The at least one sequence check circuit also includes: A first latch circuit is coupled between the first shift register circuit and the output logic gate, and is used to selectively output the first check result signal to the output logic gate according to a control signal; as well as A second latching circuit is coupled between the second shift register circuit and the output logic gate, and is used to selectively output the second check result signal to the output logic gate according to the control signal.

7. The semiconductor wafer according to claim 3, characterized in that, When at least one of the first test result signal and the second test result signal has a first voltage level, the output logic gate outputs the at least one test result signal having the first voltage level, and the processing circuit determines that the at least one signal transmission path is operating normally based on the at least one test result signal having the first voltage level. When both the first test result signal and the second test result signal have a second voltage level different from the first voltage level, the output logic gate outputs the at least one test result signal with the second voltage level, and the processing circuit determines that the at least one signal transmission path is not operating normally based on the at least one test result signal with the second voltage level.

8. The semiconductor wafer according to claim 2, characterized in that, If at least one of the two check results generated by the at least one sequence check circuit is correct, the processing circuit determines that the at least one signal transmission path is operating normally.

9. The semiconductor wafer according to claim 2, characterized in that, The data sequence of the at least one test data signal is generated by at least one sequence generation circuit included in the processing circuit.

10. The semiconductor wafer according to claim 9, characterized in that, The at least one sequence generation circuit is a pseudo-random binary sequence generator.

11. The semiconductor wafer according to claim 1, characterized in that, The semiconductor chip also includes a memory circuit that is electrically coupled to the physical layer.

12. The semiconductor wafer according to claim 11, characterized in that, The semiconductor chip also includes an interposer layer, and the physical layer and the memory circuit are coupled to each other via the interposer layer.

13. A sequence checking circuit, characterized in that, This sequence check circuit is used to check a test data signal transmitted via a signal transmission path through a physical layer, and includes: A first shift register circuit is used to perform a first check on a data sequence of a test data signal based on multiple rising edges of a clock signal, so as to output a first check result signal. A second shift register circuit is used to perform a second check on the data sequence of the test data signal based on multiple falling edges of the clock signal, so as to output a second check result signal; as well as An output logic gate is used to output a test result signal based on the voltage level of the first test result signal and the voltage level of the second test result signal, wherein the test result signal is used to indicate the operating status of the signal transmission path. The clock signal was not transmitted through the signal transmission path.

14. The sequence checking circuit according to claim 13, characterized in that, The first shift register circuit includes: A plurality of first flip-flops connected in sequence are used to temporarily store a plurality of data values ​​of the data sequence of the test data signal according to the plurality of rising edges of the clock signal. A first logic gate is used to calculate a first calculation logic value based on the data values ​​temporarily stored in a first and a second of the plurality of first flip-flops at a first time. A second flip-flop is used to temporarily store the first calculated logic value based on the plurality of rising edges of the clock signal; as well as A second logic gate is used to calculate a first verification logic value as the first check result signal based on the first calculated logic value and the data value temporarily stored in a third party among the plurality of first flip-flops at a second time after the first time.

15. The sequence checking circuit according to claim 14, characterized in that, The first logic gate and the second logic gate are each XOR gates.

16. The sequence checking circuit according to claim 13, characterized in that, The second shift register circuit includes: Multiple third flip-flops connected in sequence are used to temporarily store multiple data values ​​of the data sequence of the test data signal according to the multiple falling edges of the clock signal. A third logic gate is used to calculate a second calculation logic value based on the data values ​​temporarily stored in a first and a second of the plurality of third flip-flops at a third time. A fourth flip-flop is used to temporarily store the second calculated logic value based on the plurality of falling edges of the clock signal; as well as A fourth logic gate is used to calculate a second verification logic value as the second check result signal based on the second calculated logic value and the data value temporarily stored in a third of the plurality of third flip-flops at a fourth time after the third time.

17. The sequence checking circuit according to claim 16, characterized in that, The third and fourth logic gates are each XOR gates.

18. The sequence checking circuit according to claim 13, characterized in that, The sequence checking circuit also includes: A first latch circuit is coupled between the first shift register circuit and the output logic gate, and is used to selectively output the first check result signal to the output logic gate according to a control signal; as well as A second latching circuit is coupled between the second shift register circuit and the output logic gate, and is used to selectively output the second check result signal to the output logic gate according to the control signal.

19. The sequence checking circuit according to claim 13, characterized in that, The output logic gate is an AND gate.

20. The sequence checking circuit according to claim 13, characterized in that, The signal transmission path includes a sub-logic circuit and an input / output circuit. The sub-logic circuit is used to receive at least a first data sequence and output a second data sequence, and the input / output circuit is used to receive the second data sequence and output a third data sequence. The second data sequence or the third data sequence is used as the test data signal.

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