Laminated coil component

Abstract

The first outer conductor layer of the laminated coil component has a first portion overlapping, when viewed from the stacking direction, a portion of the second external electrode provided on the first main surface of the green sheet, a gap layer is provided at least one of the entire first inner interface and the second inner interface, and when at least one cross section of the first portion of the first outer conductor layer is observed along the stacking direction and in a direction orthogonal to the direction in which the first portion of the first outer conductor layer extends when viewed from the stacking direction, the gap layer is not provided at both the first outer interface and the second outer interface.

Description

Technical Field

[0001] This invention relates to laminated coil components. Background Technology

[0002] Patent Document 1 discloses a multilayer inductor, which is a multilayer inductor formed by firing a multilayer of a magnetic paste and a conductive paste formed by mixing a binder in magnetic powder. The inductor is characterized by having a gap between the conductor layer forming the internal coil and the magnetic layer.

[0003] Patent Document 1: Japanese Patent Application Publication No. 11-219821

[0004] In the multilayer inductor described in Patent Document 1, a gap is provided between the magnetic layer and the conductor layer in the stacking direction, so it is not affected by the stress of the conductor layer on the magnetic layer, that is, a stress mitigation effect can be obtained. However, the inventors have conducted research and found that if the multilayer inductor described in Patent Document 1 is mounted on a substrate or other mounting object, there is a concern that due to the impact load applied to the multilayer inductor in the stacking direction, cracks may be generated in the magnetic layer, starting from the gap between the conductor layer and the magnetic layer located at the outermost position in the stacking direction and overlapping with the external electrode in the stacking direction. Summary of the Invention

[0005] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a laminated coil component that can alleviate the stress generated inside the blank and suppress the generation of cracks in the insulation layer during installation.

[0006] The stacked coil component of the present invention is characterized by comprising: a blank body formed by stacking multiple insulating layers in a stacking direction; multiple conductor layers disposed inside the blank body and stacked together with the multiple insulating layers in the stacking direction; and multiple external electrodes disposed on the surface of the blank body. The blank body has a first main surface and a second main surface opposite to each other in the stacking direction. A coil electrically connected to the multiple external electrodes is formed by electrically connecting at least a portion of the multiple conductor layers. The multiple conductor layers include a first outer conductor layer located at the outermost position of the first main surface side of the blank body in the stacking direction, a second outer conductor layer located at the outermost position of the second main surface side of the blank body in the stacking direction, and at least one inner conductor layer located between the first outer conductor layer and the second outer conductor layer in the stacking direction. The multiple external electrodes include a first external electrode disposed at least on the first main surface of the blank body, and a second outer conductor layer disposed at least on the first main surface of the blank body that is separated from the first external electrode and is not electrically connected to the first outer conductor layer in the direction along the first outer conductor layer. For each of the aforementioned inner conductor layers, a first inner interface is formed between the first main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer; and a second inner interface is formed between the second main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer. Similarly, a first outer conductor layer forms a first outer interface between the first main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer; and a second outer interface is formed between the second main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer. An outer conductor layer has a first portion that overlaps with a portion of the first main surface of the second outer electrode disposed on the blank when viewed from the stacking direction. A void layer is provided at least one of the first inner interfaces and the second inner interfaces. When viewing at least one cross-section of the first portion of the first outer conductor layer along the stacking direction and in a direction orthogonal to the direction in which the first portion of the first outer conductor layer extends when viewed from the stacking direction, the void layer is not provided at either the first outer interface or the second outer interface.

[0007] According to the present invention, a laminated coil component is provided that can mitigate stress generated inside the blank and suppress the generation of cracks in the insulation layer during installation. Attached Figure Description

[0008] Figure 1 This is a perspective view showing an example of a stacked coil component of the present invention.

[0009] Figure 2 It means Figure 1 A schematic cross-sectional view of an example of a stacked coil component along line segment a1-a2.

[0010] Figure 3 It means Figure 1 A schematic cross-sectional view of an example of a stacked coil component along line segment b1-b2.

[0011] Figure 4 This indicates a perspective view from the first principal surface of the blank. Figure 2 as well as Figure 3 A plan view of the state of the stacked coil component shown.

[0012] Figure 5 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0013] Figure 6 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0014] Figure 7 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0015] Figure 8 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0016] Figure 9 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0017] Figure 10 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0018] Figure 11 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0019] Figure 12 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0020] Figure 13 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0021] Figure 14 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0022] Figure 15 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0023] Figure 16 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0024] Figure 17 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0025] Figure 18 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0026] Figure 19 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0027] Figure 20 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0028] Figure 21 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0029] Figure 22 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0030] Figure 23 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0031] Figure 24 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0032] Figure 25 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 1 as viewed from the first main surface of the blank.

[0033] Figure 26This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 2 as viewed from the first main surface of the blank.

[0034] Figure 27 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 3 as viewed from the first main surface of the blank.

[0035] Figure 28 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 4 as viewed from the first main surface of the blank.

[0036] Figure 29 This is a planar schematic diagram showing the state of the stacked coil component of Comparative Example 1 when viewed from the first main surface of the blank. Detailed Implementation

[0037] The laminated coil component of the present invention will now be described. It should be noted that the present invention is not limited to the following structure, and appropriate modifications can be made without departing from the spirit of the invention. Furthermore, structures combining multiple preferred structures described below also fall under the scope of the present invention.

[0038] The attached diagrams are schematic diagrams and may differ from the actual product in dimensions, aspect ratio, scale, etc.

[0039] In this specification, terms indicating the relationship between elements (e.g., "parallel", "orthogonal", etc.) and terms indicating the shape of elements not only indicate a strict literal manner but also a range equivalent to reality, such as a range containing a few percent of the difference.

[0040] The stacked coil component of the present invention is characterized by comprising: a blank formed by stacking multiple insulating layers in a stacking direction; multiple conductor layers disposed inside the blank and stacked together with the multiple insulating layers in the stacking direction; and multiple external electrodes disposed on the surface of the blank. The blank has a first main surface and a second main surface opposite to each other in the stacking direction. A coil electrically connected to the multiple external electrodes is formed by electrically connecting at least a portion of the multiple conductor layers. The multiple conductor layers include a first outer conductor layer located at the outermost position on the first main surface side of the blank in the stacking direction, a second outer conductor layer located at the outermost position on the second main surface side of the blank in the stacking direction, and at least one inner conductor layer located between the first outer conductor layer and the second outer conductor layer in the stacking direction. The multiple external electrodes include a first external electrode disposed at least on the first main surface of the blank, and a second external electrode disposed at least on the first main surface of the blank and separated from the first external electrode, and not electrically connected to the first outer conductor layer in the direction along the first outer conductor layer. For each of the aforementioned inner conductor layers, a first inner interface is formed between the first main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer; and a second inner interface is formed between the second main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer. Similarly, a first outer conductor layer forms a first outer interface between the first main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer; and a second outer interface is formed between the second main surface side of the blank in the aforementioned stacking direction and the adjacent insulating layer. An outer conductor layer has a first portion that overlaps with a portion of the first main surface of the second outer electrode disposed on the blank when viewed from the stacking direction. A void layer is provided at least one of the first inner interfaces and the second inner interfaces. When viewing at least one cross-section of the first portion of the first outer conductor layer along the stacking direction and in a direction orthogonal to the direction in which the first portion of the first outer conductor layer extends when viewed from the stacking direction, the void layer is not provided at either the first outer interface or the second outer interface.

[0041] Figure 1 This is a perspective view showing an example of a stacked coil component of the present invention. Figure 2 It means Figure 1 A schematic cross-sectional view of an example of a stacked coil component along line segment a1-a2. Figure 3 It means Figure 1 A schematic cross-sectional view of an example of a stacked coil component along line segment b1-b2.

[0042] Figure 1 , Figure 2 ,as well as Figure 3 The stacked coil component 1 shown has a blank 10, a coil 20, a first external electrode 31, and a second external electrode 32.

[0043] In this instruction manual, such as Figure 1 As shown, the length, height, and width directions are defined by L, T, and W, respectively. Here, the length direction L, height direction T, and width direction W are orthogonal to each other.

[0044] like Figure 1 As shown, the blank 10 has a first end face 11a and a second end face 11b opposite each other in the length direction L, a first main face 12a and a second main face 12b opposite each other in the height direction T, and a first side face 13a and a second side face 13b opposite each other in the width direction W, and is, for example, in a cuboid shape. In this specification, a cuboid shape is any shape that can actually be described as a cuboid, such as a generally cuboid shape that includes rounded corners and edges as described later.

[0045] The first end face 11a and the second end face 11b of the billet 10 do not need to be strictly orthogonal to the length direction L. Furthermore, the first main face 12a and the second main face 12b of the billet 10 do not need to be strictly orthogonal to the height direction T. Also, the first side face 13a and the second side face 13b of the billet 10 do not need to be strictly orthogonal to the width direction W.

[0046] In this specification, the height direction is shown as the vertical direction, the first main surface of the blank is shown as the lower side, and the second main surface of the blank is shown as the upper side, but it is not limited to these directions and can be appropriately changed according to the state of setting the stacked coil components.

[0047] exist Figure 1 , Figure 2 ,as well as, Figure 3 In the example shown, the first main surface 12a of the blank 10 is the mounting surface that faces the mounting object (e.g., substrate) when the stacked coil component 1 is mounted. In the stacked coil component 1, the mounting surface of the blank 10 can also be marked for easy understanding; here, the first main surface 12a of the blank 10 is marked.

[0048] Preferably, the corners and edges of the billet 10 are rounded. The corners of the billet 10 are the parts where three faces of the billet 10 intersect. The edges of the billet 10 are the parts where two faces of the billet 10 intersect.

[0049] like Figure 2 as well as Figure 3As shown, the blank 10 is formed by stacking multiple insulating layers in the stacking direction.

[0050] exist Figure 2 as well as Figure 3 In the example shown, the blank 10 is formed by stacking multiple insulating layers, including insulating layers 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i, in the height direction T.

[0051] exist Figure 2 as well as Figure 3 In the example shown, the blank 10 includes insulating layers 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i in sequence from the first main surface 12a side toward the second main surface 12b side in the height direction T.

[0052] exist Figure 2 as well as Figure 3 In the example shown, the stacking direction of the multiple insulating layers is parallel to the height direction T. In other words, in Figure 2 as well as Figure 3 In the example shown, the stacking direction of the multiple insulating layers is orthogonal to the first main surface 12a of the blank 10, which serves as the mounting surface.

[0053] In addition, although Figure 2 as well as Figure 3 For ease of explanation, the boundaries between multiple insulating layers are shown in the image, but these boundaries are not actually clearly visible.

[0054] As constituent materials of various insulating layers, examples include magnetic ferrite materials and non-magnetic ferrite materials.

[0055] The preferred magnetic ferrite material comprises Fe, Zn, Cu, and Ni. In this case, the magnetic ferrite material preferably contains, when the total amount is set to 100 mol%, 40 mol% to 49.5 mol% of Fe (converted to Fe₂O₃), 5 mol% to 35 mol% of Zn (converted to ZnO), 4 mol% to 12 mol% of Cu (converted to CuO), and the remainder of Ni (converted to NiO). Furthermore, the magnetic ferrite material may further contain additives such as Mn, Co, Sn, Bi, and Si, and may also contain unavoidable impurities.

[0056] The preferred non-magnetic ferrite material comprises Fe, Cu, and Zn. In this case, the non-magnetic ferrite material preferably contains 40 mol% to 49.5 mol% Fe (converted to Fe₂O₃), 6 mol% to 12 mol% Cu (converted to CuO), and the remainder Zn (converted to ZnO) when the total amount is set to 100 mol%. Furthermore, the non-magnetic ferrite material may further contain additives such as Mn, Co, Sn, Bi, and Si, and may also contain unavoidable impurities.

[0057] The materials that make up each insulating layer can be the same, different from each other, or different in some parts.

[0058] The thickness of each insulating layer (here, the dimension in the height direction T) can be the same, different, or different in some parts.

[0059] like Figure 2 as well as Figure 3 As shown, a coil 20 is formed by electrically connecting at least a portion of a plurality of conductor layers. The plurality of conductor layers are disposed inside the blank 10 and are stacked together with a plurality of insulating layers in the stacking direction.

[0060] exist Figure 2 as well as Figure 3 In the example shown, a plurality of conductor layers, including a first outer conductor layer 21, a second outer conductor layer 22, an inner conductor layer 23a, and an inner conductor layer 23b, are provided inside the blank 10.

[0061] The first outer conductor layer 21 is located at the outermost position of the first main surface 12a side of the blank 10 in the stacking direction (here, the height direction T) among the multiple conductor layers.

[0062] The second outer conductor layer 22 is located at the outermost position on the second main surface 12b side of the blank 10 in the stacking direction (here, the height direction T) among the multiple conductor layers.

[0063] Therefore, of the first outer conductor layer 21 and the second outer conductor layer 22, the first outer conductor layer 21 is located on the mounting surface side of the blank 10, specifically on the first main surface 12a side of the blank 10, while the second outer conductor layer 22 is located on the opposite side to the mounting surface of the blank 10, specifically on the second main surface 12b side of the blank 10. In other words, during the mounting of the stacked coil component 1, in the stacking direction (here, the height direction T), the first outer conductor layer 21 is closer to the object being mounted than the second outer conductor layer 22.

[0064] The inner conductor layer 23a and the inner conductor layer 23b are located between the first outer conductor layer 21 and the second outer conductor layer 22 in the stacking direction (here, the height direction T) among the multiple conductor layers.

[0065] Although Figure 2 as well as Figure 3 In the diagram, inner conductor layers 23a and 23b are shown as inner conductor layers existing between the first outer conductor layer 21 and the second outer conductor layer 22 in the stacking direction (here, the height direction T). However, at least one inner conductor layer may exist in addition to inner conductor layers 23a and 23b. Furthermore, the number of inner conductor layers may be either multiple or single.

[0066] exist Figure 2 as well as Figure 3 In the example shown, the first outer conductor layer 21, the second outer conductor layer 22, the inner conductor layer 23a, and the inner conductor layer 23b are stacked together in the height direction T along with the insulating layers 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, and 15i.

[0067] exist Figure 2 as well as Figure 3 In the example shown, a first outer conductor layer 21, an inner conductor layer 23a, an inner conductor layer 23b, and a second outer conductor layer 22 are sequentially stacked in the height direction T from the first main surface 12a side of the blank 10 toward the second main surface 12b side.

[0068] exist Figure 2 as well as Figure 3 In the example shown, coil 20 is formed by electrically connecting all the conductor layers, including the first outer conductor layer 21, the second outer conductor layer 22, the inner conductor layer 23a, and the inner conductor layer 23b.

[0069] exist Figure 3 In the example shown, the first outer conductor layer 21 and the inner conductor layer 23a are electrically connected via a connecting conductor 24a.

[0070] A pad portion is provided at a position that is continuous with the end of the first outer conductor layer 21, and at least connected to the connecting conductor 24a. Similarly, a pad portion is provided at a position that is continuous with the end of the inner conductor layer 23a, and at least connected to the connecting conductor 24a.

[0071] exist Figure 3 In the example shown, the second outer conductor layer 22 and the inner conductor layer 23b are electrically connected via a connecting conductor 24b.

[0072] A pad portion is provided at a position that is continuous with the end of the second outer conductor layer 22, and is at least connected to the connecting conductor 24b. Similarly, a pad portion is provided at a position that is continuous with the end of the inner conductor layer 23b, and is at least connected to the connecting conductor 24b.

[0073] In this specification, the pad portion is not included in the outer conductor layer and the inner conductor layer. The pad portion refers to the area including the portion connected to the connection conductor when viewed from the stack-up direction (here, the height direction T), and having an area of ​​120% of the area of ​​the portion connected to the connection conductor.

[0074] exist Figure 2 as well as Figure 3 In the example shown, the stacking direction of the multiple conductor layers is parallel to the height direction T. In other words, in Figure 2 as well as Figure 3 In the example shown, the stacking direction of the multiple conductor layers is orthogonal to the first main surface 12a of the blank 10, which serves as the mounting surface.

[0075] exist Figure 2 In the example shown, the coil axis C of coil 20 extends in the height direction T. In other words, in Figure 2 In the example shown, the direction of the coil axis C of the coil 20 is orthogonal to the first main surface 12a of the blank 10, which serves as the mounting surface.

[0076] Based on the above, Figure 2 as well as Figure 3 In the example shown, the stacking directions of the multiple insulating layers, the stacking directions of the multiple conductor layers, and the direction of the coil axis C of the coil 20 are all along the same height direction T, and are orthogonal to the first main surface 12a of the blank 10, which serves as the mounting surface.

[0077] When viewed from the stacking direction (here, the height direction T), each conductor layer can be a shape consisting only of straight sections, a shape consisting only of curved sections, or a shape consisting of both straight and curved sections. In other words, when viewed from the stacking direction (here, the height direction T), the coil 20 can be a shape consisting only of straight sections, a shape consisting only of curved sections, or a shape consisting of both straight and curved sections. For example, when viewed from the stacking direction (here, the height direction T), the coil 20 can be a polygon, a circle, or an ellipse.

[0078] Materials used to form the various conductor layers include, for example, Ag, Au, Cu, Pd, Ni, Al, and alloys containing at least one of these metals.

[0079] The thickness of each conductor layer (here, the dimension in the height direction T) can be the same, different, or different in some parts.

[0080] As constituent materials of each connecting conductor, examples include Ag, Au, Cu, Pd, Ni, Al, and alloys containing at least one of these metals.

[0081] The thickness of each connecting conductor (here, the dimension in the height direction T) can be the same, different, or different in a portion.

[0082] like Figure 2 As shown, coil 20 is electrically connected to the first external electrode 31.

[0083] exist Figure 2 In the example shown, the first outer conductor layer 21 constituting the coil 20 is electrically connected to the first external electrode 31 via a first lead-out conductor 25a located at one end of the first outer conductor layer 21. More specifically, in Figure 2 In the example shown, the first lead conductor 25a is exposed at the first end face 11a of the blank 10, and the first external electrode 31 is connected to the exposed portion of the first lead conductor 25a.

[0084] like Figure 2 As shown, coil 20 is electrically connected to the second external electrode 32.

[0085] exist Figure 2 In the example shown, the second outer conductor layer 22 constituting the coil 20 is electrically connected to the second external electrode 32 via a second lead-out conductor 25b located at one end of the second outer conductor layer 22. More specifically, in Figure 2 In the example shown, the second lead conductor 25b is exposed on the second end face 11b of the blank 10, and the second external electrode 32 is connected to the exposed portion of the second lead conductor 25b.

[0086] In this specification, the lead-out conductor is included in the outer conductor layer and the inner conductor layer.

[0087] The constituent materials of each lead conductor include, for example, Ag, Au, Cu, Pd, Ni, Al, and alloys containing at least one of these metals.

[0088] The thickness of each lead-out conductor (here, the dimension in the height direction T) can be the same, different, or different in a portion.

[0089] like Figure 1 As shown, the first external electrode 31 is disposed on the surface of the blank 10. More specifically, the first external electrode 31 is disposed at least on the first main surface 12a of the blank 10. Furthermore, as... Figure 1 As shown, the first external electrode 31 can also be disposed on the second main surface 12b of the blank 10, in addition to the first main surface 12a of the blank 10. Figure 1 In the example shown, the first external electrode 31 extends from the first end face 11a of the blank 10 to a portion of each of the first main face 12a, the second main face 12b, the first side face 13a, and the second side face 13b.

[0090] The configuration of the first external electrode 31 is not limited to Figure 1 As shown. For example, the first external electrode 31 may also extend from a portion of the first main surface 12a of the blank 10 to a portion of each of the first end surface 11a, the first side surface 13a, and the second side surface 13b.

[0091] like Figure 1 As shown, the second external electrode 32 is disposed on the surface of the blank 10. More specifically, the second external electrode 32 is disposed at least on the first main surface 12a of the blank 10. Furthermore, as... Figure 1 As shown, the second external electrode 32 can also be disposed on the second main surface 12b of the billet 10, in addition to the first main surface 12a. Figure 1 In the example shown, the second external electrode 32 extends from the second end face 11b of the blank 10 to a portion of each of the first main face 12a, the second main face 12b, the first side face 13a, and the second side face 13b.

[0092] The configuration of the second external electrode 32 is not limited to Figure 1 As shown. For example, the second external electrode 32 may also extend from a portion of the first main surface 12a of the blank 10 to a portion of each of the second end surface 11b, the first side surface 13a, and the second side surface 13b.

[0093] As described above, the second external electrode 32 is configured to be separated from the first external electrode 31 (here, it is configured to be separated in the length direction L).

[0094] If, as described above, the first external electrode 31 and the second external electrode 32 are disposed on the first main surface 12a of the blank 10, which serves as the mounting surface, the mountability of the stacked coil component 1 is easily improved.

[0095] like Figure 2 As shown, the second external electrode 32 is not electrically connected to the first external conductor layer 21 in the direction along the first external conductor layer 21.

[0096] In the stacked coil component 1, as long as the second external electrode 32 is not electrically connected to the first outer conductor layer 21 in the direction along the first outer conductor layer 21, other connection methods between the conductor layer and the external electrode are not particularly limited, but... Figure 2 The example shown is in the following manner.

[0097] exist Figure 2 In the example shown, the first external electrode 31 is electrically connected to the first outer conductor layer 21 in the direction along the first outer conductor layer 21.

[0098] exist Figure 2 In the example shown, the first external electrode 31 is not electrically connected to the second external conductor layer 22 in the direction along the second external conductor layer 22.

[0099] exist Figure 2 In the example shown, the second external electrode 32 is electrically connected to the second outer conductor layer 22 in the direction along the second outer conductor layer 22.

[0100] In this specification, the direction along the outer conductor layer is approximately equivalent to the direction of the surface extending (which includes the outer conductor layer and is orthogonal to the stacking direction (here, the height direction T) and includes the length direction L and the width direction W).

[0101] Each of the first external electrode 31 and the second external electrode 32 can have a single-layer structure or a multi-layer structure.

[0102] When the first external electrode 31 and the second external electrode 32 each have a single-layer structure, the constituent materials of each external electrode can be, for example, Ag, Au, Cu, Pd, Ni, Al, and alloys containing at least one of these metals.

[0103] When the first external electrode 31 and the second external electrode 32 have a multilayer structure, each external electrode can sequentially have, for example, a substrate electrode containing Ag, a Ni-plated electrode, and a Sn-plated electrode from the surface side of the blank 10.

[0104] like Figure 2 as well as Figure 3 As shown, each inner conductor layer forms a first inner interface with the adjacent insulating layer on the first main surface 12a side of the blank 10 in the stacking direction (here, the height direction T), and forms a second inner interface with the adjacent insulating layer on the second main surface 12b side of the blank 10 in the stacking direction (here, the height direction T).

[0105] In this specification, the interface between the conductor layer and the insulating layer refers to the interface between the conductor layer and the insulating layer along a planar direction (here, a direction including the length direction L and the width direction W) orthogonal to the stacking direction (here, the height direction T).

[0106] like Figure 2 as well as Figure 3 As shown, at least one of the first inner interfaces and the second inner interface is provided with a void layer 40.

[0107] exist Figure 2 as well as Figure 3 In the example shown, a void layer 40 is provided at the first inner interface between the inner conductor layer 23a and the insulating layer 15c, and at the first inner interface between the inner conductor layer 23b and the insulating layer 15e.

[0108] Alternatively, a void layer 40 may be provided at the second inner interface of the insulating layer other than the inner conductor layer 23a and the insulating layer 15c. Alternatively, a void layer 40 may be provided at the second inner interface of the insulating layer other than the inner conductor layer 23b and the insulating layer 15e.

[0109] In addition, although Figure 2 as well as Figure 3 In the figure, other inner conductor layers besides inner conductor layer 23a and inner conductor layer 23b are not shown. However, if such other inner conductor layers are present, a void layer 40 may be provided at least one of the first inner interface and the second inner interface between the other inner conductor layer and the insulating layer.

[0110] As described above, it is sufficient to have a gap layer 40 on at least one of the first inner interfaces and the second inner interfaces. Furthermore, when observing interfaces on both the first and second inner interfaces where the gap layer 40 is provided, the gap layer 40 can be provided either on the entire interface or on a portion of the interface.

[0111] Preferably, a gap layer 40 is provided in at least a portion of each of the first and second inner interfaces. For example, if there are ten locations for the first and second inner interfaces, it is preferable that a gap layer 40 is provided in at least a portion of each of the ten locations. In this case, it is more preferable that the gap layer 40 is provided entirely on at least one of the first and second inner interfaces. More specifically, the gap layer 40 may be provided entirely on one of the first and second inner interfaces, or it may be provided entirely on both the first and second inner interfaces.

[0112] In the laminated coil component 1, by providing a void layer 40 at at least one of the first inner interfaces and the second inner interfaces, the stress generated inside the blank 10 due to the difference in thermal shrinkage rates between the inner conductor layer and the insulating layer can be mitigated.

[0113] When mounting a conventional multilayer coil component, such as the multilayer inductor described in Patent Document 1, onto a substrate or other mounting object, an impact load is applied to the multilayer coil component in the stacking direction. At this time, since a gap corresponding to the thickness of the external electrode is generated between the mounting surface of the blank and the mounting object, stress caused by the impact load is applied to the blank in the direction from the surface opposite to the mounting surface in the stacking direction towards the mounting surface. If the stress caused by the impact load is applied to the blank in this way, due to the reaction from the mounting object, other stresses are applied in the opposite direction to the stress caused by the impact load, particularly to the external electrode present near the mounting surface of the blank and its surrounding insulating layer. As described above, since two stresses are applied to the multilayer coil component, tensile stress is generated inside the blank, resulting in deformation of the blank. At this point, the tensile stress in the insulating layer constituting the mounting surface of the blank is concentrated at the interface with the void layer, compared to the interface with the external electrode. This void layer is located at the interface between the conductor layer and the insulating layer at the outermost position on the mounting surface side in the stacking direction, and overlaps with the external electrode in the stacking direction. Furthermore, if the tensile stress is greater than the strength of the insulating layer, cracks will be generated in the insulating layer, starting from the void layer. When the distribution of tensile stress generated in the blank during the mounting of a stacked coil component was simulated using the finite element method analysis software "Femtet" (registered trademark) manufactured by Murata Software Co., Ltd., it was confirmed that the tensile stress in the insulating layer constituting the mounting surface of the blank is distributed as described above.

[0114] In contrast, the stacked coil component 1 has the following structure.

[0115] like Figure 2 as well as Figure 3 As shown, the first outer conductor layer 21 forms a first outer interface with the adjacent insulating layer 15a on the first main surface 12a side of the blank 10 in the stacking direction (here, the height direction T), and forms a second outer interface with the adjacent insulating layer 15c on the second main surface 12b side of the blank 10 in the stacking direction (here, the height direction T).

[0116] Figure 4 This indicates a perspective view from the first principal surface of the blank. Figure 2 as well as Figure 3 A plan view of the state of the stacked coil component shown.

[0117] In addition, Figure 4In this diagram, to focus on the first outer conductor layer 21 and the void layer 40, the first outer electrode 31, the second outer electrode 32, and the insulating layer 15a are shown in perspective. In fact, when viewing the stacked coil component 1 from the first main surface 12a side of the blank 10, the insulating layer 15a overlaps with the first outer conductor layer 21 and the void layer 40 closer to them, but... Figure 4 The insulating layer 15a, which overlaps with the first outer conductor layer 21 and the void layer 40, is not shown in the diagram.

[0118] like Figure 4 As shown, the first outer conductor layer 21 has a first portion 21a that partially overlaps with the portion of the second outer electrode 32 disposed on the first main surface 12a of the blank 10 when viewed from the stacking direction (here, the height direction T). Figure 4 In the example shown, the first portion 21a of the first outer conductor layer 21 extends toward the short side of the blank 10 (here, the width direction W).

[0119] Figure 4 The cross-sections of the structure shown are along the length direction L and the height direction T as follows: Figure 2 As shown. Figure 2 As shown, when observing along the stacking direction (in Figure 2 In the middle, it is the height direction T), and in the stacking direction (in Figure 2 In the middle, (referring to the direction of height T) when viewed from the perspective of the first outer conductor layer 21, the direction in which the first portion 21a extends is perpendicular to the first outer conductor layer 21. Figure 2 In the middle, the direction orthogonal to the width direction W) is (in Figure 2 In the middle, when at least one cross-section of the first portion 21a of the first outer conductor layer 21 (in the length direction L), at the first outer interface (in Figure 2 In the middle, is the interface between the first portion 21a of the first outer conductor layer 21 and the insulating layer 15a) and the second outer interface (in Figure 2 In the middle, there is no gap layer 40 between the first part 21a of the first outer conductor layer 21 and the insulating layer 15c.

[0120] In the stacked coil component 1, as long as the observation is along the stacking direction (in Figure 2 In the middle, it is the height direction T), and in the stacking direction (in Figure 2 In the middle, (referring to the direction of height T) when viewed from the perspective of the first outer conductor layer 21, the direction in which the first portion 21a extends is perpendicular to the first outer conductor layer 21. Figure 2 In the middle, the direction orthogonal to the width direction W) is (in Figure 2In the case of a cross-section of the first portion 21a of the first outer conductor layer 21 along the length direction L), if at least one cross-section of the first portion 21a of the first outer conductor layer 21 has no void layer 40 provided on either the first outer interface or the second outer interface, then the configuration of the void layer 40 on the other cross-sections is not particularly limited, but... Figure 2 as well as Figure 4 The example shown is in the following manner.

[0121] exist Figure 2 as well as Figure 4 In the example shown, at least a portion of the area overlapping the first portion 21a of the first outer conductor layer 21 with the first outer interface of the first outer conductor layer 21 and the insulating layer 15a when viewed from the stacking direction (here, the height direction T) is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, as... Figure 2 As shown, even when an impact load D is applied to the laminated coil component 1 in the stacking direction (here, the height direction T), the tensile stress generated by the insulating layer 15a around the first portion 21a of the first outer conductor layer 21 can be mitigated. Therefore, during the installation of the laminated coil component 1, the generation of cracks in the insulating layer 15a around the first portion 21a of the first outer conductor layer 21 can be suppressed.

[0122] Similarly, in Figure 2 as well as Figure 4 In the example shown, at least a portion of the area overlapping the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15c around the first portion 21a of the first outer conductor layer 21 can be mitigated. Thus, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15c around the first portion 21a of the first outer conductor layer 21 can be suppressed.

[0123] In this specification, the manner in which at least a portion of the area overlapping the object portion (e.g., the first portion) of the outer conductor layer at the interface between the outer conductor layer and the insulating layer is not provided with a gap layer indicates that, in a direction orthogonal to the direction extending from the object portion (e.g., the first portion) of the outer conductor layer when viewed from the stacking direction (here, the height direction T), there is at least one location at the interface between the object portion (e.g., the first portion) of the outer conductor layer and the insulating layer where the entire area from one end of the object portion (e.g., the first portion) of the outer conductor layer is not provided with a gap layer.

[0124] like Figure 4 As shown, preferably, at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, the entire area overlapping the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15a around the first portion 21a of the first outer conductor layer 21 can be sufficiently mitigated. Consequently, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15a around the first portion 21a of the first outer conductor layer 21 can be sufficiently suppressed.

[0125] Similarly, preferably, at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, the entire area overlapping the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15c around the first portion 21a of the first outer conductor layer 21 can be sufficiently mitigated. Thus, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15c around the first portion 21a of the first outer conductor layer 21 can be sufficiently suppressed.

[0126] Based on the above, it is more preferable that at least one of the first outer interface and the second outer interface, in the region where it overlaps with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), is entirely free of the void layer 40. In this case, it is more preferable that both the first outer interface and the second outer interface, in the region where they overlap with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), are entirely free of the void layer 40.

[0127] like Figure 4 As shown, the first outer conductor layer 21 may also have a second portion 21b that partially overlaps with the portion of the first outer electrode 31 disposed on the first main surface 12a of the blank 10 when viewed from the stacking direction (here, the height direction T). Figure 4 In the example shown, a portion of the second part 21b of the first outer conductor layer 21 extends toward the short side of the blank 10 (here, the width direction W).

[0128] like Figure 4As shown, preferably, at least a portion of the area overlapping the second portion 21b of the first outer conductor layer 21 with the insulating layer 15a at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, when viewed from the stacking direction (here, the height direction T), is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15a around the second portion 21b of the first outer conductor layer 21 can be mitigated. Thus, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15a around the second portion 21b of the first outer conductor layer 21 can be suppressed.

[0129] Similarly, preferably, at least a portion of the area overlapping the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15c around the second portion 21b of the first outer conductor layer 21 can be mitigated. Thus, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15c around the second portion 21b of the first outer conductor layer 21 can be suppressed.

[0130] Based on the above, it is more preferable that at least a portion of the area where the first outer interface and the second outer interface overlap with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40. In this case, it is more preferable that at least a portion of the area where the first outer interface and the second outer interface overlap with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40.

[0131] Preferably, at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, the entire area overlapping the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is free of a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15a around the second portion 21b of the first outer conductor layer 21 can be sufficiently mitigated. Consequently, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15a around the second portion 21b of the first outer conductor layer 21 can be sufficiently suppressed.

[0132] Similarly, preferably, at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, the entire area overlapping the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is not provided with a gap layer 40. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15c around the second portion 21b of the first outer conductor layer 21 can be sufficiently mitigated. Thus, during the installation of the stacked coil component 1, the generation of cracks in the insulating layer 15c around the second portion 21b of the first outer conductor layer 21 can be sufficiently suppressed.

[0133] Based on the above, it is more preferable that at least one of the first outer interface and the second outer interface, in the region where it overlaps with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), is entirely free of the void layer 40. In this case, it is even more preferable that both the first outer interface and the second outer interface, in the region where they overlap with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), are entirely free of the void layer 40.

[0134] From the viewpoint of suppressing the generation of cracks in the insulating layers 15a and 15c around the first portion 21a and the second portion 21b of the first outer conductor layer 21 during the installation of the laminated coil component 1, it is particularly preferable that the entire area of ​​the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, which overlaps with the first portion 21a and the second portion 21b of the first outer conductor layer 21 when viewed from the lamination direction, and the entire area of ​​the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, which overlaps with the first portion 21a and the second portion 21b of the first outer conductor layer 21 when viewed from the lamination direction, is not provided with a gap layer 40.

[0135] like Figure 4 As shown, the first outer conductor layer 21 may also have a first portion 21a that overlaps with the portion of the second outer electrode 32 disposed on the first main surface 12a of the blank 10 when viewed from the stacking direction (here, the height direction T), a second portion 21b that overlaps with the portion of the first outer electrode 31 disposed on the first main surface 12a of the blank 10 when viewed from the stacking direction (here, the height direction T), and a third portion 21c other than the first portion 21a and the second portion 21b. Figure 4 In the example shown, the third portion 21c of the first outer conductor layer 21 extends toward the long side of the blank 10 (here, the length direction L).

[0136] like Figure 4As shown, preferably, on the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, the following regions are excluded: the entire area overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); the entire area overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); and the region overlapping with the third portion 21c of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), where the length of the region extending from the ends E1 and E2 on both sides of the first external electrode 31 side and the second external electrode 32 side to the third portion 21c of the first outer conductor layer 21, respectively. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15a around the first portion 21a and the second portion 21b of the first outer conductor layer 21 can be sufficiently mitigated. Therefore, during the installation of the laminated coil component 1, the generation of cracks in the insulating layer 15a around the first portion 21a and the second portion 21b of the first outer conductor layer 21 can be sufficiently suppressed.

[0137] Similarly, preferably, on the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, the following regions are excluded: the entire area overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); the entire area overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); and the region overlapping with the third portion 21c of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), where the length is at least 20% of the dimension extending from the ends of both sides of the first external electrode 31 side and the second external electrode 32 side to the third portion 21c of the first outer conductor layer 21. Therefore, during the installation of the stacked coil component 1, the tensile stress generated by the insulating layer 15c around the first portion 21a and the second portion 21b of the first outer conductor layer 21 can be sufficiently mitigated. Therefore, during the installation of the laminated coil component 1, the generation of cracks in the insulating layer 15c around the first portion 21a and the second portion 21b of the first outer conductor layer 21 can be sufficiently suppressed.

[0138] Based on the above, more preferably, a void layer 40 is not provided in the following regions: the entire region overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); the entire region overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); and the region overlapping with the third portion 21c of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), in which the length is more than 20% of the dimension in the direction extending from the ends of both sides of the first external electrode 31 side and the second external electrode 32 side to the third portion 21c of the first outer conductor layer 21. In this case, more preferably, the void layer 40 is not provided in the following regions on both the first outer interface and the second outer interface: the entire region overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); the entire region overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T); and the region overlapping with the third portion 21c of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T), where the length is more than 20% of the dimension in the direction extending from the ends on both sides of the first outer electrode 31 side and the second outer electrode 32 side to the third portion 21c of the first outer conductor layer 21.

[0139] Preferably, no gap layer 40 is provided at the entire first outer interface between the first outer conductor layer 21 and the insulation layer 15a. Therefore, during the installation of the laminated coil component 1, there are no locations of tensile stress concentration in the insulation layer 15a around the first outer conductor layer 21. Consequently, during the installation of the laminated coil component 1, the generation of cracks in the insulation layer 15a around the first outer conductor layer 21 can be significantly suppressed.

[0140] Similarly, it is preferable that the entire second outer interface between the first outer conductor layer 21 and the insulating layer 15c is free of gaps 40. Therefore, during the installation of the laminated coil component 1, there are no locations of tensile stress concentration in the insulating layer 15c around the first outer conductor layer 21. Consequently, during the installation of the laminated coil component 1, the generation of cracks in the insulating layer 15c around the first outer conductor layer 21 can be significantly suppressed.

[0141] Based on the above, it is more preferable that at least one of the first outer interface and the second outer interface is not provided with a void layer 40. In this case, it is even more preferable that both the first outer interface and the second outer interface are not provided with a void layer 40.

[0142] Preferably, the area ratio of the void layer 40 to the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a is lower than the area ratio of the void layer 40 to the inner conductor layer at all the first inner interfaces and at least one of the second inner interfaces (e.g., the first inner interface between the inner conductor layer 23a and the insulating layer 15c).

[0143] In the laminated coil component 1, as described above, at least a portion of the area overlapping the first portion 21a of the first outer conductor layer 21 when viewed from the lamination direction (here, the height direction T) at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a is not provided with a gap layer 40. Therefore, the area ratio of the gap layer 40 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a to the first outer conductor layer 21 is less than 100%. On the other hand, for example, when the entire first inner interface between the inner conductor layer 23a and the insulating layer 15c is provided with a gap layer 40, the area ratio of the gap layer 40 at the first inner interface between the inner conductor layer 23a and the insulating layer 15c to the inner conductor layer 23a is 100%. In this case, the area ratio of the void layer 40 at the first outer interface of the first outer conductor layer 21 to the first outer conductor layer 21 is lower than the area ratio of the void layer 40 at the first inner interface of the inner conductor layer 23a to the inner conductor layer 23a.

[0144] The area ratio of the void layer 40 at the first outer interface of the first outer conductor layer 21 and the insulating layer 15a to the first outer conductor layer 21 is less than 100%, preferably less than 50%, and particularly preferably 0%.

[0145] Similarly, preferably, the area ratio of the void layer 40 to the first outer conductor layer 21 at the second outer interface of the first outer conductor layer 21 and the insulating layer 15c is lower than the area ratio of the void layer 40 to the inner conductor layer at at least one of the first inner interfaces and the second inner interfaces of the inner conductor layer and the insulating layer (e.g., the first inner interface of the inner conductor layer 23a and the insulating layer 15c).

[0146] The area ratio of the void layer 40 at the second outer interface of the first outer conductor layer 21 and the insulating layer 15c to the first outer conductor layer 21 is less than 100%, preferably less than 50%, and particularly preferably 0%.

[0147] Based on the above, it is more preferable that the area ratio of the void layer 40 to the first outer conductor layer 21 on at least one of the first outer interface and the second outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on at least one of the first inner interfaces and the second inner interfaces (e.g., the first inner interface between the inner conductor layer 23a and the insulating layer 15c). In this case, it is more preferable that the area ratio of the void layer 40 to the first outer conductor layer 21 on both the first outer interface and the second outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on at least one of the first inner interfaces and the second inner interfaces (e.g., the first inner interface between the inner conductor layer 23a and the insulating layer 15c). Furthermore, it is particularly preferable that the area ratio of the void layer 40 to the first outer conductor layer 21 on both the first outer interface and the second outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on all the first inner interfaces and the second inner interfaces.

[0148] At the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, the area ratio of the void layer 40 to the area overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, preferably less than 40%, more preferably less than 25%, and particularly preferably 0%.

[0149] Similarly, at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, the area ratio of the void layer 40 to the area overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, preferably less than 40%, more preferably less than 25%, and particularly preferably 0%.

[0150] Based on the above, on both the first outer interface and the second outer interface, the area ratio of the void layer 40 to the area overlapping with the first portion 21a of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, preferably less than 40%, more preferably less than 25%, and particularly preferably 0%.

[0151] Preferably, at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, the area ratio of the void layer 40 to the area overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0152] Similarly, preferably at the second outer interface between the first outer conductor layer 21 and the insulating layer 15c, the area ratio of the void layer 40 to the area overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0153] Based on the above, preferably, on both the first outer interface and the second outer interface, the area ratio of the void layer 40 to the area overlapping with the second portion 21b of the first outer conductor layer 21 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0154] Preferably, the various states at the interface between the first outer conductor layer 21 and the insulating layer are as follows, and the same applies at the interface between the second outer conductor layer 22 and the insulating layer.

[0155] The second outer conductor layer 22 may also form a third outer interface between the first main surface 12a side of the blank 10 in the stacking direction (here, the height direction T) and the adjacent insulating layer 15g, and may also form a fourth outer interface between the second main surface 12b side of the blank 10 in the stacking direction (here, the height direction T) and the adjacent insulating layer 15i.

[0156] The second outer conductor layer 22 may also have a first portion that overlaps with the portion of the first outer electrode 31 disposed on the second main surface 12b of the blank 10 when viewed from the stacking direction (here, the height direction T).

[0157] Preferably, at least a portion of the area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) at the third outer interface between the second outer conductor layer 22 and the insulating layer 15g is not provided with a void layer 40.

[0158] Similarly, preferably, at least a portion of the area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) at the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i is not provided with a void layer 40.

[0159] Based on the above, it is more preferable that at least a portion of the area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 on at least one of the third outer interface and the fourth outer interface. In this case, it is more preferable that at least a portion of the area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 on both the third outer interface and the fourth outer interface.

[0160] Preferably, on the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, the entire area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40.

[0161] Similarly, preferably, on the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, the entire area overlapping with the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40.

[0162] Based on the above, it is more preferable that at least one of the third and fourth outer interfaces, in the region where it overlaps with the first portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), is entirely free of the void layer 40. In this case, it is more preferable that at both the third and fourth outer interfaces, in the region where it overlaps with the first portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), the void layer 40 is entirely free of the void layer 40.

[0163] The second outer conductor layer 22 may also have a second portion that overlaps with a portion of the second outer electrode 32 disposed on the second main surface 12b of the blank 10 when viewed from the stacking direction (here, the height direction T).

[0164] Preferably, at least a portion of the area where the second outer conductor layer 22 overlaps with the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 at the third outer interface between the second outer conductor layer 22 and the insulating layer 15g.

[0165] Similarly, preferably, at least a portion of the area where the second outer conductor layer 22 overlaps with the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 at the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i.

[0166] Based on the above, it is more preferable that at least a portion of the area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 on at least one of the third outer interface and the fourth outer interface. In this case, it is more preferable that at least a portion of the area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40 on both the third outer interface and the fourth outer interface.

[0167] Preferably, on the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, the entire area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40.

[0168] Similarly, preferably, on the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, the entire area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is not provided with a void layer 40.

[0169] Based on the above, it is more preferable that at least one of the third and fourth outer interfaces, in the region where it overlaps with the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), the entire area is not provided with a void layer 40. In this case, it is more preferable that at both the third and fourth outer interfaces, in the region where it overlaps with the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), the entire area is not provided with a void layer 40.

[0170] It is particularly preferred that the entire area of ​​the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, which overlaps with the first and second portions of the second outer conductor layer 22 when viewed from the stacking direction, and the entire area of ​​the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, which overlaps with the first and second portions of the second outer conductor layer 22 when viewed from the stacking direction, are not provided with a void layer 40.

[0171] The second outer conductor layer 22 may also have a first portion that overlaps with the portion of the first outer electrode 31 disposed on the second main surface 12b of the blank 10 when viewed from the stacking direction (here, the height direction T), a second portion that overlaps with the portion of the second outer electrode 32 disposed on the second main surface 12b of the blank 10 when viewed from the stacking direction (here, the height direction T), and a third portion other than the first portion and the second portion.

[0172] Preferably, on the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, a void layer 40 is not provided in the following regions: the entire area overlapping the first portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T); the entire area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T); and the area overlapping the third portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), where the length is at least 20% of the dimension extending from the ends on both sides of the first outer electrode 31 side and the second outer electrode 32 side to the third portion of the second outer conductor layer 22.

[0173] Similarly, preferably, on the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, the region that overlaps with the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), the region that overlaps with the second part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), and the region that overlaps with the third part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), where the length is more than 20% of the dimension in the direction extending from the ends on both sides of the first outer electrode 31 side and the second outer electrode 32 side to the third part of the second outer conductor layer 22, respectively, is not provided with a void layer 40.

[0174] Based on the above, more preferably, a void layer 40 is not provided in at least one of the third outer interface and the fourth outer interface, in the entire region that overlaps with the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), in the entire region that overlaps with the second part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), and in the region that overlaps with the third part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), in the region extending in the direction from the ends of both sides of the first outer electrode 31 side and the second outer electrode 32 side to the third part of the second outer conductor layer 22. In this case, more preferably, the void layer 40 is not provided in the following regions on both the third and fourth outer interfaces: the entire region overlapping with the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T); the entire region overlapping with the second part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T); and the region overlapping with the third part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T), where the void layer 40 extends in a direction that is more than 20% of the dimension of the region extending from the ends on both sides of the first outer electrode 31 side and the second outer electrode 32 side to the third part of the second outer conductor layer 22.

[0175] Preferably, the entire third outer interface between the second outer conductor layer 22 and the insulating layer 15g is free of voids 40.

[0176] Similarly, it is preferable that the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i is not provided with a void layer 40.

[0177] Based on the above, it is more preferable that the void layer 40 is not provided on at least one of the third outer interface and the fourth outer interface. In this case, it is more preferable that the void layer 40 is not provided on both the third outer interface and the fourth outer interface.

[0178] Preferably, the area ratio of the void layer 40 to the second outer conductor layer 22 at the third outer interface of the second outer conductor layer 22 and the insulating layer 15g is lower than the area ratio of the void layer 40 to the inner conductor layer at all the first inner interfaces and at least one of the second inner interfaces (e.g., the first inner interface of the inner conductor layer 23b and the insulating layer 15e).

[0179] Preferably, the area ratio of the void layer 40 at the third outer interface of the second outer conductor layer 22 and the insulating layer 15g to the second outer conductor layer 22 is less than 100%, more preferably less than 50%, and particularly preferably 0%.

[0180] Similarly, preferably, the area ratio of the void layer 40 to the second outer conductor layer 22 at the fourth outer interface of the second outer conductor layer 22 and the insulating layer 15i is lower than the area ratio of the void layer 40 to the inner conductor layer at all the first inner interfaces and at least one of the second inner interfaces (e.g., the first inner interface of the inner conductor layer 23b and the insulating layer 15e).

[0181] Preferably, the area ratio of the void layer 40 on the fourth outer interface of the second outer conductor layer 22 and the insulating layer 15i to the second outer conductor layer 22 is less than 100%, more preferably less than 50%, and particularly preferably 0%.

[0182] Based on the above, it is more preferable that the area ratio of the void layer 40 to the second outer conductor layer 22 on at least one of the third outer interface and the fourth outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on at least one of the first inner interfaces and the second inner interfaces (e.g., the first inner interface between the inner conductor layer 23b and the insulating layer 15e). In this case, it is more preferable that the area ratio of the void layer 40 to the second outer conductor layer 22 on both the third outer interface and the fourth outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on at least one of the first inner interfaces and the second inner interfaces (e.g., the first inner interface between the inner conductor layer 23b and the insulating layer 15e). Furthermore, it is particularly preferable that the area ratio of the void layer 40 to the second outer conductor layer 22 on both the third outer interface and the fourth outer interface is lower than the area ratio of the void layer 40 to the inner conductor layer on all the first inner interfaces and the second inner interfaces.

[0183] Preferably, at the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, the area ratio of the void layer 40 to the area overlapping the first portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0184] Similarly, preferably at the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, the area ratio of the void layer 40 to the area overlapping the first portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0185] Based on the above, preferably on both the third and fourth outer interfaces, the area ratio of the void layer 40 to the area overlapping the first part of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0186] Preferably, at the third outer interface between the second outer conductor layer 22 and the insulating layer 15g, the area ratio of the void layer 40 to the area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0187] Similarly, preferably at the fourth outer interface between the second outer conductor layer 22 and the insulating layer 15i, the area ratio of the void layer 40 to the area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0188] Based on the above, preferably on both the third and fourth outer interfaces, the area ratio of the void layer 40 to the area overlapping the second portion of the second outer conductor layer 22 when viewed from the stacking direction (here, the height direction T) is less than 100%, more preferably less than 40%, further preferably less than 25%, and particularly preferably 0%.

[0189] The stacked coil component 1 can be manufactured, for example, by the following method.

[0190] <Process for preparing magnetic ferrite paste>

[0191] First, Fe₂O₃, ZnO, CuO, and NiO are weighed to the specified composition. At this point, additives such as Mn, Co, Sn, Bi, and Si may also be added. Next, these weighed materials are wet-mixed and pulverized. Then, the resulting pulverized material is dried and calcined. The calcination temperature is, for example, above 700°C and below 800°C. This process produces a powdered magnetic ferrite material.

[0192] The preferred magnetic ferrite material, when the total amount is set to 100 mol%, contains 40 mol% or more and 49.5 mol% of Fe (converted to Fe2O3), 5 mol% or more and 35 mol% of Zn (converted to ZnO), 4 mol% or more and 12 mol% of Cu (converted to CuO), and the remaining portion of Ni (converted to NiO).

[0193] Next, a specified amount of solvents such as ketone solvents, resins such as polyvinyl acetal, and plasticizers such as alkyd plasticizers are added to the magnetic ferrite material. The mixture is then stirred using a planetary mixer or similar equipment and dispersed using a three-roll mill or similar equipment to produce a magnetic ferrite paste.

[0194] <Process for preparing non-magnetic ferrite paste>

[0195] First, Fe₂O₃, CuO, and ZnO are weighed to the specified composition. At this point, additives such as Mn, Co, Sn, Bi, and Si may also be added. Next, these weighed materials are wet-mixed and pulverized. Then, the resulting pulverized material is dried and calcined. The calcination temperature is, for example, above 700°C and below 800°C. This process produces a powdered, non-magnetic ferrite material.

[0196] The non-magnetic ferrite material is preferably defined as follows: when the total amount is set to 100 mol%, Fe is converted to Fe2O3 and contains more than 40 mol% and less than 49.5 mol%, Cu is converted to CuO and contains more than 6 mol% and less than 12 mol%, and Zn is converted to ZnO and includes the remainder.

[0197] Next, a specified amount of solvents such as ketone solvents, resins such as polyvinyl acetal, and plasticizers such as alkyd plasticizers are added to the non-magnetic ferrite material. The mixture is then stirred using a planetary mixer or similar equipment and dispersed using a three-roll mill or similar equipment to produce a non-magnetic ferrite paste.

[0198] <Preparation of Resin Paste>

[0199] A resin paste is prepared by mixing resins such as acrylic resins with solvents such as dihydrorosinol acetate.

[0200] <Process for preparing conductor paste>

[0201] Conductor paste is prepared by adding a specified amount of solvents such as eugenol, resins such as ethyl cellulose, and dispersants to Ag powder, mixing it with a planetary mixer, and then dispersing it using a three-roll mill.

[0202] <Process of making layered blocks>

[0203] Figures 5 to 24 This is a plan view illustrating the process of fabricating a stacked block in one example of the manufacturing method of the stacked coil component of the present invention.

[0204] A substrate (not shown) is prepared on which a heat-release sheet and a polyethylene terephthalate (PET) film are sequentially laminated on the surface of a metal plate. Then, a magnetic ferrite paste is printed onto the substrate to form... Figure 5 The magnetic ferrite paste layer 115a is shown as described. After the firing process described later, the magnetic ferrite paste layer 115a becomes the insulating layer 15a in the laminated coil component 1.

[0205] By printing resin paste at specified positions on the magnetic ferrite paste layer 115a, a magnetic ferrite paste layer is formed. Figure 6 The resin paste layer 140 is as shown. Figure 6 After firing, the resin paste layer 140 shown becomes a void layer 40 disposed on the first outer interface between the first outer conductor layer 21 and the insulating layer 15a in the laminated coil component 1.

[0206] By printing conductor paste at specified positions on the magnetic ferrite paste layer 115a, a magnetic ferrite paste layer is formed. Figure 7 The conductor paste layer 125a is shown as described below. After firing, the conductor paste layer 125a becomes part of the first lead conductor 25a in the laminated coil component 1. By pre-forming the conductor paste layer 125a, the thickness of the first lead conductor 25a in the subsequently obtained laminated coil component 1 can be made greater than the thickness of the first outer conductor layer 21 other than the first lead conductor 25a. In this way, if the first lead conductor 25a is formed thicker in the subsequently obtained laminated coil component 1, the sealing performance of the laminated coil component 1 can be easily improved.

[0207] A conductor paste is formed by printing conductor paste at a location overlapping a portion of the magnetic ferrite paste layer 115a, the conductor paste layer 125a, and the resin paste layer 140. Figure 8 The conductor paste layer 121 is shown as such. A portion of the conductor paste layer 121, after being fired as described later, becomes the first outer conductor layer 21 in the laminated coil component 1.

[0208] By printing magnetic ferrite paste in the areas where the conductor paste layer 121 has not been formed, a magnetic ferrite paste is formed. Figure 9 The magnetic ferrite paste layer 115b is as shown. It is preferable that the magnetic ferrite paste layer 115b be formed to have the same thickness as the conductor paste layer 121. After firing as described later, the magnetic ferrite paste layer 115b becomes the insulating layer 15b in the laminated coil component 1.

[0209] By means of conductor paste layer 121 and conductor paste layer 125a (refer to) Figure 7 On the opposite side, near the front end, a conductor paste is printed to form... Figure 10 The conductor paste layer 124a is as shown. Preferably, the size of the conductor paste layer 124a is smaller than the size of the conductor paste layer 121 in a direction orthogonal to the direction in which the conductor paste layer 121 extends. After firing, the conductor paste layer 124a becomes the connecting conductor 24a in the laminated coil component 1.

[0210] By printing a non-magnetic ferrite paste at a location overlapping a portion of the conductor paste layer 121, a... Figure 11The non-magnetic ferrite paste layer 115ca is shown. At this time, the non-magnetic ferrite paste layer 115ca is formed with an opening at the location where the conductor paste layer 124a is formed. After firing, as described later, the non-magnetic ferrite paste layer 115ca becomes part of the insulating layer 15c in the laminated coil component 1. Thus, in the laminated coil component 1 obtained later, if the insulating layer (here, the insulating layer 15c) between the conductor layers constituting the coil 20 contains a non-magnetic ferrite material, the laminated coil component 1 is less prone to magnetic saturation, and therefore the DC overlap characteristic of the laminated coil component 1 is easily improved.

[0211] By printing magnetic ferrite paste in the areas where the non-magnetic ferrite paste layer 115ca and the conductor paste layer 124a are not formed, a magnetic ferrite paste is formed. Figure 12 The magnetic ferrite paste layer 115cb is as shown. The magnetic ferrite paste layer 115cb is the same as the non-magnetic ferrite paste layer 115ca, and after firing as described later, it becomes part of the insulating layer 15c in the laminated coil component 1.

[0212] A resin paste is formed by printing resin paste at predetermined locations on a portion of each of the non-magnetic ferrite paste layer 115ca and the magnetic ferrite paste layer 115cb. Figure 13 The resin paste layer 140 is as shown. Figure 13 After firing, the resin paste layer 140 shown becomes a void layer 40 disposed on the first inner interface between the inner conductor layer 23a and the insulating layer 15c in the laminated coil component 1.

[0213] A conductive paste is formed by printing conductive paste at a location overlapping a portion of the non-magnetic ferrite paste layer 115ca, the conductive paste layer 124a, and the resin paste layer 140. Figure 14 The conductor paste layer 123a is as shown. Thus, conductor paste layer 121 and conductor paste layer 123a are electrically connected via conductor paste layer 124a. In this case, it is preferable that the size of conductor paste layer 123a at the location where it connects to conductor paste layer 124a (including the pad portion) is the same as the size of conductor paste layer 124a in a direction orthogonal to the extending direction of conductor paste layer 123a. In other words, it is preferable that the size of conductor paste layer 123a at the location where it connects to conductor paste layer 124a (including the pad portion) is the same as the size of conductor paste layer 124a in a direction orthogonal to the extending direction of conductor paste layer 123a, and is smaller than the size of conductor paste layer 121. After the firing process described later, conductor paste layer 123a becomes the inner conductor layer 23a in the laminated coil component 1.

[0214] By printing magnetic ferrite paste in the area where the conductor paste layer 123a has not been formed, a magnetic ferrite paste is formed. Figure 15The magnetic ferrite paste layer 115d is shown as described. After firing, as described later, the magnetic ferrite paste layer 115d becomes the insulating layer 15d in the laminated coil component 1.

[0215] Then, repeat the above process. The following explains the final process performed after the above steps when creating layered blocks. Furthermore, although in the above... Figure 15 The process shown is the same as that described later. Figure 16 Several processes are involved between the processes shown, but their descriptions are omitted.

[0216] By printing magnetic ferrite paste in the area where the conductor paste layer 123b has not been formed, a magnetic ferrite paste is formed. Figure 16 The magnetic ferrite paste layer 115f is shown as described. After firing as described later, the magnetic ferrite paste layer 115f becomes the insulating layer 15f in the laminated coil component 1. After firing as described later, the conductor paste layer 123b becomes the inner conductor layer 23b in the laminated coil component 1. Furthermore, the non-magnetic ferrite paste layer 115ea and the magnetic ferrite paste layer 115eb, which are located below the magnetic ferrite paste layer 115f, become part of the insulating layer 15e in the laminated coil component 1, respectively, after firing as described later.

[0217] By printing conductor paste near one of the front ends of conductor paste layer 123b, a conductor paste is formed. Figure 17 The conductor paste layer 124b is shown as described below. After firing, the conductor paste layer 124b becomes the connecting conductor 24b in the laminated coil component 1.

[0218] A non-magnetic ferrite paste is formed by printing a portion of the magnetic ferrite paste layer 115f and a portion of the conductor paste layer 123b. Figure 18 The non-magnetic ferrite paste layer 115ga is shown. At this time, the non-magnetic ferrite paste layer 115ga is formed with an opening at the location where the conductor paste layer 124b is formed. After firing, as described later, the non-magnetic ferrite paste layer 115ga becomes part of the insulating layer 15g in the laminated coil component 1.

[0219] By printing magnetic ferrite paste in the areas where no non-magnetic ferrite paste layer 115ga and conductor paste layer 124b are formed, a magnetic ferrite paste is formed. Figure 19 The magnetic ferrite paste layer 115gb is as shown. The magnetic ferrite paste layer 115gb is the same as the non-magnetic ferrite paste layer 115ga, and after firing as described later, it becomes part of the insulating layer 15g in the laminated coil component 1.

[0220] A resin paste is formed by printing resin paste at predetermined positions on a portion of each of the non-magnetic ferrite paste layer 115ga and the magnetic ferrite paste layer 115gb. Figure 20 The resin paste layer 140 is as shown. Figure 20 After firing, the resin paste layer 140 shown becomes a void layer 40 disposed on the third outer interface between the second outer conductor layer 22 and the insulating layer 15g in the laminated coil component 1.

[0221] By printing conductor paste at specified positions on a magnetic ferrite paste layer 115gb, a conductor paste is formed. Figure 21 The conductor paste layer 125b is shown as described below. After firing, the conductor paste layer 125b becomes part of the second lead conductor 25b in the laminated coil component 1. By pre-forming the conductor paste layer 125b, the thickness of the second lead conductor 25b in the subsequently obtained laminated coil component 1 can be made greater than the thickness of the second outer conductor layer 22 other than the second lead conductor 25b. Thus, if the second lead conductor 25b is formed thicker in the subsequently obtained laminated coil component 1, the sealing performance of the laminated coil component 1 can be easily improved.

[0222] Conductor paste is formed by printing conductor paste at a location overlapping with a portion of the non-magnetic ferrite paste layer 115ga, conductor paste layer 124b, conductor paste layer 125b, and resin paste layer 140. Figure 22 The conductor paste layer 122 is as shown. Thus, the conductor paste layer 122 and the conductor paste layer 123b are electrically connected via the conductor paste layer 124b. Preferably, the dimensions of the conductor paste layer 122 at the location where it connects to the conductor paste layer 124b (including the pad portion) are the same as the dimensions of the conductor paste layer 124b, in a direction orthogonal to the direction in which the conductor paste layer 122 extends. A portion of the conductor paste layer 122, after being fired as described later, becomes the second outer conductor layer 22 in the laminated coil component 1.

[0223] By printing magnetic ferrite paste in the areas where the conductor paste layer 122 has not been formed, a magnetic ferrite paste is formed. Figure 23 The magnetic ferrite paste layer 115h is as shown. It is preferable that the magnetic ferrite paste layer 115h be formed to have the same thickness as the conductor paste layer 122. After firing as described later, the magnetic ferrite paste layer 115h becomes the insulating layer 15h in the laminated coil component 1.

[0224] By printing magnetic ferrite paste onto the magnetic ferrite paste layer 115h and the conductor paste layer 122, a magnetic ferrite paste is formed. Figure 24 The magnetic ferrite paste layer 115i is shown as described. After firing, as described later, the magnetic ferrite paste layer 115i becomes the insulating layer 15i in the laminated coil component 1.

[0225] Through the above, a multilayered block of conductor paste layers and resin paste layers is formed inside a multilayered body consisting of multiple layers of magnetic ferrite paste and non-magnetic ferrite paste.

[0226] <Processes for making the blank and coil>

[0227] First, the stacked blocks are cut into specified sizes using a dicing machine or similar equipment to create monolithic chips. Then, the resulting chips are burned into the substrate.

[0228] If the chip is burned, as described above, the magnetic ferrite paste layer and the non-magnetic ferrite paste layer become insulating layers (e.g., insulating layer 15a, etc.), the conductor paste layer becomes a conductor layer (e.g., first outer conductor layer 21, second outer conductor layer 22, inner conductor layer 23a, inner conductor layer 23b, etc.), or becomes a conductor (e.g., connecting conductor 24a, connecting conductor 24b, first lead conductor 25a, second lead conductor 25b, etc.), and the resin paste layer becomes a void layer (e.g., void layer 40).

[0229] Based on the above, the production Figure 2 as well as Figure 3 The blank 10 is formed by stacking multiple insulating layers in the stacking direction (here, the height direction T), as shown, and the coil 20 is disposed inside the blank 10 and electrically connected to multiple conductor layers stacked in the stacking direction (here, the height direction T) via connecting conductors. Here, the first lead conductor 25a is exposed at the first end face 11a of the blank 10, and the second lead conductor 25b is exposed at the second end face 11b of the blank 10.

[0230] For the blank 10, for example, the corners and edges can be rounded by putting it into a rotary drum mill together with the medium for drum grinding.

[0231] <Process for forming external electrodes>

[0232] First, by coating a conductive paste, such as a paste containing Ag and glass frit, a first coating film is formed that connects to the first lead conductor 25a exposed on the first end face 11a of the blank 10, extending from the first end face 11a of the blank 10 to a portion of each of the first main face 12a, the second main face 12b, the first side face 13a, and the second side face 13b.

[0233] In addition, by coating a conductive paste, such as a paste containing Ag and glass frit, a second coating film connected to the second lead conductor 25b exposed on the second end face 11b of the blank 10 is formed as a portion of each of the surfaces extending from the second end face 11b of the blank 10 to the first main surface 12a, the second main surface 12b, the first side surface 13a, and the second side surface 13b.

[0234] In this way, a first coating and a second coating are formed at positions on the surface of the blank 10 that are separated from each other (here, positions that are separated in the length direction L).

[0235] When forming the first coating film and the second coating film, the first coating film and the second coating film can be formed at different times or at the same time.

[0236] When the first coating and the second coating are formed at different times, they can be formed either in the order of the first coating and the second coating, or in the order of the second coating and the first coating.

[0237] Next, by firing the first coating film, a first base electrode is formed extending from the first end face 11a of the blank 10 to a portion of each of the first main face 12a, the second main face 12b, the first side face 13a, and the second side face 13b, and connected to the first lead conductor 25a.

[0238] In addition, by firing the second coating film, a second base electrode is formed extending from the second end face 11b of the blank 10 to a portion of each of the first main face 12a, the second main face 12b, the first side face 13a, and the second side face 13b, and connected to the second lead conductor 25b.

[0239] Then, by electroplating or the like, a Ni-plated electrode and a Sn-plated electrode are sequentially formed on the surface of the first base electrode. Thus, an external electrode is formed having the first base electrode, the Ni-plated electrode, and the Sn-plated electrode sequentially from the surface side of the blank 10, as an example of the first external electrode 31.

[0240] Furthermore, a Ni-plated electrode and a Sn-plated electrode are sequentially formed on the surface of the second base electrode by electroplating or the like. Thus, an external electrode is formed having the second base electrode, the Ni-plated electrode, and the Sn-plated electrode sequentially from the surface side of the blank 10, as an example of the second external electrode 32.

[0241] In this way, a first external electrode 31 electrically connected to the coil 20 via a first lead conductor 25a and a second external electrode 32 electrically connected to the coil 20 via a second lead conductor 25b are formed on the surface of the blank 10, more specifically, at least on the first main surface 12a of the blank 10.

[0242] Through the above, the laminated coil component 1 is manufactured.

[0243] In the stacked coil component 1, both the first outer conductor layer 21 and the second outer conductor layer 22, together with the inner conductor layer including the inner conductor layer 23a and the inner conductor layer 23b, constitute the coil 20. However, at least one of the first outer conductor layer 21 and the second outer conductor layer 22 may not constitute the coil 20. In other words, the conductor layer constituting the coil 20 may include only the first outer conductor layer 21, only the second outer conductor layer 22, both the first outer conductor layer 21 and the second outer conductor layer 22, or neither the first outer conductor layer 21 nor the second outer conductor layer 22 may be included.

[0244] If at least one of the first outer conductor layer 21 and the second outer conductor layer 22 does not constitute the coil 20, the outer conductor layer that does not constitute the coil 20 may also constitute a dummy coil different from the coil 20. Alternatively, if at least one of the first outer conductor layer 21 and the second outer conductor layer 22 does not constitute the coil 20, the inner conductor layer (e.g., the inner conductor layer 23a) may be electrically connected to the outer electrode in the direction along the inner conductor layer.

[0245]

Example

[0246] The following describes specific embodiments of the laminated coil component of the present invention. However, the present invention is not limited to these embodiments.

[0247] [Example 1]

[0248] As a simulation model of the laminated coil component of Embodiment 1 (hereinafter referred to only as "the laminated coil component of Embodiment 1"), it adopts a configuration other than the void layer on the first outer interface, and is similar to... Figure 1 , Figure 2 , Figure 3 ,as well as Figure 4 The structure is the same as that of the stacked coil component 1 shown.

[0249] Figure 25 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 1 as viewed from the first main surface of the blank.

[0250] like Figure 25 As shown, in the stacked coil component of Embodiment 1, a gap layer is set throughout the first outer interface between the first outer conductor layer 21 and the insulation layer 15a.

[0251] In the stacked coil component of Embodiment 1, it is configured as follows: Figure 25The various dimensions and distances shown.

[0252] • Dimension P along the length L of the laminated coil component: 2040 μm

[0253] • The distance Q1 between the outermost positions of the first external electrode 31 along the length direction L is 450 μm

[0254] • The distance Q2 between the outermost positions along the length direction L of the second external electrode 32 is 450 μm

[0255] • The distance R between the outermost positions along the length direction L of the first outer conductor layer 21 is 1640 μm

[0256] • The distance S between the outermost positions in the width direction W of the first outer conductor layer 21: 1040 μm

[0257] • The dimension F of the region on the first outer interface that overlaps with the third portion 21c of the first outer conductor layer 21 in the direction in which the third portion 21c of the first outer conductor layer 21 extends (here, the length direction L): 1140 μm

[0258] In addition, in the stacked coil component of Embodiment 1, it is configured as follows.

[0259] • Average thickness of the external electrode (here, the average dimension along the length direction L or width direction W): 30 μm

[0260] • Average width of the conductor layer (here, the average dimension along the length direction L or the width direction W): 210 μm

[0261] • Average thickness of the void layer (here, the average dimension along the height direction T): 5 μm

[0262] • Average width of the void layer (here, the average dimension along the length direction L or the width direction W): 210 μm

[0263] [Example 2]

[0264] As a simulation model of the stacked coil component of Embodiment 2 (hereinafter referred to as "the stacked coil component of Embodiment 2"), it adopts the same structure as the stacked coil component of Embodiment 1, except for the configuration of the void layer on the first outer interface.

[0265] Figure 26 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 2 as viewed from the first main surface of the blank.

[0266] like Figure 26As shown, in the laminated coil component of Embodiment 2, the gap layer 40 is not provided in a portion of the area overlapping with the first portion 21a of the first outer conductor layer 21 and a portion of the area overlapping with the second portion 21b of the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a. In other words, in the laminated coil component of Embodiment 2, the gap layer 40 is provided in the entirety of the area overlapping with the first portion 21a of the first outer conductor layer 21, the second portion 21b of the first outer conductor layer 21, and the third portion 21c of the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a.

[0267] [Example 3]

[0268] As a model for simulating the stacked coil component of Embodiment 3 (hereinafter referred to as "the stacked coil component of Embodiment 3"), it adopts the same structure as the stacked coil component of Embodiment 1, except for the configuration of the void layer on the first outer interface.

[0269] Figure 27 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 3 as viewed from the first main surface of the blank.

[0270] like Figure 27 As shown, in the laminated coil component of Embodiment 3, the entire region overlapping with the first portion 21a of the first outer conductor layer 21 and the entire region overlapping with the second portion 21b of the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a is provided with a gap layer 40. In other words, in the laminated coil component of Embodiment 3, the entire region overlapping with the third portion 21c of the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a is provided with a gap layer 40.

[0271] [Example 4]

[0272] As a simulation model of the stacked coil component of Embodiment 4 (hereinafter referred to as "the stacked coil component of Embodiment 4"), it adopts the same structure as the stacked coil component of Embodiment 1, except for the configuration of the void layer on the first outer interface.

[0273] Figure 28 This is a planar schematic diagram showing the state of the stacked coil component of Embodiment 4 as viewed from the first main surface of the blank.

[0274] like Figure 28As shown, in the stacked coil component of Embodiment 4, a gap layer 40 is not provided in a region on the first outer interface between the first outer conductor layer 21 and the insulating layer 15a, specifically in the entire region overlapping with the first portion 21a of the first outer conductor layer 21, the entire region overlapping with the second portion 21b of the first outer conductor layer 21, and the region overlapping with the third portion 21c of the first outer conductor layer 21, extending in a direction from the ends of both sides of the first external electrode 31 side and the second external electrode 32 side to the third portion 21c of the first outer conductor layer 21. In other words, in the stacked coil component of Embodiment 4, a gap layer 40 is provided in a portion of the region on the first outer interface between the first outer conductor layer 21 and the insulating layer 15a that overlaps with the third portion 21c of the first outer conductor layer 21.

[0275] [Comparative Example 1]

[0276] The simulation model of the stacked coil component of Comparative Example 1 (hereinafter referred to as "the stacked coil component of Comparative Example 1") adopts the same structure as the stacked coil component of Example 1, except for the configuration of the void layer on the first outer interface.

[0277] Figure 29 This is a planar schematic diagram showing the state of the stacked coil component of Comparative Example 1 when viewed from the first main surface of the blank.

[0278] like Figure 29 As shown, in the stacked coil component of Comparative Example 1, a void layer 40 is provided integrally at the first outer interface between the first outer conductor layer 21 and the first outer insulating layer 15a.

[0279] [evaluate]

[0280] Using the finite element method analysis software "Femtet" manufactured by Murata Software Co., Ltd., the tensile stress generated in the insulating layer 15a around the first portion 21a and the second portion 21b of the first outer conductor layer 21 during the installation of the laminated coil component of Example 1, Example 2, Example 3, Example 4, and Comparative Example 1 was simulated. At this time, the impact load (equivalent to...) applied to the laminated coil component in the lamination direction (here, the height direction T) during the installation of the laminated coil component was... Figure 2 The impact load (D) in the model is set to 53N.

[0281] The simulation results of tensile stress for each example of the laminated coil component are shown in Table 1. In addition, Table 1 also shows the dimensions of the void layer 40 in the longitudinal direction L for each example of the laminated coil component (shown as "Dimensions of Void Layer" in Table 1).

[0282] Table 1

[0283]

[0284] As shown in Table 1, in the laminated coil components of Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4, compared with the laminated coil component of Comparative Example 1, the tensile stress generated in the insulating layer 15a around the first portion 21a and the second portion 21b of the first outer conductor layer 21 is lower. Therefore, it is considered that in the laminated coil components of Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4, compared with the laminated coil component of Comparative Example 1, the generation of cracks in the insulating layer 15a around the first portion 21a and the second portion 21b of the first outer conductor layer 21 can be suppressed during the installation of the laminated coil components.

[0285] Furthermore, as shown in Table 1, with each of the stacked coil components of Embodiment 2, Embodiment 3, Embodiment 4, and Embodiment 1, the dimension of the gap layer 40 in the length direction L decreases, resulting in lower tensile stress on the insulating layer 15a surrounding the first portion 21a and the second portion 21b of the first outer conductor layer 21. Therefore, it is confirmed that, from the viewpoint of reducing the tensile stress on the insulating layer 15a surrounding the first portion 21a and the second portion 21b of the first outer conductor layer 21, it is preferable, as with the stacked coil components of Embodiment 3 and Embodiment 4, that the entire area overlapping the first portion 21a of the first outer conductor layer 21 and the entire area overlapping the second portion 21b of the first outer conductor layer 21 at the first outer interface between the first outer conductor layer 21 and the insulating layer 15a is not provided with the gap layer 40. More preferably, as with the stacked coil component of Embodiment 1, the entire first outer interface between the first outer conductor layer 21 and the insulating layer 15a is not provided with the gap layer 40.

[0286] The following information is disclosed in this specification.

[0287] <1> A stacked coil component, characterized in that it comprises:

[0288] The blank is formed by stacking multiple insulating layers in the stacking direction;

[0289] Multiple conductor layers are disposed inside the aforementioned blank and are stacked together with multiple insulating layers in the aforementioned stacking direction; and

[0290] Multiple external electrodes are disposed on the surface of the aforementioned blank.

[0291] The aforementioned blank has a first main surface and a second main surface that are opposite each other in the aforementioned stacking direction.

[0292] By electrically connecting at least a portion of the plurality of conductor layers described above, a coil electrically connected to the plurality of external electrodes is formed.

[0293] The plurality of conductor layers include a first outer conductor layer located at the outermost position of the first main surface side of the blank in the stacking direction, a second outer conductor layer located at the outermost position of the second main surface side of the blank in the stacking direction, and at least one inner conductor layer located between the first outer conductor layer and the second outer conductor layer in the stacking direction.

[0294] The plurality of external electrodes include a first external electrode disposed at least on the first main surface of the blank, and a second external electrode disposed at least on the first main surface of the blank, which is separated from the first external electrode and is not electrically connected to the first outer conductor layer in the direction along the first outer conductor layer.

[0295] Each of the aforementioned inner conductor layers forms a first inner interface with the adjacent insulating layer on the first main surface side of the blank in the aforementioned stacking direction, and forms a second inner interface with the adjacent insulating layer on the second main surface side of the blank in the aforementioned stacking direction.

[0296] The first outer conductor layer forms a first outer interface with the adjacent insulating layer on the first main surface side of the blank in the stacking direction, and a second outer interface is formed with the adjacent insulating layer on the second main surface side of the blank in the stacking direction.

[0297] The aforementioned first outer conductor layer has a first portion that overlaps with a portion of the second outer electrode disposed on the first main surface of the aforementioned blank when viewed from the aforementioned stacking direction.

[0298] At least one of the aforementioned first inner interface and the aforementioned second inner interface is provided with a void layer.

[0299] When observing at least one cross-section of the first portion of the first outer conductor layer along the aforementioned stacking direction and in a direction orthogonal to the direction in which the first portion of the first outer conductor layer extends when viewed from the aforementioned stacking direction, the aforementioned void layer is not provided at either the first outer interface or the second outer interface.

[0300] <2> According to the laminated coil component described in <1>, wherein,

[0301] The first external electrode is electrically connected to the first outer conductor layer in the direction along the first outer conductor layer.

[0302] <3> According to the stacked coil component described in <1> or <2>, wherein,

[0303] The first external electrode is not electrically connected to the second outer conductor layer in the direction along the second outer conductor layer.

[0304] <4> According to any one of <1> to <3>, the stacked coil component, wherein,

[0305] The second external electrode is electrically connected to the second outer conductor layer in the direction along the second outer conductor layer.

[0306] <5> According to any one of <1> to <4>, the stacked coil component, wherein,

[0307] The first main surface of the aforementioned blank is the mounting surface that faces the object to be mounted during the installation of the aforementioned stacked coil component.

[0308] <6> According to any one of <1> to <5>, the stacked coil component, wherein,

[0309] On both the first outer interface and the second outer interface, the entire area overlapping the first portion of the first outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

[0310] <7> According to any one of <1> to <6>, the stacked coil component, wherein,

[0311] The aforementioned first outer conductor layer also has a second portion that overlaps with a portion of the first outer electrode disposed on the first main surface of the aforementioned blank when viewed from the aforementioned stacking direction.

[0312] At least a portion of the area overlapping the second part of the first outer conductor layer when viewed from the stacking direction on both the first outer interface and the second outer interface is not provided with the aforementioned gap layer.

[0313] <8> According to the laminated coil component described in <7>, wherein,

[0314] On both the first outer interface and the second outer interface, the entire area overlapping the second portion of the first outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

[0315] <9> According to any one of <1> to <8>, the stacked coil component, wherein,

[0316] The first outer conductor layer has a first portion that overlaps with a portion of the second outer electrode disposed on the first main surface of the blank when viewed from the stacking direction, a second portion that overlaps with a portion of the first outer electrode disposed on the first main surface of the blank when viewed from the stacking direction, and a third portion other than the first portion and the second portion.

[0317] On both the first outer interface and the second outer interface, the region that overlaps with the first portion of the first outer conductor layer when viewed from the stacking direction, the region that overlaps with the second portion of the first outer conductor layer when viewed from the stacking direction, and the region that overlaps with the third portion of the first outer conductor layer when viewed from the stacking direction, having a length of more than 20% of the dimension in the direction extending from the ends of both the first and second outer electrode sides to the third portion of the first outer conductor layer, respectively, is not provided with the aforementioned void layer.

[0318] <10> According to any one of <1> to <9>, the stacked coil component, wherein,

[0319] The aforementioned void layer is not provided on either the first outer interface or the second outer interface.

[0320] <11> According to any one of <1> to <10>, the stacked coil component, wherein,

[0321] The area ratio of the void layer to the first outer conductor layer on both the first outer interface and the second outer interface is lower than the area ratio of the void layer to the inner conductor layer on at least one of the first inner interface and the second inner interface.

[0322] <12> According to any one of <1> to <11>, the stacked coil component, wherein,

[0323] In addition to the first main surface of the blank, each of the aforementioned first external electrodes and the aforementioned second external electrodes is also disposed on the second main surface of the blank.

[0324] <13> According to the laminated coil component described in <12>, wherein,

[0325] The second outer conductor layer forms a third outer interface with the adjacent insulating layer on the first main surface side of the blank in the stacking direction, and a fourth outer interface with the adjacent insulating layer on the second main surface side of the blank in the stacking direction.

[0326] The second outer conductor layer has a first portion that overlaps with a portion of the first outer electrode disposed on the second main surface of the blank when viewed from the stacking direction.

[0327] At least a portion of the area overlapping the first part of the second outer conductor layer when viewed from the stacking direction on both the third outer interface and the fourth outer interface is not provided with the aforementioned gap layer.

[0328] <14> According to the stacked coil component described in <13>, wherein,

[0329] On both the third and fourth outer interfaces, the entire area overlapping the first portion of the second outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

[0330] <15> According to the stacked coil component described in <13> or <14>, wherein,

[0331] The second outer conductor layer further has a second portion that overlaps with a portion of the second outer electrode disposed on the second main surface of the blank when viewed from the stacking direction.

[0332] At least a portion of the area overlapping the second part of the second outer conductor layer when viewed from the stacking direction on both the third outer interface and the fourth outer interface is not provided with the aforementioned gap layer.

[0333] <16> According to the laminated coil component described in <15>, wherein,

[0334] On both the third and fourth outer interfaces, the entire area overlapping the second portion of the second outer conductor layer when viewed from the stacking direction is not provided with the aforementioned void layer.

[0335] <17> According to any one of <13> to <16>, the stacked coil component, wherein,

[0336] The second outer conductor layer has a first portion that overlaps with a portion of the first outer electrode disposed on the second main surface of the blank when viewed from the stacking direction, a second portion that overlaps with a portion of the second outer electrode disposed on the second main surface of the blank when viewed from the stacking direction, and a third portion other than the first portion and the second portion.

[0337] On both the third and fourth outer interfaces, the region that overlaps with the first portion of the second outer conductor layer when viewed from the stacking direction, the region that overlaps with the second portion of the second outer conductor layer when viewed from the stacking direction, and the region that overlaps with the third portion of the second outer conductor layer when viewed from the stacking direction, having a length of more than 20% of the dimension in the direction extending from the ends of both the first and second outer electrode sides to the third portion of the second outer conductor layer, respectively, are not provided with the aforementioned void layer.

[0338] <18> According to any one of <13> to <17>, the stacked coil component, wherein,

[0339] The aforementioned void layer is not provided on either the third or fourth outer interface.

[0340] <19> According to any one of <13> to <18>, the stacked coil component, wherein,

[0341] The area ratio of the void layer to the second outer conductor layer on both the third outer interface and the fourth outer interface is lower than the area ratio of the void layer to the inner conductor layer on at least one of the first inner interface and the second inner interface.

[0342] <20> According to any one of <1> to <19>, the stacked coil component, wherein,

[0343] In all of the aforementioned first inner interfaces and the aforementioned second inner interfaces, at least a portion of each interface is provided with the aforementioned void layer.

[0344] <21> According to the laminated coil component described in <20>, wherein,

[0345] The aforementioned void layer is provided on at least one of the aforementioned first inner interface and the aforementioned second inner interface.

[0346] <22> According to the laminated coil component described in <21>, wherein,

[0347] The aforementioned void layer is provided on one of the aforementioned first inner interface and the aforementioned second inner interface.

[0348] <23> According to the laminated coil component described in <21>, wherein,

[0349] The aforementioned gap layer is provided on both the first inner interface and the second inner interface.

[0350] Explanation of reference numerals in the attached figures

[0351] 1…Layered coil component, 10…Blank, 11a…First end face of the blank, 11b…Second end face of the blank, 12a…First main face of the blank, 12b…Second main face of the blank, 13a…First side face of the blank, 13b…Second side face of the blank, 15a, 15b, 15c, 15d, 15e, 15f, 15g, 15h, 15i…Insulating layer, 20…Coil, 21…First outer conductor layer, 21a…First portion of the first outer conductor layer, 21b…Second portion of the first outer conductor layer, 21c…The third part of the first outer conductor layer, 22…The second outer conductor layer, 23a, 23b…Inner conductor layers, 24a, 24b…Connecting conductors, 25a…First lead-out conductor, 25b…Second lead-out conductor, 31…First outer electrode, 32…Second outer electrode, 40…Void layer, 115a, 115b, 115cb, 115d, 115eb, 115f, 115gb, 115h, 115i…Magnetic ferrite paste layer, 115ca, 115ea, 115ga… Non-magnetic ferrite paste layer, 121, 122, 123a, 123b, 124a, 124b, 125a, 125b… conductor paste layer, 140… resin paste layer, C… coil shaft, D… impact load, E1… the end of the first external electrode side in the region overlapping with the third part of the first outer conductor layer on the first outer interface, E2… the end of the second external electrode side in the region overlapping with the third part of the first outer conductor layer on the first outer interface, F… the dimension of the region overlapping with the third part of the first outer conductor layer on the first outer interface in the direction extending from the third part of the first outer conductor layer, L… length direction, P… dimension in the length direction of the stacked coil component, Q1… distance between the outermost positions in the length direction of the first external electrode, Q2… distance between the outermost positions in the length direction of the second external electrode, R… distance between the outermost positions in the length direction of the first outer conductor layer, S… distance between the outermost positions in the width direction of the first outer conductor layer, T… height direction, W… width direction.

Claims

1. A stacked coil component, characterized in that, have: The blank is formed by stacking multiple insulating layers in the stacking direction; Multiple conductor layers are disposed inside the aforementioned blank and are stacked together with multiple insulating layers in the aforementioned stacking direction; and Multiple external electrodes are disposed on the surface of the aforementioned blank. The aforementioned blank has a first main surface and a second main surface that are opposite each other in the aforementioned stacking direction. A coil electrically connected to the plurality of external electrodes is formed by electrically connecting at least a portion of the plurality of the aforementioned conductor layers. The plurality of conductor layers include: a first outer conductor layer located at the outermost position of the first main surface side of the blank in the stacking direction; a second outer conductor layer located at the outermost position of the second main surface side of the blank in the stacking direction; and at least one inner conductor layer located between the first outer conductor layer and the second outer conductor layer in the stacking direction. The plurality of external electrodes comprise: a first external electrode at least disposed on the first main surface of the blank, and a second external electrode at least disposed on the first main surface of the blank, which is separated from the first external electrode and is not electrically connected to the first outer conductor layer in the direction along the first outer conductor layer. Each of the aforementioned inner conductor layers forms a first inner interface on the first main surface side of the blank in the aforementioned stacking direction and between it and the adjacent insulating layer, and forms a second inner interface on the second main surface side of the blank in the aforementioned stacking direction and between it and the adjacent insulating layer. The first outer conductor layer forms a first outer interface on the first main surface side of the blank in the stacking direction and between it and the adjacent insulating layer, and forms a second outer interface on the second main surface side of the blank in the stacking direction and between it and the adjacent insulating layer. The aforementioned first outer conductor layer has a first portion that overlaps with a portion of the second outer electrode disposed on the first main surface of the aforementioned blank when viewed from the aforementioned stacking direction. At least one of the aforementioned first inner interface and the aforementioned second inner interface is provided with a void layer. When viewed in at least one cross-section of the first portion of the first outer conductor layer along the aforementioned stacking direction and in a direction orthogonal to the direction in which the first portion of the first outer conductor layer extends when viewed from the aforementioned stacking direction, the aforementioned void layer is not provided at either the first outer interface or the second outer interface.

2. The laminated coil component according to claim 1, characterized in that, The first external electrode is electrically connected to the first outer conductor layer in the direction along the first outer conductor layer.

3. The laminated coil component according to claim 1 or 2, characterized in that, The first external electrode is not electrically connected to the second outer conductor layer in the direction along the second outer conductor layer.

4. The laminated coil component according to any one of claims 1 to 3, characterized in that, The second external electrode is electrically connected to the second outer conductor layer in the direction along the second outer conductor layer.

5. The laminated coil component according to any one of claims 1 to 4, characterized in that, The first main surface of the aforementioned blank is the mounting surface that faces the object to be mounted during the installation of the aforementioned stacked coil component.

6. The laminated coil component according to any one of claims 1 to 5, characterized in that, On both the first outer interface and the second outer interface, the entire area overlapping the first portion of the first outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

7. The laminated coil component according to any one of claims 1 to 6, characterized in that, The aforementioned first outer conductor layer also has a second portion that overlaps with a portion of the first outer electrode disposed on the first main surface of the aforementioned blank when viewed from the aforementioned stacking direction. At least a portion of the area overlapping the second part of the first outer conductor layer when viewed from the stacking direction on both the first outer interface and the second outer interface is not provided with the aforementioned gap layer.

8. The laminated coil component according to claim 7, characterized in that, On both the first outer interface and the second outer interface, the entire area overlapping the second portion of the first outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

9. The laminated coil component according to any one of claims 1 to 8, characterized in that, The aforementioned first outer conductor layer has: a first portion that overlaps with a portion of the second outer electrode disposed on the first main surface of the blank when viewed from the stacking direction; a second portion that overlaps with a portion of the first outer electrode disposed on the first main surface of the blank when viewed from the stacking direction; and a third portion other than the first portion and the second portion. On both the first outer interface and the second outer interface, the region that overlaps with the first portion of the first outer conductor layer when viewed from the stacking direction, the region that overlaps with the second portion of the first outer conductor layer when viewed from the stacking direction, and the region that overlaps with the third portion of the first outer conductor layer when viewed from the stacking direction, having a length of more than 20% of the dimension in the direction extending from the ends of both the first and second outer electrode sides to the third portion of the first outer conductor layer, respectively, is not provided with the aforementioned void layer.

10. The laminated coil component according to any one of claims 1 to 9, characterized in that, The aforementioned void layer is not provided on either the first outer interface or the second outer interface.

11. The laminated coil component according to any one of claims 1 to 10, characterized in that, The area ratio of the void layer to the first outer conductor layer on both the first outer interface and the second outer interface is lower than the area ratio of the void layer to the inner conductor layer on at least one of the first inner interface and the second inner interface.

12. The laminated coil component according to any one of claims 1 to 11, characterized in that, In addition to the first main surface of the blank, each of the aforementioned first external electrodes and the aforementioned second external electrodes is also disposed on the second main surface of the blank.

13. The laminated coil component according to claim 12, characterized in that, The second outer conductor layer forms a third outer interface with the adjacent insulating layer on the first main surface side of the blank in the stacking direction, and a fourth outer interface with the adjacent insulating layer on the second main surface side of the blank in the stacking direction. The second outer conductor layer has a first portion that overlaps with a portion of the first outer electrode disposed on the second main surface of the blank when viewed from the stacking direction. At least a portion of the area overlapping the first part of the second outer conductor layer when viewed from the stacking direction on both the third outer interface and the fourth outer interface is not provided with the aforementioned gap layer.

14. The laminated coil component according to claim 13, characterized in that, On both the third and fourth outer interfaces, the entire area overlapping the first portion of the second outer conductor layer when viewed from the stacking direction is not provided with the aforementioned gap layer.

15. The laminated coil component according to claim 13 or 14, characterized in that, The second outer conductor layer further has a second portion that overlaps with a portion of the second outer electrode disposed on the second main surface of the blank when viewed from the stacking direction. At least a portion of the area overlapping the second part of the second outer conductor layer when viewed from the stacking direction on both the third outer interface and the fourth outer interface is not provided with the aforementioned gap layer.

16. The laminated coil component according to claim 15, characterized in that, On both the third and fourth outer interfaces, the entire area overlapping the second portion of the second outer conductor layer when viewed from the stacking direction is not provided with the aforementioned void layer.

17. The laminated coil component according to any one of claims 13 to 16, characterized in that, The second outer conductor layer has a first portion that overlaps with a portion of the first outer electrode disposed on the second main surface of the blank when viewed from the stacking direction, a second portion that overlaps with a portion of the second outer electrode disposed on the second main surface of the blank when viewed from the stacking direction, and a third portion other than the first portion and the second portion. On both the third and fourth outer interfaces, the region that overlaps with the first portion of the second outer conductor layer when viewed from the stacking direction, the region that overlaps with the second portion of the second outer conductor layer when viewed from the stacking direction, and the region that overlaps with the third portion of the second outer conductor layer when viewed from the stacking direction, having a length of more than 20% of the dimension in the direction extending from the ends of both the first and second outer electrode sides to the third portion of the second outer conductor layer, respectively, are not provided with the aforementioned void layer.

18. The laminated coil component according to any one of claims 13 to 17, characterized in that, The aforementioned void layer is not provided on either the third or fourth outer interface.

19. The laminated coil component according to any one of claims 13 to 18, characterized in that, The area ratio of the void layer to the second outer conductor layer on both the third outer interface and the fourth outer interface is lower than the area ratio of the void layer to the inner conductor layer on at least one of the first inner interface and the second inner interface.

20. The laminated coil component according to any one of claims 1 to 19, characterized in that, In all of the aforementioned first inner interfaces and the aforementioned second inner interfaces, at least a portion of each interface is provided with the aforementioned void layer.

21. The laminated coil component according to claim 20, characterized in that, The aforementioned void layer is provided on at least one of the aforementioned first inner interface and the aforementioned second inner interface.

22. The laminated coil component according to claim 21, characterized in that, The aforementioned void layer is provided on one of the aforementioned first inner interface and the aforementioned second inner interface.

23. The laminated coil component according to claim 21, characterized in that, The aforementioned gap layer is provided on both the first inner interface and the second inner interface.

Images