Method of forming a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure forming method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure forming method comprises the following steps: providing a substrate, the substrate comprising an initial trench and a hard mask layer on the surface of the substrate; performing dry etching on the substrate based on the hard mask layer, and etching by-products are formed on the surface of the substrate during the dry etching process; and performing high-temperature treatment on the substrate, the high-temperature treatment being used for removing the etching by-products and forming an etching hole. In the semiconductor structure forming method provided by the present disclosure, the wet cleaning process does not have to be used for the etching hole with a high aspect ratio, so that the etching hole with the high aspect ratio will not be structurally damaged due to the capillary action of the liquid, thereby avoiding the problem of pattern collapse and improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Technology

[0002] Cleaning is one of the most important and frequent steps in the entire semiconductor device manufacturing process, accounting for up to 20% of the process steps. This makes the cleanliness of the wafer surface a crucial factor affecting the reliability of semiconductor devices. The purpose of cleaning is to prevent contamination of semiconductor devices by microparticles, trace ions, and metallic impurities, thereby improving the performance and yield of semiconductor devices.

[0003] In semiconductor structures, many device structures have high aspect ratios, especially deep trenches. When the aspect ratio is very large, they are difficult to clean with existing cleaning solutions. Moreover, when the aspect ratio is greater than a certain ratio (e.g., 10:1), the pattern on the wafer surface may be deformed or even collapsed due to the capillary effect of the cleaning solution during the wet cleaning process, thereby reducing the yield of wafer products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for forming a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for forming a semiconductor structure, the method comprising:

[0007] A substrate is provided, the substrate including an initial trench and a hard mask layer located on the surface of the substrate;

[0008] Based on the hard mask layer, the substrate is dry etched, and during the dry etching process, etching byproducts are formed on the surface of the substrate.

[0009] The substrate is subjected to high-temperature treatment to remove the etching byproducts and form etched holes.

[0010] The dry etching of the substrate includes:

[0011] The bottom of the initial trench is etched using a first mixed gas as the etching gas, the first mixed gas reacting with the surface of the substrate, the first mixed gas including at least nitrogen trifluoride and hydrogen.

[0012] The first mixed gas reacts with the surface of the substrate, including:

[0013] When adsorbates form on the sidewalls and bottomwalls of the initial trench, the first mixed gas reacts with the adsorbates to generate the etching byproducts.

[0014] The first mixed gas reacts with the surface of the substrate, including:

[0015] When there are no adsorbates on the sidewalls and bottom wall of the initial trench, the first mixed gas reacts with the bottom of the initial trench to generate gaseous products.

[0016] The etching byproducts include ammonium fluorosilicate and / or fluorides.

[0017] The adsorbent includes at least silicon-containing oxides.

[0018] The substrate includes a silicon substrate, and the hard mask layer includes a first hard mask layer or a first hard mask layer and a second hard mask layer stacked sequentially. The first hard mask layer includes a silicon oxide layer, and the second hard mask layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon boron nitride layer, and a silicon carbon nitride layer.

[0019] The first mixed gas further includes an inert gas, which includes at least one of the following gases: argon, nitrogen, and argon.

[0020] The dry etching process conditions include:

[0021] The bottom of the initial trench is etched using a pulsed bias power output mode, with a pulsed bias voltage of 13.56 mHz and a source power range of 1200–3000 W. The flow rate of nitrogen trifluoride ranges from 5 to 50 sccm, and the flow rate of hydrogen ranges from 100 to 400 sccm. The dry etching time is controlled within the range of 10 s to 60 s, and the dry etching ambient pressure is controlled within the range of 100–1200 mtorr.

[0022] The process conditions for the high-temperature treatment include: the ambient temperature is controlled between 100 and 200°C.

[0023] The substrate provided includes:

[0024] A semiconductor substrate is provided, and a patterned hard mask layer is formed on the surface of the semiconductor substrate;

[0025] Using a second mixed gas as the etching gas, the semiconductor substrate is etched based on the hard mask layer to form the initial trench, wherein the aspect ratio of the initial trench is less than or equal to 10.

[0026] The second mixed gas includes at least one of chlorine and carbon tetrafluoride, oxygen, and an inert gas.

[0027] The method for forming the semiconductor structure, prior to dry etching of the substrate, further includes:

[0028] The substrate is cleaned using a cleaning solution, and the cleaning residue forms as adsorbents on the sidewalls and bottom wall of the initial trench.

[0029] The cleaning residue includes chemically formed silica formed during the cleaning process and / or naturally formed silica formed by the natural oxidation of silicon after the cleaning process.

[0030] The method for forming the semiconductor structure further includes:

[0031] The process involves performing multiple cycles to form etched holes with a target aspect ratio. Each cycle includes: dry etching the substrate and then subjecting the dry-etched substrate to high-temperature treatment.

[0032] The aspect ratio of the target is greater than 10 and less than or equal to 15.

[0033] A second aspect of this disclosure provides a semiconductor structure prepared using the semiconductor structure formation method described in the first aspect.

[0034] In the semiconductor structure formation method and semiconductor structure disclosed herein, a high aspect ratio etched hole is formed in the substrate by using a dry etching process on the initial trench and using high temperature to treat the etching byproducts generated by the etching process. Since a wet cleaning process is not required for the high aspect ratio etched hole, the structure of the high aspect ratio etched hole will not be damaged by the capillary action of the liquid, thereby avoiding the problem of pattern collapse and improving the yield of the semiconductor structure.

[0035] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0037] Figures 1 to 3 This is a schematic diagram of the various stages in the wet cleaning process for substrate cleaning in existing technologies.

[0038] Figure 4 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0039] Figure 5 This is a schematic diagram of a substrate provided during the formation of a semiconductor structure according to an exemplary embodiment.

[0040] Figure 6 This is a schematic diagram illustrating the formation of an initial trench during the formation of a semiconductor structure according to an exemplary embodiment.

[0041] Figure 7 This is a schematic diagram illustrating cleaning residues formed during the formation of a semiconductor structure according to an exemplary embodiment.

[0042] Figure 8 This is a schematic diagram illustrating etching byproducts formed on the substrate surface during the formation of a semiconductor structure according to an exemplary embodiment.

[0043] Figure 9 This is a schematic diagram illustrating the formation process of a semiconductor structure after high-temperature treatment according to an exemplary embodiment.

[0044] Figure 10 This is a schematic diagram illustrating etching byproducts formed during the formation of a semiconductor structure according to an exemplary embodiment.

[0045] Figure 11 This is a schematic diagram illustrating the formation process of a semiconductor structure after high-temperature treatment according to an exemplary embodiment.

[0046] Figure 12 This is a schematic diagram illustrating etching byproducts formed during the formation of a semiconductor structure according to an exemplary embodiment.

[0047] Figure 13 This is a schematic diagram illustrating the formation process of a semiconductor structure after high-temperature treatment according to an exemplary embodiment.

[0048] Figure 14 This is a schematic diagram of etching byproducts formed during the formation of a semiconductor structure according to another exemplary embodiment.

[0049] Figure 15 This is a schematic diagram illustrating the formation process of a semiconductor structure after high-temperature treatment according to another exemplary embodiment.

[0050] Figure 16 This is a schematic diagram illustrating the variation in the etching amount of the first mixed gas on each material layer during the formation of a semiconductor structure according to an exemplary embodiment.

[0051] Figure 17 This is a flowchart illustrating a method for forming a semiconductor structure according to another exemplary embodiment.

[0052] Figure label:

[0053] 10. Substrate; 20. Etched via; 30. Cleaning solution; 40. Opening pattern; 100. Substrate; 110. Semiconductor substrate; 120. Initial trench; 121. Bottom wall of initial trench; 122. Side wall of initial trench; 123. Etching residue; 130. Hard mask layer; 131. Second hard mask layer; 132. First hard mask layer; 150. Cleaning residue; 200. Etching byproduct; 300. Etched via. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0055] like Figures 1 to 3 As shown, Figure 1 An exemplary schematic diagram is shown of a substrate cleaning process using a wet cleaning method in the prior art. Figure 2 An exemplary schematic diagram illustrates the evaporation process of the cleaning liquid after cleaning. Figure 3 An exemplary schematic diagram of a substrate after wet cleaning is shown. It can be seen that in the prior art, especially when cleaning a substrate 10 with high aspect ratio etched holes 20 using cleaning solution 30, the sidewalls of the etched holes 20 are affected by the capillary action of the liquid (capillary action is the attraction between a liquid surface and a solid surface), causing pattern collapse, which in turn leads to device deformation and reduces the yield of the semiconductor structure.

[0056] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor structure in exemplary embodiments, such as... Figure 4 As shown, Figure 4 A flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 5-16 The diagram below illustrates the various stages of a semiconductor structure formation process. Figures 5-16 The methods for forming semiconductor structures are introduced.

[0057] This embodiment does not limit the semiconductor structure. The following description will take Dynamic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0058] like Figure 4 As shown, an exemplary embodiment of this disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0059] Step S110: Provide a substrate, the substrate including an initial trench and a hard mask layer located on the surface of the substrate.

[0060] Step S120: Based on the hard mask layer, the substrate is dry etched. During the dry etching process, etching byproducts are formed on the surface of the substrate.

[0061] Step S130: The substrate is subjected to high-temperature treatment to remove etching byproducts and form etching holes.

[0062] For example, such as Figure 9 As shown, substrate 100 serves as a support component for the memory, supporting other components disposed thereon. Substrate 100 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carb compounds. Exemplarily, substrate 100 includes a silicon substrate.

[0063] Alternatively, the substrate 100 can be a single-crystal silicon substrate or a lightly doped silicon substrate, such as an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The substrate 100 may also include transistor word lines, bit lines, source regions, drain regions, and shallow trench isolation structures (not shown in the figure).

[0064] like Figure 9 As shown, the hard mask layer 130 is located on the substrate 100, and at least one initial trench 120 is located within the substrate 100. For ease of illustration, this embodiment exemplarily shows one initial trench 120. The number of initial trenches 120 can be designed according to actual design requirements and is not specifically limited here.

[0065] like Figure 9 , Figure 14 , Figure 15As shown, the hard mask layer 130 includes a first hard mask layer 132 or a first hard mask layer 132 and a second hard mask layer 131 stacked sequentially. The first hard mask layer 132 includes a silicon oxide layer, and the second hard mask layer 131 includes at least one of a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon boron nitride (SiBN) layer, and a silicon carbon nitride (SiCN) layer. The material of the hard mask layer can also be a material with a high selectivity to the material of the substrate 100. In this embodiment, for example, the hard mask layer 130 is the first hard mask layer 132. Alternatively, the hard mask layer 130 includes a first hard mask layer 132 and a second hard mask layer 131, where the first hard mask layer 132 is a silicon oxide layer and the second hard mask layer 131 is a silicon nitride layer.

[0066] In one embodiment, the substrate is a silicon substrate, and the hard mask layer is a silicon oxide layer, such as... Figure 9 As shown, the initial trench 120 can be formed within the substrate 100 using existing conventional processes, such as dry etching. Exemplarily, the depth of the initial trench 120 is D1 (as shown in the figure). Exemplarily, the initial trench 120 can be a shallow trench, for example, the aspect ratio of the initial trench 120 is less than or equal to 10.

[0067] like Figure 9 and Figure 10 As shown, a dry etching process can be used to further etch the substrate 100 to transform the initial trench 120 into a high aspect ratio (e.g., aspect ratio greater than 10) etched hole 300 (see reference). Figure 11 In step S120, a dry etching process is used to continue etching the shallow trenches so that a selective etching process can be used in subsequent processes. Figure 8 and Figure 10 As shown, when dry etching is performed on the substrate 100 using a hard mask layer 130 as a mask, non-volatile or difficult-to-remove etching byproducts 200 are generated. These byproducts 200 remain on the surface of the substrate 100. For example, they may accumulate on the surface of the hard mask layer 130 or form on the sidewalls and bottom walls of the initial trench 120. Therefore, the etching byproducts 200 need to be treated to prevent them from affecting the etched structure and causing deformation of the high aspect ratio etched hole 300 structure formed in subsequent processes.

[0068] In step S120 of this embodiment, the substrate is dry etched, which can be implemented using the following methods:

[0069] The bottom of the initial trench in the substrate is etched using a first mixed gas as the etching gas. Exemplarily, the first mixed gas includes at least nitrogen trifluoride (NF3) and hydrogen (H2).

[0070] like Figure 9 and Figure 10 As shown, a first mixed gas is introduced into the reaction chamber where the substrate 100 is located. The first mixed gas reacts with the surface of the substrate to etch the bottom of the initial trench 120, thereby deepening the etching of the initial trench 120 to form the etched hole 300 (see reference). Figure 12 The concentration of the etching gas can be controlled by controlling the flow rate of the first mixed gas introduced into the reaction chamber each time. For example, the flow rate of nitrogen trifluoride can be controlled in the range of 5 to 50 sccm, and the flow rate of hydrogen can be controlled in the range of 100 to 400 sccm.

[0071] For example, when introducing the first mixed gas into the reaction chamber, an inert gas can be used as the carrier gas, including at least one of the following gases: argon, nitrogen, and argon. Additionally, the pressure in the reaction chamber can be adjusted using the inert gas to ensure that the first mixed gas contacts the bottom of the initial trench.

[0072] For example, when performing deep etching on substrate 100, the uniformity of etching depth can be improved by controlling the etching process conditions related to the etching process. For instance, the etching environment pressure can be controlled within the range of 100–1200 mtorr, and the source power within the range of 1200–3000 W. A low-frequency pulsed bias power output mode can be used to deepen the etching of substrate 100; the pulsed bias can be controlled at 13.56 mHz. The dry etching time is controlled within the range of 10 s–60 s.

[0073] like Figure 6 As shown, adsorbates may exist on the surface of substrate 100. These adsorbates include at least silicon-containing oxides. For example, the adsorbates may be silicon oxides generated from previous processes, or silicon oxides formed after the silicon on the exposed surface of substrate 100 is oxidized in air. When the first mixed gas is introduced into the chamber containing substrate 100, it reacts with the adsorbates on the surface of substrate 100 to generate etching byproducts, including ammonium fluorosilicate and / or fluorides. If no adsorbates are present on the surface of substrate 100, the bottom of the initial trench 120 can be directly etched using the first mixed gas to form the etched hole 300 (see reference). Figure 11 ).

[0074] For example, such as Figures 6-10As shown, when the material of the hard mask layer 130 includes silicon oxide (such as SiO2), the surface material of the hard mask layer 130 is silicon oxide. In step S120, when the first mixed gas is introduced into the reaction chamber where the substrate 100 is located, the first mixed gas reacts with the surface of the hard mask layer 130 to generate etching byproduct 200. For example, nitrogen trifluoride (NF3) reacts with silicon dioxide (SiO2) as follows: SiO2 + NF3 + H2 → (NH4)2SiF6 + 2H2O, generating ammonium hexafluorosilicate ((NH4)2SiF6). Ammonium hexafluorosilicate, as etching byproduct 200, adheres to the surface of the hard mask layer 130. Figure 10 As shown.

[0075] like Figure 6 and Figure 8 As shown, in the preceding process such as the cleaning process, the cleaning solution (such as a cleaning solution including hydrogen peroxide) forms chemical silicon oxide on the surface of the initial trench 120. The chemical silicon oxide will act as an adsorbent and adhere to the surface of the initial trench 120 (the sidewalls and bottom wall of the initial trench); or, because the surface of the initial trench 120 is exposed to air, native silicon oxide will also be generated and adhere to the surface of the sidewalls 122 and bottom wall 121 of the initial trench 120. The native silicon oxide will act as an adsorbent and adhere to the surface of the initial trench 120. When chemically bonded silicon dioxide adheres to the surface of the initial trench 120 as an adsorbent, or when native silicon dioxide adheres to the surface of the initial trench 120 as an adsorbent, the first mixed gas also reacts with the adsorbent to generate etching byproducts 200 during dry etching of the substrate 100. The etching byproducts 200 also cover the surface of the initial trench 120, which has a certain impact on the etching process. Therefore, it is necessary to perform high-temperature treatment on the substrate to remove the etching byproducts located on the surface of the initial trench 120, and then introduce the first mixed gas into the reaction chamber where the substrate is located to perform deep etching on the bottom of the initial trench 120 to form an etched hole.

[0076] refer to Figure 9 When there are no adsorbates on the surfaces of the bottom wall 121 and side wall 122 of the initial trench 120, the introduced first mixed gas can directly contact the bottom of the initial trench 120 and react, such as... Figure 10 As shown, the first mixed gas reacts with the surface of substrate 100, such as silicon, to generate gaseous products, such as nitrogen trifluoride (NF3), which reacts with silicon (Si) as follows: NF3 + e → N F(3-x)+xF (free radical) + 2e, Si + 4F → SiF4 (g), generating silicon tetrafluoride (SiF4), which is also an etching byproduct 200. Since silicon tetrafluoride (SiF4) is a gaseous product (gas), it will not be adsorbed on the surface of the substrate 100. At the same time, after the initial etched hole 120 is deepened, the depth changes from D1 to D2, where D2 is greater than D1.

[0077] like Figure 10 As shown, since the fluorides in the gas do not adhere to the surface of the substrate 100, they can be carried away by the gas in the reaction apparatus. However, the ammonium fluorosilicate produced will accumulate in large quantities as the etching time increases. With increasing etching time, the thickness of the etching byproducts 200 generated by the reaction of the first mixed gas with the surface of the hard mask layer 130 will also gradually increase, potentially affecting the initial trench 120 (reference). Figure 9 The opening of the initial trench 120 is blocked, preventing the first mixed gas from contacting the bottom of the initial trench 120, thus causing premature termination of the etching process. Therefore, after a preset etching time on the substrate 100, a high-temperature treatment is required to remove the etching byproducts 200, ensuring that the etching gas can contact the bottom of the initial trench 120 and that the etching process can continue. The duration of the high-temperature treatment can be adjusted according to the actual situation.

[0078] like Figure 10 As shown, the etching byproduct 200 formed on the surface of substrate 100 is, for example, ammonium hexafluorosilicate ((NH4)2SiF6). Since ammonium hexafluorosilicate is a white crystalline powder, according to its chemical properties, it can be directly sublimated at high temperatures. Therefore, the etching byproduct 200 can be removed directly using high-temperature treatment technology, and thus the byproducts that cause pollution from etching will no longer be adsorbed on the surface of substrate 100. For example, the ambient temperature for high-temperature treatment of the substrate is controlled at 100–200°C, such as 100°C, 110°C, 120°C, etc.

[0079] like Figure 10 and Figure 11 As shown, the initial trench 120 after high-temperature treatment and deep etching of the substrate 100 (reference) Figure 9The initial trench 120 is transformed into an etched hole 300. It is evident that the depth D2 of the etched hole 300 is greater than the depth D1 of the initial trench 120, resulting in an etched hole 300 with a higher aspect ratio (e.g., greater than 10) than the initial trench 120. When the depth D2 of the etched hole 300 meets the requirements, further etching of the initial trench 120 is unnecessary, thus obtaining an etched hole 300 that meets the design requirements. In this step, the high aspect ratio etched hole does not require wet cleaning; instead, high-temperature treatment is used to remove the etching byproducts 200 located on the surface of the substrate 100. This avoids the structural damage caused by capillary action during wet cleaning of the high aspect ratio etched hole, thereby preventing pattern collapse.

[0080] In the semiconductor structure formation method disclosed herein, a high aspect ratio etched hole is formed in the substrate by using a dry etching process on the initial trench and using high temperature to treat the etching byproducts generated by the etching process. Since a wet cleaning process is not required for the high aspect ratio etched hole, the structure of the high aspect ratio etched hole will not be damaged by the capillary action of the liquid, thereby avoiding the problem of pattern collapse and improving the yield of the semiconductor structure.

[0081] According to an exemplary embodiment, this embodiment is a further description of the above embodiment, and the embodiment is a description of step S120 in the above embodiment. In this embodiment, the time for dry etching of the substrate is controlled within the range of 10S to 60S.

[0082] like Figure 10 As shown, as the etching process proceeds, a large amount of etching byproducts 200 generated by the first mixed gas on the surface of the hard mask layer 130 will accumulate. Therefore, it is necessary to control the dry etching time and the time of introducing the first mixed gas to avoid generating excessive etching byproducts 200, which would affect the etching process. For example, the etching time used for deep etching of the substrate 100 is controlled within the range of 10S to 60S. In addition, controlling the dry etching time within a reasonable range will prevent the generation of excessive etching byproducts, thereby saving time for high-temperature processing in subsequent processes and shortening the formation time of the etched holes.

[0083] According to an exemplary embodiment, this embodiment is a further description of the above embodiment. The embodiment is a description of step S130 in the above embodiment. In this embodiment, the time for high-temperature treatment of the substrate is controlled within the range of 1 min to 2 min.

[0084] like Figure 10 and Figure 11As shown, in order to completely remove the etching byproducts 200 located on the surface of the substrate 100, the high-temperature treatment time of the substrate 100 is controlled within 1 min to 2 min. For example, the high-temperature treatment time is 1 min, 1.5 min, or 2 min, etc., and no specific limitation is made here.

[0085] like Figure 17 As shown, a method for forming a semiconductor structure according to another exemplary embodiment of this disclosure includes the following steps:

[0086] Step 210: Provide a semiconductor substrate and form a patterned hard mask layer on the surface of the semiconductor substrate.

[0087] like Figure 5 As shown, a semiconductor substrate 110 is provided, and the material of the semiconductor substrate 110 includes, but is not limited to, single-crystal or polycrystalline semiconductor materials. A hard mask layer 130 with an opening pattern 40 is formed on the semiconductor substrate 110. Exemplarily, the hard mask layer includes a first hard mask layer or a first hard mask layer and a second hard mask layer stacked sequentially. The first hard mask layer includes a silicon oxide layer, and the second hard mask layer includes at least one of a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon boron nitride (SiBN) layer, and a silicon carbon nitride (SiCN) layer. The material of the hard mask layer can also be a material with a high selectivity to other materials of the same substrate. In this embodiment, for example, the hard mask layer is a silicon oxide layer. Alternatively, the hard mask layer includes a first hard mask layer and a second hard mask layer, where the first hard mask layer is a silicon oxide layer and the second hard mask layer is a silicon nitride layer. The opening pattern 40 can be used to define an initial trench 120 (see reference). Figure 6 The shape and position of ).

[0088] Step 220: Using the second mixed gas as the etching gas, etch the semiconductor substrate based on the hard mask layer to form the initial trench.

[0089] like Figure 6 As shown, a second mixed gas is introduced as an etching gas to etch the semiconductor substrate 110 to form a substrate 100 with an initial trench 120. The second mixed gas includes at least one of chlorine and carbon tetrafluoride, oxygen, and an inert gas. The inert gas is one or more of helium, nitrogen, and argon. Using the second mixed gas to etch the semiconductor substrate 110 increases the etching rate, thereby obtaining an initial trench 120 with a certain aspect ratio in the shortest possible time, saving semiconductor structure fabrication time. For example, the aspect ratio of the initial trench 120 is less than or equal to 10.

[0090] In one embodiment, the second mixed gas includes chlorine, carbon tetrafluoride, oxygen, and an inert gas (such as argon), wherein the flow rate of chlorine is 200-500 sccm, the flow rate of carbon tetrafluoride is 70-170 sccm, the flow rate of oxygen is 20-300 sccm, and the flow rate of the inert gas is 50-300 sccm.

[0091] Step 230: Wet cleaning of the substrate using a cleaning solution, with cleaning residue forming as adsorbents on the sidewalls and bottomwalls of the initial trench.

[0092] like Figure 6 As shown, etching residue 123 generated during the etching process adheres to the surface of substrate 100. Etching residue 123 is, for example, CH. x F y One or more of the following: (methylalkanes), SiOx (silicon oxide), SiNy (silicon nitride), strong acid residues Cl (chlorine), Br (bromine), HCl (hydrogen chloride), and HBr (hydrogen bromide). To achieve better etching results, etching residue 123 needs to be removed.

[0093] In this embodiment, a wet cleaning process is used for removal. The cleaning solution includes one or more of the following solutions: hydrofluoric acid solution (HF), ammonia-hydrogen peroxide mixture (APM), hydrochloric acid-hydrogen peroxide mixture (HPM), and sulfuric acid-hydrogen peroxide-hydrofluoric acid mixture (DSP). The cleaning solution in the wet cleaning process does not have the effect of liquid capillary action on the initial trench 120 with a low aspect ratio, so the structure of the initial trench 120 is not damaged.

[0094] like Figure 7 As shown, during the wet cleaning process of substrate 100, the substances in the cleaning liquid react with the etching residue 123 on the surface of semiconductor substrate 110 to generate cleaning residue 150, which acts as an adsorbent and adheres to the surface of the sidewall 122 and bottom wall 121 of the initial trench 120. The cleaning residue 150 may be, for example, a chemical silicon oxide layer (SiO2) generated by hydrogen peroxide reacting with the silicon surface, and / or natural silicon oxide (SiOx) naturally formed on the substrate surface after the cleaning process (not shown in the figure).

[0095] Step 240: Based on the hard mask layer, the bottom of the initial trench is etched using the first mixed gas as the etching gas. During the dry etching process, etching byproducts are formed on the surface of the substrate.

[0096] like Figure 7 and Figure 8As shown, a first mixed gas, such as nitrogen trifluoride and hydrogen as etching gases, and argon, helium, or nitrogen as carrier gases, is introduced into the chamber containing the substrate 100 to perform dry etching on the substrate 100. Since the surface of the substrate 100 is coated with cleaning residue 150, the introduced first mixed gas reacts with the cleaning residue 150 to generate etching byproducts 200, which cover the surfaces of the sidewalls 122 and bottom wall 121 of the initial trench 120. Simultaneously, the first mixed gas also reacts with the hard mask layer 130 (such as silicon oxide) to generate etching byproducts 200, which also cover the surface of the hard mask layer 130. Figure 8 As shown, etching byproducts 200 cover the surface of the hard mask layer 130, the sidewalls 122 and the bottom wall 121 of the initial trench 120. The etching byproducts 200 prevent the first mixed gas from contacting the bottom wall 121 of the initial trench 120, so the etching byproducts 200 need to be removed.

[0097] Step 250: As Figure 9 As shown, the substrate is subjected to high-temperature treatment to remove etching byproducts.

[0098] like Figure 10 As shown, with the introduction of the first mixed gas to etch the bottom wall 121 of the initial trench, during the etching process, the first mixed gas reacts with the silicon oxide in the hard mask layer 130, generating more and thicker etching byproducts 200 on the surface of the substrate 100, which may lead to the inability to etch the initial trench 120 (see reference). Figure 9 Deepen the etching, therefore, as Figure 11 As shown, after introducing a preset amount of the first mixed gas, the substrate 100 needs to be subjected to high-temperature treatment to remove the etching by-products 200 covering the surface of the substrate 100, thereby obtaining a substrate 100 with a clean surface. In this embodiment, the process of high-temperature treatment of the substrate 100 is the same as the process of step S130 in the above embodiment, and will not be described again here.

[0099] Step 260: Perform multiple cycles of the process to form an etched hole with the target aspect ratio. Each cycle includes: dry etching of the substrate and high-temperature treatment of the substrate after dry etching.

[0100] like Figure 9 As shown, the first mixed gas is introduced again into the reaction chamber containing the substrate 100. Since the surface of the substrate 100 is free of contaminants after the processing in step S250, the first mixed gas comes into direct contact with the surface of the semiconductor substrate 110, thereby allowing the first mixed gas to further deepen the initial trench 120. The first mixed gas reacts with the bottom of the initial trench to generate gaseous products, which are discharged from the reaction chamber along with the gas.

[0101] like Figure 10 As shown, during the deepening process of the initial trench 120, the first mixed gas reacts with at least the silicon oxide layer in the hard mask layer 130 to generate etching byproducts 200. As etching progresses, the etching byproducts 200 gradually increase, which will have a certain impact on the etching of the bottom wall 121 of the initial trench 120. To remove the etching byproducts 200, such as... Figure 11 As shown, the etching byproducts 200 are treated in a high-temperature environment to remove the etching byproducts 200 located on the hard mask layer 130 (reference). Figure 10 In this embodiment, the process of high-temperature treatment of substrate 100 is the same as step S130 in the above embodiment, and will not be described again here.

[0102] like Figures 9-11 As shown, the first cycle process can be defined as the high-temperature treatment after the initial trench 120 is deeply etched. After the first cycle process is executed, an etched hole 300 with a depth D2 is formed, where D2 > D1 (the depth of the initial trench 120). When the etched hole 300 with a depth D2 does not reach the target etching depth, that is, the etched hole 300 does not reach the target aspect ratio, then the substrate 100 can be subjected to a second cycle process.

[0103] like Figure 11 As shown in Figure 13, the substrate 100 is further etched using the first mixed gas as the etching gas. Then, the substrate 100 is subjected to high-temperature treatment to remove etching byproducts 200, resulting in an etched hole 300 with a depth of D3, where D3 > D2. If the etched hole 300 with a depth of D3 still does not achieve the target aspect ratio, a third cycle process, a fourth cycle process, etc., are performed sequentially until a etched hole 300 meeting the requirements is obtained. Figure 13 As shown, the process cycle terminates when the etched hole 300 reaches the target aspect ratio. For example, the target aspect ratio can be controlled within a range greater than 10 and less than or equal to 15.

[0104] like Figure 16 As shown, this example illustrates a comparison of the etching amounts of the first mixed gas on various materials in a semiconductor structure during each of three cycle processes. Nitrogen trifluoride (NF3) and hydrogen (H2) are used as the main gases in the first mixed gas for illustration. In multiple cycle processes, as... Figure 16As shown, line A represents the change in etching amount of silicon nitride etched by the first mixed gas. Silicon nitride shows almost no loss during the cycle process, indicating that nitrogen trifluoride (NF3) and hydrogen (H2) hardly etch the silicon nitride. For example, the etching rate of silicon nitride by nitrogen trifluoride (NF3) and hydrogen (H2) is less than 0.3 nm / min. Line B represents the change in etching amount of silicon oxide etched by the first mixed gas. With increasing cycle number, the etching amount of silicon oxide gradually increases, indicating that silicon oxide gradually experiences loss during the cycle process. Line C represents the change in etching amount of the semiconductor substrate (silicon substrate) etched by the first mixed gas. With increasing cycle number, the etching amount of the semiconductor substrate increases significantly. This shows that using nitrogen trifluoride (NF3) and hydrogen (H2) as etching gases has a significant effect on deepening the etching of the silicon substrate without causing excessive loss to other materials besides the silicon substrate, which is beneficial for maintaining the morphology of the semiconductor structure.

[0105] According to an exemplary embodiment, this embodiment is a further description of the above embodiment, and the embodiment is a description of the hard mask layer 130 in the above embodiment. In this embodiment, the hard mask layer is a multilayer film structure.

[0106] In this embodiment, as Figure 15 As shown, the hard mask layer 130 is a multi-layer structure composed of silicon oxide and silicon nitride. For example, the first hard mask layer 132 is silicon oxide and the second hard mask layer 131 is silicon nitride. The thickness of the first hard mask layer 132 can be smaller than the thickness of the second hard mask layer 131. This reduces the etching byproducts 200 generated on the surface of the hard mask layer 130 during the dry etching process on the substrate 100, thereby appropriately increasing the dry etching time to improve the speed of forming etched holes with the target aspect ratio and accelerating the formation of semiconductor structures.

[0107] In addition, in this embodiment, since there are fewer etching byproducts 200 generated on the surface of the substrate 100, the time consumed in the high-temperature processing stage is also reduced, thereby increasing the speed of semiconductor structure fabrication.

[0108] This disclosure provides a semiconductor structure in exemplary embodiments, which is fabricated using the semiconductor structure formation method described in the above embodiments. The semiconductor structure of this embodiment can be used in memory chips, specifically in Dynamic Random Access Memory (DRAM). However, it can also be applied to Static Random-Access Memory (SRAM), flash EPROM, ferroelectric random-access memory (FRAM), magnetic random-access memory (MRAM), phase-change random-access memory (PRAM), and the like. In this embodiment, the semiconductor structure forms etching holes with a high aspect ratio within the substrate. Since a wet cleaning process is unnecessary during the etching process, the high aspect ratio etching holes are not damaged by liquid capillary action, thus avoiding pattern collapse and improving the yield of the semiconductor structure.

[0109] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0110] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0111] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0112] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0113] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0114] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method for forming the semiconductor structure includes: A substrate is provided, the substrate including an initial trench and a hard mask layer located on the surface of the substrate; Based on the hard mask layer, the substrate is dry etched, and during the dry etching process, etching byproducts are formed on the surface of the substrate. The substrate is subjected to high-temperature treatment to remove the etching byproducts and form etched holes; Dry etching of the substrate includes: The bottom of the initial trench is etched using a first mixed gas as the etching gas, the first mixed gas reacting with the surface of the substrate, the first mixed gas including at least nitrogen trifluoride and hydrogen; Provide a substrate, including: A semiconductor substrate is provided, and a patterned hard mask layer is formed on the surface of the semiconductor substrate; Using a second mixed gas as the etching gas, the semiconductor substrate is etched based on the hard mask layer to form the initial trench, wherein the aspect ratio of the initial trench is less than or equal to 10; Before dry etching the substrate, the method for forming the semiconductor structure further includes: The substrate is cleaned using a cleaning solution, and the cleaning residue forms as adsorbents on the sidewalls and bottom wall of the initial trench. The cleaning residue includes chemically formed silica during the cleaning process and / or naturally formed silica formed by the natural oxidation of silicon after the cleaning process is completed. The method for forming the semiconductor structure further includes: The process involves performing multiple cycles to form etched holes with a target aspect ratio. Each cycle includes: dry etching the substrate and then subjecting the dry-etched substrate to high-temperature treatment.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first mixed gas reacts with the surface of the substrate, including: Adsorbents are formed on the sidewalls and bottomwalls of the initial trench, and the first mixed gas reacts with the adsorbents to generate the etching byproducts.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The first mixed gas reacts with the surface of the substrate, including: There are no adsorbates on the sidewalls and bottom wall of the initial trench. The first mixed gas reacts with the bottom of the initial trench to generate gaseous products.

4. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The etching byproducts include ammonium fluorosilicate and / or fluorides.

5. The method for forming a semiconductor structure according to claim 2 or 3, characterized in that, The adsorbent includes at least silicon-containing oxides.

6. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The substrate includes a silicon substrate, and the hard mask layer includes a first hard mask layer or a first hard mask layer and a second hard mask layer stacked sequentially. The first hard mask layer includes a silicon oxide layer, and the second hard mask layer includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon boron nitride layer, and a silicon carbon nitride layer.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The first mixed gas also includes an inert gas, which includes at least one of the following gases: argon, nitrogen, and argon.

8. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The dry etching process conditions include: The bottom of the initial trench is etched using a pulsed bias power output mode, with a pulsed bias of 13.56 MHz and a source power range of 1200–3000 W. The flow rate of nitrogen trifluoride ranges from 5 to 50 sccm, and the flow rate of hydrogen ranges from 100 to 400 sccm. The dry etching time is controlled within the range of 10 to 60 seconds, and the ambient pressure for dry etching is controlled within the range of 100 to 1200 mTorr.

9. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that, The process conditions for the high-temperature treatment include: the ambient temperature is controlled between 100 and 200°C.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The second mixed gas includes at least one of chlorine, carbon tetrafluoride, oxygen, and an inert gas.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The target aspect ratio is greater than 10 and less than or equal to 15.

12. A semiconductor structure, characterized in that, The semiconductor structure is prepared according to the semiconductor structure formation method according to any one of claims 1 to 11.

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