Wafer trimming method, device, equipment and medium

Abstract

The present disclosure provides a wafer tuning method, device, equipment and medium, and relates to the technical field of semiconductor manufacturing. The method comprises: obtaining wafer grain data of a plurality of grains on a wafer to be tuned, wherein the wafer grain data of each grain comprises a performance parameter to be tuned of the grain and an actual tuning requirement identifier of the grain; for each grain, the following steps are performed: in a plurality of sets of tuning strategies, a set of tuning strategies corresponding to the actual tuning requirement identifier of the grain is selected, wherein a set of tuning strategies corresponds to a first corresponding relationship, and each first corresponding relationship is a corresponding relationship between a performance parameter and a tuning identifier; according to the first corresponding relationship corresponding to the selected set of tuning strategies, a target tuning identifier corresponding to the performance parameter to be tuned of the grain is determined, so as to perform tuning on the performance parameter to be tuned of the grain according to the tuning scheme corresponding to the target tuning identifier. According to the embodiment of the present disclosure, the manufacturing yield of the chip can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a wafer trimming method, apparatus, equipment and medium. Background Technology

[0002] In semiconductor manufacturing technology, a wafer with multiple grains distributed on it can be formed first, and then chips can be prepared by various processes such as slicing and packaging on a grain-by-grain basis.

[0003] During the manufacturing process, the yield of chips can be improved by adjusting the wafers.

[0004] However, the current chip manufacturing yield often needs further improvement.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a wafer trimming method, apparatus, equipment, and medium that improves chip manufacturing yield to at least a certain extent.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to one aspect of this disclosure, a wafer trimming method is provided, comprising: Acquire the grain data of multiple dies on the wafer to be repaired, wherein the grain data of each die includes the performance parameters to be repaired of the die and the actual repair requirement identifier of the die. For each grain, perform the following steps: Among multiple tuning strategies, a tuning strategy corresponding to the actual tuning requirement identifier of the grain is selected. Each tuning strategy corresponds to a first correspondence relationship, and each first correspondence relationship is used to characterize the correspondence between performance parameters and tuning identifiers. Based on the first correspondence of the selected set of adjustment strategies, a target adjustment identifier corresponding to the performance parameters to be adjusted of the grain is determined, and the adjustment scheme corresponding to the target adjustment identifier is executed to adjust the performance parameters to be adjusted of the grain.

[0009] In one embodiment, before selecting a tuning strategy corresponding to the actual tuning requirement identifier of the grain from multiple tuning strategies, the method further includes: Multiple dies are classified according to the adjustment requirement identifier, resulting in multiple categories. Each die in each category corresponds to the same adjustment requirement identifier. Among multiple tuning strategies, select the one that corresponds to the tuning requirement identifier of the grain, specifically including: For each category, perform the following steps: Among multiple adjustment strategies, determine the adjustment strategy that corresponds to this category; The set of adjustment strategies corresponding to this category is determined as a set of adjustment strategies corresponding to the adjustment requirement identifier of each grain within this category.

[0010] In one embodiment, among multiple adjustment strategies, determining a set of adjustment strategies corresponding to the category includes: Obtain the second correspondence, which is a one-to-one correspondence between multiple sets of adjustment strategies and multiple benchmark adjustment requirement identifiers; Among multiple baseline adjustment requirement identifiers, identify the target baseline adjustment requirement identifier corresponding to this category; The set of adjustment strategies corresponding to the target baseline adjustment requirement identifier in the second correspondence is determined as the set of adjustment strategies corresponding to this category.

[0011] In one embodiment, among multiple tuning strategies, a tuning strategy corresponding to the actual tuning requirement identifier of the grain is determined, including: Obtain the second correspondence, which is a one-to-one correspondence between multiple sets of adjustment strategies and multiple benchmark adjustment requirement identifiers; Among multiple baseline adjustment requirement identifiers, identify the target baseline adjustment requirement identifier that matches the actual adjustment requirement identifier of the grain. The set of adjustment strategies corresponding to the target benchmark adjustment requirement identifier in the second correspondence is determined as the set of adjustment strategies corresponding to the actual adjustment requirement identifier of the grain.

[0012] In one embodiment, before obtaining the second correspondence, the method further includes: Obtain multiple adjustment strategies; Establish a correspondence between the maintenance requirement identifiers of multiple maintenance strategies and the multiple maintenance strategies to obtain the second correspondence.

[0013] In one embodiment, the first correspondence includes: a one-to-one correspondence between multiple preset adjustment identifiers and multiple benchmark performance parameters; Based on the first correspondence corresponding to the selected set of tuning strategies, determine the target tuning identifier corresponding to the performance parameters to be tuned for the grain, including: Among multiple benchmark performance parameters, a target benchmark performance parameter that matches the performance parameter to be adjusted for this grain is determined. In the first correspondence, the preset adjustment identifier corresponding to the target benchmark performance parameter is determined as the target adjustment identifier.

[0014] In one embodiment, before selecting a tuning strategy corresponding to the actual tuning requirement identifier of the grain from multiple tuning strategies, the method further includes: Receive multiple sets of adjustment and repair request data. Each set of adjustment and repair request data includes multiple sets of corresponding baseline performance parameters and preset adjustment and repair identifiers defined by the user. For each set of adjustment and repair requirements data, a first correspondence is generated based on multiple sets of corresponding benchmark performance parameters and preset adjustment and repair identifiers; The first correspondence is used as a set of adjustment strategies.

[0015] In one embodiment, the method further includes: Multiple feasible adjustment schemes for the grain are determined, wherein any two feasible adjustment schemes correspond to different parameter adjustment amounts; Assign different identifiers to multiple feasible adjustment solutions; The identifiers of multiple feasible adjustment schemes are used as multiple preset adjustment identifiers.

[0016] In one embodiment, after determining the target adjustment identifier corresponding to the actual measurement value, the method further includes: Target tuning files are generated using the target tuning identifiers corresponding to each of the multiple grains. The target tuning file is sent to the target tuning module so that the target tuning module can perform tuning processing on multiple dies based on the target tuning file.

[0017] In one embodiment, the adjustment scheme is a scheme of melting and breaking the grains; After determining the target adjustment identifier corresponding to the performance parameters to be adjusted for the grain, the method further includes: For each grain, based on the adjustment scheme corresponding to the target adjustment identifier of the grain, the melting state of each of the multiple fuses of the grain is determined. The melting state is either the first melting state indicating melting or the second melting state indicating no melting. The fuse in the first melting state among multiple fuses is melted to achieve the adjustment of the characteristic parameters of the grain to be adjusted.

[0018] In one embodiment, the performance parameters to be adjusted for each grain include the voltage parameter and / or time parameter of that grain.

[0019] In one embodiment, the actual adjustment requirements of each grain are identified by a parameter reflecting the adjustment requirements of that grain; The adjustment requirement identifier includes at least one of the following: the customer identifier of the customer to which the die belongs, the identity identifier of the die, and the classification identifier of the die.

[0020] According to another aspect of this disclosure, a wafer trimming apparatus is provided, comprising: The data acquisition module is used to acquire the grain data of multiple dies on the wafer to be repaired. The grain data of each die includes the performance parameters to be repaired of the die and the actual repair requirement identifier of the die. The tuning strategy selection module is used to select a tuning strategy that corresponds to the actual tuning requirement identifier of each die from multiple tuning strategies. Each tuning strategy corresponds to a first correspondence relationship, and each first correspondence relationship is used to characterize the correspondence between performance parameters and tuning identifiers. The adjustment scheme selection module is used to determine the target adjustment identifier corresponding to the performance parameters to be adjusted of each die according to the first correspondence of the selected adjustment strategy, so as to execute the adjustment scheme corresponding to the target adjustment identifier to adjust the performance parameters to be adjusted of the die.

[0021] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described wafer trimming method by executing the executable instructions.

[0022] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the wafer trimming method described above.

[0023] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the wafer trimming method described above.

[0024] The wafer trimming method, apparatus, device, and medium provided in this disclosure can obtain the actual trimming requirement identifiers of each die on the wafer to be trimmed. Since the actual trimming requirement identifiers reflect the actual trimming requirements of each die, a suitable trimming strategy can be selected individually based on the die's trimming requirements. Then, using the correspondence between the performance parameters recorded in this trimming strategy and the trimming identifiers, a matching target trimming identifier is selected based on the die's performance parameters to be trimmed, and the trimming scheme corresponding to the target trimming identifier is used to trim the die's performance parameters. Therefore, the technical solution provided in this disclosure can select a suitable trimming scheme from a suitable trimming strategy according to the trimming requirements of each die, improving the wafer trimming accuracy and thus improving the chip manufacturing yield.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 A schematic diagram of the semiconductor manufacturing process is shown; Figure 2 A schematic diagram of a wafer structure provided in an embodiment of this disclosure is shown; Figure 3 This illustration shows a schematic diagram of a wafer trimming method according to an embodiment of the present disclosure. Figure 4 This diagram illustrates a wafer trimming method according to an embodiment of the present disclosure. Figure 5 This diagram illustrates another wafer trimming method according to an embodiment of the present disclosure. Figure 6 A schematic flowchart of an exemplary wafer trimming method provided in an embodiment of this disclosure is shown; Figure 7 A schematic flowchart of an exemplary wafer trimming method provided in an embodiment of this disclosure is shown; Figure 8A and Figure 8B An exemplary diagram of the parsed circuit breaker file is shown; Figure 9 A schematic flowchart of another wafer trimming method provided in an embodiment of this disclosure is shown; Figure 10 This diagram illustrates a wafer trimming apparatus according to an embodiment of the present disclosure. Figure 11 This diagram illustrates a structural block diagram of an electronic device according to an embodiment of the present disclosure. Figure 12 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0029] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0030] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0031] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0032] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0033] This disclosure provides a wafer trimming method that can be applied to semiconductor manufacturing technology. To facilitate a comprehensive understanding of the technical solutions provided in this disclosure, the semiconductor manufacturing process will first be described in conjunction with the accompanying drawings.

[0034] Figure 1 A schematic diagram of a semiconductor manufacturing process is shown. (For example...) Figure 1 As shown, semiconductor manufacturing processes can be divided into front-end processes and back-end processes.

[0035] Specifically, the front-end process refers to the process applied to the entire wafer, which may include wafer fabrication 11 and wafer probing (CP) 12. Among these, Figure 2 A schematic diagram of a wafer structure provided in an embodiment of this disclosure is shown. Figure 2 As shown, the wafer 20 may include multiple dies 21. During wafer testing, for example, a probe station can be used to perform probe testing on the dies on the wafer.

[0036] Furthermore, the subsequent processes are the various processes that proceed from wafer dicing and packaging to individual chips, which may include processes such as packaging 13, final testing 14, and finished product warehousing 15.

[0037] In the semiconductor manufacturing process described above, to improve chip manufacturing yield, wafers can be modified to increase the yield. For example, individual dies on the wafer can be modified using methods such as melting to optimize one or more performance parameters of the wafer. This brings the performance parameters of each modified die within the corresponding specification range, thereby improving the wafer yield.

[0038] However, the current chip manufacturing yield is often low and needs to be further improved.

[0039] Therefore, improving chip manufacturing yield has become an urgent problem to be solved.

[0040] The inventors discovered through research that, to meet practical needs, different grades of dies can be manufactured on the same wafer. For example, different customers may have different requirements for the characteristic parameters of dies. If the same tuning scheme is used to tune the characteristic parameters of the dies, the target adjustment values ​​for the characteristic parameters of each die may be the same, failing to meet customer needs and thus affecting the wafer manufacturing yield and chip manufacturing yield. Therefore, as wafer yield and cost increase, it is possible to manufacture dies of different grades and specifications on a single wafer to meet the needs of different customers.

[0041] Based on this, embodiments of this disclosure provide a wafer trimming method, apparatus, device, and medium, which can be applied in semiconductor manufacturing scenarios. For example, it can be applied to specific scenarios of wafer probing (CP), or it can be used in the repair stage after wafer probing, without specific limitations. In embodiments of this disclosure, a suitable trimming scheme can be selected from appropriate trimming strategies according to the trimming requirements of each die, improving the trimming accuracy of the wafer and thus improving the chip manufacturing yield.

[0042] The specific solutions provided in the embodiments of this disclosure will be described next.

[0043] Before describing the technical solutions provided in the embodiments of this disclosure, for ease of understanding, an example will be used to illustrate the embodiments of this disclosure in conjunction with a specific wafer trimming scenario.

[0044] Figure 3 This illustration shows a schematic diagram of a wafer trimming method provided in an embodiment of this disclosure. Figure 3 As shown, firstly, test data 31 of multiple dies on the wafer can be obtained. For example, test data 31 may include multiple dies such as voltage parameters, time parameters, and performance parameters such as BIAS1, BIAS2, BIAS3, BIAS4, BIAS5, ...

[0045] Then, when dynamically adjusting each grain, a specific adjustment strategy corresponding to each grain can be selected from multiple adjustment strategies 32. For details regarding multiple adjustment strategies, please refer to [link to relevant documentation]. Figure 3 Each column of adjustment identifiers in the multiple adjustment strategies 32 corresponds to a different adjustment strategy. For example, the first column represents the first adjustment strategy 321. Furthermore, the adjustment identifiers in each column are the target adjustment identifiers to be used for each die when employing that adjustment strategy. Also, adjustment identifiers in the same row correspond to different adjustment requirements. For example, for a die with performance parameter BIAS4 to be adjusted, if the adjustment scheme corresponding to the "#x4" adjustment identifier is used, it can meet the requirements of Customer 1; if the adjustment scheme corresponding to the "#y4" adjustment identifier is used, it can meet the requirements of Customer 2.

[0046] Then, if multiple chips are customized by customer 1, that is, multiple chips correspond to the first set of adjustment strategies 321, the adjustment identifier 33 corresponding to the performance parameters to be adjusted of each chip can be determined by the first adjustment strategy. Then, the adjustment identifier 33 corresponding to the performance parameters to be adjusted of each chip is used to perform a fuse blown on each chip, so that the performance parameters of each chip after the fuse blown can meet the needs of customer 1.

[0047] In passing Figure 3 After introducing the technical solutions of the embodiments of this disclosure, the following will describe the exemplary implementation methods in detail with reference to the accompanying drawings and embodiments.

[0048] First, this disclosure provides a wafer trimming method, which can be executed by any electronic device with computing capabilities. For example, this method can be executed by an automated chip testing device.

[0049] Figure 4 This diagram illustrates a wafer trimming method according to an embodiment of the present disclosure, as follows: Figure 4 As shown, the wafer trimming method provided in this embodiment includes the following steps S410 to S430.

[0050] S410: Acquire the die data of multiple dies on the wafer to be adjusted. The die data for each die includes the performance parameters to be adjusted for that die and the actual adjustment requirement identifier for that die.

[0051] The wafer to be repaired can be a wafer prepared for repair processing. For example, it can be a wafer that has entered the wafer testing process.

[0052] For multiple grains, they can be at least a portion of the grains on the wafer to be modified, which are intended to undergo modification processing. In some embodiments, to improve preparation efficiency, they can be selected good bins on the wafer to be modified, or grains that can be transformed into good bins through modification processing.

[0053] The performance parameter to be adjusted can be a parameter that can be corrected or optimized through grain adjustment. In some embodiments, if adjustment is performed by melting the fuse in the grain, the performance parameter to be adjusted can be a parameter that can be corrected by melting.

[0054] For example, the performance parameters to be adjusted for each die include the die's voltage parameters and / or time parameters. For instance, the voltage parameters can be the die's internal voltages such as the program / erase voltage (VPP) and bit line precharge voltage (VBLP).

[0055] This example demonstrates how to customize the time and voltage parameters of a wafer according to its specific needs. This allows for the manufacture of dies with different time and / or voltage characteristics based on the same wafer, thereby improving die manufacturing yield.

[0056] The actual repair requirement identifier can be a parameter that directly or indirectly reflects the die repair requirement, wherein the repair requirement can be a requirement for repair using a specific repair strategy. For example, it can include at least one of the following: the customer identifier of the die's owner, the die's identity identifier, and the die's classification identifier. The die's identity identifier can be the die's position parameter on the wafer or other information that distinguishes it from other dies. It should be noted that if the die can undergo different repair processes based on one or more characteristic data, then the actual repair requirement parameter can be that characteristic data, without specific limitations.

[0057] This example demonstrates how to select a suitable tuning strategy for different customers, individual dies, or different types of dies, thereby improving wafer tuning accuracy and enabling dies on the same wafer to meet different manufacturing requirements, thus improving chip manufacturing yield and precision.

[0058] In some embodiments, S410 may specifically include: obtaining the grain data of multiple grains on the wafer to be adjusted by testing pre-set target test items. It should be noted that the grain data can also be obtained through other methods, and no specific limitations are imposed on this.

[0059] After introducing the S410, the S420 will be explained next.

[0060] S420: For each die, select the adjustment strategy that corresponds to the actual adjustment requirement of the die from multiple adjustment strategies.

[0061] For each set of adjustment strategies, each set of adjustment strategies corresponds to a first correspondence relationship, and each first correspondence relationship is the correspondence between performance parameters and adjustment identifiers.

[0062] In some embodiments, the first correspondence between any two sets of adjustment strategies may be the same or different, and no specific limitation is made thereto.

[0063] In some embodiments, S420 may include: determining a set of adjustment strategies corresponding to the actual adjustment requirement identifier based on the correspondence between the adjustment strategy and the adjustment requirement identifier.

[0064] The correspondence between the adjustment strategy and the adjustment requirement identifier can be a relational function, or a one-to-one correspondence between multiple baseline adjustment requirement identifiers and multiple adjustment strategies, without specific restrictions.

[0065] For example, this correspondence can be a one-to-one correspondence between multiple baseline maintenance requirement parameters and multiple maintenance strategies. For instance, the first baseline maintenance requirement parameter bin1 corresponds to the first maintenance requirement strategy target1, the second baseline maintenance requirement parameter bin2 corresponds to the second maintenance requirement strategy target2, and so on, with the m-th baseline maintenance requirement parameter corresponding to the m-th maintenance requirement strategy targetm, where m is any positive integer. It should be noted that the first correspondence can also be other specific forms that reflect the relationship between maintenance requirement strategies and performance parameters; no specific limitations are imposed on this.

[0066] For example, each tuning strategy can correspond to a target tuning value, which is the expected performance parameter of the die when using that tuning strategy. Accordingly, this correspondence can be between the target tuning value and the tuning requirement parameters.

[0067] S430: For each die, based on the first correspondence of the selected set of adjustment strategies, determine the target adjustment identifier corresponding to the performance parameter to be adjusted of the die, and execute the adjustment scheme corresponding to the target adjustment identifier to adjust the performance parameter to be adjusted of the die.

[0068] The first correspondence is used to characterize the correspondence between performance parameters and adjustment identifiers.

[0069] In one embodiment, the first correspondence can be a relationship function between performance parameters and adjustment identifiers.

[0070] Accordingly, in S430, the target adjustment identifier can be calculated using this relational function and the performance parameters to be adjusted.

[0071] In another example, the first correspondence can be a one-to-one correspondence between multiple baseline performance parameters and multiple preset adjustment identifiers. For example, the first baseline performance parameter data1 corresponds to the first preset adjustment identifier code1, the second baseline performance parameter data2 corresponds to the second preset adjustment identifier code2, and so on, with the nth baseline performance parameter datan corresponding to the nth preset adjustment identifier coden, where n is any positive integer. It should be noted that the first correspondence can also be other specific forms that reflect the association between adjustment identifiers and performance parameters, and there are no specific limitations on this.

[0072] Accordingly, S430 may include the following steps A1 and A2.

[0073] Step A1: Among multiple reference performance parameters, determine the target reference performance parameter that matches the performance parameter to be adjusted for the grain.

[0074] For example, from multiple baseline performance parameters, one can select the one that is closest to the performance parameter to be adjusted (e.g., the one with the smallest absolute difference) as the target baseline performance parameter. It should be noted that other methods can also be used to select the target baseline performance parameter from the baseline performance parameters; there are no specific restrictions on this.

[0075] Step A2: In the first correspondence, the preset adjustment identifier corresponding to the target baseline performance parameter is determined as the target adjustment identifier.

[0076] For example, continuing with the example above, if the target baseline performance parameter is the second baseline performance parameter data2, then the corresponding second preset adjustment identifier code2 can be determined as the target adjustment identifier.

[0077] By using steps A1 and A2 above, the target adjustment identifier that best matches the performance parameters to be adjusted of the grain can be quickly and accurately determined by the correspondence between the preset benchmark performance parameters and the corresponding preset adjustment identifiers, thus ensuring both adjustment accuracy and adjustment efficiency.

[0078] In another example, the first correspondence could be the target adjustment value.

[0079] Accordingly, in S430, the difference between the target adjustment value and the performance parameter to be adjusted of the grain can be determined. Then, among the adjustment amounts corresponding to multiple preset adjustment identifiers, the adjustment amount that is closest to the difference (e.g., the smallest absolute difference) is selected, and the preset adjustment identifier corresponding to the selected adjustment amount is determined as the target adjustment identifier.

[0080] In one embodiment, if multiple tuning strategies all record a tuning identifier corresponding to a certain baseline tuning requirement parameter, then the tuning identifier corresponding to the baseline tuning requirement parameter in each tuning strategy may be the same or different. For example, if the performance parameter to be tuned for a certain die is data2, then a tuning strategy may use the tuning scheme corresponding to the preset tuning identifier code1 to tune it, so that the change in its performance parameter is... In another tuning strategy, the tuning scheme corresponding to the preset tuning identifier code3 needs to be used to tune it so that the change in its performance parameters is... .

[0081] The wafer trimming method provided in this embodiment obtains the actual trimming requirement identifiers of each die on the wafer to be trimmed through the above steps S410-S430. Since the actual trimming requirement identifiers reflect the actual trimming requirements of each die, a suitable trimming strategy can be selected in a personalized manner according to the trimming requirements of the die. Then, using the correspondence between the performance parameters recorded in the trimming strategy and the trimming identifiers, a matching target trimming identifier is selected according to the performance parameters to be trimmed of the die, so as to trim the performance parameters to be trimmed of the die using the trimming scheme corresponding to the target trimming identifier. Therefore, the technical solution provided in this embodiment can select a suitable trimming scheme from a suitable trimming strategy in a personalized manner according to the trimming requirements of each die, thereby improving the trimming accuracy of the wafer and thus improving the chip manufacturing yield.

[0082] Furthermore, the embodiments disclosed herein can improve wafer manufacturing yield and manufacture dies on the same wafer to meet different needs, thereby reducing wafer costs and increasing the flexibility of wafer and die adjustment.

[0083] In some embodiments, after S420, the wafer trimming method provided in this disclosure further includes steps related to constructing a first correspondence, namely steps A3 to A5 below.

[0084] Step A3: Receive multiple sets of adjustment and repair request data. Each set of adjustment and repair request data includes multiple sets of corresponding baseline performance parameters and preset adjustment and repair identifiers defined by the user.

[0085] It should be noted that a set of adjustment requirement data can also specify target adjustment values ​​for users. Users can set information related to the first correspondence according to the actual scenario and specific needs, without specific restrictions.

[0086] Step A4: For each set of adjustment and repair requirement data, generate a first correspondence relationship based on multiple sets of corresponding baseline performance parameters and preset adjustment and repair identifiers.

[0087] It should be noted that the specific content of the first correspondence can be found in the relevant content of the above-mentioned parts of the embodiments of this disclosure, and there is no specific limitation thereto.

[0088] Step A5: Treat each first correspondence as a set of adjustment strategies.

[0089] In one example, a correspondence can be established between each first correspondence and the baseline adjustment requirement identifier, so that during the actual adjustment process of the die, an appropriate adjustment strategy can be selected for the die based on the actual adjustment requirement identifier of the die.

[0090] Through steps A3 and A5 above, the die can be adjusted according to the adjustment plan specified by the user, thereby enabling different dies to be manufactured on the same wafer according to different user needs, improving manufacturing flexibility and wafer manufacturing yield.

[0091] In some embodiments, the present disclosure also provides steps for constructing a preset adjustment identifier. Specifically, the wafer adjustment method provided in the present disclosure further includes the following steps B1 to B3.

[0092] Step B1: Determine multiple feasible adjustment schemes for the grain. Any two feasible adjustment schemes can correspond to different parameter adjustment amounts.

[0093] In one example, taking fuse-based repair as an example, different feasible fuse-breaking methods for multiple fuses on a single die can serve as multiple feasible repair solutions. The fuse can be an electrically programmable fuse (E_fuse) or a laser fuse; there are no specific restrictions on the fuse type.

[0094] For example, Table 1 shows several feasible fusing schemes for a grain containing four fuses. "0" indicates no fusing and "1" indicates fusing.

[0095] Table 1

[0096] As shown in Table 1, if a grain includes 4 fuses, it can correspond to 16 adjustment methods P1-P16.

[0097] Step B2 assigns different identifiers to multiple feasible adjustment solutions.

[0098] The identifier can be a combination of numbers, letters, Chinese characters, etc., capable of distinguishing different feasible adjustment schemes, without specific limitations. For example, continuing to refer to Table 1, it can be the characters 0-F shown in Table 1 above.

[0099] In one embodiment, in order to facilitate the determination of the corresponding fuse-breaking scheme based on the identifier in the subsequent process, the identifier of each feasible adjustment scheme can be generated based on the bit sequence composed of the fuse-breaking states of each fuse in the feasible fuse-breaking scheme.

[0100] For example, continuing to refer to Table 1, for feasible adjustment scheme P12, the bit sequence composed of the fuse states of each fuse is "1011", so its fuse flag can be set to "1011", or other base characters, such as hexadecimal "B", without specific restrictions.

[0101] Step B3: The identifiers of multiple feasible adjustment schemes are used as multiple preset adjustment identifiers.

[0102] For example, referring to Table 1 above, all identifiers 0-F can be used as preset adjustment identifiers.

[0103] Through steps B1-B3 above, a correspondence between feasible adjustment schemes and preset adjustment identifiers can be established. This makes it easier to determine the target adjustment identifier corresponding to the die among multiple preset adjustment identifiers, and then quickly and accurately determine the target adjustment scheme corresponding to the target adjustment identifier. This target adjustment scheme can then be used to accurately adjust the die, thus balancing adjustment efficiency and accuracy.

[0104] In some embodiments, the wafer trimming method provided in this disclosure further includes the following steps C1 and C2 after S430.

[0105] Step C1: Generate target adjustment files using the target adjustment identifiers corresponding to each of the multiple grains.

[0106] The target tuning file can be a file that records the target tuning identifiers for each grain. For example, when the tuning method used is fuse blowing, the target tuning file can be a file that records the target fuse blowing scheme identifiers for each grain. Accordingly, the target tuning file can be called a fuse blown file.

[0107] Step C2: Send the target tuning file to the target tuning module so that the target tuning module can perform tuning processing on multiple dies based on the target tuning file.

[0108] Through the above steps C1 and C2, after determining the target adjustment identifier of each die, a target adjustment file is generated that records the target adjustment identifier of each die in the wafer. This allows the target adjustment module to perform batch and accurate adjustment processing on the dies on the wafer according to the target adjustment file, thereby improving the manufacturing efficiency of wafers and chips.

[0109] In some embodiments, if the adjustment scheme is a scheme of melting the grain, then after S430, the following steps D1 and D2 are also included.

[0110] Step D1: For each grain, based on the adjustment scheme corresponding to the target adjustment identifier of that grain, determine the respective melting states of the multiple fuses of that grain. The melting state is either a first melting state indicating melting or a second melting state indicating no melting.

[0111] In one example, referring to Table 1, if the target adjustment identifier corresponding to a certain grain is 8, the fusing state of fuses E1-E3 can be determined as the second fusing state (not fusing) according to the feasible fusing scheme P09, and the fusing state of fuse E4 is the first fusing state (fusing).

[0112] Step D2: For each grain, the fuse in the first melting state among the multiple fuses is melted to achieve the adjustment of the grain's characteristic parameters to be adjusted.

[0113] Continuing with the previous example, the fuse E4 in the grain can be melted.

[0114] Through the above steps D1 and D2, each fuse in the die can be accurately processed according to the target adjustment mark, thereby accurately adjusting the performance parameters of the die to be adjusted, so that the adjusted performance parameters can meet the requirements, thereby improving the manufacturing yield of wafers and chips.

[0115] Figure 5 This illustration shows a schematic flowchart of another wafer trimming method provided by an embodiment of the present disclosure. This embodiment is an optimization based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0116] like Figure 5 As shown, the wafer trimming method provided in this embodiment may include the following steps S510 to S550.

[0117] S510, acquire the grain data of multiple dies on the wafer to be adjusted, wherein the grain data of each die includes the performance parameters to be adjusted of the die and the actual adjustment requirement identifier of the die.

[0118] S510 is similar to S410; please refer to the details of S410 for further information, which will not be repeated here.

[0119] S520 classifies multiple dies according to the adjustment requirement identifier, resulting in multiple categories. Dies within each category correspond to the same adjustment requirement identifier.

[0120] For the identification of adjustment and repair needs, please refer to the relevant description in the above section of the embodiments of this disclosure, and will not be repeated here.

[0121] For example, Figure 6 A schematic flowchart of an exemplary wafer trimming method provided in an embodiment of this disclosure is shown. Figure 6 As shown, the target test items can be used to obtain grain data for multiple grains on the wafer. Then, the grains are classified, resulting in multiple categories, such as "bin1", "bin2", "bin4", etc.

[0122] S530: For each category, among multiple adjustment strategies, determine the adjustment strategy corresponding to that category.

[0123] Optionally, the adjustment strategy corresponding to each category can be determined based on the pre-set correspondence between the classification and the adjustment strategy.

[0124] In some embodiments, S530 may include the following steps E1 to E3.

[0125] Step E1: Obtain the second correspondence. The second correspondence is a one-to-one correspondence between multiple adjustment strategies and multiple baseline adjustment requirement identifiers.

[0126] Among them, the benchmark adjustment and maintenance requirement identifier can be a parameter that reflects the adjustment and maintenance requirement, such as the classification identifier "bin1", "bin2", etc.

[0127] Step E2: Among multiple baseline adjustment requirement identifiers, determine the target baseline adjustment requirement identifier corresponding to this category.

[0128] For example, a baseline repair request identifier that matches the repair request identifier of the category can be determined as the target baseline repair request identifier corresponding to the category. It should be noted that other methods can also be used to determine the target baseline request identifier of the category, and no specific limitation is made thereto.

[0129] Step E3: Determine the set of adjustment strategies corresponding to the target baseline adjustment requirement identifier in the second correspondence as the set of adjustment strategies corresponding to this category.

[0130] For example, see [link to previous article] Figure 6 Strategy 1 can be defined as a set of tuning strategies corresponding to category "bin1", in which the target tuning identifier corresponding to the die in category "bin1" can be selected, such as identifier C1. And strategy 2 can be defined as a set of tuning strategies corresponding to category "bin2", in which the target tuning identifier corresponding to the die in category "bin2" can be selected, such as identifier C2.

[0131] Optionally, to facilitate subsequent adjustment processing, after determining the target adjustment identifier of the grains in each category, a target adjustment file such as the fuse file 63 can be generated accordingly for adjustment processing.

[0132] Through the above steps E1-E3, a set of adjustment strategies corresponding to each category can be determined according to the second correspondence. This adjustment strategy is then used as the adjustment strategy for each die in that category. This allows for the rapid determination of the adjustment strategy for each category based on the second correspondence. Then, this adjustment strategy can be used to adjust each die in that category, improving adjustment efficiency and thus increasing the fabrication efficiency of wafers and chips.

[0133] In some embodiments, the method further includes the step of establishing a second correspondence, that is, before step A1, it may also include the following steps E4 and E5.

[0134] Step E4: Obtain multiple adjustment strategies.

[0135] It should be noted that the specific details of each adjustment strategy can be found in the relevant descriptions in the above sections of the embodiments of this disclosure, and will not be repeated here.

[0136] Step E5: Establish the correspondence between the adjustment and maintenance requirement identifiers of multiple adjustment and maintenance strategies and the multiple adjustment and maintenance strategies to obtain the second correspondence.

[0137] The second correspondence can be a relation function or multiple sets of baseline correspondences, without specific limitations.

[0138] By using steps E4 and E5, the correspondence between the pre-set adjustment requirement identifier and the adjustment strategy can be established. This allows for the rapid and accurate determination of the adjustment strategy to be used during wafer adjustment based on the actual adjustment requirement identifier, thereby improving wafer adjustment efficiency and ultimately increasing the wafer and chip fabrication efficiency.

[0139] S540, for each category, a set of adjustment strategies corresponding to that category is determined as a set of adjustment strategies corresponding to the adjustment requirement identifier of each grain in that category.

[0140] For example, if category "bin1" corresponds to strategy 1, then the tuning strategy corresponding to each grain belonging to "bin1" is strategy 1.

[0141] S550: For each die, based on the first correspondence of the selected set of adjustment strategies, determine the target adjustment identifier corresponding to the performance parameters to be adjusted of the die, and execute the adjustment scheme corresponding to the target adjustment identifier to adjust the performance parameters to be adjusted of the die.

[0142] S550 is similar to S430; please refer to the details of S430 for further information, which will not be repeated here.

[0143] The wafer trimming method provided in this disclosure can obtain the actual trimming requirement identifiers of each die on the wafer to be trimmed. Since the actual trimming requirement identifiers can reflect the actual trimming requirements of each die, a suitable trimming strategy can be selected individually based on the trimming requirements of the die. Then, using the correspondence between the performance parameters recorded in this trimming strategy and the trimming identifiers, a matching target trimming identifier is selected according to the performance parameters to be trimmed of the die, so as to trim the performance parameters to be trimmed of the die using the trimming scheme corresponding to the target trimming identifier. Therefore, the technical solution provided in this disclosure can select a suitable trimming scheme from a suitable trimming strategy according to the trimming requirements of each die, improving the trimming accuracy of the wafer and thus improving the chip manufacturing yield. Furthermore, through steps S510 to S550, the dies can be classified first, and then each die in the class can be precisely adjusted according to a set of adjustment strategies corresponding to each class, thereby taking into account both adjustment accuracy and adjustment efficiency, and improving the manufacturing efficiency of wafers and chips.

[0144] In a specific example Figure 7 A schematic flowchart of an exemplary wafer trimming method provided in an embodiment of this disclosure is shown. Figure 7 As shown, after obtaining test results including grain data through the target test items, S701 to S703 can be executed to generate the fuse file 72.

[0145] Specifically, in step S701, the wafers are classified using the actual repair requirement identifiers of each wafer in the wafer data. Then, in step S702, the repair strategy corresponding to each classification can be determined, and the target repair identifier of the wafers in each classification can be determined based on the repair strategy corresponding to each classification. Then, in step S703, each wafer and its corresponding target repair identifier can be written to a file to generate a circuit breaker file 72.

[0146] For circuit breaker document 72, Figure 8A and Figure 8B An exemplary diagram of the parsed circuit breaker file is shown. (For example...) Figure 8A As shown, for each die classified as chip 1, if classification 1 corresponds to adjustment strategy 2, then the adjustment identifier corresponding to each die in adjustment strategy 2 can be determined as the fuse identifier used in the actual fuse-breaking scheme. And, as... Figure 8B As shown, for each die in chip category 2, if category 2 corresponds to adjustment strategy 1, then the fuse can be blown according to the fuse scheme corresponding to the adjustment identifier of each die in adjustment strategy 1.

[0147] And, through Figure 8A and Figure 8B It is known that for the same grain, when using adjustment strategy 1 or adjustment strategy 2 for fusing, the fusing schemes employed can be different. For example, for Figure 8A For the first row of the corresponding grains, if adjustment strategy 1 and adjustment strategy 2 are adopted, the corresponding fusing schemes for fusing identifier 8 and adjustment identifier 0 need to be used for processing, respectively.

[0148] Figure 9 This illustration shows a schematic flowchart of another wafer trimming method provided by an embodiment of the present disclosure. This embodiment is an optimization based on the above embodiments, and can be combined with various optional solutions from one or more of the above embodiments.

[0149] like Figure 9 As shown, the wafer trimming method provided in this embodiment may include the following steps S910 to S950.

[0150] S910 acquires the grain data of multiple grains on the wafer to be adjusted.

[0151] The grain data for each grain includes the performance parameters to be adjusted for that grain and the actual adjustment requirements for that grain.

[0152] S910 is similar to S410; please refer to the details of S410 for further information, which will not be repeated here.

[0153] S920, obtain the second correspondence.

[0154] The second correspondence is a one-to-one correspondence between multiple adjustment strategies and multiple benchmark adjustment requirement identifiers.

[0155] It should be noted that the specific details of the second correspondence can be found in the relevant descriptions in the above sections of the embodiments of this disclosure, and will not be repeated here.

[0156] S930, for each die, determines the target reference adjustment requirement identifier that matches the actual adjustment requirement identifier of the die from multiple reference adjustment requirement identifiers.

[0157] In one example, the benchmark maintenance requirement identifier that is closest to or the same as the actual maintenance requirement identifier can be selected as the target benchmark maintenance requirement identifier. It should be noted that other methods can also be used to determine the target benchmark maintenance requirement identifier, and no specific limitations are imposed on this.

[0158] S940, for each die, determine a set of adjustment strategies corresponding to the target reference adjustment requirement identifier in the second correspondence as a set of adjustment strategies corresponding to the actual adjustment requirement identifier of the die.

[0159] S950: For each die, based on the first correspondence of the selected set of adjustment strategies, determine the target adjustment identifier corresponding to the performance parameters to be adjusted of the die, and execute the adjustment scheme corresponding to the target adjustment identifier to adjust the performance parameters to be adjusted of the die.

[0160] S950 is similar to S430; please refer to the details of S430 for further information, which will not be repeated here.

[0161] In some embodiments, prior to S920, the wafer trimming method may further include steps B1 and B2.

[0162] Step B1: Obtain multiple adjustment strategies.

[0163] Step B2: Establish the correspondence between the adjustment and maintenance requirement identifiers of multiple adjustment and maintenance strategies and the multiple adjustment and maintenance strategies to obtain the second correspondence.

[0164] The specific details of steps B1 and B2 can be found in the above description of steps A4 and A5 in the embodiments of this disclosure, and will not be repeated here.

[0165] The wafer trimming method provided in this disclosure can obtain the actual trimming requirement identifiers of each die on the wafer to be trimmed. Since the actual trimming requirement identifiers can reflect the actual trimming requirements of each die, a suitable trimming strategy can be selected in a personalized manner according to the trimming requirements of the die. Then, using the correspondence between the performance parameters recorded in the trimming strategy and the trimming identifiers, a matching target trimming identifier is selected according to the performance parameters to be trimmed of the die, so as to trim the performance parameters to be trimmed of the die using the trimming scheme corresponding to the target trimming identifier. Therefore, the technical solution provided in this disclosure can select a suitable trimming scheme from a suitable trimming strategy in a personalized manner according to the trimming requirements of each die, thereby improving the trimming accuracy of the wafer and thus improving the chip manufacturing yield.

[0166] Based on the same inventive concept, this disclosure also provides a wafer trimming apparatus, as shown in the following embodiments. In one example, the wafer trimming apparatus can be implemented as a functional module or component in an automated testing device, and there is no specific limitation thereto.

[0167] Figure 10 A schematic diagram of a wafer trimming apparatus according to an embodiment of this disclosure is shown, such as... Figure 10 As shown, the wafer adjustment device 1000 includes: a data acquisition module 1010, an adjustment strategy selection module 1020, and an adjustment scheme selection module 1030.

[0168] The data acquisition module 1010 is used to acquire the grain data of multiple grains on the wafer to be repaired. The grain data of each grain includes the performance parameters to be repaired of the grain and the actual repair requirement identifier of the grain. The tuning strategy selection module 1020 is used to select a tuning strategy that corresponds to the actual tuning requirement identifier of the die from multiple tuning strategies for each die. Each tuning strategy corresponds to a first correspondence relationship, and each first correspondence relationship is used to characterize the correspondence between performance parameters and tuning identifiers. The tuning scheme selection module 1030 is used to determine, for each die, a target tuning identifier corresponding to the performance parameters to be tuned of that die based on the first correspondence relationship corresponding to the selected tuning strategy, so as to execute the tuning scheme corresponding to the target tuning identifier to tune the performance parameters to be tuned of that die. The wafer trimming apparatus provided in this disclosure can acquire the actual trimming requirement identifiers of each die on the wafer to be trimmed. Since the actual trimming requirement identifiers reflect the actual trimming requirements of each die, a suitable trimming strategy can be selected in a personalized manner based on the trimming requirements of the die. Then, using the correspondence between the performance parameters recorded in the trimming strategy and the trimming identifiers, a matching target trimming identifier is selected according to the performance parameters to be trimmed of the die, so as to trim the performance parameters to be trimmed of the die using the trimming scheme corresponding to the target trimming identifier. Therefore, the technical solution provided in this disclosure can select a suitable trimming scheme from a suitable trimming strategy in a personalized manner according to the trimming requirements of each die, thereby improving the trimming accuracy of the wafer and thus improving the chip manufacturing yield.

[0169] In one embodiment, the wafer trimming apparatus 1000 further includes: The wafer classification module is used to classify multiple dies according to the repair requirement identifier, resulting in multiple categories. Each die in a category corresponds to the same repair requirement identifier. The adjustment strategy selection module 1020 specifically includes: The strategy selection unit is used to determine, from multiple sets of adjustment strategies, a set of adjustment strategies corresponding to each category. The strategy determination unit is used to determine a set of adjustment strategies corresponding to the category as a set of adjustment strategies corresponding to the adjustment requirement identifier of each grain in the category.

[0170] In one embodiment, the strategy selection unit includes: Obtain the sub-unit, which is used to obtain the second correspondence relationship. The second correspondence relationship is a one-to-one correspondence between multiple sets of adjustment strategies and multiple benchmark adjustment requirement identifiers. The identifier determination subunit is used to identify the target benchmark adjustment requirement identifier corresponding to the category among multiple benchmark adjustment requirement identifiers; The strategy determination subunit is used to determine a set of adjustment strategies corresponding to the target baseline adjustment requirement identifier in the second correspondence as a set of adjustment strategies corresponding to the category.

[0171] In one embodiment, the adjustment strategy selection module 1020 specifically includes: The relationship acquisition unit is used to acquire the second correspondence relationship, which is a one-to-one correspondence between multiple sets of adjustment strategies and multiple benchmark adjustment requirement identifiers. The identifier determination unit is used to determine, from multiple reference adjustment requirement identifiers, the target reference adjustment requirement identifier that matches the actual adjustment requirement identifier of the grain. The strategy determination unit is used to determine a set of adjustment strategies corresponding to the target benchmark adjustment requirement identifier in the second correspondence as a set of adjustment strategies corresponding to the actual adjustment requirement identifier of the grain.

[0172] In one embodiment, the wafer trimming apparatus 1000 further includes: The strategy acquisition unit is used to acquire multiple adjustment strategies; The relationship establishment unit is used to establish the correspondence between the maintenance requirement identifiers of multiple maintenance strategies and the multiple maintenance strategies, and to obtain the second correspondence.

[0173] In one embodiment, the first correspondence includes: a one-to-one correspondence between multiple preset adjustment identifiers and multiple benchmark performance parameters; The adjustment and repair scheme selection module 1030 includes: The parameter determination unit is used to determine, among multiple reference performance parameters, a target reference performance parameter that matches the performance parameter to be adjusted of the grain. The identifier determination unit is used to determine the preset adjustment identifier corresponding to the target reference performance parameter in the first correspondence relationship as the target adjustment identifier.

[0174] In one embodiment, the wafer trimming apparatus 1000 further includes: The data receiving unit is used to receive multiple sets of adjustment and maintenance requirement data, wherein each set of adjustment and maintenance requirement data includes multiple sets of corresponding benchmark performance parameters and preset adjustment and maintenance identifiers defined by the user. The relationship generation unit is used to generate a first correspondence relationship for each set of adjustment and repair requirement data, based on multiple sets of corresponding benchmark performance parameters and preset adjustment and repair identifiers. The strategy generation unit is used to treat each first correspondence as a set of adjustment strategies.

[0175] In one embodiment, the wafer trimming apparatus 1000 further includes: The adjustment scheme determination module is used to determine multiple feasible adjustment schemes for the grain, wherein any two feasible adjustment schemes correspond to different parameter adjustment amounts. The identifier assignment module is used to assign different identifiers to multiple feasible adjustment and repair schemes; The identifier determination module is used to identify multiple feasible adjustment schemes as multiple preset adjustment identifiers.

[0176] In one embodiment, the wafer trimming apparatus 1000 further includes: The file generation module is used to generate target adjustment files by utilizing the target adjustment identifiers corresponding to multiple grains. The file sending module is used to send the target tuning file to the target tuning module, so that the target tuning module can perform tuning processing on multiple dies based on the target tuning file.

[0177] In one embodiment, the adjustment scheme is a scheme of melting and breaking the grains; The wafer adjustment device 1000 also includes a fuse handling module.

[0178] The circuit breaker module is specifically configured as follows: For each grain, based on the adjustment scheme corresponding to the target adjustment identifier of the grain, the melting state of each of the multiple fuses of the grain is determined. The melting state is either the first melting state indicating melting or the second melting state indicating no melting. The fuse in the first melting state among multiple fuses is melted to achieve the adjustment of the characteristic parameters of the grain to be adjusted.

[0179] In one embodiment, the performance parameters to be adjusted for each grain include the voltage parameter and / or time parameter of that grain.

[0180] In one embodiment, the actual adjustment requirements of each grain are identified by a parameter reflecting the adjustment requirements of that grain; The adjustment requirement identifier includes at least one of the following: the customer identifier of the customer to which the die belongs, the identity identifier of the die, and the classification identifier of the die.

[0181] It should be noted that, Figure 10 The wafer trimming device 1000 shown can perform... Figures 4 to 9 The various steps in the method embodiment shown are implemented. Figures 4 to 9 The various processes and effects in the method embodiments shown are not elaborated here.

[0182] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0183] The following reference Figure 11 To describe an electronic device 1100 according to such an embodiment of the present disclosure. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0184] like Figure 11 As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, and a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110).

[0185] The storage unit stores program code that can be executed by the processing unit 1110, causing the processing unit 1110 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0186] Storage unit 1120 may include readable media in the form of volatile storage units, such as random access memory (RAM) 11201 and / or cache memory 11202, and may further include read-only memory (ROM) 11203.

[0187] Storage unit 1120 may also include a program / utility 11204 having a set (at least one) program module 11205, such program module 11205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0188] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0189] Electronic device 1100 can also communicate with one or more external devices 1140 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1100, and / or with any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). Such communication can be performed through input / output (I / O) interface 1150.

[0190] Furthermore, the electronic device 1100 can also communicate with one or more networks (such as local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via the network adapter 1160.

[0191] like Figure 11 As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130.

[0192] It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0193] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0194] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Figure 12 This illustration shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure, such as... Figure 12 As shown, the computer-readable storage medium 1200 stores a program product capable of implementing the methods described above.

[0195] In some possible implementations, various aspects of this disclosure may also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the “Exemplary Methods” section of this specification according to various exemplary embodiments of this disclosure.

[0196] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0197] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein readable program code is carried. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof.

[0198] A readable signal medium can also be any readable medium other than a readable storage medium, which can send, propagate or transmit a program for use by or in connection with an instruction execution system, apparatus or device.

[0199] In some examples, program code contained on a computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0200] In practical implementation, program code for performing the operations of this disclosure can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0201] In cases involving remote computing devices, the remote computing devices can be connected to user computing devices via any type of network, including local area networks (LANs) or wide area networks (WANs), or they can be connected to external computing devices (e.g., via the Internet using an Internet service provider).

[0202] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the wafer trimming method provided in various alternative embodiments of this disclosure.

[0203] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units. Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0204] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware.

[0205] Therefore, the technical solution according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the method according to the embodiments of this disclosure.

[0206] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein.

[0207] This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A wafer trimming method, characterized in that, The method includes: Acquire the grain data of multiple dies on the wafer to be repaired, wherein the grain data of each die includes the performance parameters to be repaired of the die and the actual repair requirement identifier of the die. For each grain, perform the following steps: Among multiple tuning strategies, a tuning strategy corresponding to the actual tuning requirement identifier of the grain is selected. Each tuning strategy corresponds to a first correspondence relationship, and each first correspondence relationship is used to characterize the correspondence between performance parameters and tuning identifiers. Based on the first correspondence of the selected set of adjustment strategies, a target adjustment identifier corresponding to the performance parameters to be adjusted of the grain is determined, and the adjustment scheme corresponding to the target adjustment identifier is executed to adjust the performance parameters to be adjusted of the grain.

2. The method according to claim 1, characterized in that, Before selecting a tuning strategy from among multiple tuning strategies that corresponds to the actual tuning requirement identifier of the grain, the method further includes: The multiple grains are classified according to the adjustment requirement identifier to obtain multiple categories, wherein the grains in each category correspond to the same adjustment requirement identifier. The step of selecting a tuning strategy from multiple tuning strategies that corresponds to the tuning requirement identifier of the grain specifically includes: For each category, perform the following steps: Among the multiple adjustment and repair strategies, determine the adjustment and repair strategy that corresponds to this category; The set of adjustment strategies corresponding to the category is determined as a set of adjustment strategies corresponding to the adjustment requirement identifier of each grain within the category.

3. The method according to claim 2, characterized in that, The step of determining a set of adjustment strategies corresponding to the category from among the multiple adjustment strategies includes: Obtain the second correspondence relationship, which is a one-to-one correspondence between the multiple sets of adjustment strategies and the multiple benchmark adjustment requirement identifiers; Among the plurality of benchmark adjustment and repair requirement identifiers, the target benchmark adjustment and repair requirement identifier corresponding to this category is determined; The set of adjustment strategies corresponding to the target benchmark adjustment requirement identifier in the second correspondence is determined as the set of adjustment strategies corresponding to the category.

4. The method according to claim 1, characterized in that, Among multiple adjustment strategies, determining the adjustment strategy corresponding to the actual adjustment requirement identifier of the grain includes: Obtain the second correspondence relationship, which is a one-to-one correspondence between the multiple sets of adjustment strategies and the multiple benchmark adjustment requirement identifiers; Among the plurality of reference adjustment requirement identifiers, a target reference adjustment requirement identifier that matches the actual adjustment requirement identifier of the grain is determined. The set of adjustment strategies corresponding to the target benchmark adjustment requirement identifier in the second correspondence is determined as the set of adjustment strategies corresponding to the actual adjustment requirement identifier of the grain.

5. The method according to claim 3 or 4, characterized in that, Before obtaining the second correspondence, the method further includes: Obtain multiple adjustment strategies; Establish a correspondence between the maintenance requirement identifiers of multiple maintenance strategies and the multiple maintenance strategies to obtain the second correspondence.

6. The method according to claim 1, characterized in that, The first correspondence includes: a one-to-one correspondence between multiple preset adjustment identifiers and multiple benchmark performance parameters; The step of determining the target adjustment identifier corresponding to the performance parameters to be adjusted of the grain based on the first correspondence of the selected set of adjustment strategies includes: Among the plurality of reference performance parameters, a target reference performance parameter that matches the performance parameter to be adjusted for the grain is determined; The preset adjustment identifier corresponding to the target benchmark performance parameter in the first correspondence is determined as the target adjustment identifier.

7. The method according to claim 1, characterized in that, Before selecting the adjustment strategy corresponding to the actual adjustment requirement identifier of the grain from multiple adjustment strategies, the method further includes: Receive multiple sets of adjustment and repair request data. Each set of adjustment and repair request data includes multiple sets of corresponding baseline performance parameters and preset adjustment and repair identifiers defined by the user. For each set of adjustment and repair requirements data, a first correspondence is generated based on multiple sets of corresponding benchmark performance parameters and preset adjustment and repair identifiers; The first correspondence is used as a set of adjustment strategies.

8. The method according to claim 6, characterized in that, The method further includes: Multiple feasible adjustment schemes for the grain are determined, wherein any two feasible adjustment schemes correspond to different parameter adjustment amounts; Different identifiers are assigned to the multiple feasible adjustment solutions; The identifiers of the multiple feasible adjustment schemes are used as the multiple preset adjustment identifiers.

9. The method according to claim 1, characterized in that, After determining the target adjustment identifier corresponding to the performance parameter to be adjusted for the grain, the method further includes: Using the target adjustment identifiers corresponding to each of the multiple grains, a target adjustment file is generated; The target tuning file is sent to the target tuning module so that the target tuning module can perform tuning processing on the plurality of grains based on the target tuning file.

10. The method according to claim 1, characterized in that, The adjustment scheme is a scheme to melt and break the grains; After determining the target adjustment identifier corresponding to the performance parameter to be adjusted for the grain, the method further includes: For each grain, based on the adjustment scheme corresponding to the target adjustment identifier of the grain, the melting state of each of the multiple fuses of the grain is determined. The melting state is either the first melting state indicating melting or the second melting state indicating no melting. The fuse in the first melting state among the plurality of fuses is melted to achieve the adjustment of the performance parameters of the grain to be adjusted.

11. The method according to claim 1, characterized in that, The performance parameters to be adjusted for each grain include the voltage parameter and / or time parameter of that grain.

12. The method according to claim 1, characterized in that, The actual adjustment requirements of each grain are identified by parameters that reflect the adjustment requirements of that grain; The actual adjustment and repair requirement identifier includes at least one of the following: the customer identifier of the customer to which the die belongs, the identity identifier of the die, and the classification identifier of the die.

13. A wafer trimming device, characterized in that, include: The data acquisition module is used to acquire the grain data of multiple dies on the wafer to be repaired. The grain data of each die includes the performance parameters to be repaired of the die and the actual repair requirement identifier of the die. The tuning strategy selection module is used to select a tuning strategy that corresponds to the actual tuning requirement identifier of each die from multiple tuning strategies. Each tuning strategy corresponds to a first correspondence relationship, and each first correspondence relationship is used to characterize the correspondence between performance parameters and tuning identifiers. The adjustment scheme selection module is used to determine, for each die, a target adjustment identifier corresponding to the performance parameters to be adjusted of the die according to the first correspondence of the selected adjustment strategy, so as to execute the adjustment scheme corresponding to the target adjustment identifier to adjust the performance parameters to be adjusted of the die.

14. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the wafer trimming method of any one of claims 1-12 by executing the executable instructions.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the wafer trimming method according to any one of claims 1-12.

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