Packaging structure

Abstract

A package structure includes a leadframe, at least two chips, at least one spacer layer, and a plastic encapsulation material. The leadframe includes a die pad. The chips are disposed on the die pad of the leadframe. The spacer layer is disposed between at least one of the chips and the die pad. The plastic encapsulation material is disposed on the leadframe and covers the chips. One of the edges of the spacer layer and one of the edges of the die pad has a first minimum edge distance, one of the edges of the chip and one of the edges of the die pad has a second minimum edge distance, and the first minimum edge distance is greater than the second minimum edge distance. Thus, the risk of delamination of the plastic encapsulation material when the package structure is stressed can be reduced, wherein the spacer layer can increase the design flexibility of the package structure and can be used to protect the chips from damage.

Description

Technical Field

[0001] This disclosure relates to a packaging structure, and more particularly to a packaging structure that increases the contact area between the plastic packaging material and the chip carrier to a sufficient extent. Background Technology

[0002] In today's semiconductor packaging industry, the volume of packaging structures is gradually decreasing due to technological advancements. This reduction is achieved by shrinking the area of ​​the chip mount in the lead frame and the chip area. However, shrinking the chip mount area can lead to insufficient distance between the chip edge and the mount edge, resulting in inadequate contact area between the plastic packaging material and the mount. Consequently, when the packaging structure is subjected to stress, the plastic packaging material is prone to severe delamination defects at the mount edges.

[0003] Therefore, developing a packaging structure that can reduce the risk of delamination of plastic packaging materials under stress has become an important and urgent problem for the industry. Summary of the Invention

[0004] This disclosure provides a packaging structure that, through a spacer layer, allows the plastic packaging material to have sufficient contact area with the chip carrier, thereby reducing the risk of delamination of the plastic packaging material under stress.

[0005] According to one embodiment of this disclosure, a packaging structure is provided, comprising a lead frame, at least two chips, at least two spacers, and a plastic encapsulation material. The lead frame includes a chip mount. Chips are disposed on the chip mount of the lead frame. Spacers are disposed between each chip and the chip mount. The plastic encapsulation material is disposed on the lead frame and covers the chips. A first minimum distance is formed between one of the edges of a spacer and one of the edges of the chip mount, and a second minimum distance is formed between one of the edges of the chip and one of the edges of the chip mount, wherein the first minimum distance is greater than the second minimum distance. The thickness of one spacer is different from the thickness of the other spacer.

[0006] According to the packaging structure of the embodiment described above, the first minimum margin can be at least 40 micrometers.

[0007] According to the packaging structure of the embodiment described above, the thickness of each spacer layer can be greater than or equal to 40 micrometers and less than or equal to 500 micrometers.

[0008] According to the packaging structure of the embodiment described above, the material of each spacer layer can be silicon.

[0009] According to the packaging structure of the embodiment described above, the area of ​​one chip may be different from the area of ​​the other chip.

[0010] According to the packaging structure of the embodiment described above, the area of ​​each spacer layer may be less than the total area of ​​the chip. Attached Figure Description

[0011] Figure 1 A plan view of the encapsulation structure according to the first embodiment of the present invention is shown; Figure 2 Draw Figure 1 A cross-sectional view of the encapsulation structure in the first embodiment; Figure 3 A plan view of the encapsulation structure according to the second embodiment of the present invention is shown; Figure 4 Draw Figure 3 A cross-sectional view of the encapsulation structure in the second embodiment; Figure 5 A plan view of the packaging structure according to the third embodiment of the present invention is shown; Figure 6 Draw Figure 5 A cross-sectional view of the packaging structure in the third embodiment; Figure 7 A plan view of the encapsulation structure according to the fourth embodiment of the present invention is shown; Figure 8 Draw Figure 7 A cross-sectional view of the encapsulation structure in the fourth embodiment; Figure 9 A plan view of the encapsulation structure according to the fifth embodiment of the present invention is shown; Figure 10 Draw Figure 9 A cross-sectional view of the encapsulation structure in the fifth embodiment; and Figure 11 Draw Figure 9 Ultrasonic scanning analysis image of the encapsulation structure in the fifth embodiment.

[0012] The reference numerals in the attached figures are explained as follows: 100, 200, 300, 400, 500: Package structure 111, 211, 311, 411, 511: Chip socket 112, 212, 312, 412, 512: Pins 121, 122, 221, 222, 321, 322, 421, 422, 520: Chips 130, 231, 232, 331, 332, 430, 530: Spacer layers 140, 240, 340, 440, 540: Plastic encapsulation materials 151, 251, 351, 451, 551: Connecting pads 152, 252, 352, 452, 552: Conductors D: Layered section L1, L1': First minimum margin L2, L2': Second minimum margin T, T1, T2: Thickness Detailed Implementation

[0013] Please refer to Figure 1 and Figure 2 ,in Figure 1 A plan view of the encapsulation structure 100 according to the first embodiment of the present invention is shown. Figure 2 Draw Figure 1 A cross-sectional view of the encapsulation structure 100 in the first embodiment. (By...) Figure 1 and Figure 2 As can be seen, the packaging structure 100 includes a lead frame (not shown in the figure), two chips 121 and 122, a spacer layer 130, and a plastic packaging material 140, wherein the plastic packaging material 140 is disposed on the lead frame and covers the chips 121 and 122.

[0014] Furthermore, the lead frame includes a chip socket 111 and multiple pins 112, and chips 121 and 122 each include multiple pads 151. Chips 121 and 122 are disposed on the chip socket 111, and multiple wires 152 connect the pins 112 and the pads 151. A spacer layer 130 is disposed between chips 121 and 122 and the chip socket 111.

[0015] A first minimum margin L1 is provided between one of the plurality of edges of spacer layer 130 and one of the plurality of edges of chip socket 111, and a second minimum margin L2 is provided between one of the plurality of edges of chips 121 and 122 and one of the edges of chip socket 111, wherein the first minimum margin L1 is greater than the second minimum margin L2, and the first minimum margin L1 may be at least 40 micrometers. In a first embodiment, the second minimum margin L2 is located between one of the edges of chip 121 and one of the edges of chip socket 111. Thus, when chips 121 and 122 are arranged side-by-side on chip socket 111, the plastic encapsulation material 140 and chip socket 111 still have sufficient contact area to reduce the risk of delamination of the plastic encapsulation material 140 when the encapsulation structure 100 is under stress, wherein the increased contact area due to spacer layer 130 is as follows: Figure 2 At the thick chain line. Furthermore, the area of ​​the spacer layer 130 can be smaller than the combined area of ​​chips 121 and 122, and the areas of chip 121 and chip 122 can be different.

[0016] Furthermore, the spacer layer 130 increases the flexibility of chip placement for chips 121 and 122, meaning the placement of chips 121 and 122 is not limited by the area of ​​chip socket 111, thereby increasing the design flexibility of package structure 100, especially when placing larger chips in a smaller package structure. Moreover, the spacer layer 130 protects chips 121 and 122 from damage caused by external stress impacting package structure 100.

[0017] In detail, the thickness T of the spacer layer 130 can be greater than or equal to 40 micrometers and less than or equal to 500 micrometers. When the thickness T of the spacer layer 130 is less than the above-mentioned range, the spacer layer 130 cannot achieve the effect of increasing the contact area between the plastic encapsulation material 140 and the chip carrier 111; when the thickness T of the spacer layer 130 is greater than the above-mentioned range, the encapsulation structure 100 has the problem of exceeding the specified thickness, or the wire 152 is too close to the plastic encapsulation material 140.

[0018] The spacer layer 130 may be made of silicon. Specifically, the spacer layer 130 may be a blank silicon wafer, but is not limited thereto.

[0019] Furthermore, the packaging structure 100 of the first embodiment is a QFN package type, but the packaging structure disclosed herein can be applied not only to QFN, but also to TSOP, SO, and QFP package types, but is not limited thereto.

[0020] Please refer to Figure 3 and Figure 4 ,in Figure 3 A plan view of the encapsulation structure 200 according to the second embodiment of the present invention is shown. Figure 4 Draw Figure 3 A cross-sectional view of the encapsulation structure 200 in the second embodiment. (By...) Figure 3 and Figure 4 As can be seen, the packaging structure 200 includes a lead frame (not shown in the figure), two chips 221 and 222, two spacer layers 231 and 232, and a plastic packaging material 240, wherein the plastic packaging material 240 is disposed on the lead frame and covers the chips 221 and 222.

[0021] Furthermore, the lead frame includes a chip socket 211 and multiple pins 212, and chips 221 and 222 each include multiple pads 251. Chips 221 and 222 are disposed on the chip socket 211, and multiple wires 252 connect the pins 212 and the pads 251. A spacer layer 231 is disposed between the chip 221 and the chip socket 211, and a spacer layer 232 is disposed between the chip 222 and the chip socket 211.

[0022] A first minimum margin L1 is provided between one of the edges of spacers 231 and 232 and one of the edges of chip socket 211, and a second minimum margin L2 is provided between one of the edges of chips 221 and 222 and one of the edges of chip socket 211, wherein the first minimum margin L1 is greater than the second minimum margin L2. In the second embodiment, the first minimum margin L1 is located between one of the edges of spacer 231 and one of the edges of chip socket 211, and the second minimum margin L2 is located between one of the edges of chip 221 and one of the edges of chip socket 211. Thus, when chips 221 and 222 are arranged side-by-side on chip socket 211, the plastic encapsulation material 240 and chip socket 211 still have sufficient contact area to reduce the risk of delamination of the plastic encapsulation material 240 when the encapsulation structure 200 is under stress, wherein the increased contact area due to spacers 231 and 232 is as follows: Figure 4 At the medium-thick chain line.

[0023] Furthermore, the structure and arrangement of the remaining components in the second embodiment are the same as those in the first embodiment, and will not be described again here.

[0024] Please refer to Figure 5 and Figure 6 ,in Figure 5 A plan view of the encapsulation structure 300 according to the third embodiment of the present invention is shown. Figure 6 Draw Figure 5 A cross-sectional view of the encapsulation structure 300 in the third embodiment. (By...) Figure 5 and Figure 6 As can be seen, the packaging structure 300 includes a lead frame (not shown in the figure), two chips 321 and 322, two spacer layers 331 and 332, and a plastic packaging material 340, wherein the plastic packaging material 340 is disposed on the lead frame and covers the chips 321 and 322.

[0025] Furthermore, the lead frame includes a chip socket 311 and multiple pins 312, and chips 321 and 322 each include multiple pads 351. Chips 321 and 322 are disposed on the chip socket 311, and multiple wires 352 connect the pins 312 and the pads 351. A spacer layer 331 is disposed between the chip 321 and the chip socket 311, and a spacer layer 332 is disposed between the chip 322 and the chip socket 311.

[0026] A first minimum margin L1 is provided between one of the edges of spacers 331 and 332 and one of the edges of chip socket 311, and a second minimum margin L2 is provided between one of the edges of chips 321 and 322 and one of the edges of chip socket 311, wherein the first minimum margin L1 is greater than the second minimum margin L2. In a third embodiment, the first minimum margin L1 is located between one of the edges of spacer 331 and one of the edges of chip socket 311, and the second minimum margin L2 is located between one of the edges of chip 321 and one of the edges of chip socket 311. Thus, when chips 321 and 322 are arranged side-by-side on chip socket 311, the plastic encapsulation material 340 and chip socket 311 still have sufficient contact area to reduce the risk of delamination of the plastic encapsulation material 340 when the encapsulation structure 300 is under stress, wherein the increased contact area due to spacers 331 and 332 is as follows: Figure 6 At the medium-thick chain line.

[0027] Furthermore, the thickness T1 of spacer layer 331 is different from the thickness T2 of spacer layer 332, with thickness T1 being less than thickness T2. When the total area of ​​chips 321 and 332 is similar to the area of ​​chip socket 311, using spacer layers 331 and 332 of different thicknesses can further increase the vertical distance between chips 321 and 322, thus avoiding the problem of insufficient distance for wires 352 due to the chips being too close together. In detail, increasing the vertical distance between chips 321 and 322 can shorten the horizontal distance between chips 321 and 322, thereby maintaining the connection strength of wires 352.

[0028] Furthermore, the structure and arrangement of the remaining components in the third embodiment are the same as those in the first embodiment, and will not be described again here.

[0029] Please refer to Figure 7 and Figure 8 ,in Figure 7 A plan view of the encapsulation structure 400 according to the fourth embodiment of the present invention is shown. Figure 8 Draw Figure 7 A cross-sectional view of the encapsulation structure 400 in the fourth embodiment. Figure 7 and Figure 8 As can be seen, the packaging structure 400 includes a lead frame (not shown in the figure), two chips 421 and 422, a spacer layer 430, and a plastic packaging material 440, wherein the plastic packaging material 440 is disposed on the lead frame and covers the chips 421 and 422.

[0030] Furthermore, the lead frame includes a chip socket 411 and multiple pins 412, and chips 421 and 422 each include multiple pads 451. Chips 421 and 422 are disposed on the chip socket 411, and multiple wires 452 connect the pins 412 and the pads 451. A spacer layer 430 is disposed between the chip 422 and the chip socket 411.

[0031] A first minimum distance L1 exists between one of the plurality of edges of the spacer layer 430 and one of the plurality of edges of the chip socket 411, and a second minimum distance L2 exists between one of the plurality of edges of the chips 421 and 422 and one of the edges of the chip socket 411, wherein the first minimum distance L1 is greater than the second minimum distance L2. In the fourth embodiment, the second minimum distance L2 is located between one of the edges of the chip 422 and one of the edges of the chip socket 411. By providing the spacer layer 430 between the chip 422 and the chip socket 411 and not providing the spacer layer 430 between the chip 421 and the chip socket 411, the vertical distance between the chips 421 and 422 is increased, thereby maintaining the connection strength of the wire 452. Therefore, when chips 421 and 422 are arranged side-by-side on chip socket 411, the plastic encapsulation material 440 and chip socket 411 still have sufficient contact area to reduce the risk of delamination of the plastic encapsulation material 440 when the encapsulation structure 400 is under stress. The increased contact area due to the spacer layer 430 is as follows: Figure 8 At the medium-thick chain line.

[0032] Furthermore, the structure and arrangement of the remaining components in the fourth embodiment are the same as those in the first embodiment, and will not be described again here.

[0033] Please refer to Figure 9 and Figure 10 ,in Figure 9 A plan view of the encapsulation structure 500 according to the fifth embodiment of the present invention is shown. Figure 10 Draw Figure 9 A cross-sectional view of the encapsulation structure 500 in the fifth embodiment. Figure 9 and Figure 10 As can be seen, the packaging structure 500 includes a lead frame (not shown in the figure), a chip 520, a spacer layer 530 and a plastic encapsulation material 540, wherein the plastic encapsulation material 540 is disposed on the lead frame and covers the chip 520.

[0034] Furthermore, the lead frame includes a chip socket 511 and multiple pins 512, and the chip 520 includes multiple pads 551, wherein the chip 520 is disposed on the chip socket 511, multiple wires 552 connect the pins 512 and the pads 551, and a spacer layer 530 is disposed between the chip 520 and the chip socket 511.

[0035] The area of ​​the spacer layer 530 is smaller than the area of ​​the chip 520. Furthermore, one of the plurality of edges of the spacer layer 530 has a first minimum margin L1' with one of the plurality of edges of the chip socket 511, and one of the plurality of edges of the chip 520 has a second minimum margin L2' with one of the edges of the chip socket 511. The first minimum margin L1' is greater than the second minimum margin L2', and the first minimum margin L1' may be at least 40 micrometers.

[0036] Please refer to Figure 11 , it is Figure 9 The fifth embodiment shows an ultrasonic scanning analysis (SAT) image of the packaging structure 500. Specifically, when the area of ​​the chip 520 is similar to the area of ​​the chip carrier 511, the spacer layer 530 can increase the contact area between the plastic packaging material 540 and the chip carrier 511. That is, when the plastic packaging material 540 and the chip carrier 511 have sufficient contact area, the risk of delamination of the plastic packaging material 540 under stress can be reduced. Figure 11 As shown, after ultrasound scanning analysis, there is almost no delamination, with only scattered delaminations (D) on one side of the chip holder 511. Furthermore, the increased contact area due to the spacer layer 530 is as follows... Figure 10 At the medium-thick chain line.

[0037] Furthermore, the spacer layer 530 increases the flexibility of chip 520 placement, meaning the placement of chip 520 is not limited by the area of ​​chip socket 511, thereby increasing the design flexibility of package structure 500, especially when a larger chip is placed in a smaller package structure. Moreover, the spacer layer 530 protects chip 520, preventing damage to chip 520 when external stress impacts package structure 500.

[0038] In detail, the thickness T of the spacer layer 530 can be greater than or equal to 40 micrometers and less than or equal to 500 micrometers. When the thickness T of the spacer layer 530 is less than the above-mentioned range, the spacer layer 530 cannot achieve the effect of increasing the contact area between the plastic encapsulation material 540 and the chip carrier 511; when the thickness T of the spacer layer 530 is greater than the above-mentioned range, the encapsulation structure 500 has the problem of exceeding the specified thickness, or the wire 552 is too close to the plastic encapsulation material 540.

[0039] The spacer layer 530 may be made of silicon. Specifically, the spacer layer 530 may be a blank silicon wafer, but is not limited thereto.

[0040] It must be stated that, Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11To facilitate the representation of the arrangement of other components (such as lead frames, chips, and spacers), the labeling of the plastic encapsulation material is omitted.

[0041] In summary, regardless of whether it's a single-chip or multi-chip package, spacers can provide sufficient contact area between the plastic encapsulation material and the chip socket. This reduces the risk of delamination of the plastic encapsulation material when the package structure is under stress. Applying spacers to both single-chip and multi-chip packages increases the flexibility of chip placement, meaning the chip arrangement is not limited by the size of the chip socket, thus increasing the design flexibility of the package structure. Furthermore, spacers protect the chip from damage caused by external stress impacts on the package structure.

[0042] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A packaging structure, characterized in that, Include: A conductor frame, comprising: One chip socket; At least two chips are disposed on the chip socket of the lead frame; At least two spacer layers, each spacer layer being disposed between each chip and the chip socket; and A plastic encapsulation material is disposed on the lead frame and covers the at least two chips; Wherein, one of the plurality of edges of the at least two spacer layers has a first minimum margin with one of the plurality of edges of the chip base, and one of the plurality of edges of the at least two chips has a second minimum margin with the same edge as the plurality of edges of the chip base, and the first minimum margin is greater than the second minimum margin. The thickness of one of the at least two spacer layers is different from the thickness of the other of the at least two spacer layers.

2. The packaging structure as described in claim 1, characterized in that, The first minimum margin is at least 40 micrometers.

3. The packaging structure as described in claim 1, characterized in that, The thickness of each spacer layer is greater than or equal to 40 micrometers and less than or equal to 500 micrometers.

4. The packaging structure as described in claim 1, characterized in that, The material of each spacer layer is silicon.

5. The packaging structure as described in claim 1, characterized in that, The area of ​​one of the at least two chips is different from the area of ​​the other of the at least two chips.

6. The packaging structure as described in claim 1, characterized in that, The total area of ​​the at least two spacer layers is less than the total area of ​​the at least two chips.

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