Electrostatic discharge protection circuit, semiconductor structure and method of forming the same

Abstract

The application discloses an electrostatic discharge protection circuit, a semiconductor structure and a forming method thereof. The electrostatic discharge protection circuit comprises a first triode structure, an emitter of the first triode structure being connected with an external circuit; a second triode structure, a base of the second triode structure being connected with a collector of the first triode structure, an emitter of the second triode structure being grounded, a collector of the second triode structure being connected with the external circuit, and the collector of the second triode structure being disconnected with the base of the first triode structure. The electrostatic discharge protection circuit, the semiconductor structure and the forming method thereof have high effectiveness and stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to an electrostatic discharge protection circuit, a semiconductor structure, and a method for forming the same. Background Technology

[0002] Electrostatic discharge (ESD) is a common phenomenon during the fabrication, production, and testing of semiconductor devices. ESD primarily occurs when a large amount of charge accumulated on the device is introduced through the electrical interconnects of the integrated circuit and damages its internal circuitry, leading to device failure.

[0003] To prevent device damage caused by electrostatic discharge (ESD), protection circuits are typically designed into integrated circuits. When a large amount of charge accumulates on the device, this protection circuit preferentially conducts, conducting the charge away and thus protecting the device's internal circuitry from damage.

[0004] SCR (Silicon Controlled Rectifier) ​​circuits have excellent anti-electrostatic discharge capabilities and are widely used as electrostatic discharge protection circuits in integrated circuits.

[0005] However, during normal operation, SCR circuits are susceptible to external interference, which can cause false triggering, leading to latch-up and chip failure. Therefore, the effectiveness and stability of current SCR circuits as electrostatic discharge protection circuits still need improvement. Summary of the Invention

[0006] The technical problem solved by this invention is to provide an electrostatic discharge protection circuit, a semiconductor structure and a method for forming the same, which have high effectiveness and stability.

[0007] To solve the above-mentioned technical problems, the present invention provides an electrostatic discharge protection circuit, comprising: a first transistor structure, wherein the emitter of the first transistor structure is connected to an external circuit; a second transistor structure, wherein the base of the second transistor structure is connected to the collector of the first transistor structure, the emitter of the second transistor structure is grounded, the collector of the second transistor structure is connected to an external circuit, and there is an open circuit between the collector of the second transistor structure and the base of the first transistor structure.

[0008] Optionally, the first transistor structure is a PNP transistor structure.

[0009] Optionally, the second transistor structure is an NPN transistor structure.

[0010] Optionally, the first transistor structure and the second transistor structure constitute a first protection circuit; the electrostatic discharge protection circuit further includes a diode structure, which is connected in parallel with the first protection circuit, one end of which is connected to an external circuit, and the other end of which is grounded.

[0011] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate having a first conductive ion therein; a first region located within the substrate, the first region including a first well region, the first well region being doped with a second conductive ion, the conductivity type of the second conductive ion being different from that of the first conductive ion, the first well region having a first doped region and a second doped region, the first doped region having a third conductive ion, the conductivity type of the third conductive ion being different from that of the second conductive ion, the second doped region being doped with a fourth conductive ion, the conductivity type of the fourth conductive ion being the same as that of the second conductive ion; an isolation structure located between the first doped region and the second doped region, the isolation structure causing a circuit break between the second doped region and the first doped region; a second region located within the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the conductivity type of the fifth conductive ion being different from that of the first conductive ion; and an electrical connection layer located on the substrate, the electrical connection layer being electrically connected to the first doped region and the third doped region respectively.

[0012] Optionally, the semiconductor structure further includes a gate structure located on a substrate between the third doped region and the second doped region, the gate structure being electrically connected to the electrical connection layer.

[0013] Optionally, the semiconductor structure further includes: a diode structure located within the substrate, the diode structure including: a second well region having a sixth conductive ion; a fourth doped region located within the second well region having a seventh conductive ion, the seventh conductive ion having a different conductivity type than the sixth conductive ion, the fourth doped region being connected to the electrical connection layer.

[0014] Optionally, the second region further includes a fifth doped region adjacent to the third doped region, wherein the conductivity type of the fifth doped region is different from that of the third doped region, and the conductivity type of the fifth doped region is the same as that of the substrate, and the fifth doped region is electrically connected to the electrical connection layer.

[0015] Optionally, the sixth conductive ion is a P-type conductive ion; the seventh conductive ion is an N-type conductive ion.

[0016] Optionally, the first conductive ion is a P-type conductive ion.

[0017] Optionally, the second conductive ion is an N-type conductive ion.

[0018] Optionally, the third conductive ion is a P-type conductive ion.

[0019] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a first conductive ion therein; forming a first region in the substrate, the first region including a first well region, the first well region being doped with a second conductive ion, the conductivity type of the second conductive ion being different from that of the first conductive ion, the first well region having a first doped region and a second doped region, the first doped region having a third conductive ion, the conductivity type of the third conductive ion being different from that of the second conductive ion, the second doped region being doped with a fourth conductive ion, the conductivity type of the fourth conductive ion being the same as that of the second conductive ion; forming an isolation structure located between the first doped region and the second doped region, the isolation structure causing a circuit break between the second doped region and the first doped region; forming a second region in the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the conductivity type of the fifth conductive ion being different from that of the first conductive ion; and forming an electrical connection layer located on the substrate, the electrical connection layer being electrically connected to the first doped region and the third doped region respectively.

[0020] Optionally, the method for forming a semiconductor structure further includes: forming a diode structure located within the substrate, the diode structure comprising: a second well region having a sixth conductive ion; a fourth doped region located within the second well region having a seventh conductive ion, the seventh conductive ion having a different conductivity type than the sixth conductive ion, the fourth doped region being connected to the electrical connection layer.

[0021] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0022] In the electrostatic discharge protection circuit provided by the present invention, the base of the second transistor structure is connected to the collector of the first transistor structure, and there is an open circuit between the base of the first transistor structure and the collector of the second transistor structure. When a large external instantaneous current is generated, the current enters the emitter of the first transistor structure and the collector of the second transistor structure. Because there is an open circuit between the base of the first transistor structure and the collector of the second transistor structure, the current in the closed circuit formed by the base of the first transistor structure, the collector of the second transistor structure, the base of the second transistor structure, and the collector of the first transistor structure is prevented from being continuously amplified and triggering a latch-up effect, thus avoiding the possibility of the electrostatic discharge protection circuit being burned out and improving the stability and effectiveness of the electrostatic discharge protection circuit. Finally, the external current is conducted away through the collector of the first transistor structure and the emitter of the second transistor structure, thereby protecting other circuit structures of the device and improving the overall stability of the device.

[0023] Furthermore, the electrostatic discharge protection circuit also includes a diode structure connected to an external circuit, wherein the diode structure is connected in parallel with the first protection circuit formed by the first transistor structure and the second transistor structure. When a large current is generated by the external circuit, the diode structure conducts, thereby sharing a portion of the current flowing to the first protection circuit, thus improving the protection capability and stability of the electrostatic discharge protection circuit.

[0024] In the semiconductor structure provided by the technical solution of the present invention, since there is an open circuit between the second doped region and the first doped region, when an external instantaneous large current is generated, the current in the circuit composed of the semiconductor structure is prevented from being continuously amplified and triggering the latch-up effect, thereby improving the stability and effectiveness of the semiconductor structure as an electrostatic discharge protection structure.

[0025] In the semiconductor structure formation method provided by the technical solution of the present invention, since the second doped region and the first doped region are disconnected, when an external instantaneous large current is generated, the current in the circuit formed by the semiconductor structure is continuously amplified and the latch-up effect is triggered, thereby improving the stability and effectiveness of the formed semiconductor structure as an electrostatic discharge protection structure. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of an SCR circuit;

[0027] Figure 2 yes Figure 1 A cross-sectional schematic diagram of the semiconductor structure corresponding to the SCR circuit in the diagram.

[0028] Figure 3 This is a circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention;

[0029] Figure 4 yes Figure 3 A cross-sectional schematic diagram of the semiconductor structure corresponding to the electrostatic discharge protection circuit in the diagram.

[0030] Figure 5 This is a circuit diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, under current technology, SCR circuits are susceptible to external interference, which can cause false triggering, resulting in latch-up and chip failure. As an electrostatic discharge protection circuit, its effectiveness and stability still need to be improved.

[0032] Figure 1 This is a circuit diagram of an SCR circuit; Figure 2 yes Figure 1 A cross-sectional schematic diagram of the semiconductor structure corresponding to the SCR circuit in the diagram.

[0033] Please refer to Figure 1 The SCR circuit includes: a first transistor structure 131, which includes a first emitter, a first collector, and a first base located between the first emitter and the first collector, the first emitter being connected to an external circuit; and a second transistor structure 132, which includes a second emitter, a second collector, and a second base located between the second emitter and the second collector, the second base being connected to the first collector, and the first base being electrically connected to the second collector, the second emitter being grounded, and the second collector being connected to an external circuit.

[0034] Please refer to Figure 2Accordingly, the semiconductor structure includes: a substrate 100 having P-type conductive ions within it; a first well region 101 located within the substrate 100, the first well region 101 being doped with N-type conductive ions; a first doped region 103 located within the first well region 101, the first doped region 103 having P-type conductive ions; a second doped region 102 in contact with the first well region 101, the second doped region 102 being doped with N-type conductive ions, and the second doped region 102 and the first doped region 103 being electrically connected via an electrical connection layer 111; an isolation structure 120 located between the second doped region 102 and the first doped region 103; a third doped region 104 and an adjacent fourth doped region 105 located within the substrate 100, the third doped region having N-type conductive ions and the fourth doped region 105 having P-type conductive ions; and an electrical connection layer 111 located on the substrate 100, the electrical connection layer 111 being electrically connected to the first doped region 103 and the third doped region 104, respectively.

[0035] Because the first base of the first transistor structure is short-circuited to the second collector of the second transistor structure, the closed circuit formed by the first base, the second collector, the second base, and the first collector (as shown in the image) is closed. Figure 1 As shown at point A, the presence of current triggers a latch-up effect, continuously amplifying the current in the closed circuit, causing the SCR circuit to burn out and thus fail.

[0036] To address the aforementioned technical problems, the present invention provides an electrostatic discharge protection circuit, comprising a first transistor structure and a second transistor structure, wherein the base of the first transistor structure and the collector of the second transistor structure are disconnected. When a large external instantaneous current is generated, the disconnection between the base of the first transistor structure and the collector of the second transistor structure prevents the current in the closed circuit formed by the base of the first transistor structure, the collector of the second transistor structure, the base of the second transistor structure, and the collector of the first transistor structure from being continuously amplified and triggering a latch-up effect, thus improving the stability and effectiveness of the electrostatic discharge protection circuit. By conducting the external current away through the collector of the first transistor structure and the emitter of the second transistor structure, the other circuit structures of the device are protected, thereby improving the overall stability of the device.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figure 3 This is a circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention; Figure 4 yes Figure 3 A cross-sectional schematic diagram of the semiconductor structure corresponding to the electrostatic discharge protection circuit in the diagram.

[0039] Please refer to Figure 3 The electrostatic discharge protection circuit includes: a first transistor structure 231, the emitter of the first transistor structure 231 being connected to an external circuit; a second transistor structure 232, the base of the second transistor structure 232 being connected to the collector of the first transistor structure 231, the emitter of the second transistor structure 232 being grounded, the collector of the second transistor structure 232 being connected to an external circuit, and an open circuit between the collector of the second transistor structure 232 and the base of the first transistor structure 231.

[0040] In this embodiment, the first transistor structure 231 is a PNP transistor structure.

[0041] In this embodiment, the second transistor structure 232 is an NPN transistor structure.

[0042] In this embodiment, when the device containing the electrostatic discharge protection circuit is working, a large instantaneous current is generated and enters from the input terminal IN of the electrostatic discharge protection circuit, and is introduced to ground through the first transistor structure 231 and the second transistor structure 232 respectively.

[0043] In this embodiment, current enters the emitter of the first transistor structure 231 and the collector of the second transistor structure 232. Since there is an open circuit between the base of the first transistor structure 231 and the collector of the second transistor structure 232, the current in the closed circuit formed by the base of the first transistor structure 231, the collector of the second transistor structure 232, and the base of the second transistor structure 232 and the collector of the first transistor structure 231 is prevented from being continuously amplified. This reduces the possibility of triggering a latch-up effect, thereby preventing the area where the electrostatic discharge protection circuit is located from being burned out and failing. Therefore, the stability and effectiveness of the electrostatic discharge protection circuit are improved. Finally, the external current is conducted away through the collector of the first transistor structure 231 and the emitter of the second transistor structure 232, thereby protecting other circuit structures of the device and improving the overall stability of the device.

[0044] In this embodiment, a portion of the electrostatic discharge protection circuit also has internal resistance of wires or devices, which are here labeled as the first internal resistance 233 and the second internal resistance 234.

[0045] The electrostatic discharge protection circuit described in this embodiment can be used in the chip circuit of fingerprint recognition products to provide electrostatic discharge protection.

[0046] Please refer to Figure 4 , Figure 4 yes Figure 3 A cross-sectional schematic diagram of the semiconductor structure corresponding to the electrostatic discharge protection circuit in the diagram.

[0047] The semiconductor structure includes: a substrate 200 having a first conductive ion within it; a first region (not shown) located within the substrate 200, the first region including a first well region 201, the first well region 201 being doped with a second conductive ion, the second conductive ion having a different conductivity type than the first conductive ion; the first well region 201 having a first doped region 203 and a second doped region 202; the first doped region 203 having a third conductive ion, the third conductive ion having a different conductivity type than the second conductive ion; and the second doped region 202 being doped with a fourth conductive ion. The conductivity type of the first doped region 202 is the same as that of the second doped region 203; an isolation structure 220 is located between the first doped region 203 and the second doped region 202, the isolation structure 220 disconnects the second doped region 202 from the first doped region 203; a second region (not shown) is located within the substrate 200, the second region includes a third doped region 204, the third doped region 204 contains a fifth doped ion, the conductivity type of the fifth doped ion is different from that of the first doped ion; an electrical connection layer 211 is located on the substrate 200, the electrical connection layer 211 is electrically connected to the first doped region 203 and the third doped region 204 respectively.

[0048] In this embodiment, the first conductive ion is a P-type conductive ion.

[0049] In this embodiment, the second conductive ion is an N-type conductive ion.

[0050] In this embodiment, the third conductive ion is a P-type conductive ion.

[0051] In this embodiment, the fourth conductive ion is an N-type conductive ion.

[0052] In this embodiment, the fifth conductive ion is an N-type conductive ion.

[0053] Please combine Figure 3 refer to Figure 4 In this embodiment, the first doped region 203, the first well region 201, and the substrate 200 constitute a first transistor structure 231, which is a PNP transistor structure; the third doped region 204, the substrate 200, and the first well region 201 constitute a second transistor structure 232, which is an NPN transistor structure.

[0054] Specifically, in this embodiment, the emitter of the first transistor structure 231 is the first doped region 203, the base of the first transistor structure 231 is the first well region 201, and the collector of the first transistor structure 231 is the substrate 200; the first doped region 203 is in contact with the electrical connection layer 211, thereby electrically connecting the first transistor structure 231 to the external circuit, and the substrate 200 is grounded.

[0055] In this embodiment, the emitter of the second transistor structure 232 is the third doped region 204, the base of the second transistor structure 232 is the substrate 200, and the collector of the second transistor structure 232 is the first well region 201; the third doped region 204 is in contact with the electrical connection layer 211, and the electrical connection layer 211 is grounded, thereby grounding the emitter of the second transistor structure 232.

[0056] Since the conductivity type of the conductive ions in the second doped region 202 is the same as that in the first well region 201, the second doped region 202 is connected to the first well region 201. The second doped region 202 is connected to an external circuit (not shown) through an electrical connection layer 211, thereby connecting the second transistor structure 232 to the external circuit.

[0057] In this embodiment, the base of the second transistor structure 232 and the collector of the first transistor structure 231 are both substrates 200. Therefore, the base of the second transistor structure 232 and the collector of the first transistor structure 231 are connected.

[0058] In this embodiment, there is an isolation structure 220 between the first doped region 203 and the second doped region 202, and the second doped region 202 is not electrically connected to the first doped region 203. Therefore, when an external instantaneous large current is generated, the current in the circuit composed of the semiconductor structure is prevented from being continuously amplified, the latch-up effect is reduced, and the possibility of the semiconductor structure being burned out is avoided, thereby improving the stability and effectiveness of the semiconductor structure as an electrostatic discharge protection structure.

[0059] In this embodiment, the second region of the semiconductor structure further includes a fifth doped region 205 adjacent to the third doped region 204. The conductivity type of the fifth doped region 205 is different from that of the third doped region 204, and the conductivity type of the fifth doped region 205 is the same as that of the substrate 200. The fifth doped region 205 is electrically connected to the electrical connection layer 211, and the electrical connection layer 211 is grounded. Specifically, the fifth doped region 205 contains P-type doped ions.

[0060] In this embodiment, the semiconductor structure further includes a gate structure 210 located on a substrate 200 between the third doped region 204 and the second doped region 202. The gate structure 210 is electrically connected to an electrical connection layer 211, which is grounded.

[0061] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0062] Please continue to refer to this. Figure 4 The method for forming the semiconductor structure includes: providing a substrate 200, wherein the substrate 200 contains a first conductive ion; forming a first region (not shown) within the substrate 200, the first region including a first well region 201, wherein the first well region 201 is doped with a second conductive ion, the conductivity type of the second conductive ion being different from that of the first conductive ion; the first well region 201 having a first doped region 203 and a second doped region 202; the first doped region 203 containing a third conductive ion, the conductivity type of the third conductive ion being different from that of the second conductive ion; and the second doped region 202 being doped with a fourth conductive ion. The conductivity type of the fourth conductive ion is the same as that of the second conductive ion; an isolation structure 220 is formed between the first doped region 203 and the second doped region 202, the isolation structure 220 disconnects the second doped region 202 from the first doped region 203; a second region is formed in the substrate 200, the second region including a third doped region 204, the third doped region 204 having a fifth conductive ion, the conductivity type of the fifth conductive ion being different from that of the first conductive ion; an electrical connection layer 211 is formed on the substrate 200, the electrical connection layer 211 being electrically connected to the first doped region 203 and the third doped region 204 respectively. Figure 5 This is a circuit diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention.

[0063] Please refer to Figure 5 The electrostatic discharge protection circuit includes: a first transistor structure 331, the emitter of the first transistor structure 331 being connected to an external circuit; a second transistor structure 332, the base of the second transistor structure 332 being connected to the collector of the first transistor structure 331, the emitter of the second transistor structure 332 being grounded, the collector of the second transistor structure 332 being connected to an external circuit, and an open circuit between the collector of the second transistor structure 332 and the base of the first transistor structure 331.

[0064] In this embodiment, the first transistor structure 331 is a PNP transistor structure; the second transistor structure 332 is an NPN transistor structure. The first transistor structure 331 and the second transistor structure 332 constitute the first protection circuit 340.

[0065] In this embodiment, the electrostatic discharge protection circuit further includes a diode structure 350, which is connected in parallel with the first protection circuit 340. One end of the diode structure 350 is connected to an external circuit, and the other end of the diode structure 350 is grounded.

[0066] Because of the presence of the diode structure 350, when a large current is generated by the external circuit, the diode structure 350 conducts. The diode structure 350 and the first protection circuit share the large current input to the electrostatic discharge protection circuit, thereby improving the protection capability and stability of the electrostatic discharge protection circuit and enhancing the device's tolerance to instantaneous large currents.

[0067] Accordingly, another embodiment of the present invention also provides a semiconductor structure, the semiconductor structure corresponding to Figure 5 Electrostatic discharge protection circuit in the system.

[0068] The semiconductor structure includes: a substrate having a first conductive ion within it; a first region located within the substrate, the first region including a first well region, the first well region being doped with a second conductive ion, the second conductive ion having a different conductivity type than the first conductive ion, the first well region having a first doped region and a second doped region, the first doped region having a third conductive ion, the third conductive ion having a different conductivity type than the second conductive ion, the second doped region being doped with a fourth conductive ion, the fourth conductive ion having the same conductivity type as the second conductive ion; an isolation structure located between the first doped region and the second doped region, the isolation structure breaking the circuit between the second doped region and the first doped region; a second region located within the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the fifth conductive ion having a different conductivity type than the first conductive ion; and an electrical connection layer located on the substrate, the electrical connection layer being electrically connected to the first doped region and the third doped region, respectively.

[0069] In this embodiment, the first conductive ion is a P-type conductive ion.

[0070] In this embodiment, the second conductive ion is an N-type conductive ion.

[0071] In this embodiment, the third conductive ion is a P-type conductive ion.

[0072] In this embodiment, the fourth conductive ion is an N-type conductive ion.

[0073] In this embodiment, the fifth conductive ion is an N-type conductive ion.

[0074] In this embodiment, the semiconductor structure further includes: a diode structure located within the substrate, the diode structure including: a second well region having a sixth conductive ion; a fourth doped region located within the second well region having a seventh conductive ion, the seventh conductive ion having a different conductivity type than the sixth conductive ion, and the fourth doped region being connected to the electrical connection layer.

[0075] Specifically, the sixth conductive ion is a P-type conductive ion; the seventh conductive ion is an N-type conductive ion. Correspondingly, another embodiment of the present invention also provides a method for forming a semiconductor structure.

[0076] The method for forming the semiconductor structure includes: providing a substrate having a first conductive ion therein; forming a first region in the substrate, the first region including a first well region, the first well region being doped with a second conductive ion, the second conductive ion having a different conductivity type than the first conductive ion, the first well region having a first doped region and a second doped region, the first doped region having a third conductive ion, the third conductive ion having a different conductivity type than the second conductive ion, the second doped region being doped with a fourth conductive ion, the fourth conductive ion having the same conductivity type as the second conductive ion, and the second doped region being disconnected from the first doped region; forming a second region in the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the fifth conductive ion having a different conductivity type than the first conductive ion; and forming an electrical connection layer on the substrate, the electrical connection layer being electrically connected to the first doped region and the third doped region, respectively.

[0077] In this embodiment, the method for forming the semiconductor structure further includes: forming a diode structure located within the substrate, the diode structure including: a second well region having a sixth conductive ion; a fourth doped region located within the second well region having a seventh conductive ion, the seventh conductive ion having a different conductivity type than the sixth conductive ion, and the fourth doped region being connected to the electrical connection layer.

[0078] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that, include: The first transistor structure has its emitter connected to an external circuit. The second transistor structure has its base connected to the collector of the first transistor structure, its emitter grounded, its collector connected to an external circuit, and an open circuit between the collector of the second transistor structure and the base of the first transistor structure.

2. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The first transistor structure is a PNP type transistor structure.

3. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The second transistor structure is an NPN transistor structure.

4. The electrostatic discharge protection circuit as described in claim 1, characterized in that, The first transistor structure and the second transistor structure constitute the first protection circuit; The electrostatic discharge protection circuit further includes a diode structure, which is connected in parallel with the first protection circuit. One end of the diode structure is connected to an external circuit, and the other end of the diode structure is grounded.

5. A semiconductor structure, characterized in that, include: A substrate having first conductive ions within it; A first region located within the substrate includes a first well region, in which a second conductive ion is doped, the conductivity type of which is different from that of the first conductive ion. The first well region has a first doped region and a second doped region. The first doped region contains a third conductive ion, the conductivity type of which is different from that of the second conductive ion. The second doped region is doped with a fourth conductive ion, the conductivity type of which is the same as that of the second conductive ion. An isolation structure located between the first doped region and the second doped region, the isolation structure causing a circuit break between the second doped region and the first doped region; A second region located within the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the fifth conductive ion having a different conductivity type than the first conductive ion; An electrical connection layer is located on the substrate, and the electrical connection layer is electrically connected to the first doped region and the third doped region, respectively.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: A gate structure located on a substrate between the third doped region and the second doped region, the gate structure being electrically connected to the electrical connection layer.

7. The semiconductor structure as described in claim 5, characterized in that, Also includes: A diode structure located within the substrate, the diode structure comprising: a second well region having a sixth conductive ion; The fourth doped region is located within the second well region. The fourth doped region contains a seventh conductive ion. The conductivity type of the seventh conductive ion is different from that of the sixth conductive ion. The fourth doped region is connected to the electrical connection layer.

8. The semiconductor structure as described in claim 5, characterized in that, The second region further includes a fifth doped region adjacent to the third doped region, wherein the conductivity type of the fifth doped region is different from that of the third doped region and the conductivity type of the fifth doped region is the same as that of the substrate, and the fifth doped region is electrically connected to the electrical connection layer.

9. The semiconductor structure as described in claim 7, characterized in that, The sixth conductive ion is a P-type conductive ion; the seventh conductive ion is an N-type conductive ion.

10. The semiconductor structure as described in claim 5, characterized in that, The first conductive ion is a P-type conductive ion.

11. The semiconductor structure as described in claim 5, characterized in that, The second conductive ion is an N-type conductive ion.

12. The semiconductor structure as described in claim 5, characterized in that, The third conductive ion is a P-type conductive ion.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein the substrate contains first conductive ions; A first region is formed within the substrate. The first region includes a first well region. The first well region is doped with a second conductive ion, the conductivity type of which is different from that of the first conductive ion. The first well region has a first doped region and a second doped region. The first doped region contains a third conductive ion, the conductivity type of which is different from that of the second conductive ion. The second doped region is doped with a fourth conductive ion, the conductivity type of which is the same as that of the second conductive ion. An isolation structure is formed between the first doped region and the second doped region, the isolation structure causing a circuit break between the second doped region and the first doped region; A second region is formed within the substrate, the second region including a third doped region, the third doped region having a fifth conductive ion, the fifth conductive ion having a different conductivity type than the first conductive ion; An electrical connection layer is formed on the substrate, and the electrical connection layer is electrically connected to the first doped region and the third doped region, respectively.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, Also includes: A diode structure is formed within the substrate, the diode structure comprising: a second well region having a sixth conductive ion; The fourth doped region is located within the second well region. The fourth doped region contains a seventh conductive ion. The conductivity type of the seventh conductive ion is different from that of the sixth conductive ion. The fourth doped region is connected to the electrical connection layer.

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