Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The structure includes a substrate, a gate structure formed on the substrate, source / drain doped layers formed in the substrate on both sides of the gate structure, a dielectric layer on top of the gate structure, source / drain plugs on top of the source / drain doped layers, the substrate, sidewalls of the source / drain plugs, sidewalls of the gate structure, and sidewalls of the dielectric layer forming a trench, the trench including a first portion on the side of the gate structure and a second portion on the side of the dielectric layer in communication with the top of the first portion, the first portion having a larger opening size than the second portion, and a sealing layer on top of the dielectric layer and the source / drain plugs, the sealing layer also sealing the top of the trench. The present invention reduces the capacitive coupling between the gate structure and the source / drain plugs, thereby reducing power consumption and increasing the operating speed of the device, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As integrated circuits become increasingly dense and semiconductor process technology nodes shrink, the distance between adjacent devices becomes smaller. On the same chip, the decreasing distance between the gate structures of different transistors leads to a larger parasitic capacitance between adjacent gate structures and source / drain plugs. This parasitic capacitance increases capacitive coupling between the gate structure and the source / drain plug, thereby increasing energy consumption and raising the resistance-capacitance (RC) time constant. This affects the chip's operating speed and severely impacts the reliability of the devices on the chip.

[0003] In the prior art, low-k materials are typically used to form sidewalls on the sidewall surface of the gate structure to reduce the parasitic capacitance between adjacent gate structures and source / drain plugs, thereby improving transistor performance.

[0004] As the spacing between gate structures decreases further, the difficulty of forming low-k sidewalls on both sides of the gate structure increases. At the same time, the sidewalls formed by traditional low-k materials cannot further reduce the dielectric constant. The existing methods have limited effect on improving parasitic capacitance, and the performance of transistors needs to be further improved.

[0005] Currently, air gaps are typically introduced between the gate structure and the source / drain plugs to further reduce the dielectric constant. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, a channel layer, a gate structure, and a gate sidewall located on the substrate, and source / drain doped layers located in the substrate on both sides of the gate structure; a dielectric layer located on top of the gate structure; a source / drain plug located on top of the source / drain doped layers, wherein the substrate, the source / drain plug sidewall, the gate structure sidewall, and the dielectric layer sidewall form a trench, the trench comprising a first portion formed by the gap between the gate structure and the source / drain plug, and a second portion connected to the top of the first portion and formed by the gap between the dielectric layer and the source / drain plug, wherein the opening size of the first portion is larger than the opening size of the second portion, and the first portion and the second portion are flush with the sidewall on one side of the source / drain plug; and a sealing layer located on top of the dielectric layer and the source / drain plug, the sealing layer also sealing the top of the trench.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, and source / drain doped layers are formed in the substrate on both sides of the gate structure; forming a first sacrificial layer on the sidewall of the gate structure; forming a dielectric layer on top of the gate structure and the first sacrificial layer, wherein the sidewall of the dielectric layer is flush with the sidewall of the first sacrificial layer; forming a second sacrificial layer on the sidewall of the dielectric layer and the first sacrificial layer, wherein the second sacrificial layers adjacent to the side of the gate structure form a first trench, the first trench exposing the top of the source / drain doped layers; forming a source / drain plug in the first trench; after forming the source / drain plug, removing the first and second sacrificial layers to form a second trench surrounded by the substrate, the sidewall of the source / drain plug, the sidewall of the gate structure, and the sidewall of the dielectric layer; and forming a sealing layer on top of the dielectric layer and the source / drain plug, wherein the sealing layer seals the top of the second trench.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] This invention provides a semiconductor structure in which a substrate, source / drain plug sidewalls, a gate structure sidewall, and a dielectric layer sidewall form a trench. The trench includes a first portion located on the side of the gate structure and a second portion connected to the top of the first portion and located on the side of the dielectric layer. The opening size of the first portion is larger than the opening size of the second portion. Since the opening size of the first portion is larger than the opening size of the second portion, the opening size of the trench on the dielectric layer sidewall is smaller. This facilitates better sealing of the trench by the sealing layer, reducing the probability of damage to the top of the trench and accidental opening during subsequent processes on the top of the sealing layer. This helps to ensure the performance of the semiconductor structure. Furthermore, since the dielectric constant of air is smaller than that of the dielectric material, the larger opening size of the trench on the side of the gate structure introduces a larger air gap between the gate structure and the source / drain plug, effectively reducing the parasitic capacitance between adjacent gate structures and source / drain plugs. This reduces capacitive coupling between the gate structure and the source / drain plugs, thereby reducing power consumption and increasing device operating speed, ultimately improving the performance of the semiconductor structure.

[0011] In the formation method provided by the embodiments of the present invention, a first sacrificial layer is formed on the sidewall of the gate structure, a dielectric layer is formed on the top of the gate structure and the first sacrificial layer, the sidewall of the dielectric layer is flush with the sidewall of the first sacrificial layer, a second sacrificial layer is formed on the sidewall of the dielectric layer and the first sacrificial layer, and the second sacrificial layers on adjacent sides of the gate structure form a first trench, a source / drain plug is formed in the first trench, after the source / drain plug is formed, the first and second sacrificial layers are removed to form a second trench surrounded by a substrate, the sidewall of the source / drain plug, the sidewall of the gate structure, and the sidewall of the dielectric layer, and a sealing layer is formed on the top of the dielectric layer and the source / drain plug to seal the top of the second trench; the embodiments of the present invention, through the respective occupancy of the first and second sacrificial layers, make the second trench include a first portion located on the side of the gate structure, and a portion connected to the top of the first portion and positioned... In the second part on the dielectric layer side, the opening size of the first part is larger than the opening size of the second part. Therefore, the opening size of the second trench on the dielectric layer sidewall is smaller, which helps the sealing layer to better seal the second trench. This reduces the probability of the second trench being accidentally opened due to damage to the top of the sealing layer during subsequent processes, thus helping to ensure the performance of the semiconductor structure. At the same time, the dielectric constant of air is smaller than that of the dielectric material. Therefore, the opening size of the second trench on the gate structure side is larger, which introduces a larger air gap between the gate structure and the source / drain plug. This effectively reduces the parasitic capacitance between adjacent gate structures and source / drain plugs, thereby reducing the capacitive coupling between the gate structure and the source / drain plug, reducing power consumption, increasing device operating speed, and improving the performance of the semiconductor structure. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a semiconductor structure.

[0013] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 3 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0016] Figure 1 This is a schematic diagram of a semiconductor structure.

[0017] refer to Figure 1The semiconductor structure includes: a substrate 10, a gate structure 20 formed on the substrate 10, and source / drain doped layers 11 formed in the substrate 10 on both sides of the gate structure 20; a first dielectric layer 40 covering the sidewalls and top of the gate structure 20; a source / drain plug 53 located on top of the source / drain doped layers 11, and the substrate 10, the sidewalls of the source / drain plug 53, and the first dielectric layer 40 forming a trench 34; and a second dielectric layer 60 located on top of the first dielectric layer 40 and the source / drain plug 53, and sealing the trench 34.

[0018] The source / drain doping 53 and the electrical properties of the gate structure 20 need to be brought out subsequently. In the subsequent process, a first opening 41 is formed in the second dielectric layer 60 on top of the source / drain plug 53, exposing the top of the source / drain plug 53. A second opening 42 is formed in the first dielectric layer 40 and the second dielectric layer 60 on top of the gate structure 53, exposing the gate structure 20. Because the opening size at the top of the trench 34 is relatively large, the sealing performance of the second dielectric layer 60 on the trench 34 is poor. Therefore, when forming the first opening 41, it is easy to over-etch the second dielectric layer 60 sealing the trench 34 (e.g., ...). Figure 1 (As shown by the dashed circle) exposing the trench 34, when the first opening 41 is filled with metal material, the metal material can easily flow into the trench 34, affecting the performance of the semiconductor structure. Correspondingly, when forming the second opening 42, the first dielectric layer 40 on the side of the second opening 42 is easily over-etched (e.g., as shown by the dashed circle). Figure 1 (As shown by the dashed coil) The second opening 42 is connected to the trench 34, so when the metal material is filled in the second opening 42, the metal material can easily flow into the trench 34 and affect the performance of the semiconductor structure.

[0019] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, a trench layer, a gate structure, and a gate sidewall located on the substrate, and source / drain doped layers located on both sides of the gate structure in the substrate; a dielectric layer located on top of the gate structure; a source / drain plug located on top of the source / drain doped layers, the substrate, the source / drain plug sidewall, the gate structure sidewall, and the dielectric layer sidewall forming a trench, the trench including a first portion formed by the gap between the gate structure and the source / drain plug, and a second portion connected to the top of the first portion and formed by the gap between the dielectric layer and the source / drain plug, the opening size of the first portion being larger than the opening size of the second portion, and the sidewalls of the first portion and the second portion being flush with each other on the source / drain plug sidewall; and a sealing layer located on top of the dielectric layer and the source / drain plug, the sealing layer also sealing the top of the trench.

[0020] In the semiconductor structure provided by this invention, the opening size of the first part is larger than the opening size of the second part. This results in a smaller opening size of the trench on the sidewall of the dielectric layer, which helps the sealing layer to better seal the trench. This reduces the probability of damage to the top of the trench during subsequent processes on the top of the sealing layer, thus ensuring the performance of the semiconductor structure. Simultaneously, since the dielectric constant of air is less than that of the dielectric material, the opening size of the trench on the side of the gate structure is larger. This introduces a larger air gap between the gate structure and the source / drain plug, effectively reducing the parasitic capacitance between adjacent gate structures and source / drain plugs. This reduces capacitive coupling between the gate structure and the source / drain plugs, thereby reducing power consumption and increasing device operating speed, ultimately improving the performance of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0023] The semiconductor structure includes: a substrate 101, a channel layer, a gate structure 201, and a gate sidewall 211 located on the substrate 101, and source / drain doped layers 111 located on both sides of the gate structure 201 in the substrate 101; a dielectric layer 401 located on top of the gate structure 201; and a source / drain plug 531 located on top of the source / drain doped layer 111. The substrate 101, the sidewalls of the source / drain plug 531, the sidewalls of the gate structure 201, and the sidewalls of the dielectric layer 401 form a trench 341. The trench 341 includes the gate structure 201 and the source / drain plug 531. The first part 342 is formed by the gap between the plugs 531, and the second part 343 is connected to the top of the first part 342 and is formed by the gap between the dielectric layer 401 and the source / drain plug 531. The opening size d1 of the first part 342 is larger than the opening size d2 of the second part 343. The first part 342 and the second part 343 are flush with the sidewall on one side of the source / drain plug 531. The sealing layer 601 is located on the top of the dielectric layer 401 and the source / drain plug 531. The sealing layer 601 also seals the top of the groove 341.

[0024] Substrate 101 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include planar transistors, FinFETs, or gate-all-around (GAA) transistors.

[0025] In this embodiment, taking a finned field-effect transistor as an example, the substrate 101 includes a substrate and fins protruding from the substrate. The substrate material is silicon. In other embodiments, the substrate material can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material can be a material suitable for process requirements or easy to integrate.

[0026] For clarity, the fins are not shown in the accompanying drawings of this embodiment.

[0027] In this embodiment, the gate structure 201 is a device gate structure, which is used to control the opening or closing of the transistor channel.

[0028] In this embodiment, the gate structure 201 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0029] The gate dielectric layer is used to isolate the gate electrode layer and the fins. In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0030] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the fin. Specifically, the material of the gate oxide layer can be silicon oxide.

[0031] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0032] In this embodiment, the gate structure 201 is a metal gate structure.

[0033] Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0034] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0035] In this embodiment, in the semiconductor structure, the gate sidewall 211 is located on the sidewall of the gate structure 201.

[0036] The gate sidewall 211 is used to protect the gate structure 201 during the formation of the trench 341, thereby reducing the impact of the trench 341 formation process on the gate structure 201.

[0037] Accordingly, in this embodiment, the trench 341 is formed by the substrate 101, the sidewalls of the source / drain plug 531, the gate sidewall 211, and the sidewalls of the dielectric layer 401.

[0038] In this embodiment, the gate sidewall 211 also extends to cover a portion of the top of the substrate 101, serving as an etching stop position in the step of forming the trench 341.

[0039] In this embodiment, the gate sidewall 211 is a single-layer structure, and the material of the gate sidewall 211 includes silicon nitride or a low-k dielectric material. In other embodiments, the gate sidewall may also be a multilayer structure, and the material of the gate sidewall may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0040] Silicon nitride has high hardness, which helps to enhance the protective effect of the gate sidewall 211. Using a low-k dielectric material helps to reduce the overall dielectric constant of the gate sidewall 211 and the trench 341.

[0041] The source / drain doped layer 111 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 111 is the same as the channel conductivity type of the corresponding transistor.

[0042] The dielectric layer 401 is used to isolate adjacent devices, and the dielectric layer 401 is also used to form the trench 341.

[0043] The dielectric layer 401 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0044] In this embodiment, the width of the dielectric layer 401 at the top of the gate structure 201 is greater than the width of the gate structure 201. Thus, the first part 342 of the trench 341 can be obtained with a size greater than the second part 343 through the sidewalls of the gate structure 201 and the dielectric layer 401. This makes the method of forming the trench 341 with this morphology simpler.

[0045] The source / drain plug 531 is used to bring out the electrical properties of the source / drain doped layer 111.

[0046] In this embodiment, the source / drain plug 531 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0047] In this embodiment, the semiconductor structure further includes a source / drain plug sidewall 511, located on the sidewall of the source / drain plug 531.

[0048] The source / drain plug sidewall 511 is used to protect the source / drain plug 531 during the formation of the trench 341, thereby reducing the impact of the trench 341 formation process on the source / drain plug 531.

[0049] Accordingly, in this embodiment, the trench 341 is formed by the substrate 101, the source / drain plug sidewall 511, the gate structure 201 sidewall, and the dielectric layer 401 sidewall.

[0050] In this embodiment, the material of the source / drain plug sidewall 511 includes silicon nitride or a low-k dielectric material. In other embodiments, the material of the source / drain plug sidewall may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0051] Silicon nitride has high hardness, which helps to enhance the protective effect of the source / drain plug sidewall 511. Using low-k dielectric material helps to reduce the overall dielectric constant of the source / drain plug sidewall 511 and the trench 341.

[0052] The substrate 101, the sidewalls of the source / drain plug 531, the sidewalls of the gate structure 201, and the sidewalls of the dielectric layer 401 form a trench 341. Since the dielectric constant of air is less than that of the dielectric material, as the distance between the gate structures 201 becomes smaller and the capacitance between adjacent gate structures 201 and the source / drain plug 531 becomes larger, this embodiment introduces a trench 341 at the sidewall position of the gate structure 201 to effectively reduce the parasitic capacitance between adjacent gate structures 201 and the source / drain plug 531, thereby reducing the capacitive coupling between the gate structure 201 and the source / drain plug 531, thereby reducing power consumption and improving the operating speed of the device, thus improving the performance of the semiconductor structure.

[0053] In this embodiment, the opening size d1 of the first part 342 is larger than the opening size d2 of the second part 343. Therefore, the opening size of the trench 341 on the sidewall of the dielectric layer 401 is smaller, which is beneficial for the sealing layer 601 to seal the trench 341 better. This reduces the probability of the top of the trench 341 being damaged and accidentally opened during subsequent processes on the top of the sealing layer 601, thus helping to ensure the performance of the semiconductor structure. At the same time, the dielectric constant of air is smaller than that of the dielectric material. Therefore, the opening size d1 of the trench 341 on the side of the gate structure 201 is larger, that is, a larger air gap is introduced between the gate structure 201 and the source / drain plug 531. This effectively reduces the parasitic capacitance between adjacent gate structures 201 and source / drain plugs 531, thereby reducing the capacitive coupling between the gate structure 201 and the source / drain plugs 531, thereby reducing power consumption and increasing the operating speed of the device, and improving the performance of the semiconductor structure.

[0054] It should be noted that the opening size d1 of the first part 342 should not be too large or too small. If the opening size d1 of the first part 342 is too large, it will easily occupy too much space on the side of the gate structure 201, making it difficult to provide enough space in the process of semiconductor structure size shrinking. If the opening size d1 of the first part 342 is too small, the air gap space introduced between the gate structure 201 and the source / drain plug 531 will be too small, making it difficult to meet the process requirement of reducing the dielectric constant between the gate structure 201 and the adjacent source / drain plug 531. This will result in a correspondingly worse effect on reducing the parasitic capacitance between the gate structure 201 and the adjacent source / drain plug 531, making it difficult to improve the performance of the semiconductor structure. Moreover, the first part 342 is formed by occupying space by forming a sacrificial layer and then removing the sacrificial layer. If the opening size d1 of the first part 342 is too small, the width of the sacrificial layer will be too small, increasing the difficulty of forming the sacrificial layer. At the same time, it also increases the difficulty of removing the sacrificial layer. Therefore, in this embodiment, the opening size d1 of the first part 342 is 5nm to 10nm.

[0055] It should be noted that the opening size d2 of the second part 343 should not be too large or too small. If the opening size d2 of the second part 343 is too large, it will easily occupy too much space between the dielectric layer 401 and the source / drain plug 531, making it difficult to keep up with the trend of increasingly smaller semiconductor structure sizes. Moreover, if the opening size d2 of the second part 343 is too large, the sealing layer 601 will have difficulty sealing the trench 341 well. This could lead to damage to the top of the trench 341 during subsequent processes on top of the sealing layer 601, potentially opening the trench 341 and affecting the performance of the semiconductor structure. If the opening size d2 of the second part 343 is too small, since the second part 343 is formed by occupying space with a sacrificial layer and then removing the sacrificial layer, a small opening size d2 would result in a very small sacrificial layer width, increasing the difficulty of forming and removing the sacrificial layer. Therefore, in this embodiment, the opening size d2 of the second part 343 is 2nm to 5nm.

[0056] The sealing layer 601 is used to seal the top of the trench 341. The sealing layer 601 is also located on top of the dielectric layer 401 and the source / drain plug 531, which helps to enhance the sealing effect of the sealing layer 601 on the trench 341.

[0057] In this embodiment, the material of the sealing layer 601 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride. Silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride have high density, thus possessing good sealing performance. Furthermore, they are difficult to fill small gaps, which is beneficial for sealing the top of the groove 341 while ensuring that the groove 341 still retains a relatively large air gap after the sealing layer 601 is sealed.

[0058] It should be noted that the thickness of the sealing layer 601 cannot be too large or too small. If the thickness of the sealing layer 601 is too large, it may easily compress the process window for subsequent source / drain plug formation, affecting the subsequent semiconductor structure fabrication process. If the thickness of the sealing layer 601 is too small, its sealing performance will be affected, making it difficult for the sealing layer 601 to completely seal the trench 341, which will impact the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the sealing layer 601 is 5 nanometers to 100 nanometers.

[0059] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0060] Figures 3 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0061] refer to Figure 3A substrate 100 is provided, on which a gate structure 200 is formed, and source / drain doped layers 110 are formed in the substrate 100 on both sides of the gate structure 200.

[0062] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include planar transistors, fin field-effect transistors, or fully enclosed gate transistors.

[0063] In this embodiment, taking a finned field-effect transistor as an example, the substrate 100 includes a substrate and fins protruding from the substrate. The substrate material is silicon. In other embodiments, the substrate material can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material can be a material suitable for process requirements or easy to integrate.

[0064] For clarity, the fins are not shown in the accompanying drawings of this embodiment.

[0065] In this embodiment, the gate structure 200 is a device gate structure, which is used to control the opening or closing of the transistor channel.

[0066] In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0067] The gate dielectric layer is used to isolate the gate electrode layer and the fins. In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0068] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the fin. Specifically, the material of the gate oxide layer can be silicon oxide.

[0069] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0070] In this embodiment, the gate structure 200 is a metal gate structure.

[0071] Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0072] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0073] In this embodiment, during the step of providing the substrate 100, a gate sidewall 210 is formed on the sidewall of the gate structure 200, and the gate sidewall 210 extends to cover the top of the substrate 100 between adjacent gate structures 200.

[0074] The gate sidewall 210 is used to protect the gate structure 200 during the subsequent trench formation process, thereby reducing the impact of the trench formation process on the gate structure 200.

[0075] In this embodiment, the gate sidewall 210 also extends to cover a portion of the top of the substrate 100, serving as an etch stop position in the subsequent step of forming the first sacrificial layer.

[0076] In this embodiment, the gate sidewall 210 is a single-layer structure, and the material of the gate sidewall 210 includes silicon nitride or a low-k dielectric material. In other embodiments, the gate sidewall may also be a multilayer structure, and the material of the gate sidewall may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0077] Silicon nitride has high hardness, which helps to enhance the protective effect of the gate sidewall 210. Using a low-k dielectric material helps to reduce the dielectric constant of the gate sidewall 210 and the trench formed subsequently.

[0078] The source / drain doped layer 110 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0079] Reference Figure 4 and Figure 5 A first sacrificial layer 310 is formed on the sidewall of the gate structure 200.

[0080] The first sacrificial layer 310 is used to reserve space for the subsequent formation of trenches.

[0081] It should be noted that the width d3 of the first sacrificial layer 310 should not be too large or too small. The space occupied by the first sacrificial layer 310 is the space of a portion of the trench located on the side of the gate structure 200 in the subsequently formed trench. If the width d3 of the first sacrificial layer 310 is too large, it will easily occupy too much space on the side of the gate structure 200, making it difficult to provide sufficient space in the process of increasingly smaller semiconductor structure sizes. If the width d3 of the first sacrificial layer 310 is too small, it increases the difficulty of forming the first sacrificial layer 310, and also increases the difficulty of removing the first sacrificial layer 310. Moreover, after removing the first sacrificial layer 310, the air gap space introduced between the gate structure 200 and the source / drain plugs is too small, making it difficult to meet the process requirement of reducing the dielectric constant between the gate structure 200 and the adjacent source / drain plugs. This results in a correspondingly worse effect on reducing the parasitic capacitance between the gate structure 200 and the adjacent source / drain plugs, making it difficult to improve the performance of the semiconductor structure. Therefore, in this embodiment, the width d3 of the first sacrificial layer 310 is 2nm to 5nm.

[0082] In this embodiment, the material of the first sacrificial layer 310 includes amorphous silicon or silicon carbide.

[0083] Amorphous silicon or silicon carbide is an easy-to-remove material, and it has a large etching selectivity with the material of the gate sidewall 210 and the material of the dielectric layer formed subsequently, which helps to reduce the damage to the gate sidewall 210 and the dielectric layer caused by the subsequent removal of the first sacrificial layer 310.

[0084] Specifically, in this embodiment, the step of forming the first sacrificial layer 310 on the sidewall of the gate structure 200 includes: referencing Figure 4 A first sacrificial material layer 300 is formed covering the top of the gate structure 200, the sidewalls, and the top of the substrate 100.

[0085] The first sacrificial material layer 300 is used to directly form the first sacrificial layer 310.

[0086] Accordingly, in this embodiment, the material of the first sacrificial material layer 300 includes amorphous silicon or silicon carbide.

[0087] In this embodiment, the first sacrificial material layer 300 is formed using atomic layer deposition (ALD).

[0088] The first sacrificial material layer 300 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the first sacrificial material layer 300 to conformally cover the top, sidewalls and top of the gate structure 200 and the substrate 100.

[0089] refer to Figure 5Remove the first sacrificial material layer 300 on the top of the gate structure 200 and the top of the substrate 100, and retain the first sacrificial material layer 300 located on the sidewall of the gate structure 200 as the first sacrificial layer 310.

[0090] In this embodiment, a dry etching process is used to remove the first sacrificial material layer 300 on the top of the gate structure 200 and the top of the substrate 100.

[0091] Dry etching is characterized by anisotropic etching. Therefore, by selecting dry etching, the etching becomes more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first sacrificial layer 310.

[0092] In this embodiment, in the step of removing the first sacrificial material layer 300 on the top of the substrate 100, the first sacrificial material layer 300 on the top of the substrate 100 is removed with the gate sidewall 210 as the etching stop position.

[0093] Using the gate sidewall 210 as the etching stop position is beneficial for better control of the etching amount and for reducing the probability of over-etching of the source / drain doped layer 110.

[0094] refer to Figure 6 A dielectric layer 400 is formed on top of the gate structure 200 and the first sacrificial layer 310, with the sidewalls of the dielectric layer 400 flush with the sidewalls of the first sacrificial layer 310.

[0095] The dielectric layer 400 serves as an isolation layer between adjacent devices and is also used to form trenches in the future.

[0096] In this embodiment, the sidewall of the dielectric layer 400 is flush with the sidewall of the first sacrificial layer 310, providing a better platform for the subsequent formation of the second sacrificial layer on the sidewalls of the dielectric layer 400 and the first sacrificial layer 310. Moreover, since the sidewall of the dielectric layer 400 is flush with the sidewall of the first sacrificial layer 310, the width of the dielectric layer 400 at the top of the gate structure 200 is greater than the width of the gate structure 200. Thus, the morphology of the first part of the trench being larger than the second part can be obtained through the sidewalls of the gate structure 200 and the sidewalls of the dielectric layer 400, which makes the method of forming the trench to obtain this morphology simpler.

[0097] The dielectric layer 400 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0098] Specifically, in this embodiment, the step of forming a dielectric layer 400 on top of the gate structure 200 and the first sacrificial layer 310 includes: forming a dielectric material layer (not shown) covering the gate structure 200, the first sacrificial layer 310 and the substrate 100.

[0099] The dielectric material layer is used to directly form the dielectric layer 400.

[0100] In this embodiment, the dielectric material layer between the adjacent first sacrificial layers 310 located on the sidewall of the adjacent gate structure 200 is removed, and the dielectric material layer located on top of the gate structure 200 and the first sacrificial layer 310 is retained as the dielectric layer 400.

[0101] In this embodiment, a dry etching process is used to remove the dielectric material layer between adjacent first sacrificial layers 310 located on the sidewalls of adjacent gate structures 200.

[0102] Dry etching is anisotropic, so by selecting dry etching, the etching becomes more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of dielectric layer 400.

[0103] In this embodiment, in the step of removing the dielectric material layer between adjacent first sacrificial layers 310 located on the sidewall of adjacent gate structure 200, the dielectric material layer between adjacent first sacrificial layers 310 located on the sidewall of adjacent gate structure 200 is removed with the gate sidewall 210 as the etching stop position.

[0104] Using the gate sidewall 210 as the etching stop position is beneficial for better control of the etching amount and for reducing the probability of over-etching of the source / drain doped layer 110.

[0105] In this embodiment, after removing the dielectric material layer between the adjacent first sacrificial layers 310 located on the sidewall of the adjacent gate structure 200, the gate sidewall 210 on the top of the exposed substrate 100 is removed, exposing the source / drain doped layer 110.

[0106] Remove the gate sidewall 210 on the top of the exposed substrate 100 to expose the source / drain doped layer 110, in preparation for the subsequent formation of source / drain plugs.

[0107] Reference Figures 7 to 9 A second sacrificial layer 330 is formed on the sidewall of the dielectric layer 400 and the first sacrificial layer 310. The second sacrificial layer 330 on the side of the adjacent gate structure 200 forms a first trench 520, and the first trench 520 exposes the top of the source and drain doped layer 110.

[0108] The second sacrificial layer 330 is used to occupy space for the subsequent formation of trenches. The first trench 520 exposes the top of the source / drain doped layer 110, preparing for the subsequent formation of source / drain plugs in the first trench 520 that are in contact with the source / drain doped layer 110.

[0109] It should be noted that the width d4 of the second sacrificial layer 330 should not be too large or too small. The space occupied by the second sacrificial layer 330 includes the remaining space of the trench on the side of the gate structure 200 and the space of the trench on the side of the dielectric layer 400 in the subsequently formed trench. If the width d4 of the second sacrificial layer 330 is too large, it will easily occupy too much space on the side of the gate structure 200 and the side of the dielectric layer 400. In the development process of semiconductor structure size becoming smaller and smaller, it is difficult to provide too much space. Moreover, if the width d4 of the second sacrificial layer 330 is too large, the top dimension of the trench will be too large, and the subsequent sealing layer will have difficulty sealing the trench well. Therefore, when performing subsequent processes on the top of the sealing layer, the top of the trench may be damaged, and the trench may be accidentally opened. This issue can affect the performance of the semiconductor structure. If the width d4 of the second sacrificial layer 330 is too small, it increases the difficulty of forming the second sacrificial layer 330 and the subsequent removal of the second sacrificial layer 330. Moreover, after the second sacrificial layer 330 is removed, the air gap introduced between the gate structure 200 and the source / drain plugs is formed by the space occupied by the first sacrificial layer 310 and the second sacrificial layer 300, which can easily lead to the air gap being too small. This makes it difficult to meet the process requirement of reducing the dielectric constant between the gate structure 200 and the adjacent source / drain plugs, resulting in a correspondingly worse effect on reducing the parasitic capacitance between the gate structure 200 and the adjacent source / drain plugs, making it difficult to improve the performance of the semiconductor structure. Therefore, in this embodiment, the width d4 of the second sacrificial layer 330 is 2nm to 5nm.

[0110] In this embodiment, the material of the second sacrificial layer 330 includes amorphous silicon or silicon carbide.

[0111] Amorphous silicon or silicon carbide is an easy-to-remove material and has a large etching selectivity with the material of the gate sidewall 210 and the dielectric layer 400, which helps to reduce the damage to the gate sidewall 210 and the dielectric layer caused by the subsequent removal of the second sacrificial layer 330.

[0112] In this embodiment, the first sacrificial layer 310 and the second sacrificial layer 330 are made of the same material, which is beneficial for removing the first sacrificial layer 310 and the second sacrificial layer 330 in the same step in the future, thereby improving process efficiency.

[0113] Specifically, in this embodiment, the step of forming the second sacrificial layer 330 on the sidewalls of the dielectric layer 400 and the first sacrificial layer 310 includes: referencing Figure 7 A second sacrificial material layer 320 is formed covering the top and sidewalls of the dielectric layer 400, the sidewalls of the first sacrificial layer 310, and the top of the substrate 100.

[0114] The second sacrificial material layer 320 is used to directly form the second sacrificial layer 330.

[0115] Accordingly, in this embodiment, the material of the second sacrificial material layer 320 includes amorphous silicon or silicon carbide.

[0116] In this embodiment, an atomic layer deposition process is used to form the second sacrificial material layer 320.

[0117] The second sacrificial material layer 320 formed by atomic layer deposition has good thickness uniformity and good step coverage ability, which enables the second sacrificial material layer 320 to conformally cover the top and sidewalls of the dielectric layer 400, the sidewalls of the first sacrificial layer 310, and the top of the substrate 100.

[0118] refer to Figure 9 Remove the second sacrificial material layer 320 from the top of the dielectric layer 400 and the top of the substrate 100, and retain the second sacrificial material layer 320 located on the sidewall of the dielectric layer 400 and the sidewall of the first sacrificial layer 310 as the second sacrificial layer 330.

[0119] In this embodiment, a dry etching process is used to remove the second sacrificial material layer 320 on top of the dielectric layer 400 and the substrate 100.

[0120] Dry etching is characterized by anisotropic etching. Therefore, by selecting dry etching, the etching becomes more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the second sacrificial layer 330.

[0121] Reference Figure 8 and Figure 9 After the first trench 520 is formed, and before the source and drain plug is formed, the process also includes: forming a source and drain plug sidewall 510 on the sidewall of the first trench 520.

[0122] The source / drain plug sidewall 510 is used to protect the source / drain plug during the subsequent trenching process, thereby reducing the impact of the trenching process on the source / drain plug.

[0123] In this embodiment, the material of the source / drain plug sidewall 510 includes silicon nitride or a low-k dielectric material. In other embodiments, the material of the source / drain plug sidewall may also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, or boron carbonitride.

[0124] Silicon nitride has high hardness, which helps to enhance the protective effect of the source / drain plug sidewall 510. Using low-k dielectric material helps to reduce the dielectric constant of the source / drain plug sidewall 510 and the trench as a whole.

[0125] Specifically, the step of forming the source / drain plug sidewall 510 on the sidewall of the first trench 520 includes: (Referring to...) Figure 8 After the second sacrificial material layer 320 is formed, a sidewall material layer 500 is formed to cover the second sacrificial material layer 320 in a conformal manner.

[0126] The sidewall material layer 500 is used to directly form the source / drain plug sidewall 510.

[0127] In this embodiment, the source / drain plug sidewall 510 is formed using atomic layer deposition (ALD).

[0128] The source / drain plug sidewall 510 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the source / drain plug sidewall 510 to cover the second sacrificial material layer 320 in good conformal manner.

[0129] refer to Figure 9 Remove the sidewall material layer 500 on top of dielectric layer 400 and substrate 100, and retain the sidewall material layer 500 on the sidewall of second sacrificial layer 330 as source / drain plug sidewall 510.

[0130] In this embodiment, a dry etching process is used to remove the sidewall material layer 500 on top of the dielectric layer 400 and the substrate 100.

[0131] Dry etching is anisotropic, so by selecting dry etching, the etching is more directional, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the source / drain plug sidewall 510.

[0132] In this embodiment, removing the second sacrificial material layer 320 and the sidewall material layer 500 on top of the dielectric layer 400 and the substrate 100 in the same step is beneficial to improving process efficiency.

[0133] refer to Figure 10 Source / drain plug 530 is formed in the first trench 520.

[0134] The source / drain plug 530 is used to bring out the electrical properties of the source / drain doped layer 110.

[0135] In this embodiment, the source / drain plug 530 is made of tungsten. In other embodiments, the source / drain plug may also be made of cobalt or ruthenium.

[0136] refer to Figure 11 After forming the source / drain plug 530, the first sacrificial layer 310 and the second sacrificial layer 330 are removed to form a second trench 340 surrounded by the substrate 100, the sidewall of the source / drain plug 530, the sidewall of the gate structure 200, and the sidewall of the dielectric layer 400.

[0137] The substrate 100, the sidewalls of the source / drain plug 530, the sidewalls of the gate structure 200, and the sidewalls of the dielectric layer 400 form a second trench 340. Since the dielectric constant of air is less than that of the dielectric material, as the distance between the gate structures 200 becomes smaller and the capacitance between adjacent gate structures 200 and the source / drain plug 530 becomes larger, this embodiment introduces a second trench 340 at the sidewall position of the gate structure 200. This effectively reduces the parasitic capacitance between adjacent gate structures 200 and the source / drain plug 530, thereby reducing the capacitive coupling between the gate structure 200 and the source / drain plug 530, thereby reducing power consumption and increasing the operating speed of the device, thus improving the performance of the semiconductor structure.

[0138] In this embodiment of the invention, by occupying space with the first sacrificial layer 310 and the second sacrificial layer 330 respectively, the second trench 340 includes a first portion located on the side of the gate structure 200 and a second portion connected to the top of the first portion and located on the side of the dielectric layer 400. The opening size of the first portion is larger than the opening size of the second portion, resulting in a smaller opening size of the second trench 340 on the sidewall of the dielectric layer 400. This facilitates better sealing of the second trench 340 by the sealing layer, thereby reducing damage to the top of the second trench 340 during subsequent processes on top of the sealing layer. The probability of accidentally opening the second trench 340 is reduced, which helps to ensure the performance of the semiconductor structure. At the same time, the dielectric constant of air is less than that of the dielectric material. Therefore, the opening size of the second trench 340 on the side of the gate structure 200 is larger, that is, a larger air gap is introduced between the gate structure 200 and the source-drain plug 530. This effectively reduces the parasitic capacitance between adjacent gate structures 200 and source-drain plugs 530, thereby reducing the capacitive coupling between the gate structure 200 and the source-drain plugs 530, thereby reducing power consumption and increasing the operating speed of the device, and improving the performance of the semiconductor structure.

[0139] In this embodiment, the gate structure 200 has a gate sidewall 210 formed on its sidewall, and the second trench 340 is formed by the substrate 100, the source / drain plug 530 sidewall, the gate sidewall 210, and the dielectric layer 400 sidewall.

[0140] In this embodiment, the source drain plug 530 has a source drain plug sidewall 510 formed on its sidewall, and the second trench 340 is formed by the substrate 100, the source drain plug 530 sidewall, the gate structure 200 sidewall, and the dielectric layer 400 sidewall.

[0141] Specifically, in this embodiment, the second trench 340 is formed by a substrate 100, a source / drain plug sidewall 510, a gate sidewall 210, and a dielectric layer 400 sidewall.

[0142] In this embodiment, the first sacrificial layer 310 and the second sacrificial layer 330 are removed in the same step.

[0143] In this embodiment, the first sacrificial layer 310 and the second sacrificial layer 330 are made of the same material, which makes them easy to remove in the same step and helps to improve process efficiency.

[0144] In this embodiment, an isotropic etching process is used to remove the first sacrificial layer 310 and the second sacrificial layer 330.

[0145] The use of isotropic etching process is beneficial to remove the first sacrificial layer 310 and the second sacrificial layer 330 cleanly. Moreover, the isotropic etching process is easy to achieve a large etching selectivity, which helps to reduce damage to the dielectric layer 400, the gate sidewall 210 and the source-drain plug sidewall 510 during the removal of the first sacrificial layer 310 and the second sacrificial layer 330.

[0146] Continue to refer to Figure 11 A sealing layer 600 is formed on top of the dielectric layer 400 and the source / drain plug 530, and the sealing layer 600 seals the top of the second trench 340.

[0147] The sealing layer 600 is used to seal the top of the second trench 340. The sealing layer 600 is also located on top of the dielectric layer 400 and the source / drain plug 530, which helps to enhance the sealing effect of the sealing layer 600 on the second trench 340.

[0148] In this embodiment, the material of the sealing layer 600 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride. Silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride have high density, thus possessing good sealing performance. Furthermore, they are difficult to fill small gaps, which is beneficial for sealing the top of the groove 340 while ensuring that after the sealing layer 600 is sealed, the second groove 340 still retains a relatively large air gap.

[0149] It should be noted that the thickness of the sealing layer 600 cannot be too large or too small. If the thickness of the sealing layer 600 is too large, it may easily compress the process window for subsequent source / drain plug formation, affecting the subsequent semiconductor structure fabrication process. If the thickness of the sealing layer 600 is too small, its sealing performance will be affected, making it difficult for the sealing layer 600 to completely seal the second trench 340, thus impacting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the sealing layer 600 is between 5 nanometers and 100 nanometers.

[0150] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate, the channel layer, the gate structure and the gate sidewall located on the substrate, and the source / drain doped layers in the substrate located on both sides of the gate structure; A dielectric layer is located on top of the gate structure; A source / drain plug is located on top of the source / drain doped layer. The substrate, the source / drain plug sidewall, the gate structure sidewall, and the dielectric layer sidewall form a trench. The trench includes a first part formed by the gap between the gate structure and the source / drain plug, and a second part connected to the top of the first part and formed by the gap between the dielectric layer and the source / drain plug. The opening size of the first part is larger than the opening size of the second part. The first part and the second part are flush with the sidewall on one side of the source / drain plug. A sealing layer is located on top of the dielectric layer and the source / drain plugs, and the sealing layer also seals the top of the trench.

2. The semiconductor structure as described in claim 1, characterized in that, The width of the dielectric layer at the top of the gate structure is greater than the width of the gate structure.

3. The semiconductor structure as described in claim 1, characterized in that, In the semiconductor structure, the gate sidewall is located on the sidewall of the gate structure; The trench is formed by the substrate, source / drain plug sidewalls, gate sidewalls, and dielectric layer sidewalls.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a source / drain plug sidewall, located on the source / drain plug sidewall; The trench is formed by the substrate, source / drain plug sidewalls, gate structure sidewalls, and dielectric layer sidewalls.

5. The semiconductor structure as described in claim 1, characterized in that, The opening size of the first part is 4nm to 10nm.

6. The semiconductor structure as described in claim 1, characterized in that, The opening size of the second part is 2nm to 5nm.

7. The semiconductor structure as described in claim 1, characterized in that, The sealing layer is made of one or more of silicon nitride, silicon oxide, silicon carbide, and silicon carbonitride.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure; A first sacrificial layer is formed on the sidewall of the gate structure; A dielectric layer is formed on top of the gate structure and the first sacrificial layer, and the sidewalls of the dielectric layer are flush with the sidewalls of the first sacrificial layer. A second sacrificial layer is formed on the sidewalls of the dielectric layer and the first sacrificial layer. The second sacrificial layer adjacent to the side of the gate structure forms a first trench, and the first trench exposes the top of the source and drain doped layer. A source / drain plug is formed in the first trench; After the source / drain plug is formed, the first sacrificial layer and the second sacrificial layer are removed to form a second trench surrounded by the substrate, the source / drain plug sidewall, the gate structure sidewall, and the dielectric layer sidewall. A sealing layer is formed on top of the dielectric layer and the source / drain plug, and the sealing layer seals the top of the second trench.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming a first sacrificial layer on the sidewall of the gate structure includes: forming a first sacrificial material layer covering the top of the gate structure, the sidewall, and the top of the substrate; Remove the first sacrificial material layer at the top of the gate structure and the top of the substrate, and retain the first sacrificial material layer located on the sidewall of the gate structure as the first sacrificial layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, the sidewalls of the gate structure are formed with gate sidewalls, and the gate sidewalls extend to cover the top of the substrate between adjacent gate structures; In the step of removing the first sacrificial material layer on top of the substrate, the first sacrificial material layer on top of the substrate is removed with the gate sidewall as the etching stop position. In the step of removing the first sacrificial layer and the second sacrificial layer, the second trench is formed by the substrate, the source / drain plug sidewall, the gate sidewall, and the dielectric layer sidewall.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first sacrificial material layer is formed using atomic layer deposition (ALD).

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming a dielectric layer on top of the gate structure and the first sacrificial layer includes: forming a dielectric material layer covering the gate structure, the first sacrificial layer and the substrate; Remove the dielectric material layer between adjacent first sacrificial layers located on the sidewalls of adjacent gate structures, and retain the dielectric material layer located on top of the gate structure and the first sacrificial layer as the dielectric layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, the sidewalls of the gate structure are formed with gate sidewalls, and the gate sidewalls extend to cover the top of the substrate between adjacent gate structures; In the step of removing the dielectric material layer between adjacent first sacrificial layers located on the sidewalls of adjacent gate structures, the dielectric material layer between adjacent first sacrificial layers located on the sidewalls of adjacent gate structures is removed with the gate sidewall as the etching stop position. After removing the dielectric material layer between adjacent first sacrificial layers located on the sidewalls of adjacent gate structures, the gate sidewalls on top of the exposed substrate are removed to expose the source / drain doped layers.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of forming a second sacrificial layer on the sidewalls of the dielectric layer and the first sacrificial layer includes: forming a second sacrificial material layer covering the top and sidewalls of the dielectric layer, the sidewalls of the first sacrificial layer, and the top of the substrate; Remove the second sacrificial material layer at the top of the dielectric layer and the top of the substrate, and retain the second sacrificial material layer located on the sidewall of the dielectric layer and the sidewall of the first sacrificial layer as the second sacrificial layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The second sacrificial material layer is formed using atomic layer deposition (ALD).

16. The method for forming a semiconductor structure as described in claim 8, characterized in that, After the first trench is formed and before the source / drain plug is formed, the method further includes: forming a source / drain plug sidewall on the sidewall of the first trench; In the step of removing the first sacrificial layer and the second sacrificial layer, the second trench is formed by the substrate, the source / drain plug sidewall, the gate structure sidewall, and the dielectric layer sidewall.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first sacrificial layer and the second sacrificial layer are made of the same material.

18. The method for forming a semiconductor structure as described in claim 8 or 17, characterized in that, The first and second sacrificial layers are removed in the same step.

19. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first and second sacrificial layers are removed using an isotropic etching process.

20. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the first sacrificial layer includes amorphous silicon or silicon carbide; the material of the second sacrificial layer includes amorphous silicon or silicon carbide.

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