Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: forming, on a substrate, a stack structure in a sub-device region, a first dielectric wall in an isolation region, and a second dielectric wall between adjacent device unit regions, the stack structure extending along a second direction, and the stack structures of adjacent sub-device regions in a device unit region being separated by the first dielectric wall, and the stack structures of adjacent device unit regions being separated by the second dielectric wall; the stack structure comprising a protruding portion and one or more channel stacks on the protruding portion, each channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer. Embodiments of the present application further reduce the distance between adjacent sub-device regions in a device unit region and the distance between adjacent device unit regions, thereby further reducing the area of the device, and facilitating the improvement of the integration of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0003] As device dimensions continue to shrink, achieving smaller spacing between NMOS and PMOS devices with fully enclosed gate structures becomes increasingly difficult and challenging. A forksheet transistor has been proposed to address this issue, creating a dielectric wall between the NMOS and PMOS devices, thereby enabling a smaller spacing between them.

[0004] However, the size of the device still needs to be further miniaturized. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which further reduces the distance between adjacent sub-device regions within a device unit region and the distance between adjacent device unit regions, thereby further reducing the area of ​​the device and improving the integration density of the device.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a plurality of device unit regions, each device unit region including a sub-device region and an isolation region located between the sub-device regions, the sub-device regions and the isolation regions being arranged along a first direction, and a second direction being parallel to the substrate and perpendicular to the first direction; a first dielectric wall, disposed on the substrate of the isolation region, the first dielectric wall extending along the second direction; a stacked structure, located on the substrate of the sub-device regions, the stacked structure extending along the second direction, and the stacked structures of adjacent sub-device regions being isolated by the first dielectric wall; the stacked structure including: a protrusion; one or more channel layers sequentially spaced apart and suspended on the protrusion; a second dielectric wall, located on the substrate between adjacent device unit regions, the second dielectric wall isolating the stacked structures of adjacent device unit regions; a gate structure, spanning the stacked structures of the sub-device regions, and the gate structure of each sub-device region surrounding the channel layers exposed by the first dielectric wall and the second dielectric wall; and source / drain doped layers, located on both sides of the gate structure and in contact with the ends of the channel layers.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a plurality of device unit regions, each device unit region including a sub-device region and an isolation region located between the sub-device regions, the sub-device regions and the isolation regions being arranged along a first direction, and a second direction being parallel to the substrate and perpendicular to the first direction; forming on the substrate a stacked structure located in the sub-device regions, a first dielectric wall located in the isolation regions, and a second dielectric wall located between adjacent device unit regions, the stacked structure extending along the second direction, and the stacked structure of adjacent sub-device regions within the device unit regions... The stacked structures of adjacent device cell regions are isolated by a first dielectric wall and by a second dielectric wall. The stacked structure includes a protrusion and one or more channel stacks located on the protrusion. Each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer. A dummy gate structure is formed across the stacked structure and the first and second dielectric walls. Source and drain doped layers are formed in the channel stacks on both sides of the dummy gate structure. The dummy gate structure is removed to form a gate opening. Through the gate opening, the sacrificial layer is removed to form a through trench, which is connected to the gate opening. A gate structure is formed in the through trench and the gate opening.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention, on the one hand, isolates the stacked structures of adjacent sub-device regions within a device unit region by a first dielectric wall, and on the other hand, isolates the stacked structures of adjacent device unit regions by a second dielectric wall. In the step of forming the source and drain doped layers, the first dielectric wall can prevent the source and drain doped layers of adjacent sub-device regions from merging, and the second dielectric wall can prevent the source and drain doped layers of adjacent device unit regions from merging. Accordingly, by adjusting the width of the first and second dielectric walls, the distance between adjacent sub-device regions within the device unit region and the distance between adjacent device unit regions can be reduced, thereby further reducing the area of ​​the device and improving the integration density of the device. In addition, by adjusting the width of the second dielectric wall, the width of the sub-device regions can be adjusted, thereby enabling the sub-device regions within the device unit region to have diverse widths, improving the freedom of device size design.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, a stacked structure located in a sub-device region, a first dielectric wall located in an isolation region, and a second dielectric wall located between adjacent device unit regions are formed on a substrate. On the one hand, the stacked structures of adjacent sub-device regions within a device unit region are isolated by the first dielectric wall; on the other hand, the stacked structures of adjacent device unit regions are isolated by the second dielectric wall. In the step of forming the source / drain doped layer, the first dielectric wall can prevent the source / drain doped layers of adjacent sub-device regions from merging, and the second dielectric wall can prevent the source / drain doped layers of adjacent device unit regions from merging. Accordingly, by adjusting the width of the first and second dielectric walls, the distance between adjacent sub-device regions within a device unit region and the distance between adjacent device unit regions can be reduced, thereby further reducing the device area and improving the device integration density. In addition, by adjusting the width of the second dielectric wall, the width of the sub-device region can be adjusted, thereby enabling the sub-device regions within a device unit region to have diverse widths and improving the freedom of device size design.

[0011] In an alternative approach, after forming the stacked structure and the first dielectric wall, a second dielectric wall is formed on the substrate between adjacent device cell regions. The second dielectric wall isolates the stacked structure of adjacent device cell regions, so as to provide sufficient space for forming the stacked structure, thereby reducing the difficulty of forming the stacked structure and improving process compatibility.

[0012] In an optional embodiment, after forming the stacked structure and the first dielectric wall, a second dielectric wall is formed on the substrate between adjacent device cell regions. The steps of forming the stacked structure located in the sub-device region and the first dielectric wall located in the isolation region on the substrate include: forming a first dielectric wall discretely on the substrate of the isolation region, the first dielectric wall extending along a second direction; forming a stacked structure on the substrate of the sub-device region, and the stacked structures of adjacent sub-device regions are isolated by the first dielectric wall. Thus, in the step of forming the first dielectric wall, the width of the first dielectric wall along the first direction is not limited by the distance between the stacked structures of adjacent sub-device regions, which is beneficial to achieving a smaller width of the first dielectric wall, thereby achieving a smaller spacing between adjacent sub-device regions, which is beneficial to further miniaturization of device size and also simplifies process complexity. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a semiconductor structure.

[0014] Figures 2 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0015] Figures 5 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0016] Figure 11 A top view is shown of a conventional nanosheet transistor, a conventional forksheet transistor, and the semiconductor structure formed in this embodiment;

[0017] Figure 12 A top view of two semiconductor structures is shown. Detailed Implementation

[0018] As the background technology shows, the size of devices still needs to be further miniaturized. This paper analyzes the reasons why the size of devices still needs to be further miniaturized in conjunction with a semiconductor structure formation method. Figure 1 This is a schematic diagram of a semiconductor structure.

[0019] refer to Figure 1 The substrate 10 includes multiple device unit regions 10s, each device unit region 10s including a sub-device region (not shown) and an isolation region (not shown) located between the sub-device regions, the sub-device regions and the isolation regions being connected along a first direction (e.g., Figure 1 Arranged in the X direction; a stacked structure, located on the substrate 10 of the sub-device region and along the second direction (as shown in the X direction); Figure 1Extending in the Y direction (as shown in the middle), the second direction is perpendicular to the first direction; the stacked structure includes: a protrusion 11; one or more channel layers 12 suspended at intervals, suspended on the protrusion 11; a dielectric wall 13 located on the substrate of the isolation region, and the dielectric wall is located between the stacked structures of adjacent sub-device regions; an isolation layer 14 located on the substrate 10 and surrounding the protrusion 11; a gate structure 15 located on the isolation layer 14 and spanning the stacked structure of the sub-device region, the gate structure 15 surrounding the channel layer 12 exposed by the dielectric wall 13; and source / drain doped layers 16 located on both sides of the gate structure 15 and in contact with the ends of the channel layer 12.

[0020] In a semiconductor structure, by setting dielectric walls 13 between the stacked structures of adjacent sub-device regions, a smaller spacing can be achieved between adjacent sub-device regions, for example, a smaller spacing can be achieved between NMOS devices and PMOS devices.

[0021] However, a relatively large distance D is still required between adjacent device cell regions 10s to achieve isolation between the source and drain doped layers 16 of adjacent device cell regions and prevent the source and drain doped layers 16 of adjacent device cell regions 10s from merging. Therefore, the size of the device still needs to be further miniaturized.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure. On one hand, the stacked structures of adjacent sub-device regions within a device unit region are isolated by a first dielectric wall. On the other hand, the stacked structures of adjacent device unit regions are isolated by a second dielectric wall. In the step of forming the source / drain doped layers, the first dielectric wall prevents the source / drain doped layers of adjacent sub-device regions from merging, and the second dielectric wall prevents the source / drain doped layers of adjacent device unit regions from merging. Accordingly, by adjusting the widths of the first and second dielectric walls, the distance between adjacent sub-device regions within the device unit region and the distance between adjacent device unit regions can be reduced, thereby further reducing the device area and improving the device integration density. Furthermore, by adjusting the width of the second dielectric wall, the width of the sub-device regions can be adjusted, thereby allowing the sub-device regions within the device unit region to have diverse widths, increasing the freedom of device size design.

[0023] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 2 to 4 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 2 This is a schematic diagram of the three-dimensional structure. Figure 3 and Figure 4 This is a top view.

[0024] In this embodiment, the semiconductor structure includes: a substrate 100, comprising a plurality of device unit regions 100s, each device unit region 100s including a sub-device region and an isolation region located between the sub-device regions, the sub-device regions and the isolation regions being arranged along a first direction, and a second direction perpendicular to the first direction; a first dielectric wall 110, disposed on the substrate 100 of the isolation region, the first dielectric wall 110 extending along the second direction; and a stacked structure, located on the substrate 100 of the sub-device regions, the stacked structure extending along the second direction, and the stacked structures of adjacent sub-device regions being isolated by the first dielectric wall 110; the stacked structure includes... : Protrusion 105; one or more channel layers 140 suspended at intervals on the protrusion 105; second dielectric wall 120 located on substrate 100 between adjacent device cell regions 100s, the second dielectric wall 120 isolating the stacked structure of adjacent device cell regions 100s; gate structure 180 spanning the stacked structure of sub-device regions and the gate structure 180 of each sub-device region surrounds the channel layer 140 exposed by the first dielectric wall 110 and the second dielectric wall 120; source / drain doped layer 160 located on both sides of the gate structure 180 and in contact with the end of the channel layer 140.

[0025] The substrate 100 is used to provide a platform for the process technology.

[0026] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may be other suitable semiconductor materials.

[0027] In this embodiment, the device unit area 100s is used to form device units.

[0028] In this embodiment, the sub-device region is used to form MOS devices, and the isolation region is used to achieve isolation between adjacent MOS devices.

[0029] Within device cell region 100s, the number of sub-device regions can be two or more. As an example, within device cell region 100s, the number of sub-device regions is two.

[0030] Accordingly, in this embodiment, the device unit region 100s includes a first sub-device region and a second sub-device region. The first sub-device region is used to form a first type MOS device, and the second sub-device region is used to form a second type MOS device. The first type MOS device and the second type MOS device have different channel conductivity types.

[0031] For example, the first sub-device region can be used to form an NMOS transistor, and the second sub-device region can be used to form a PMOS transistor; or, the first sub-device region can be used to form a PMOS transistor, and the second sub-device region can be used to form an NMOS transistor.

[0032] The protrusion 105 is used to provide support for the channel structure layer.

[0033] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure. Correspondingly, the protrusion 105 and the substrate 100 are made of the same material, silicon. In other embodiments, the protrusion and the substrate may be made of different materials.

[0034] The channel layer 140 in the channel structure layer 40 is used to provide a conductive channel for the field-effect transistor to operate.

[0035] The stacking direction of one or more channel layers 140 is perpendicular to the surface of the substrate 100.

[0036] As an example, in each channel structure layer 40, there are three channel layers 140. In other embodiments, the number of channel layers in each channel structure layer may be other numbers.

[0037] In this embodiment, the material of the channel layer 140 includes silicon.

[0038] The first dielectric wall 110 is used to isolate adjacent sub-device areas, which helps to achieve smaller spacing between adjacent sub-device areas.

[0039] Therefore, the first dielectric wall 110 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride, thereby ensuring that the first dielectric wall 110 can play an isolation role. In this embodiment, the first dielectric wall 110 is made of silicon nitride.

[0040] The second dielectric wall 120 is used to isolate adjacent device cell regions 100s. The second dielectric wall 120 can prevent the source and drain doped layers 160 of adjacent device cell regions 100s from contacting each other. Correspondingly, by adjusting the width of the first dielectric wall 110 and the second dielectric wall 120, the distance between adjacent sub-device regions within the device cell region 100s and the distance between adjacent device cell regions 100s can be reduced, thereby further reducing the device area and improving the device integration density. In addition, by adjusting the width of the second dielectric wall 120, the width of the sub-device regions can be adjusted, thereby allowing the sub-device regions within the device cell region to have diverse widths and improving the freedom of device size design.

[0041] Therefore, the material of the second dielectric wall 120 is a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride, thereby ensuring that the second dielectric wall 120 can play an isolation role. In this embodiment, the material of the second dielectric wall 120 is silicon nitride.

[0042] As an example, the material of the second dielectric wall 120 is the same as that of the first dielectric wall 110, which helps to improve process compatibility.

[0043] In this embodiment, the top surface of the stacked structure and the second dielectric wall 120 is flush with the top surface of the first dielectric wall 110.

[0044] When the device is operating, the source / drain doped layer 160 is used to provide a carrier source. Moreover, in this embodiment, the material of the source / drain doped layer 160 includes a stress layer, which can provide stress to the channel when the device is operating, thereby improving the carrier mobility of the MOS device.

[0045] As an example, the first sub-device region i (e.g. Figure 4 (As shown) is used to form an NMOS device. The source / drain doped layer 160 of the first sub-device region i includes a stress layer doped with N-type ions, and the material of the stress layer includes silicon; the second sub-device region ii (as shown) is used to form an NMOS device. Figure 4 As shown, the source and drain doped layer 160 of the second sub-device region ii is used to form a PMOS device, and the stress layer is made of Si or SiGe.

[0046] In this embodiment, the semiconductor structure further includes an insulating layer 145 located within the protrusions 105 on both sides of the gate structure 180, and the insulating layer 145 exposes one or more channel layers 40 that are spaced apart and suspended.

[0047] The insulating layer 145 is used to achieve isolation between adjacent protrusions 105.

[0048] In this embodiment, the insulating layer 145 is made of silicon oxide. In other embodiments, the insulating layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.

[0049] As one embodiment, the bottom surface of the insulating layer 145 is in contact with the substrate 100, that is, the insulating layer 145 is relatively deep, which is beneficial to improving the isolation effect between adjacent protrusions 105.

[0050] Accordingly, the source / drain doped layer 160 is located on the insulating layer 145 on both sides of the gate structure 180 and is in contact with the end of the channel layer 40. Therefore, the source / drain doped layer 160 is isolated from the substrate 100 by the insulating layer 145, which helps to reduce the leakage current of the device.

[0051] When the device is in operation, the gate structure 180 is used to control the opening or closing of the conductive channel of the MOS transistor.

[0052] As an example, the gate structure 180 is a metal gate structure, including a high-k gate dielectric layer (not shown) on the channel layer 140, a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

[0053] The high-k gate dielectric layer is used to electrically isolate the channel layer and the work function layer, as well as to isolate the protrusion 105 and the work function layer. In this embodiment, the material of the high-k gate dielectric layer includes high-k dielectric materials, such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0054] The work function layer is used to adjust the work function of the MOS device. In this embodiment, when forming a PMOS transistor, the material of the work function layer is a P-type work function material, including one or more of Ta, TiN, TaN, TaSiN, and TiSiN; when forming an NMOS transistor, the material of the work function layer is an N-type work function material, including one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN.

[0055] The gate electrode layer serves as an electrode, enabling electrical connections between the gate structure and external circuitry or other interconnect structures. Materials for the gate electrode layer include W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0056] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer (not shown), located on the substrate 100 on the side of the gate structure 180, and covering the source / drain doped layer 160. The interlayer dielectric layer is used to isolate adjacent gate structures 180.

[0057] The interlayer dielectric layer is made of an insulating dielectric material. As an example, the interlayer dielectric layer is made of silicon oxide. In this embodiment, the interlayer dielectric layer is located on the insulating layer 145.

[0058] Reference Figure 3 ,in, Figure 3 (a), (b), and (c) show top views of a conventional nanosheet transistor, a conventional forksheet transistor, and the semiconductor structure formed in this embodiment, respectively.

[0059] Depend on Figure 3 It is known that traditional fork-gate transistors can save about 30% of the area compared to traditional nanowire transistors, while the semiconductor structure formed in this embodiment can save about 20% of the area compared to traditional fork-gate transistors. Therefore, this embodiment is conducive to further reducing the area of ​​the device and improving the integration of the device.

[0060] Reference Figure 4 The diagram shows top views of two semiconductor structures, in which... Figure 4 In (a) and 4(b), the second sub-device region ii has different area sizes. In this embodiment, the width of the sub-device region (e.g., w1 and w2) can be adjusted by adjusting the width of the second dielectric wall 120 (e.g., d1 or d2), thereby enabling the sub-device regions within the device unit region 100s to have diverse widths, improving the freedom of device size design.

[0061] Specifically, in conjunction with reference Figure 4 , Figure 4 (a) The width of the first sub-device area i is w0, the width of the second sub-device area ii is w1, w0 and w1 are the same size, and the distance between adjacent device unit areas 100s is d1. Figure 4 In (b), the width of the first sub-device area i is w0, the width of the second sub-device area ii is w2, w0 and w2 are different in size, and the distance between adjacent device unit areas 100s is d2, d2 and d1 are different in size.

[0062] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0063] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0064] refer to Figure 5 A substrate 100 is provided, the substrate 100 including a plurality of device cell regions 100s, each device cell region 100s including a sub-device region (not shown) and an isolation region (not shown) located between the sub-device regions, the sub-device regions and the isolation regions being separated along a first direction (e.g., Figure 5 The arrangement (as shown in the X direction) is parallel to the substrate and perpendicular to the first direction, which is the second direction (as shown in the X direction). Figure 5 shown in the Y direction).

[0065] Substrate 100 is used to provide a platform for process technology.

[0066] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may be other suitable semiconductor materials.

[0067] Device cell area 100s is used to form device cells.

[0068] The sub-device region is used to form MOS devices, and the isolation region is used to achieve isolation between adjacent MOS devices.

[0069] Within device cell region 100s, the number of sub-device regions can be two or more. As an example, within device cell region 100s, the number of sub-device regions is two.

[0070] Accordingly, in this embodiment, the device unit region 100s includes a first sub-device region and a second sub-device region. The first sub-device region is used to form a first type MOS device, and the second sub-device region is used to form a second type MOS device. The first type MOS device and the second type MOS device have different channel conductivity types.

[0071] For example, the first sub-device region i can be used to form an NMOS transistor, and the second sub-device region ii can be used to form a PMOS transistor; or, the first sub-device region i can be used to form a PMOS transistor, and the second sub-device region ii can be used to form an NMOS transistor.

[0072] Reference Figures 5 to 8 A stacked structure 200 located in a sub-device region, a first dielectric wall 110 located in an isolation region, and a second dielectric wall 120 located between adjacent device cell regions 100s are formed on a substrate 100. The stacked structure 200 extends along a second direction, and the stacked structures 200 of adjacent sub-device regions within the device cell region 100s are isolated by the first dielectric wall 110, and the stacked structures 200 of adjacent device cell regions 100s are isolated by the second dielectric wall 120. The stacked structure includes a protrusion 105 and one or more channel stacks located on the protrusion 105. Each channel stack 20 includes a sacrificial layer 130 and a channel layer 140 located on the sacrificial layer 130.

[0073] By forming a stacked structure 200 located in the sub-device region, a first dielectric wall 110 located in the isolation region, and a second dielectric wall 120 located between adjacent device cell regions 100s, on the one hand, the stacked structures 200 of adjacent sub-device regions within the device cell region 100s are isolated by the first dielectric wall 110, and on the other hand, the stacked structures 200 of adjacent device cell regions 100s are isolated by the second dielectric wall 120. In the subsequent step of forming source and drain doped layers, the first dielectric wall 110 can prevent the source and drain doped layers of adjacent sub-device regions from merging, and the second dielectric wall 120 can prevent the source and drain doped layers of adjacent device cell regions 100s from merging. Accordingly, by adjusting the width of the first dielectric wall 110 and the second dielectric wall 120, the distance between adjacent sub-device regions within the device cell region 100s and the distance between adjacent device cell regions 100s can be reduced, thereby further reducing the device area and improving the device integration density.

[0074] Furthermore, in this embodiment, the width of the sub-device area can be adjusted by adjusting the width of the second dielectric wall 160, thereby enabling the sub-device area within the device unit area 100s to have diverse widths, thus improving the freedom of device size design.

[0075] The stacked structure 200 serves as a foundation for the subsequent formation of channel layers 140 that are suspended at intervals.

[0076] The protrusion 105 is used to provide support for the channel stacking.

[0077] In this embodiment, the protrusion 105 and the substrate 100 are an integral structure. Correspondingly, the protrusion 105 and the substrate 100 are made of the same material, silicon. In other embodiments, the protrusion and the substrate may be made of different materials.

[0078] The stacking direction of the multiple channel stacks 20 is perpendicular to the surface of the substrate 100.

[0079] The channel stack 20 provides a technological basis for the subsequent formation of a channel layer with suspended space partitions.

[0080] As an example, the number of channel stacks 20 is three. In other embodiments, the number of channel stacks 20 may also be other numbers.

[0081] The channel layer 140 is used to provide a conductive channel for the device; the sacrificial layer 130 is used to support the channel layer 140. After the sacrificial layer 130 is removed, the channel layer 140 can be suspended by spacing. The sacrificial layer 130 is used to occupy space for the subsequent formation of the gate structure.

[0082] In this embodiment, the material of the sacrificial layer 130 includes silicon germanium; the material of the channel layer 140 includes silicon.

[0083] The first dielectric wall 110 is used to isolate adjacent sub-device areas, which helps to achieve smaller spacing between adjacent sub-device areas.

[0084] Therefore, the first dielectric wall 110 is made of a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride, thereby ensuring that the first dielectric wall 110 can play an isolation role. In this embodiment, the first dielectric wall 110 is made of silicon nitride.

[0085] The second dielectric wall 120 is used to isolate adjacent device cell regions 100s. The second dielectric wall can prevent the source and drain doped layers of adjacent device cell regions 100s from contacting each other. Correspondingly, by adjusting the width of the first dielectric wall 110 and the second dielectric wall 120, the distance between adjacent sub-device regions within the device cell region 100s and the distance between adjacent device cell regions 100s can be reduced, thereby further reducing the device area and improving the device integration density. In addition, by adjusting the width of the second dielectric wall 120, the width of the sub-device regions can be adjusted, thereby allowing the sub-device regions within the device cell region 100s to have diverse widths, improving the freedom of device size design.

[0086] Therefore, the material of the second dielectric wall 120 is a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride, thereby ensuring that the second dielectric wall 120 can play an isolation role. In this embodiment, the material of the second dielectric wall 120 is silicon nitride.

[0087] As an example, the material of the second dielectric wall 120 is the same as that of the first dielectric wall, which helps to improve process compatibility.

[0088] In this embodiment, the top surface of the stacked structure 200 and the second dielectric wall 120 is flush with the top surface of the first dielectric wall 110.

[0089] In this embodiment, the steps of forming the stacked structure 200, the first dielectric wall 110, and the second dielectric wall 120 include:

[0090] like Figures 5 to 7 As shown, a stacked structure 200 located in the sub-device region and a first dielectric wall 110 located in the isolation region are formed on the substrate 100.

[0091] As a specific embodiment, the steps of forming a stacked structure 200 located in the sub-device region and a first dielectric wall 110 located in the isolation region on the substrate 100 include: as follows Figure 5 As shown, a first dielectric wall 110 is formed on the substrate 100 of the isolation region, and the first dielectric wall 110 extends along the second direction; as Figures 6 to 7 As shown, a stacked structure 200 is formed on the substrate 100 of the sub-device region, and the stacked structures 200 of adjacent sub-device regions are isolated by a first dielectric wall 110.

[0092] In this embodiment, after forming the stacked structure 200 and the first dielectric wall 110, a second dielectric wall 120 is formed on the substrate 100 between adjacent device cell regions 100s. The steps of forming the stacked structure 200 located in the sub-device region and the first dielectric wall 110 located in the isolation region on the substrate 100 include: forming the first dielectric wall 110 discretely on the substrate 100 of the isolation region, the first dielectric wall 110 extending along a second direction; forming the stacked structure 200 on the substrate 100 of the sub-device region, and the stacked structures 200 of adjacent sub-device regions are isolated by the first dielectric wall 110. Thus, in the step of forming the first dielectric wall 110, the width of the first dielectric wall 110 along the first direction is not limited by the distance between the stacked structures 200 of adjacent sub-device regions, which is beneficial to achieving a smaller width of the first dielectric wall 110, thereby achieving a smaller spacing between adjacent sub-device regions, which is beneficial to further miniaturization of device size and also simplifies process complexity.

[0093] In this embodiment, the step of forming the first dielectric wall 110 includes: forming a first dielectric material layer (not shown) on the substrate 100; removing the first dielectric material layer on the substrate 100 located between the sub-device region and the adjacent device unit region 100s, and retaining the first dielectric material layer located on the isolation region as the first dielectric wall 110.

[0094] In this embodiment, the step of removing the first dielectric material layer on the substrate 100 located between the sub-device region and the adjacent device unit region 100s, and retaining the first dielectric material layer located on the isolation region as the first dielectric wall 110 includes: patterning the first dielectric material layer to form an initial dielectric layer; performing sidewall thinning on the initial dielectric layer along a direction parallel to the substrate 100, and using the remaining initial dielectric layer as the first dielectric wall 110.

[0095] By thinning the initial dielectric layer along a direction parallel to the substrate 100, the remaining initial dielectric layer is used as the first dielectric wall 110. This allows for a further reduction in the width of the first dielectric wall 110 under the limitations of existing photolithography processes, which is beneficial for achieving a smaller spacing between adjacent sub-device regions within the device unit region 100s.

[0096] As an example, an isotropic etching process is used to thin the sidewalls of the initial dielectric layer along a direction parallel to the substrate 100. The isotropic etching process has the characteristics of isotropic etching, which enables the etching of the sidewalls of the initial dielectric layer along a direction parallel to the substrate 100, thereby achieving the thinning of the width of the initial dielectric layer.

[0097] As an example, isotropic etching processes include one or both of wet etching and isotropic etching processes.

[0098] In this embodiment, the steps for forming the stacked structure 200 include: as follows Figure 6 As shown, an initial stacked structure 115 is formed on the substrate 100 exposed by the first dielectric wall 110. The initial stacked structure 115 includes a raised material layer 101 and one or more initial channel stacks 102 located on the raised material layer 101; as Figure 7 As shown, the initial stacked structure 115 on the substrate 100 located between adjacent device cell regions 100s is removed, and the remaining initial stacked structure 115 on the substrate 100 in the sub-device region is used as the stacked structure 200.

[0099] In other embodiments, the step of forming a stacked structure located in a sub-device region and a first dielectric wall located in an isolation region on a substrate includes: forming a stacked structure discrete on the substrate in the sub-device region; and forming a first dielectric wall located between adjacent stacked structures in the isolation region.

[0100] like Figure 8 As shown, after forming the stacked structure 200 and the first dielectric wall 110, a second dielectric wall 120 is formed on the substrate 100 between adjacent device cell regions 100s. The second dielectric wall 120 isolates the stacked structure 200 of the adjacent device cell regions 100s.

[0101] After forming the stacked structure 200 and the first dielectric wall 110, a second dielectric wall 120 is formed on the substrate 100 between adjacent device cell regions 100s. The second dielectric wall 120 isolates the stacked structure 200 of the adjacent device cell regions 100s, so as to provide sufficient space for forming the stacked structure 200, thereby reducing the difficulty of forming the stacked structure 200 and improving process compatibility.

[0102] In this embodiment, the step of forming the second dielectric wall 120 includes: filling the region enclosed between the stacked structure 200 of the adjacent device cell regions 100s and the substrate 100 with a second dielectric material layer (not shown), the second dielectric material layer is also formed on the top of the stacked structure 200 and the first dielectric wall 110; removing the second dielectric material layer above the top of the stacked structure 200, and the remaining second dielectric material layer located between the adjacent device cell regions 100s is used as the second dielectric wall 120.

[0103] In this embodiment, the process for forming the second dielectric material layer includes a flow chemical vapor deposition process.

[0104] In this embodiment, the process of removing the second dielectric material layer above the top of the stacked structure 200 includes a chemical mechanical planarization process.

[0105] refer to Figure 9This forms a pseudo-gate structure 150 that spans the stacked structure 200, the first dielectric wall 110, and the second dielectric wall 120.

[0106] The pseudo-gate structure 150 is used to reserve space for the subsequent formation of the gate structure.

[0107] In this embodiment, the dummy gate structure 150 includes a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer. As an example, the material of the dummy gate oxide layer includes one or both of silicon oxide and silicon oxynitride. As an example, the material of the dummy gate layer includes polycrystalline silicon or amorphous silicon.

[0108] In this embodiment, the pseudo-gate structure 150 is a strip structure, and the pseudo-gate structure 150 extends along the first direction.

[0109] Continue to refer to Figure 9 Source / drain doped layers 160 are formed in the channel stack 20 on both sides of the pseudo-gate structure 150.

[0110] When the device is operating, the source / drain doped layer 160 is used to provide a carrier source. Moreover, in this embodiment, the material of the source / drain doped layer 160 includes a stress layer, which can provide stress to the channel when the device is operating, thereby improving the carrier mobility of the MOS device.

[0111] As an example, the first sub-device region is used to form an NMOS device, and the source / drain doped layer 160 of the first sub-device region includes a stress layer doped with N-type ions, the material of which is silicon; the second sub-device region is used to form a PMOS device, and the source / drain doped layer 160 of the second sub-device region includes a stress layer doped with P-type ions, the material of which is Si or SiGe.

[0112] It should be noted that, as an example, after forming the dummy gate structure 150 and before forming the source / drain doped layer 160, the method for forming the semiconductor structure further includes: removing the stacked structure 200 exposed by the dummy gate structure 150; forming an insulating layer 145 on the substrate 100 exposed by the dummy gate structure 200, the first dielectric wall, and the second dielectric wall, thereby exposing the channel stacked layer 40.

[0113] The insulating layer 145 is used to achieve isolation between adjacent protrusions 105.

[0114] In this embodiment, the insulating layer 145 is made of silicon oxide. In other embodiments, the insulating layer may also be made of other insulating materials such as silicon nitride or silicon oxynitride.

[0115] As an example, the steps of forming insulating layer 145 include: filling an insulating material layer (not shown) on substrate 100 exposed by the dummy gate structure; etching back the insulating material layer above substrate 100, with the remaining insulating material layer used as insulating layer 145.

[0116] As an example, a flow-through chemical vapor deposition process is used to form an insulating material layer.

[0117] As one embodiment, the bottom surface of the insulating layer 145 is in contact with the substrate 100, that is, the insulating layer 145 is relatively deep, which is beneficial to improving the isolation effect between adjacent protrusions 105.

[0118] Accordingly, the source / drain doped layer 160 is located on the insulating layer 145 on both sides of the gate structure 180 and is in contact with the end of the channel layer 40. Therefore, the source / drain doped layer 160 is isolated from the substrate 100 by the insulating layer 145, which helps to reduce the leakage current of the device.

[0119] It should also be noted that, in this embodiment, the method for forming the semiconductor structure further includes: after forming the source / drain doped layer 160 and before removing the dummy gate structure 150, forming an interlayer dielectric layer (not shown) on the substrate 100 on the side of the dummy gate structure 150, covering the source / drain doped layer 160 and exposing the top of the dummy gate structure 150.

[0120] Specifically, the interlayer dielectric layer is formed on the insulating layer 145.

[0121] The interlayer dielectric layer is used to isolate adjacent dummy gate structures 150. After the dummy gate structures 150 and sacrificial layer 130 are subsequently removed to form the gate structure, the interlayer dielectric layer is also used to isolate adjacent gate structures.

[0122] The material of the interlayer dielectric layer is an insulating dielectric material. As an example, the material of the interlayer dielectric layer is silicon oxide.

[0123] refer to Figure 10 Remove the dummy gate structure 150 to form a gate opening (not shown); remove the sacrificial layer 130 through the gate opening to form a through trench (not shown), which is connected to the gate opening; form a gate structure 180 in the through trench and the gate opening.

[0124] Gate openings are used to provide space for the subsequent formation of the gate structure.

[0125] Furthermore, after removing the dummy gate structure 150, the gate opening exposes the channel stack 20 so that the sacrificial layer 130 can be removed subsequently through the channel stack 20 exposed by the gate opening.

[0126] Specifically, the process for removing the pseudo-gate structure 150 includes one or both of dry etching and wet etching.

[0127] In this embodiment, during the step of removing the dummy gate structure 150, a gate opening is formed in the interlayer dielectric layer.

[0128] The through-slot and gate opening provide space for forming the gate structure. The through-slot and gate opening are connected.

[0129] In this embodiment, after the through-slot is formed, along the extension direction of the channel layer (i.e., the second direction), the two ends of the channel layer 140 are connected to the source / drain doped layer 160 and suspended in the gate opening so that the subsequent gate structure can surround the channel layer 140.

[0130] After removing the sacrificial layer 130, one or more channel layers 140 are sequentially suspended at intervals. The one or more channel layers 140 suspended at intervals are used to form the channel structure layer 40. The channel structure layer 40 is located on the protrusion 105 and is suspended at intervals from the protrusion 105.

[0131] When the device is in operation, the gate structure 180 is used to control the opening or closing of the conductive channel of the MOS transistor.

[0132] As an example, the gate structure 180 is a metal gate structure, including a high-k gate dielectric layer (not shown) located at the bottom and sidewalls of the gate opening, and a channel layer 140 surrounding the first dielectric wall 110 and the second dielectric wall 120, a work function layer (not shown) located on the high-k gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the gate opening and the through-hole.

[0133] The high-k gate dielectric layer is used to electrically isolate the channel layer 140 from the work function layer, and to isolate the protrusion 105 from the work function layer. In this embodiment, the material of the high-k gate dielectric layer includes a high-k dielectric material, such as HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0134] The work function layer is used to adjust the work function of the MOS device. In this embodiment, when forming a PMOS transistor, the material of the work function layer is a P-type work function material, including one or more of Ta, TiN, TaN, TaSiN, and TiSiN; when forming an NMOS transistor, the material of the work function layer is an N-type work function material, including one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN.

[0135] The gate electrode layer serves as an electrode to achieve electrical connection between the gate structure 180 and external circuits or other interconnect structures. Materials for the gate electrode layer include W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

[0136] Reference Figure 11 ,in, Figure 11(a), (b), and (c) show top views of a conventional nanosheet transistor, a conventional forksheet transistor, and the semiconductor structure formed in this embodiment, respectively.

[0137] Depend on Figure 11 It is known that traditional fork-gate transistors can save about 30% of the area compared to traditional nanowire transistors, while the semiconductor structure formed in this embodiment can save about 20% of the area compared to traditional fork-gate transistors. Therefore, this embodiment is conducive to further reducing the area of ​​the device and improving the integration of the device.

[0138] Reference Figure 12 The diagram shows top views of two semiconductor structures, in which... Figure 12 In (a) and 12(b), the second sub-device region ii has different area sizes. In this embodiment, the width of the sub-device region (e.g., w1 and w2) can be adjusted by adjusting the width of the second dielectric wall 120 (e.g., d1 or d2), thereby enabling the sub-device regions within the device unit region 100s to have diverse widths and improving the freedom of device size design.

[0139] Specifically, in conjunction with reference Figure 12 , Figure 12 (a) The width of the first sub-device area i is w0, the width of the second sub-device area ii is w1, w0 and w1 are the same size, and the distance between adjacent device unit areas 100s is d1. Figure 12 In (b), the width of the first sub-device area i is w0, the width of the second sub-device area ii is w2, w0 and w2 are different in size, and the distance between adjacent device unit areas 100s is d2, d2 and d1 are different in size.

[0140] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple device unit regions, each device unit region including a sub-device region and an isolation region located between the sub-device regions, the sub-device regions and the isolation regions being arranged along a first direction, and a second direction being parallel to the substrate and perpendicular to the first direction; A first dielectric wall is disposed on the substrate of the isolation region, and the first dielectric wall extends along a second direction; A stacked structure is located on the substrate of the sub-device region, the stacked structure extends along a second direction, and the stacked structures of adjacent sub-device regions are isolated by the first dielectric wall; The stacked structure includes: a protrusion; and one or more channel layers that are suspended at intervals on the protrusion. The second dielectric wall is located on the substrate between adjacent device cell regions, and the second dielectric wall isolates the stacked structure of the adjacent device cell regions; A gate structure, a stacked structure spanning the sub-device regions, wherein the gate structure of each sub-device region surrounds the channel layer exposed by the first and second dielectric walls. The source and drain doped layers are located on both sides of the gate structure and are in contact with the ends of the channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the second dielectric wall is the same as that of the first dielectric wall.

3. The semiconductor structure as described in claim 1, characterized in that, The top surface of the stacked structure and the second dielectric wall is flush with the top surface of the first dielectric wall.

4. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride. The material of the second dielectric wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon carbonitride.

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped layer.

6. The semiconductor structure as described in claim 1, characterized in that, The device unit region includes a first sub-device region and a second sub-device region. The first sub-device region is used to form a first type MOS device, and the second sub-device region is used to form a second type MOS device. The first type MOS device and the second type MOS device have different channel conductivity types.

7. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an insulating layer located within the protrusions on both sides of the gate structure, and the insulating layer exposing the one or more spaced-apart channel layers; the source / drain doped layers are located on the insulating layers on both sides of the gate structure and are in contact with the ends of the channel layers.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a plurality of device unit regions, each device unit region including a sub-device region and an isolation region located between the sub-device regions, the sub-device regions and the isolation regions being arranged along a first direction, and a second direction being parallel to the substrate and perpendicular to the first direction; A stacked structure located in the sub-device region, a first dielectric wall located in the isolation region, and a second dielectric wall located between adjacent device cell regions are formed on the substrate. The stacked structure extends along a second direction, and the stacked structures of adjacent sub-device regions within the device cell region are isolated by the first dielectric wall, and the stacked structures of adjacent device cell regions are isolated by the second dielectric wall. The stacked structure includes a protrusion and one or more channel stacks located on the protrusion, and each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer. A pseudo-gate structure is formed that spans the stacked structure, the first dielectric wall, and the second dielectric wall; Source and drain doped layers are formed in the channel stack on both sides of the pseudo-gate structure; Remove the pseudo-gate structure to form a gate opening; Through the gate opening, the sacrificial layer is removed to form a through trench, which is connected to the gate opening; A gate structure is formed in the through slot and the gate opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The steps of forming the stacked structure, the first dielectric wall, and the second dielectric wall include: forming a stacked structure located in the sub-device region and a first dielectric wall located in the isolation region on the substrate; after forming the stacked structure and the first dielectric wall, forming a second dielectric wall on the substrate between adjacent device cell regions, the second dielectric wall isolating the stacked structure of adjacent device cell regions.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming a stacked structure located in the sub-device region and a first dielectric wall located in the isolation region on the substrate includes: forming a first dielectric wall discrete on the substrate of the isolation region, the first dielectric wall extending along a second direction; A stacked structure is formed on the substrate of the sub-device region, and the stacked structures of adjacent sub-device regions are isolated by the first dielectric wall.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of forming the first dielectric wall includes: forming a first dielectric material layer on the substrate; Remove the first dielectric material layer on the substrate located between the sub-device region and the adjacent device unit region, and retain the first dielectric material layer located on the isolation region as a first dielectric wall.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of removing the first dielectric material layer on the substrate located between the sub-device region and the adjacent device unit region, and retaining the first dielectric material layer located on the isolation region as the first dielectric wall includes: patterning the first dielectric material layer to form an initial dielectric layer; performing sidewall thinning on the initial dielectric layer along a direction parallel to the substrate, and using the remaining initial dielectric layer as the first dielectric wall.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming a stacked structure located in the sub-device region and a first dielectric wall located in the isolation region on the substrate includes: forming a stacked structure discrete on the substrate of the sub-device region; and forming a first dielectric wall located between adjacent stacked structures in the isolation region.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of forming the stacked structure includes: forming an initial stacked structure on a substrate exposed by the first dielectric wall, the initial stacked structure including a raised material layer and one or more initial channel stacks located on the raised material layer; The initial stacked structure on the substrate located between adjacent device unit regions is removed, and the remaining initial stacked structure on the substrate of the sub-device region is used as the stacked structure.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the second dielectric wall includes: filling a second dielectric material layer in the region enclosed between the stacked structure of adjacent device cell regions and the substrate, the second dielectric material layer also being formed on top of the stacked structure and the first dielectric wall; removing the second dielectric material layer above the top of the stacked structure, the remaining second dielectric material layer located between adjacent device cell regions being used as the second dielectric wall.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process for forming the second dielectric material layer includes flow chemical vapor deposition.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process for removing the second dielectric material layer above the top of the stacked structure includes a chemical mechanical planarization process.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the semiconductor structure further includes: after forming the source / drain doped layer and before removing the dummy gate structure, forming an interlayer dielectric layer on the substrate on the side of the dummy gate structure, covering the source / drain doped layer and exposing the top of the dummy gate structure. In the step of removing the dummy gate structure, a gate opening is formed in the interlayer dielectric layer.

19. The method for forming a semiconductor structure as described in claim 8, characterized in that, The device unit region includes a first sub-device region and a second sub-device region. The first sub-device region is used to form a first type MOS device, and the second sub-device region is used to form a second type MOS device. The first type MOS device and the second type MOS device have different channel conductivity types.

20. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming the dummy gate structure and before forming the source / drain doped layers, the method for forming the semiconductor structure further includes: removing the stacked structure exposed by the dummy gate structure; forming an insulating layer on the substrate exposed by the dummy gate structure, the first dielectric wall, and the second dielectric wall, thereby exposing the channel stacked layer.

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