Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, including a substrate and a channel structure protruding from the substrate, and further including an isolation layer on the substrate, the channel structure including a channel region; forming a first trench through the isolation layer and extending into the substrate between adjacent channel structures; forming a buried power rail in a partial height of the first trench, leaving a remaining first trench as a second trench; forming a sacrificial layer on sidewalls of the second trench; forming source / drain doped layers on the channel structure on both sides of the channel region; forming a dielectric layer covering the isolation layer, the source / drain doped layers and the sacrificial layer; forming a third trench in the dielectric layer to expose a source / drain doped layer of an adjacent source / drain doped layer on a same side of the buried power rail as the sacrificial layer; removing the sacrificial layer through the third trench to form a fourth trench exposing the buried power rail; filling the fourth trench to form a power rail contact plug; and filling the third trench to form a source / drain conductive layer. The present application improves the reliability of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] Modern integrated circuits comprise transistors, capacitors, and other devices formed on a semiconductor substrate. These devices are initially isolated from each other on the substrate and then interconnected via interconnect structures to form a functional circuit. Typical interconnect structures include lateral interconnect structures (e.g., metal interconnects) and vertical interconnect structures (e.g., through-hole interconnects and contacts).

[0004] A buried power rail (BPR) is an interconnect structure embedded in a substrate. The BPR is formed during the front end of line (FEOL) process and supplies power to the integrated circuit. Specifically, the BPR can be used as either a Vdd or Vss power line. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the reliability of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, including a substrate and a channel structure protruding from the substrate; the substrate further including an isolation layer on the substrate; the channel structure including a channel region along its extension direction; the isolation layer covering a portion of the sidewalls of the channel structure in the channel region; and the top surface of the isolation layer being lower than the top surface of the channel structure; a buried power rail located between adjacent channel structures; a portion of the buried power rail extending vertically downward into the substrate and lower than the bottom of the channel structure; and a portion of the buried power rail extending vertically upward into the isolation layer and lower than the top surface of the channel structure; and a gate structure. A transverse channel structure; sidewalls covering the sidewalls of the gate structure; source / drain doped layers located on the channel structure on both sides of the channel region with the bottom of the source / drain doped layers embedded in the end of the channel structure; a dielectric layer located on the isolation layer and covering the source / drain doped layers; a source / drain conductive layer located in the dielectric layer on top of the source / drain doped layers and electrically connected to the source / drain doped layers; and a power rail contact plug located in the isolation layer between the source / drain conductive layer and the buried power rail, electrically connecting the source / drain conductive layer and the buried power rail, with the power rail contact plug close to the sidewall of the buried power rail facing the source / drain doped layer connected to the source / drain conductive layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a channel structure protruding from the substrate, the substrate further including an isolation layer located on the substrate, the channel structure including a channel region along its extension direction, the isolation layer covering the sidewalls of the channel structure of the channel region; forming a first trench between adjacent channel structures, penetrating the isolation layer and extending into the substrate; forming a buried power rail in a portion of the height of the first trench, retaining the remaining first trench as a second trench; forming a sacrificial layer on the sidewalls of the second trench; after forming the sacrificial layer, forming source / drain doped layers on the channel structures on both sides of the channel region; forming a dielectric layer covering the isolation layer, the source / drain doped layers and the sacrificial layer; forming a third trench in the dielectric layer exposing the source / drain doped layers in adjacent source / drain doped layers located on the same side as the sacrificial layer on the buried power rail, the third trench spanning the channel structure and extending to expose the top of the sacrificial layer; removing the sacrificial layer through the third trench to form a fourth trench exposing the buried power rail; filling the fourth trench to form a power rail contact plug; filling the third trench to form a source / drain conductive layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, the power rail contact plug is located near the sidewall of the source / drain doped layer in the buried power rail that is connected to the source / drain conductive layer. This allows for a larger spacing between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer. This increases the process window for forming the power rail contact plug, reduces the probability of bridging between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer, and thus improves the reliability of the semiconductor structure.

[0010] In the formation method provided by this embodiment of the invention, a sacrificial layer is formed on the sidewall of the second trench. After the sacrificial layer is formed, source / drain doped layers are formed on the channel structure on both sides of the channel region. A dielectric layer covering the isolation layer, source / drain doped layer, and sacrificial layer is formed. A third trench is formed in the dielectric layer, exposing the source / drain doped layer in the adjacent source / drain doped layer located on the same side of the buried power rail as the sacrificial layer. The third trench spans the channel structure and extends to expose the top of the sacrificial layer. The sacrificial layer is removed through the third trench, forming a fourth trench exposing the buried power rail. The fourth trench is filled to form a power rail contact plug, and the third trench is filled to form a source / drain conductive layer. This embodiment of the invention uses a sacrificial layer for pre-positioning. By flexibly selecting the material of the sacrificial layer, the subsequent removal of the sacrificial layer is made easier, thereby reducing the difficulty of forming the fourth trench and correspondingly facilitating the formation of the power rail contact plug. Moreover, the buried power rail is made easier to form a fourth trench. The remaining first trench exposed by the power rail serves as the second trench, and a sacrificial layer is formed on the sidewall of the second trench. The formation position of the sacrificial layer is defined by the sidewall of the second trench, thus the positional accuracy of the sacrificial layer relative to the buried power rail is higher. The third trench exposes the source / drain doped layer in the adjacent source / drain doped layer that is located on the same side of the buried power rail as the sacrificial layer. In the two opposite sidewalls of the buried power rail, it is easier to make the power rail contact plug closer to the sidewall of the source / drain doped layer in the buried power rail that is connected to the source / drain conductive layer. This is beneficial to make the spacing between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer larger, thereby increasing the process window for forming the power rail contact plug, reducing the probability of bridging between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer, and thus improving the reliability of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 4 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] The reliability of semiconductor structures currently needs improvement. This paper analyzes the reasons why the reliability of a semiconductor structure needs to be improved, using a specific semiconductor structure formation method as an example.

[0015] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate 10 is provided, including a substrate 11 and a channel structure 12 protruding from the substrate 11. The substrate 10 also includes an isolation layer 13 located on the substrate 11. The channel structure 12 includes a channel region (not shown) along its extension direction. The isolation layer 13 covers a portion of the sidewalls of the channel structure 12 covering the channel region. Buried power rails 21 are formed in the substrate 11 between adjacent channel structures 12 and in the isolation layer 13 of a certain thickness. Source and drain doped layers 40 are formed on the channel structures 12 on both sides of the channel region. A dielectric layer 50 covering the source and drain doped layers 40 is formed on the isolation layer 13.

[0017] refer to Figure 2 A trench is formed in the isolation layer 13 and dielectric layer 50 at the top of the buried power rail 21, including a first trench exposing any source or drain doped layer 40, and a second trench communicating with the first trench and penetrating the isolation layer 13 at the top of the buried power rail 21; the second trench and the second trench are filled to form a power rail contact plug 62 located in the second trench and a source or drain conductive layer 61 located in the first trench.

[0018] In the step of forming trenches in the isolation layer 13 and dielectric layer 50 on top of the buried power rail 21, a double damask process is usually used to etch the trenches. Since the size of the second trench is small, it is more difficult to form the second trench. At the same time, the accuracy of defining the formation position of the second trench is poor. Moreover, when etching the isolation layer 13 to form the second trench, due to the offset of the formation position or etching error, it is easy to cause the second trench to have too small a distance from the unexposed source and drain doped layer 40 in the adjacent source and drain doped layer 40. As a result, after the power rail contact plug 62 is formed, it is easy to cause the power rail contact plug 62 to bridge with the unexposed source and drain doped layer 40, thereby affecting the reliability of the semiconductor structure.

[0019] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a channel structure protruding from the substrate, the substrate further including an isolation layer located on the substrate, the channel structure including a channel region along its extension direction, the isolation layer covering the sidewalls of the channel structure of the channel region; forming a first trench between adjacent channel structures, penetrating the isolation layer and extending into the substrate; forming a buried power rail in a portion of the height of the first trench, retaining the remaining first trench as a second trench; forming a sacrificial layer on the sidewalls of the second trench; after forming the sacrificial layer, forming source / drain doped layers on the channel structures on both sides of the channel region; forming a dielectric layer covering the isolation layer, the source / drain doped layers, and the sacrificial layer; forming a third trench in the dielectric layer exposing a source / drain doped layer in an adjacent source / drain doped layer located on the same side as the sacrificial layer on the buried power rail, the third trench spanning the channel structure and extending to expose the top of the sacrificial layer; removing the sacrificial layer through the third trench to form a fourth trench exposing the buried power rail; filling the fourth trench to form a power rail contact plug; filling the third trench to form a source / drain conductive layer.

[0020] In this embodiment of the invention, a sacrificial layer is used for pre-positioning. By flexibly selecting the material of the sacrificial layer, it is easier to remove the sacrificial layer later, thereby reducing the difficulty of forming the fourth trench. This is conducive to the formation of the power rail contact plug. Moreover, the remaining first trench exposed by the buried power rail is used as the second trench, and a sacrificial layer is formed on the sidewall of the second trench. The formation position of the sacrificial layer is defined by the sidewall of the second trench, so the positional accuracy of the sacrificial layer relative to the buried power rail is higher. The third trench exposes the source / drain doped layer in the adjacent source / drain doped layer that is located on the same side of the buried power rail as the sacrificial layer. In this way, the power rail contact plug is more likely to be closer to the sidewall of the source / drain doped layer in the buried power rail that is connected to the source / drain conductive layer. This is beneficial to make the distance between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer larger, thereby increasing the process window for forming the power rail contact plug and reducing the probability of bridging between the power rail contact plug and the channel structure below the source / drain doped layer that is not connected to the source / drain conductive layer, thereby improving the reliability of the semiconductor structure.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figure 3 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0023] The semiconductor structure includes: a substrate 101, including a substrate 111 and a channel structure 121 protruding on the substrate 111; the substrate 101 also includes an isolation layer 131 on the substrate 111; the channel structure 121 includes a channel region (not shown) along its extension direction; the isolation layer 131 covers a portion of the sidewalls of the channel structure 121 covering the channel region; the top surface of the isolation layer 131 is lower than the top surface of the channel structure 121; a buried power rail 211 is located between adjacent channel structures 121; a portion of the buried power rail 211 extends vertically downward into the substrate 111 and is lower than the bottom of the channel structure 121; a portion of the buried power rail 211 extends vertically upward into the isolation layer 131 and is lower than the top surface of the channel structure 121; and a gate structure spanning the protruding channel structure. 121; sidewall, covering the sidewall of the gate structure; source / drain doped layer 401, located on the channel structure 121 on both sides of the channel region and with the bottom of the source / drain doped layer 401 embedded in the end of the channel structure 121; dielectric layer 501, located on the isolation layer 131 and covering the source / drain doped layer 401; source / drain conductive layer 611, located in the dielectric layer 501 on top of the source / drain doped layer 401 and electrically connected to the source / drain doped layer 401; power rail contact plug 621, located in the isolation layer 131 between the source / drain conductive layer 611 and the buried power rail 211 and electrically connected to the source / drain conductive layer 611 and the buried power rail 211, and the power rail contact plug 621 is close to the sidewall of the buried power rail 211 facing the source / drain doped layer 401 connected to the source / drain conductive layer 611.

[0024] Substrate 101 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include planar transistors, FinFETs, or gate-all-around (GAA) transistors.

[0025] The substrate 111 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0026] In this embodiment, the portion of the channel structure 121 covered by the gate structure is the channel region of the channel structure 121, and the channel structure 121 in the channel region is used to provide the channel for the transistor.

[0027] In this embodiment, the material of the channel structure 121 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel structure 121 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0028] In this embodiment, taking a finned field-effect transistor as an example, the channel structure 121 is a fin. The fin includes a bottom fin and a working fin located on the bottom fin. The isolation layer 131 covering part of the sidewall of the channel structure 121 in the channel region refers to the isolation layer 131 covering the sidewall of the bottom fin.

[0029] In other embodiments, the semiconductor structure may also be a fully enclosed gate transistor, the channel structure is a bottom fin and a channel stack located above the bottom fin, and the isolation layer covering part of the sidewall of the channel structure in the channel region refers to the isolation layer covering the sidewall of the bottom fin.

[0030] The isolation layer 131 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 131 is usually formed between NMOS transistors and PMOS transistors.

[0031] The material of the isolation layer 131 is an insulating material. As an example, the material of the isolation layer 131 is silicon oxide.

[0032] In this embodiment, the semiconductor structure further includes a gate structure (not shown) that spans the channel structure 121 and extends in a direction perpendicular to the channel structure 121, the gate structure covering the top and part of the sidewalls of the channel structure 121 in the channel region.

[0033] In this embodiment, the gate structure is a device gate structure, which is used to control the opening or closing of the transistor channel.

[0034] In this embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0035] The gate dielectric layer is used to isolate the gate electrode layer and the channel structure. In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0036] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel structure. Specifically, the material of the gate oxide layer can be silicon oxide.

[0037] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0038] In this embodiment, the gate structure is a metal gate structure.

[0039] Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0040] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0041] The buried power rail (BPR) 211 is used to realize the electrical connection of the source and drain conductive layers 611 and to apply the corresponding voltage to the source and drain conductive layers 611. The buried power rail 211 includes embedded power wiring (VDD) and embedded ground wiring (VSS).

[0042] In this embodiment, the buried power rail 211 is located in the substrate 111 and in a partial thickness of the isolation layer 131, thereby burying the buried power rail 211 in the substrate 101. This provides a better isolation effect between the buried power rail 211 and other film layers above it. Furthermore, the top of the buried power rail 211 is lower than the top of the isolation layer 131, providing space for the power rail contact plug 621 located on top of the buried power rail 211. This reduces the probability of damage to the top of the buried power rail 211 in subsequent manufacturing processes, thereby improving the performance of the semiconductor structure.

[0043] In this embodiment, the embedded power rail 211 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the embedded power rail 211, thereby reducing power consumption. In other embodiments, the embedded power rail can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0044] The source / drain doped layer 401 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 401 is the same as the channel conductivity type of the corresponding transistor.

[0045] Specifically, the source and drain doped layers 401 are located on the channel structures 121 on both sides of the gate structure.

[0046] The dielectric layer 501 serves as an isolation layer between adjacent devices and also provides a process platform for the formation of the source-drain conductive layer 611.

[0047] The dielectric layer 501 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0048] The source / drain conductive layer 611 is used to electrically connect the buried power rail 211 and the source / drain doped layer 401, and to apply voltage to the source / drain doped layer 401.

[0049] In this embodiment, the material of the source / drain conductive layer 611 includes tungsten, ruthenium, or molybdenum.

[0050] Tungsten, ruthenium, or molybdenum are metallic materials with good electrical conductivity, which is beneficial for achieving a better electrical connection between the source / drain doped layer 401 and the source / drain conductive layer 611.

[0051] The power rail contact plug 621 is used to electrically connect the source drain conductive layer 611 and the embedded power rail 211.

[0052] In this embodiment, the power rail contact plug 621 is close to the sidewall of the source / drain doped layer 401 in the buried power rail 211 that is connected to the source / drain conductive layer 401. Therefore, in the source / drain doped layer 401 adjacent to the power rail contact plug 621, it is beneficial to have a larger spacing between the power rail contact plug 621 and the channel structure 121 below the source / drain doped layer 401 that is not connected to the source / drain conductive layer 611. This helps to increase the process window for forming the power rail contact plug 621, reduce the probability of bridging between the power rail contact plug 621 and the channel structure 121 below the source / drain doped layer 401 that is not connected to the source / drain conductive layer 611, and thus improve the reliability of the semiconductor structure.

[0053] It should be noted that the width of the power rail contact plug 621 along the extension direction perpendicular to the channel structure 121 should not be too large or too small. If the width of the power rail contact plug 621 is too large, the distance between the power rail contact plug 621 and the adjacent channel structure 121 may be too small, thereby increasing the probability of bridging between the power rail contact plug 621 and the adjacent channel structure 121 and affecting the reliability of the semiconductor structure. If the width of the power rail contact plug 621 is too small, it may increase the difficulty of forming the power rail contact plug 621, affecting the formation of the semiconductor structure, and may also affect the conductivity of the power rail contact plug 621, affecting the electrical connection performance of the power rail contact plug to the source / drain conductive layer 611 and the embedded power rail 211, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the width of the power rail contact plug 621 along the extension direction perpendicular to the channel structure 121 is 8 nm to 14 nm.

[0054] In this embodiment, the material of the power rail contact plug 621 includes tungsten, ruthenium, or molybdenum.

[0055] Tungsten, ruthenium, or molybdenum are metallic materials with good electrical conductivity, which facilitates better electrical connection between the power rail contact plug 621 and the source / drain conductive layer 611, as well as between the power rail contact plug 621 and the embedded power rail 211.

[0056] It should be noted that in this embodiment, the power rail contact plug 621 and the source / drain conductive layer 611 are formed in the same step, so that the power rail contact plug 621 and the source / drain conductive layer 611 are made of the same material.

[0057] In this embodiment, the semiconductor structure further includes a sacrificial layer 311 located in the isolation layer 131 on top of the buried power rail 211. The sidewall of the sacrificial layer 311 is disposed opposite to the sidewall of the power rail contact plug 621. Along the extension direction perpendicular to the channel structure 121, the width of the power rail contact plug 621 is equal to the width of the sacrificial layer 311.

[0058] In this embodiment, the power rail contact plug 621 is formed by using a sacrificial layer 311 as a spacer for the power rail contact plug 621.

[0059] Specifically, in this embodiment, the method for forming the semiconductor structure includes: forming a first trench between adjacent channel structures 121 that penetrates the isolation layer 131 and extends into the substrate 111; forming a buried power rail 211 in a portion of the height of the first trench, and retaining the remaining first trench as a second trench; forming a sacrificial layer 311 on the sidewall of the second trench; removing the sacrificial layer 311 on the same side as the source / drain doped layer 401 that needs to be electrically connected; and forming a power rail contact plug 621 at the location of the removed sacrificial layer 311.

[0060] In this embodiment, a sacrificial layer 311 is used for pre-positioning. By flexibly selecting the material of the sacrificial layer 311, it is easy to remove the sacrificial layer 311, thereby reducing the difficulty of forming the power rail contact plug 621 and thus facilitating the formation of the power rail contact plug 621. Moreover, the remaining first groove exposed by the embedded power rail 211 is used as the second groove, and the sacrificial layer 311 is formed on the sidewall of the second groove. The formation position of the sacrificial layer 311 is defined by the sidewall of the second groove, so the positional accuracy of the sacrificial layer 311 relative to the embedded power rail 211 is higher.

[0061] Specifically, in this embodiment, the step of forming a sacrificial layer 311 on the sidewall of the second trench includes: forming a sacrificial material layer covering the top of the embedded power rail 211, the sidewall of the second trench, and the top of the isolation layer 131, with the sacrificial material layer located on the sidewall of the second trench serving as the sacrificial layer 311; removing the sacrificial material layer covering the top of the embedded power rail 211 and the top of the isolation layer 131, and retaining the sacrificial layer 311.

[0062] Therefore, in this embodiment, two sidewalls of the second trench are formed with sacrificial layers 311 of equal width, and one of the sacrificial layers 311 is subsequently replaced by a power rail contact plug 621. Thus, in this embodiment, the sacrificial layer 311 is located in the isolation layer 131 at the top of the embedded power rail 211, and the sidewall of the sacrificial layer 311 is disposed opposite to the sidewall of the power rail contact plug 621. Along the extension direction perpendicular to the trench structure 121, the width of the power rail contact plug 621 is equal to the width of the sacrificial layer 311.

[0063] In this embodiment, an embedded power rail 211 is formed in a first trench of a certain height, and the remaining first trench is retained as a second trench. A sacrificial layer 311 is formed on both sidewalls of the second trench. In the two sacrificial layers 311, the sidewalls facing away from each other are flush with the sidewalls of the embedded power rail 211. One of the sacrificial layers 311 is subsequently replaced by a power rail contact plug 621, so that the sidewall of the power rail contact plug 621 facing away from the sacrificial layer 311 is flush with the sidewall of the embedded power rail 211, and the sidewall of the sacrificial layer 311 facing away from the power rail contact plug 621 is flush with the sidewall of the embedded power rail 211.

[0064] In this embodiment, the sacrificial layer 311 and the isolation layer 131 need to have an etching selectivity ratio, so as to reduce the damage to the isolation layer 131 during the removal of the sacrificial layer 311. Therefore, in this embodiment, the material of the sacrificial layer 311 includes silicon oxycarbide, amorphous silicon, silicon nitride or silicon carbide.

[0065] In this embodiment, the semiconductor structure further includes an isolation layer 331, which is located in the isolation layer 131 on top of the buried power rail 211. The isolation layer 331 is located between the sacrificial layer 311 and the power rail contact plug 621.

[0066] The isolation layer 331 is used to isolate the sacrificial layer 311 on the two sidewalls of the second trench, which is beneficial to the subsequent removal of the corresponding sacrificial layer 311. Moreover, after the power rail contact plug 621 is formed, when the sacrificial layer 311 disposed opposite to the power rail contact plug 621 is also used to form other interconnect structures, the isolation layer 331 can also be used to isolate the power rail contact plug 621 from other interconnect structures.

[0067] In this embodiment, the material of the insulating layer 331 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride, which makes the insulating layer 331 have a better isolation effect and can select a material with an etching selectivity ratio to the sacrificial layer 311, thereby reducing damage to the insulating layer 331 during the removal of the sacrificial layer 311.

[0068] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure.

[0069] Figures 4 to 14This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0070] refer to Figure 4 A substrate 100 is provided, including a substrate 110 and a channel structure 120 protruding from the substrate 110. The substrate 100 also includes an isolation layer 130 located on the substrate 110. The channel structure 120 includes a channel region (not shown) along its extension direction. The isolation layer 130 covers the sidewalls of the channel structure 120 of the channel region.

[0071] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include planar transistors, fin field-effect transistors, or fully enclosed gate transistors.

[0072] The substrate 110 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0073] In this embodiment, the portion of the channel structure 120 covered by the gate structure is the channel region of the channel structure 120, and the channel structure 120 in the channel region is used to provide the channel for the transistor.

[0074] In this embodiment, the material of the channel structure 120 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel structure 120 is silicon. In other embodiments, the material of the channel structure is determined according to the type and performance of the transistor.

[0075] In this embodiment, taking a finned field-effect transistor as an example, the channel structure 120 is a fin. The fin includes a bottom fin and a working fin located on the bottom fin. The isolation layer 130 covering the sidewall of the channel structure 120 in the channel region means that the isolation layer 130 covers the sidewall of the fin.

[0076] In other embodiments, the semiconductor structure may also be a fully enclosed gate transistor, the channel structure is a bottom fin and a channel stack located above the bottom fin, and the isolation layer covering the sidewalls of the channel structure in the channel region means that the isolation layer covers the sidewalls of the bottom fin and the channel stack.

[0077] The isolation layer 130 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 130 is usually formed between NMOS transistors and PMOS transistors.

[0078] The material of the insulating layer 130 is an insulating material. As an example, the material of the insulating layer 130 is silicon oxide.

[0079] In this embodiment, the semiconductor structure further includes a gate structure (not shown) that spans the channel structure 120 and extends in a direction perpendicular to the channel structure 120, the gate structure covering the top and part of the sidewalls of the channel structure 120 in the channel region.

[0080] In this embodiment, the gate structure is a device gate structure, which is used to control the opening or closing of the transistor channel.

[0081] In this embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0082] The gate dielectric layer is used to isolate the gate electrode layer and the channel structure. In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0083] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel structure. Specifically, the material of the gate oxide layer can be silicon oxide.

[0084] In this embodiment, the gate electrode layer is made of one or more of the following materials: TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0085] In this embodiment, the gate structure is a metal gate structure.

[0086] Therefore, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0087] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0088] refer to Figure 5 A first trench 140 is formed between adjacent channel structures 120, penetrating the isolation layer 130 and extending into the substrate 110.

[0089] The first trench 140 is used to provide space for the subsequent formation of the embedded power rail, and also to provide positioning for the subsequent formation of the sacrificial layer.

[0090] In this embodiment, an anisotropic etching process is used to form the first trench 140.

[0091] Specifically, the first trench 140 is formed by an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and the etching is more directional, which is beneficial to improving the opening size accuracy of the first trench 140.

[0092] Reference Figure 6 and Figure 7 An embedded power rail 210 is formed in a first groove 140 at a certain height, and the remaining first groove 140 is retained as a second groove 150.

[0093] The embedded power rail 210 is used to realize the electrical connection of the subsequent source and drain conductive layers and to apply the corresponding voltage to the source and drain conductive layers. The embedded power rail 210 includes embedded power wiring (VDD) and embedded ground wiring (VSS).

[0094] In this embodiment, the buried power rail 210 is located in the substrate 110 and within a partial thickness of the isolation layer 130, thereby burying the buried power rail 210 in the substrate 100. This provides better isolation between the buried power rail 210 and other film layers above it. Furthermore, the top of the buried power rail 210 is lower than the top of the isolation layer 130, providing space for the power rail contact plug subsequently formed on top of the buried power rail 210. This reduces the probability of damage to the top of the buried power rail 210 during subsequent manufacturing processes, thereby improving the performance of the semiconductor structure.

[0095] In this embodiment, the embedded power rail 210 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the embedded power rail 210, thereby reducing power consumption. In other embodiments, the embedded power rail can also be made of conductive materials such as cobalt, ruthenium, or nickel.

[0096] The second trench 150 is used to position and provide spatial location for the formation of the subsequent sacrificial layer.

[0097] Specifically, in this embodiment, the step of forming the embedded power rail 210 in the first trench 140 of a certain height includes: referring to Figure 6 The first trench 140 is filled to form a pre-embedded power supply material layer 200.

[0098] The embedded power material layer 200 is used to form the embedded power rail 210.

[0099] Accordingly, in this embodiment, the material of the embedded power supply material layer 200 is tungsten.

[0100] refer to Figure 7 Remove part of the thickness of the embedded power material layer 200, and retain the remaining height of the embedded power material layer 200 in the first trench 140 as the embedded power rail 210.

[0101] In this embodiment, by first forming the embedded power material layer 200 and then removing part of the thickness of the embedded power material layer 200, it is beneficial to control the thickness of the removed embedded power material layer 200 and obtain an embedded power rail 210 with a thickness that meets the process requirements.

[0102] In this embodiment, an anisotropic etching process is used to remove a portion of the thickness of the embedded power material layer 200.

[0103] Specifically, an anisotropic dry etching process is used to remove a portion of the thickness of the embedded power material layer 200. The process parameters of the anisotropic etching process are easy to control, which is beneficial for controlling the etching amount and improving the thickness accuracy of the removed embedded power material layer 200. This, in turn, helps to improve the dimensional accuracy of the embedded power rail 210. Moreover, the anisotropic dry etching process has the characteristics of anisotropic etching, making the etching more directional, which is beneficial for improving the opening size accuracy of the second trench 150.

[0104] Reference Figure 8 and Figure 9 A sacrificial layer 310 is formed on the sidewall of the second trench 150.

[0105] The sacrificial layer 310 is used to occupy space for the subsequent formation of the power rail contact plug.

[0106] In this embodiment, a sacrificial layer 310 is used for pre-positioning. By flexibly selecting the material of the sacrificial layer 310, the sacrificial layer 310 is easy to remove, thereby reducing the difficulty of forming the power rail contact plug.

[0107] It should be noted that in the step of forming the sacrificial layer 310 on the sidewall of the second trench 150, the width of the sacrificial layer 310 along the extension direction perpendicular to the channel structure 120 should not be too large or too small. If the width of the sacrificial layer 310 along the extension direction perpendicular to the channel structure 120 is too large, the width of the subsequently formed power rail contact plug will be too large, which may easily lead to the spacing between the power rail contact plug and the adjacent channel structure 120 being too small, thereby easily increasing the probability of bridging between the power rail contact plug and the adjacent channel structure 120, affecting the reliability of the semiconductor structure. If the width of the sacrificial layer 310 along the extension direction perpendicular to the channel structure 120 is too small, it may easily increase the difficulty of forming the sacrificial layer 310, correspondingly increasing the process difficulty of forming the power rail contact plug, affecting the formation of the semiconductor structure, and may also easily affect the conductivity of the power rail contact plug, affecting the electrical connection performance of the power rail contact plug to the source drain conductive layer and the buried power rail 210, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the width of the sacrificial layer 310 is 8 nm to 14 nm along the extension direction perpendicular to the channel structure 120.

[0108] In this embodiment, the sacrificial layer 310 and the isolation layer 130 need to have an etching selectivity ratio, so as to reduce the damage to the isolation layer 130 during the removal of the sacrificial layer 310. Therefore, in this embodiment, the material of the sacrificial layer 310 includes silicon oxycarbonate, amorphous silicon, silicon nitride or silicon carbide.

[0109] In this embodiment, in the step of forming a sacrificial layer 310 on the sidewall of the second trench 150, a sacrificial layer 310 is formed on both sidewalls of the second trench 150.

[0110] With sacrificial layers 310 formed on both sidewalls of the second trench 150, any source or drain doped layer on either side of the buried power rail 210 that needs to be electrically connected to the buried power rail 210 via a power rail contact plug can be formed by selecting the sacrificial layer 310 on the same side, which helps to improve the flexibility of power rail contact plug formation.

[0111] Specifically, in this embodiment, the step of forming a sacrificial layer 310 on the sidewall of the second trench 150 includes: referencing Figure 8 A sacrificial material layer 300 is formed covering the top of the embedded power rail 210, the sidewall of the second trench 150, and the top of the isolation layer 130. The sacrificial material layer 300 located on the sidewall of the second trench 150 serves as the sacrificial layer 310.

[0112] The sacrificial material layer 300 is used to form the sacrificial layer 310.

[0113] Accordingly, in this embodiment, the material of the sacrificial material layer 300 includes silicon oxycarbonate, amorphous silicon, silicon nitride, or silicon carbide.

[0114] In this embodiment, an atomic layer deposition process is used to form the sacrificial material layer 300.

[0115] The sacrificial material layer 300 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the sacrificial material layer 300 to cover the top of the embedded power rail 210, the sidewall of the second trench 150 and the top of the isolation layer 130 in good conformal manner, and also helps to make the thickness uniformity of the sacrificial layer 310 better.

[0116] refer to Figure 9 Remove the sacrificial material layer 300 covering the top of the embedded power rail 210 and the top of the isolation layer 130, and retain the sacrificial layer 310.

[0117] In this embodiment, an anisotropic etching process is used to remove the sacrificial material layer 300 covering the top of the embedded power rail 210 and the top of the isolation layer 130.

[0118] Specifically, the use of anisotropic dry etching process makes the etching more directional, which is beneficial to improving the sidewall quality and precision of the sacrificial layer 310. In addition, it is also beneficial to reduce damage to the embedded power rail 210 at the bottom of the sacrificial material layer 300.

[0119] Reference Figure 10 and Figure 11 After the sacrificial layer 310 is formed, before the source / drain doped layer is formed, the formation method further includes: forming an isolation layer 330 in the remaining space of the second trench 150.

[0120] The isolation layer 330 is used to isolate the sacrificial layer 310 on the two sidewalls of the second trench 150, which is beneficial to the subsequent removal of the corresponding sacrificial layer 310. Moreover, after the power rail contact plug is formed, when the sacrificial layer 310 disposed opposite to the power rail contact plug is also used to form other interconnection structures, the isolation layer 330 can also be used to isolate the power rail contact plug from other interconnection structures.

[0121] In this embodiment, the material of the insulating layer 330 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride, which makes the insulating layer 330 have a better isolation effect and allows the selection of materials with an etching selectivity ratio to the sacrificial layer 310, thereby reducing damage to the insulating layer 330 during the removal of the sacrificial layer 310.

[0122] Specifically, in this embodiment, the step of forming the insulating layer 330 includes: referencing Figure 10 This forms an insulating material layer 320 that fills the second trench 150 and covers the top of the insulating layer 130.

[0123] The insulating material layer 320 is used to form the insulating layer 330.

[0124] Accordingly, in this embodiment, the material of the insulating material layer 320 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0125] In this embodiment, an atomic layer deposition process is used to form the insulating material layer 320.

[0126] The insulating material layer 320 formed by atomic layer deposition has good thickness uniformity and good step coverage, which enables the insulating material layer 320 to fill the second trench 150 and cover the top of the isolation layer 130 well.

[0127] refer to Figure 11 Remove the insulating material layer 320 covering the top of the insulating layer 130, and retain the insulating material layer 320 filling the second trench 150 as the insulating layer 330.

[0128] In this embodiment, an anisotropic etching process is used to remove the insulating material layer 320 covering the top of the insulating layer 130.

[0129] Specifically, the use of anisotropic dry etching process makes the etching more directional, which is beneficial to improving the top quality and precision of the isolation layer 330. In addition, it is also beneficial to reduce damage to the isolation layer 130 and the channel structure 120 below the isolation material layer 320.

[0130] refer to Figure 12 After the sacrificial layer 310 is formed, source and drain doped layers 400 are formed on the channel structure 120 on both sides of the channel region.

[0131] The source / drain doped layer 400 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 400 is the same as the channel conductivity type of the corresponding transistor.

[0132] Specifically, in this embodiment, after forming the sacrificial layer 310 and before forming the source / drain doped layer 400, the forming method further includes: removing a portion of the thickness of the isolation layer 130 to expose a portion of the height of the channel structure 120.

[0133] A portion of the isolation layer 130 is removed to expose a portion of the channel structure 120, in preparation for the formation of the source / drain doped layer 400. Specifically, the source / drain doped layer 400 is formed in the exposed portion of the channel structure 120 on both sides of the channel region.

[0134] In this embodiment, taking a finned field-effect transistor as an example, the channel structure 120 is a fin. The fin includes a bottom fin and a working fin located on the bottom fin. A portion of the isolation layer 130 is removed to expose the working fin.

[0135] In other embodiments, the semiconductor structure may also be a fully enclosed gate transistor, the channel structure may be a bottom fin and a channel stack located above the bottom fin, and a partial thickness of the isolation layer may be removed to expose the channel stack.

[0136] Continue to refer to Figure 12 A dielectric layer 500 is formed covering the isolation layer 130, the source / drain doped layer 400, and the sacrificial layer 310.

[0137] The dielectric layer 500 serves as an isolation layer between adjacent devices and also provides a process platform for the subsequent formation of source and drain conductive layers.

[0138] In this embodiment, the dielectric layer 500 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0139] Continue to refer to Figure 12 A third trench 510 is formed in the dielectric layer 500 to expose the source / drain doped layer 400 in the adjacent source / drain doped layer 400, which is located on the same side of the sacrificial layer 310 as the buried power rail 210. The third trench 510 spans the channel structure 120 and extends to expose the top of the sacrificial layer 310.

[0140] The third trench 510 is used to provide space for the subsequent formation of the source and drain conductive layers.

[0141] In this embodiment, an anisotropic etching process is used to form the third trench 510.

[0142] Specifically, the third trench 510 is formed by an anisotropic dry etching process. The process parameters of the anisotropic etching process are easy to control, which is beneficial to control the etching amount and expose the corresponding source and drain doped layers 400. Moreover, the anisotropic dry etching process has the characteristics of anisotropic etching, and the etching is more directional, which is beneficial to improve the opening size accuracy of the third trench 510.

[0143] In this embodiment, during the step of forming the third trench 510, the third trench 510 exposes the source / drain doped layer 400 located on the same side of the buried power rail 210 as any sacrificial layer 310.

[0144] Both sidewalls of the second trench 150 are formed with sacrificial layers 310. According to process requirements, the third trench 510 exposes the source / drain doped layer 400 located on the same side of the buried power rail 210 as any sacrificial layer 310, so that the source / drain doped layer 400 can be electrically connected later.

[0145] refer to Figure 13 The sacrificial layer 310 is removed through the third trench 510 to form a fourth trench 520 that exposes the embedded power rail 210.

[0146] The fourth groove 520 is used to provide space for the subsequent formation of the power rail contact plug.

[0147] In this embodiment, a sacrificial layer 310 is used for pre-positioning. By flexibly selecting the material of the sacrificial layer 310, it is easy to remove, thereby reducing the difficulty of forming the fourth trench 520. This is conducive to the subsequent formation of the power rail contact plug. Moreover, the remaining first trench 140 exposed by the embedded power rail 210 is used as the second trench 150, and the sacrificial layer 310 is formed on the sidewall of the second trench 150. The formation position of the sacrificial layer 310 is defined by the sidewall of the second trench 150, so the positional accuracy of the sacrificial layer 310 relative to the embedded power rail 210 is higher. The third trench 510 exposes the adjacent source / drain doped layer 400, which is located in the same position as the sacrificial layer 310. The source / drain doped layer 400 on the same side of the buried power rail 210 makes it easier for the subsequently formed power rail contact plug to be closer to the sidewall of the buried power rail 210 facing the source / drain doped layer 400 that is connected to the subsequently formed source / drain conductive layer. This is beneficial for increasing the spacing between the power rail contact plug and the channel structure 120 below the source / drain doped layer 400 that is not connected to the source / drain conductive layer. This helps to increase the process window for forming the power rail contact plug, reduce the probability of bridging between the power rail contact plug and the channel structure 120 below the source / drain doped layer 400 that is not connected to the source / drain conductive layer, and thus improve the reliability of the semiconductor structure.

[0148] In this embodiment, the fourth trench 520 is formed using an isotropic etching process.

[0149] Using an isotropic etching process is beneficial for completely removing the sacrificial layer 310. The isotropic etching process also makes it easier to achieve a large etching selectivity, thereby reducing damage to the isolation layer 130 and the isolation layer 330 during the removal of the sacrificial layer 310. Specifically, in this embodiment, an isotropic dry etching process can be used to form the fourth trench 520. Since the isolation layer 330 is also formed on the sidewall of the sacrificial layer 310, an isotropic wet etching process can also be used to form the fourth trench 520.

[0150] It should be noted that in the step of removing the sacrificial layer 310 through the third trench 510, an etching process is used to remove the sacrificial layer 310, and the etching selectivity ratio between the sacrificial layer 310 and the isolation layer 130 should not be too small. If the etching selectivity ratio between the sacrificial layer 310 and the isolation layer 130 is too small, the isolation layer 130 is easily damaged during the removal of the sacrificial layer 310, affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of removing the sacrificial layer 310 through the third trench 510, an etching process is used to remove the sacrificial layer 310, and the etching selectivity ratio between the sacrificial layer 310 and the isolation layer 130 is greater than or equal to 5.

[0151] refer to Figure 14 The fourth trench 520 is filled to form a power rail contact plug 620; the third trench 510 is filled to form a source / drain conductive layer 610.

[0152] The source / drain conductive layer 610 is used to electrically connect the buried power rail 210 and the source / drain doped layer 400, and to apply voltage to the source / drain doped layer 400.

[0153] In this embodiment, the material of the source / drain conductive layer 610 includes tungsten, ruthenium, or molybdenum.

[0154] Tungsten, ruthenium, or molybdenum are metallic materials with good electrical conductivity, which is beneficial for achieving a better electrical connection between the source / drain doped layer 400 and the source / drain conductive layer 610.

[0155] The power rail contact plug 620 is used to electrically connect the source / drain conductive layer 610 and the embedded power rail 210.

[0156] In this embodiment, the material of the power rail contact plug 620 includes tungsten, ruthenium, or molybdenum.

[0157] Tungsten, ruthenium, or molybdenum are metallic materials with good electrical conductivity, which facilitates better electrical connection between the power rail contact plug 620 and the source / drain conductive layer 610, as well as between the power rail contact plug 620 and the embedded power rail 210.

[0158] It should be noted that in this embodiment, the fourth trench 520 and the third trench 510 are filled in the same step to form the power rail contact plug 620 and the source / drain conductive layer 610, which saves process time and improves process efficiency. Correspondingly, the power rail contact plug 620 and the source / drain conductive layer 610 are made of the same material.

[0159] In this embodiment, the process of filling the fourth trench 520 and the third trench 510 includes atomic layer deposition, chemical vapor deposition, or electroplating.

[0160] Atomic layer deposition, chemical vapor deposition, or electroplating processes have good gap filling capabilities, which are beneficial for filling the fourth trench 520 and the third trench 510 well, forming a power rail contact plug 620 and a source / drain conductive layer 610 with high film quality.

[0161] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate includes a substrate and a channel structure protruding on the substrate, the substrate further includes an isolation layer on the substrate, the channel structure includes a channel region along its extension direction, the isolation layer covers a portion of the sidewall of the channel structure in the channel region, and the top surface of the isolation layer is lower than the top surface of the channel structure; An embedded power rail is located between adjacent channel structures, wherein a portion of the embedded power rail extends vertically downward into the substrate and is below the bottom of the channel structure, and a portion of the embedded power rail extends vertically upward into the isolation layer and is below the top surface of the channel structure. A gate structure that spans the protruding channel structure; Sidewalls, covering the sidewalls of the gate structure; Source and drain doped layers are located on the channel structure on both sides of the channel region, and the bottom of the source and drain doped layers is embedded in the end of the channel structure; A dielectric layer is located on the isolation layer and covers the source / drain doped layer; A source / drain conductive layer is located in a dielectric layer on top of the source / drain doped layer and is electrically connected to the source / drain doped layer. A power rail contact plug is located in an isolation layer between the source / drain conductive layer and the buried power rail, and electrically connects the source / drain conductive layer and the buried power rail. The power rail contact plug is close to the sidewall of the buried power rail facing the source / drain doped layer connected to the source / drain conductive layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a sacrificial layer located in the isolation layer at the top of the embedded power rail, wherein the sidewall of the sacrificial layer is disposed opposite to the sidewall of the power rail contact plug, and the width of the power rail contact plug is equal to the width of the sacrificial layer along the extension direction perpendicular to the channel structure.

3. The semiconductor structure as described in claim 2, characterized in that, The sidewall of the power rail contact plug facing away from the sacrificial layer is flush with the sidewall of the embedded power rail, and the sidewall of the sacrificial layer facing away from the power rail contact plug is flush with the sidewall of the embedded power rail.

4. The semiconductor structure as described in claim 2, characterized in that, The material of the sacrificial layer includes silicon oxycarbide, amorphous silicon, silicon nitride, or silicon carbide.

5. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes an isolation layer located on top of the embedded power rail, the isolation layer being situated between the sacrificial layer and the power rail contact plug.

6. The semiconductor structure as described in claim 5, characterized in that, The materials of the insulating layer include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

7. The semiconductor structure as described in claim 1 or 2, characterized in that, Along the direction perpendicular to the channel structure, the width of the power rail contact plug is 8 nm to 14 nm.

8. The semiconductor structure as described in claim 1, characterized in that, The power rail contact plug is made of materials including tungsten, ruthenium, or molybdenum.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a channel structure protruding from the substrate, the substrate further including an isolation layer located on the substrate, the channel structure including a channel region along its extension direction, and the isolation layer covering the sidewalls of the channel structure of the channel region; A first trench is formed between adjacent channel structures, penetrating the isolation layer and extending into the substrate; Embedded power rails are formed in the first trench at a certain height, and the remaining first trench is retained as a second trench. A sacrificial layer is formed on the sidewall of the second trench; After the sacrificial layer is formed, source and drain doped layers are formed on the channel structure on both sides of the channel region; A dielectric layer is formed covering the isolation layer, source / drain doped layer, and sacrificial layer; A third trench is formed in the dielectric layer to expose the source and drain doped layer in the adjacent source and drain doped layer that is located on the same side of the buried power rail as the sacrificial layer. The third trench spans the channel structure and extends to expose the top of the sacrificial layer. The sacrificial layer is removed through the third trench to form a fourth trench that exposes the embedded power rail; The fourth groove is filled to form a power rail contact plug; The third trench is filled to form a source / drain conductive layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming an embedded power rail in the first trench at a certain height includes: filling the first trench to form a pre-embedded power material layer; Remove a portion of the pre-embedded power material layer, leaving the remaining height of the pre-embedded power material layer in the first trench as the embedded power rail.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a sacrificial layer on the sidewall of the second trench, the sacrificial layer is formed on both sidewalls of the second trench; In the step of forming the third trench, the third trench exposes the source / drain doped layer located on the same side as any of the sacrificial layers on the buried power rail.

12. The method for forming a semiconductor structure as described in claim 9 or 11, characterized in that, The step of forming a sacrificial layer on the sidewall of the second trench includes: forming a sacrificial material layer covering the top of the embedded power rail, the sidewall of the second trench, and the top of the isolation layer, wherein the sacrificial material layer located on the sidewall of the second trench serves as the sacrificial layer; Remove the sacrificial material layer covering the top of the embedded power rail and the top of the isolation layer, leaving the sacrificial layer intact.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The sacrificial material layer is formed using atomic layer deposition (ALD).

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, After the sacrificial layer is formed and before the source / drain doped layer is formed, the formation method further includes: forming an isolation layer in the remaining space of the second trench.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The step of forming the insulating layer includes: forming an insulating material layer that fills the second trench and covers the top of the insulating layer; Remove the insulating material layer covering the top of the insulating layer, and retain the insulating material layer filling the second trench as the insulating layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The insulating material layer is formed using an atomic layer deposition process.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The third trench is formed using an anisotropic etching process; the fourth trench is formed using an isotropic etching process.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the sacrificial layer on the sidewall of the second trench, the width of the sacrificial layer is 8 nm to 14 nm along the extension direction perpendicular to the trench structure.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of removing the sacrificial layer through the third trench, the sacrificial layer is removed by an etching process, and the etching selectivity ratio of the sacrificial layer and the isolation layer is greater than or equal to 5.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, After the sacrificial layer is formed but before the source / drain doped layer is formed, the formation method further includes: removing a portion of the thickness of the isolation layer to expose a portion of the height of the channel structure.

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