Irregular multi-gate sf gate structure

Abstract

The application discloses a special-shaped multi-gate SF gate structure, which is a special-shaped structure, and a source side gate and a drain side gate present a differential structure, which is a special-shaped gate structure, the width of a source side gate is small, and the width of a drain side gate is large, so that RTS noise of the SF is reduced; the gate structure of the special-shaped multi-gate is divided into different functions and is called a functional gate, which includes a modulation gate and a bias gate, the modulation gate is connected with an FD node, and the bias gate is connected with a bias voltage. According to the degree of proximity to the drain, the bias gate is graded, wherein the bias gate close to the drain is a high-potential bias gate, and the bias gate far from the drain is a low-potential bias gate. Compared with a traditional SF rectangular gate, the SF special-shaped multi-gate structure can greatly reduce the parasitic capacitance of the FD node, so that the conversion gain is improved, and the 1 / f noise and the RTS noise of the SF are also reduced.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor technology, and in particular to an irregularly shaped multi-gate SF gate structure. Background Technology

[0002] Low-light imaging technology refers to the technology of imaging devices in low-light environments such as nighttime. It has important applications in various fields such as national defense, biomedicine, deep-sea exploration, and aerospace. Low-light CMOS image sensors have the characteristics of low readout noise and high sensitivity, thus effectively amplifying optical signals under low-light conditions without being affected by noise. The readout circuit eliminates KTC noise and some fixed-mode noise from the reset transistor by using correlated double sampling technology, and uses a high-gain amplifier to significantly amplify the weak readout signal under low-light conditions.

[0003] High-sensitivity low-light CMOS image sensors require pixels to possess high conversion gain and low noise characteristics. Conversion gain is a crucial evaluation metric for CMOS image sensor pixels, affecting the sensor's sensitivity, signal-to-noise ratio, and consequently, its low-light imaging performance. The conversion gain of a pixel unit is inversely proportional to the capacitance of the floating diffusion node (FD); the smaller the capacitance of the FD node, the higher the conversion gain.

[0004] Some studies have suggested that the gate capacitance of the source follower (SF) can be reduced by decreasing the gate size, thereby reducing the capacitance of the FD node. However, this would result in greater 1 / f noise in the SF. Summary of the Invention

[0005] The present invention aims to propose an irregularly shaped multi-gate SF gate structure, which can reduce the gate capacitance of SF, improve the conversion gain, and at the same time reduce 1 / f noise and RTS noise.

[0006] The technical solution adopted to achieve the purpose of this invention is:

[0007] An irregularly shaped multi-gate SF gate structure is described. The source-side gate and the drain-side gate exhibit different structures, which is an irregular gate structure. The width of the gate on the source side is small, and the width of the gate on the drain side is large, in order to reduce the RTS noise of SF.

[0008] Among them, the gate structure of the irregular multi-gate is divided into different functions, called functional gates, including modulation gate and bias gate. The modulation gate is connected to the FD node, and the bias gate is connected to the bias voltage. The bias gate is classified according to its proximity to the drain. The bias gate that is closer to the drain is the high-potential bias gate, and the bias gate that is farther away from the drain is the low-potential bias gate.

[0009] The bias gate includes at least a high-potential bias gate BGH and a low-potential bias gate BGL. The modulation gate MG is close to the source S, the high-potential bias gate BGH is close to the drain D, and the low-potential bias gate BGL is between the modulation gate MG and the high-potential bias gate BGH. The width of the irregular gate gradually increases along the direction from the source S to the drain D.

[0010] Wherein, the modulation gate MG has an upper width W1 = 0.2 μm, a lower width W2 = 0.28 μm, and a length L1 = 0.2 μm; the low-potential bias gate BGL has an upper width W2 = 0.28 μm, a lower width W3 = 0.36 μm, and a length L2 = 0.2 μm; and the high-potential bias gate BGH has an upper width W3 = 0.36 μm, a lower width W4 = 0.44 μm, and a length L3 = 0.2 μm.

[0011] The width of the source electrode is equal to the upper width W1, and the width of the drain electrode is equal to the lower width W4.

[0012] The gap length L4 between the low-potential bias gate BGL and the high-potential bias gate BGH and the modulation gate MG is 0.1-0.13 μm.

[0013] Wherein, the doping concentration of the entire irregular gate is N. SF The N-type doping, the gap between the modulation gate MG and the low-potential bias gate BGL, is doped once with a concentration of N. gap1 The N-type doping, the gap between the low-potential bias gate BGL and the high-potential bias gate BGH, is doped once with a concentration of N. gap2 N-type doping, and the doping concentration N SF <N gap1 <N gap2 .

[0014] The modulation gate MG is connected to the FD node via a metal wire, the low-potential bias gate BGL and the high-potential bias gate BGH are connected to different bias voltages, the source S is connected to the selector, and the drain D is connected to the power supply.

[0015] During operation, the FD node outputs voltage, the modulation gate MG is connected to the FD node, and the output voltage of the FD node makes the potential under the modulation gate MG V. MG The low-potential bias gate BGL and the high-potential bias gate BGH are connected with different bias voltages, resulting in gate potentials of V respectively. BGL and V BGH Adjust the N-type doping concentration of the gap between the low-potential bias gate BGL, the high-potential bias gate BGH, and the modulation gate MG so that the potential of the gap between the modulation gate MG and the low-potential bias gate BGL is V. gap1 The potential of the gap between the low-potential bias gate BGL and the high-potential bias gate BGH is V. gap2 Satisfying V MG <Vgap1 <V BGL <V gap2 <V BGH This allows electrons to be smoothly transferred from the source S of the source follower to the drain D; when the FD node voltage is not output, the bias gate BG is connected to a negative voltage, making the potential under the bias gate BG very low, so that the source S and drain D of SF form good isolation.

[0016] The SF irregular multi-gate structure of the present invention can significantly reduce the parasitic capacitance of the FD node compared with the traditional SF rectangular gate, thereby improving the conversion gain, while also reducing the 1 / f noise and RTS noise of SF. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the capacitor composition at the FD node.

[0018] Figure 2 This is a schematic diagram of the pinch-off characteristics of a source follower.

[0019] Figure 3 This is a schematic cross-sectional view of the irregularly shaped multi-gate source follower according to an embodiment of the present invention.

[0020] Figure 4 This is a top view schematic diagram of an irregularly shaped multi-gate source follower according to an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the potential distribution of the irregularly shaped multi-gate source follower according to an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0023] Since the gate capacitance of SF accounts for a large proportion of the capacitance of FD node, this application proposes a gate design for SF that reduces SF noise while ensuring high conversion gain, which has important research value.

[0024] The present invention achieves the above-mentioned objective by using multiple irregularly shaped, small-area SF gates.

[0025] The capacitance of the FD node is as follows: Figure 1 As shown:

[0026] C = C1 + C2 + C3 + C4 + C5, where C1 is the junction capacitance of the FD node, which is related to the doping conditions of the FD node; C2 is the overlap capacitance between the FD node and the transfer gate; C3 is the overlap capacitance between the FD node and the reset gate, which is the coupling capacitance between the FD node and the gate and is related to the overlap area; C4 is the parasitic capacitance of the metal line connecting the FD and SF gates; and C5 is the gate capacitance of the SF. The gate capacitance of the SF is proportional to the area of ​​the SF gate; the smaller the area of ​​the SF, the smaller the gate capacitance of the SF.

[0027] Pixel unit noise includes photon shot noise, dark current, random telephone signal (RTS) noise, and 1 / f noise of the photodiode. Photon shot noise originates from the fact that photons follow a Poisson distribution; the standard deviation of the Poisson distribution is the photon shot noise. Dark current mainly originates from the trap contacts at the interface between the photodiode and the oxide semiconductor, where carriers are trapped and released, generating dark current. RTS noise is the fluctuation of voltage and current over time; carriers are trapped at the oxide semiconductor interface and in the gate oxide layer, causing the current to decrease. After the carriers are released, the current returns to normal levels.

[0028] There are three well-known models for 1 / f noise in SF6 (Semiconductor Field Synthetic) batteries: the McWhorter model attributes it to carrier fluctuations caused by trap release; the Hooge model attributes it to mobility fluctuations caused by phonon scattering; and the Berkely model attributes it to both carrier quantity fluctuations and mobility fluctuations. The mobility fluctuation, unlike the Hooge model, is attributed to charge scattering at the Si-SiO2 interface. All three models suggest that increasing the gate area of ​​the SF6 battery can result in lower 1 / f noise.

[0029] Therefore, in this invention, the SF gate adopts an irregular structure, with the source-side gate and drain-side gate exhibiting differentiated structures, referred to as an irregular gate structure. See [link to relevant documentation]. Figure 3 , Figure 4 As shown, advantageously, a smaller gate width on the source side and a larger gate width on the drain side effectively reduce the RTS noise of the SF. Traps on the source side of the SF have a significant impact on RTS noise. This is because the SF is in the saturation region under normal operating conditions, such as... Figure 2 As shown, the pinch-off point is close to the drain. The vertical electric field strength between the gate and the channel is smaller on the drain side, resulting in a lower carrier concentration. Therefore, the traps at the drain are less active than those at the source. If the width of the SF gate is reduced, the number of traps on the source side will decrease, while the carrier concentration will increase. This will reduce the impact of traps trapping and releasing electrons, thus decreasing the RTS noise amplitude.

[0030] This invention divides the SF (Short-Side) irregular gate region into multiple functional gates with small gaps between them. The functional gate closest to the source (S) serves as the modulation gate (MG) connected to the FD (Distribution Facility). The remaining functional gates serve as bias gates (BG) connected to the bias voltage. The bias gates (BG) are graded according to their proximity to the drain (D): the bias gate (MG) closest to the drain (D) is the high-potential bias gate (BGH), and the bias gate (BG) furthest from the drain (D) is the low-potential bias gate (BGL). The source (S) of the source follower is connected to the selector, and the drain (D) is connected to the power supply. The parasitic capacitance of the bias gates does not affect the capacitance of the FD node, significantly reducing the parasitic capacitance of the FD node. The overall area of ​​the SF gate is relatively large, effectively reducing 1 / f noise.

[0031] When the SF gate is turned on, the potential under the irregular gate increases, and the gaps between multiple functional gates can easily form potential barriers or wells, affecting carrier transport and consequently the gain of the source follower. To solve this problem, N-type doping is performed under the irregular gate of the SF gate to form an N-type region. Carriers are transported through the N-type channel under the SF gate. Additional N-type doping is applied to the gaps between the gates. By adjusting the N-type doping concentration in the gaps between the gates, the turn-on voltage of the bias gate is gradually increased from low to high potential. This causes the potential under the SF gate to gradually increase from the side near the source to the side near the drain when the FD node voltage is output. At other times, the bias gate is connected to a negative voltage, keeping the potential under the bias gate very low and ensuring good isolation between the source and drain of the SF gate. Meanwhile, when no voltage is applied to the SF irregular gate, electrons in the N-type region under the SF gate diffuse to the P-type substrate, and holes in the P-type substrate diffuse to the N-type region, forming a depletion region. The boundary potential of the depletion region is highest near the N-type region. Electrons travel along a path from low to high potential, away from the oxide semiconductor interface, further reducing RTS noise.

[0032] SF's irregular multi-gate structure can reduce parasitic capacitance at the FD node, significantly improve conversion gain, reduce 1 / f noise, and ensure a narrow gate width on the source side, effectively reducing RTS noise. This achieves the requirements of high conversion gain and low noise for low-light pixels.

[0033] As a specific embodiment, in this application, the gate of the source follower adopts an irregular structure, consisting of a modulation gate and two bias gates. The modulation gate is close to the source, the high-bias gate is close to the drain, and the low-bias gate is between the modulation gate and the high-bias gate. The width of the irregular gate gradually increases from the source to the drain. The width of the modulation gate MG is W1 = 0.2 μm, W2 = 0.28 μm, and the length is L1 = 0.2 μm. The width of the low-bias gate BGL is W2 = 0.28 μm, W3 = 0.36 μm, and the length is L2 = 0.2 μm. The width of the high-bias gate BGH is W3 = 0.36 μm, W4 = 0.44 μm, and the length is L3 = 0.2 μm. The gap length between the functional gates is L4 = 0.1-0.13 μm. The width of the source of the source follower is equal to W1, and the width of the drain is equal to W4. The overall doping concentration of the irregular gate of the source follower is N. SF The N-type doping, the gap between the modulation gate and the low-potential bias gate, is doped once with a concentration of N. gap1 The N-type doping, the gap between the low-potential bias gate and the high-potential bias gate, is doped once with a concentration of N. gap2 N-type doping ensures a doping concentration of N SF <N gap1 <N gap2 The source follower modulation gate is connected to the FD node via a metal wire. The low-bias gate and the high-bias gate are connected to different bias voltages. The source is connected to the selector transistor, and the drain is connected to the power supply.

[0034] During operation, when the FD node voltage is output, the potential distribution of SF is as follows: Figure 5 As shown, the modulation gate is connected to the FD node, and the output voltage of the FD node makes the potential under the modulation gate V. MG The low-potential bias gate and the high-potential bias gate are connected with different bias voltages, resulting in gate potentials of V respectively. BGL and V BGH Adjust the N-type doping concentration of the gap between the functional gates to make the potential of the gap between the modulation gate and the low-potential bias gate V. gap1 The potential of the gap between the low-potential bias gate and the high-potential bias gate is V. gap2 Satisfying V MG <V gap1 <V BGL <V gap2 <V BGH This allows electrons to be smoothly transferred from the source to the drain of the source follower. When the FD node voltage is not output, the bias gate is connected to a negative voltage, making the potential under the bias gate very low, ensuring good isolation between the source and drain of the SF.

[0035] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0036] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0037] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An irregularly shaped multi-gate SF gate structure, characterized in that, It has an irregular structure, with the source-side gate and drain-side gate exhibiting different structures, hence the name irregular gate structure. The width of the gate on the source side is small, while the width of the gate on the drain side is large, in order to reduce the RTS noise of SF. The gate structure of the irregular multi-gate is divided into different functions, called functional gates, including modulation gate and bias gate. The modulation gate is connected to the FD node, and the bias gate is connected to the bias voltage. The bias gate is classified according to its proximity to the drain. The bias gate closer to the drain is the high-potential bias gate, and the bias gate farther from the drain is the low-potential bias gate. The bias gate includes at least a high-potential bias gate BGH and a low-potential bias gate BGL. The modulation gate MG is close to the source S, the high-potential bias gate BGH is close to the drain D, and the low-potential bias gate BGL is between the modulation gate MG and the high-potential bias gate BGH. The width of the irregular gate gradually increases along the direction from the source S to the drain D. The modulation gate MG has an upper width W1 = 0.2 μm, a lower width W2 = 0.28 μm, and a length L1 = 0.2 μm; the low-potential bias gate BGL has an upper width W2 = 0.28 μm, a lower width W3 = 0.36 μm, and a length L2 = 0.2 μm; the high-potential bias gate BGH has an upper width W3 = 0.36 μm, a lower width W4 = 0.44 μm, and a length L3 = 0.2 μm. The overall doping concentration under the irregular gate is N. SF The N-type doping, the gap between the modulation gate MG and the low-potential bias gate BGL, is doped once with a concentration of N. gap1 The N-type doping, the gap between the low-potential bias gate BGL and the high-potential bias gate BGH, is doped once with a concentration of N. gap2 N-type doping, and the doping concentration N SF <N gap1 <N gap2 .

2. The irregularly shaped multi-gate SF gate structure according to claim 1, characterized in that, The width of the source electrode is equal to the upper width W1, and the width of the drain electrode is equal to the lower width W4.

3. The irregularly shaped multi-gate SF gate structure according to claim 1, characterized in that, The gap length L4 between the low-potential bias gate BGL and the high-potential bias gate BGH and the modulation gate MG is 0.1-0.13 μm.

4. The irregularly shaped multi-gate SF gate structure according to claim 1, characterized in that, The modulation gate MG is connected to the FD node via a metal wire, the low-potential bias gate BGL and the high-potential bias gate BGH are connected to different bias voltages, the source S is connected to the selector, and the drain D is connected to the power supply.

5. The irregularly shaped multi-gate SF gate structure according to claim 1, characterized in that, During operation, the FD node outputs voltage, and the modulation gate MG is connected to the FD node. The output voltage of the FD node makes the potential under the modulation gate MG V. MG The low-potential bias gate BGL and the high-potential bias gate BGH are connected with different bias voltages, resulting in gate potentials of V respectively. BGL and V BGH Adjust the N-type doping concentration of the gap between the low-potential bias gate BGL, the high-potential bias gate BGH, and the modulation gate MG so that the potential of the gap between the modulation gate MG and the low-potential bias gate BGL is V. gap1 The potential of the gap between the low-potential bias gate BGL and the high-potential bias gate BGH is V. gap2 Satisfying V MG <V gap1 <V BGL <V gap2 <V BGH This allows electrons to be smoothly transferred from the source S of the source follower to the drain D; when the FD node voltage is not output, the bias gate BG is connected to a negative voltage, making the potential under the bias gate BG very low, so that the source S and drain D of SF form good isolation.

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