Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, comprising: a first semiconductor layer, a first surface of the first semiconductor layer forms a plurality of first protrusions; a second semiconductor layer formed on the first semiconductor layer, and a surface of the second semiconductor layer facing away from the first semiconductor layer forms a plurality of second protrusions corresponding to the first protrusions; the second semiconductor layer has the same conductivity type as the first semiconductor layer, and a doping concentration less than that of the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer, the third semiconductor layer has an opposite conductivity type to the first semiconductor layer. Since the first surface forms the first protrusions, the side of the second semiconductor layer facing away from the first semiconductor layer forms the second protrusions, compared with the method of forming the second protrusions by etching, the second semiconductor layer is avoided from being damaged by etching, and then the damage between the interface of the second semiconductor layer and the third semiconductor layer is avoided, and the introduction of interface impurities is avoided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of science and technology, semiconductor structures have attracted increasing attention.

[0003] Schottky diodes are an important semiconductor structure, widely used in power electronics, microwave radio frequency, and other fields due to their high reliability and ease of circuit design. A key technical indicator of a Schottky diode is its reverse breakdown voltage, which limits the device's performance and reliability. In the fabrication of vertical Schottky diodes, many factors can affect the reverse breakdown voltage, such as etching processes that can damage the interface and introduce interface impurities. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure and its fabrication method that can avoid the introduction of interface impurities.

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0006] A first semiconductor layer, the first semiconductor layer including opposing first and second surfaces, the first surface forming a plurality of first protrusions;

[0007] A second semiconductor layer is formed on the first semiconductor layer. A plurality of second protrusions are formed on the surface of the second semiconductor layer facing away from the first semiconductor layer. The second protrusions correspond to the first protrusions, and a second groove is formed between two adjacent second protrusions. The second semiconductor layer has the same conductivity type as the first semiconductor layer, and the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.

[0008] A third semiconductor layer is formed on the second semiconductor layer, and the third semiconductor layer has the opposite conductivity type to the first semiconductor layer.

[0009] Furthermore, a buffer layer is provided between the first semiconductor layer and the second semiconductor layer.

[0010] Furthermore, a plurality of third protrusions corresponding to the second protrusions are formed on the surface of the third semiconductor layer facing away from the second semiconductor layer.

[0011] Furthermore, the surface of the third semiconductor layer facing away from the second semiconductor layer is a plane, filling the second groove.

[0012] Furthermore, it also includes a fourth semiconductor structure, wherein the third semiconductor layer is mesh-like, with the mesh corresponding to the second protrusion, and the fourth semiconductor structure is formed on the second protrusion. The fourth semiconductor structure has the same conductivity type as the first semiconductor layer and the opposite conductivity type to the third semiconductor layer.

[0013] Furthermore, the horizontal projection of the first protrusion is circular, and after the second semiconductor layer is grown, the horizontal projection of the second protrusion is hexagonal.

[0014] Furthermore, a plurality of third protrusions are formed conformally on the surface of the third semiconductor layer facing away from the second semiconductor layer, and the third protrusions correspond to the second protrusions; the first protrusion, the second protrusion and the third protrusion are strip-shaped.

[0015] Furthermore, it also includes:

[0016] The semiconductor structure includes a source, a gate, and a drain. The source is disposed on the fourth semiconductor structure, the gate is disposed on the top surface of the third semiconductor layer, and the drain is disposed on the second surface of the first semiconductor layer.

[0017] Furthermore, it also includes:

[0018] The first electrode is disposed on the top surface of the second protrusion;

[0019] The second electrode is disposed on the second surface of the first semiconductor layer.

[0020] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0021] A first semiconductor layer is provided, the first semiconductor layer including opposing first and second surfaces, the first surface forming a plurality of first protrusions;

[0022] A second semiconductor layer is formed covering the first surface. The second semiconductor layer has a plurality of second protrusions formed conformally on the surface of the second semiconductor layer away from the first semiconductor layer. The second protrusions correspond to the first protrusions, and a second groove is formed between two adjacent second protrusions. The second semiconductor layer has the same conductivity type as the first semiconductor layer, and the doping concentration of the second semiconductor layer is less than that of the first semiconductor layer.

[0023] A third semiconductor layer is formed to cover the second semiconductor layer.

[0024] Furthermore, it also includes,

[0025] Form a mask layer covering the third semiconductor layer;

[0026] A window is formed on the mask layer, the window exposing the portion of the third semiconductor layer located on the top surface of the second protrusion;

[0027] The portion of the third semiconductor layer located on the top surface of the second protrusion is etched to expose the top surface of the second protrusion.

[0028] Furthermore, the method for fabricating the semiconductor structure further includes:

[0029] A fourth semiconductor structure is formed on the top surface of the second protrusion.

[0030] Furthermore, a plurality of third protrusions are formed conformally on the surface of the third semiconductor layer facing away from the second semiconductor layer, and the third protrusions correspond to the second protrusions.

[0031] Furthermore, the surface of the third semiconductor layer facing away from the second semiconductor layer is a plane, filling the second groove.

[0032] Furthermore, the first surface forms a plurality of first protrusions, including:

[0033] Etch the first surface to form a plurality of first protrusions; or

[0034] The first semiconductor layer is conformally grown on the surface of a patterned substrate to form a plurality of first protrusions on the first semiconductor layer.

[0035] Furthermore, the method for fabricating the semiconductor structure further includes:

[0036] A source, a gate, and a drain are formed. The source is disposed on the top surface of the second protrusion to contact the second semiconductor layer. The gate is disposed on the top surface of the third semiconductor layer. The drain is disposed on the second surface of the first semiconductor layer.

[0037] Furthermore, the method for fabricating the semiconductor structure further includes:

[0038] A first electrode is formed on the top surface of the second protrusion, which contacts the third semiconductor layer;

[0039] A second electrode is formed on the second surface of the first semiconductor layer.

[0040] The semiconductor structure and its fabrication method disclosed herein involve forming a second semiconductor layer on the first surface of a first semiconductor layer. Since a first protrusion is formed on the first surface, a second protrusion is formed on the side of the second semiconductor layer facing away from the first semiconductor layer. Compared with the method of forming the second protrusion by etching, the etching damage to the second semiconductor layer is avoided, thereby avoiding damage between the interface of the second semiconductor layer and the third semiconductor layer and avoiding the introduction of interface impurities. Attached Figure Description

[0041] Figure 1(a) is a schematic diagram of the formation of the second semiconductor layer in Embodiment 1 of this disclosure.

[0042] Figures 1(b), 1(c), and 1(e) are top views of the structure shown in Figure 1(a).

[0043] Figure 1(d) and Figure 1(f) are top views of the first semiconductor layer in Figure 1(a).

[0044] Figure 2 This is a schematic diagram of the formation of the third semiconductor layer in Embodiment 1 of this disclosure.

[0045] Figure 3 This is a schematic diagram of the mask layer after it has been formed in Embodiment 1 of this disclosure.

[0046] Figure 4 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 1 of this disclosure.

[0047] Figure 5 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 2 of this disclosure.

[0048] Figure 6 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 3 of this disclosure.

[0049] Figure 7 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 4 of this disclosure.

[0050] Figure 8 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 5 of this disclosure.

[0051] Figure 9 This is a schematic diagram of the semiconductor structure prepared according to Embodiment Six of this disclosure.

[0052] Explanation of reference numerals in the attached figures: 1. First semiconductor layer; 101. First groove; 102. First protrusion; 2. Second semiconductor layer; 201. Second groove; 202. Second protrusion; 3. Third semiconductor layer; 301. Third groove; 302. Third protrusion; 4. Source; 5. Gate; 6. Drain; 7. Mask layer; 701. Window; 8. Fourth semiconductor structure; 9. Buffer layer; 901. Buffer layer groove; 10. First electrode; 11. Second electrode. Detailed Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0054] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this disclosure and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0055] Example 1

[0056] This disclosure provides a method for fabricating a semiconductor structure according to Embodiment 1. Figure 1(a) is a schematic diagram after the formation of the second semiconductor layer 2 in Embodiment 1 of this disclosure. Figures 1(b), 1(c), and 1(e) are top views of the structure shown in Figure 1(a). Figures 1(d) and 1(f) are top views of the first semiconductor layer 1 in Figure 1(a). Figure 2 This is a schematic diagram of the formation of the third semiconductor layer 3 in Embodiment 1 of this disclosure. Figure 3 This is a schematic diagram of the mask layer 7 formed in Embodiment 1 of this disclosure. Figure 4 This is a schematic diagram of a semiconductor structure prepared according to Embodiment 1 of this disclosure. The method for preparing this semiconductor structure may include steps S100-S120, wherein:

[0057] Step S100: Provide a first semiconductor layer 1, the first semiconductor layer 1 including a first surface and a second surface opposite to each other, the first surface forming a plurality of first protrusions 102.

[0058] Step S110: Form a second semiconductor layer 2 covering the first surface. A plurality of second protrusions 202 are formed on the surface of the second semiconductor layer 2 facing away from the first semiconductor layer 1. The second protrusions 202 correspond to the first protrusions 102. A second groove 201 is formed between two adjacent second protrusions 202. The second semiconductor layer 2 and the first semiconductor layer 1 have the same conductivity type. The doping concentration of the second semiconductor layer 2 is less than that of the first semiconductor layer 1.

[0059] Step S120: Form a third semiconductor layer 3 covering the second semiconductor layer 2, wherein the third semiconductor layer 3 has the opposite conductivity type to the first semiconductor layer 1.

[0060] In the semiconductor structure fabrication method of this disclosure embodiment, the second semiconductor layer 2 is formed on the first surface of the first semiconductor layer 1. Since the first surface has a first protrusion 102, a second protrusion 202 is formed on the side of the second semiconductor layer facing away from the first semiconductor layer. Compared with the method of forming the second protrusion 202 by etching, the second semiconductor layer 2 is protected from etching damage, thereby avoiding damage between the interface of the second semiconductor layer 2 and the third semiconductor layer 3 and avoiding the introduction of interface impurities.

[0061] The steps of the method for fabricating the semiconductor structure according to the embodiments of this disclosure will be described in detail below:

[0062] In step S100, a first semiconductor layer 1 is provided. The first semiconductor layer 1 includes a first surface and a second surface opposite to each other. A plurality of first protrusions 102 are formed on the first surface.

[0063] As shown in Figure 1, the material of the first semiconductor layer 1 can be a III-V group compound. Specifically, the material of the first semiconductor layer 1 can be at least one selected from Si, SiC, GaN, Ga2O3, AlGaN, InGaN, and AlInGaN. In other embodiments of this disclosure, the material of the first semiconductor layer 1 can also be at least one selected from Si and SiC. The first semiconductor layer 1 can be doped with n-type ions to make the first semiconductor layer 1 an n-type semiconductor layer. The n-type ions can be at least one selected from Si ions, Ge ions, Sn ions, Se ions, or Te ions. The concentration of n-type ions doped in the first semiconductor layer 1 is relatively high to make the first semiconductor layer 1 a heavily n-type doped layer, and the doping concentration of impurity ions in the first semiconductor layer 1 can be 10. 18 / cm 3The first semiconductor layer 1 can be a single-layer structure or a stacked structure. Each layer can be made of GaN, AlGaN, or AlInGaN, or other semiconductor materials including Ga and N atoms, or a mixture of at least two of the above materials. Alternatively, the first semiconductor layer 1 can be a p-type semiconductor layer. The first surface and the second surface can be two opposing surfaces in the thickness direction of the first semiconductor layer 1.

[0064] The number of first protrusions 102 can be multiple, and the multiple first protrusions 102 are spaced apart. The horizontal projection of the first protrusion 102 can be circular, but it can also be strip, rectangle, or other shapes. As shown in FIG1(d), the multiple first protrusions 102 with circular horizontal projections can be arranged in a hexagonal pattern; as shown in FIG1(f), the multiple first protrusions 102 with rectangular horizontal projections can be arranged in a matrix. Taking the first protrusion 102 as a strip, the multiple first protrusions 102 can be arranged in parallel and spaced apart. Forming multiple first protrusions 102 on the first surface can include: conformally growing a first semiconductor layer 1 on the surface of a patterned substrate and removing the sacrificial layer to form multiple first protrusions 102 on the first semiconductor layer 1. In other embodiments of this disclosure, the first surface can also be etched to form multiple first protrusions 102. In addition, a first groove 101 is formed between two adjacent first protrusions 102.

[0065] In step S110, a second semiconductor layer 2 covering the first surface is formed. A plurality of second protrusions 202 are formed on the surface of the second semiconductor layer 2 facing away from the first semiconductor layer 1. The second protrusions 202 correspond to the first protrusions 102. A second groove 201 is formed between two adjacent second protrusions 202. The second semiconductor layer 2 and the first semiconductor layer 1 have the same conductivity type. The doping concentration of the second semiconductor layer 2 is less than that of the first semiconductor layer 1.

[0066] The material of the second semiconductor layer 2 can be a group III-V compound. Specifically, the material of the second semiconductor layer 2 can be at least one of Si, SiC, GaN, Ga2O3, AlGaN, InGaN, and AlInGaN. The second semiconductor layer 2 has the same conductivity type as the first semiconductor layer 1. Taking the first semiconductor layer 1 as an n-type semiconductor layer as an example, the second semiconductor layer 2 is also an n-type semiconductor layer; taking the first semiconductor layer 1 as a p-type semiconductor layer as an example, the second semiconductor layer 2 is also a p-type semiconductor layer. The doping concentration of the second semiconductor layer 2 is lower than that of the first semiconductor layer 1. Taking the first semiconductor layer 1 as a heavily n-type doped layer as an example, the second semiconductor layer 2 can be a lightly n-type doped layer, and the doping concentration of impurity ions in the second semiconductor layer 2 can be 10. 18 / cm 3Below the order of magnitude. The second semiconductor layer 2 can be a single-layer structure or a stacked structure. The material of each layer can be GaN, AlGaN or AlInGaN, or other semiconductor materials including Ga atoms and N atoms, or a mixture of at least two of the above materials.

[0067] The number of the second protrusions 202 can be multiple. Further, the number of the second protrusions 202 can be the same as the number of the first protrusions 102, but this embodiment does not specifically limit this. Taking the horizontal projection of the first protrusion 102 as a strip, as shown in Figure 1(b), the horizontal projection of the second protrusion 202 can also be a strip; taking the horizontal projection of the first protrusion 102 as a circle, as shown in Figure 1(c), the horizontal projection of the second protrusion 202 can be hexagonal and arranged in a hexagonal pattern; taking the horizontal projection of the first protrusion 102 as a rectangle, as shown in Figure 1(e), the horizontal projection of the second protrusion 202 can be rectangular and arranged in a matrix. Taking the horizontal projection of the second protrusion 202 as a strip, multiple second protrusions 202 can be arranged in parallel and spaced apart. A second groove 201 is formed between adjacent second protrusions 202. The horizontal width of the first strip-shaped protrusion 102 can be greater than the horizontal width of the second strip-shaped protrusion 202, and conversely, the horizontal width of the first strip-shaped protrusion 102 can be smaller than the horizontal width of the second strip-shaped protrusion 202. The second semiconductor layer 2 can be formed by epitaxial growth, but this embodiment does not specifically limit this. Specifically, the second semiconductor layer 2 can form the second protrusion 202 conformally during epitaxial growth. This configuration reduces the number of etching steps, thereby reducing the non-uniformity caused by etching and the impact of etching on the epitaxial layer. This allows for closer approximation to the theoretical design objective. As defects are reduced, conductivity decreases, i.e., the number of charge carriers decreases, further increasing the reverse breakdown voltage.

[0068] In step S120, a third semiconductor layer 3 is formed covering the second semiconductor layer 2.

[0069] like Figure 2As shown, the material of the third semiconductor layer 3 can be a semiconductor layer, for example, the material of the third semiconductor layer 3 can be at least one of Si, SiC, GaN, Ga2O3, AlGaN, InGaN, and AlInGaN. The conductivity type of the third semiconductor layer 3 is different from that of the first semiconductor layer 1. Taking the first semiconductor layer 1 as an n-type semiconductor layer as an example, the third semiconductor layer 3 is a p-type semiconductor layer; taking the first semiconductor layer 1 as a p-type semiconductor layer as an example, the third semiconductor layer 3 is an n-type semiconductor layer. The third semiconductor layer 3 can be a single-layer structure or a stacked structure, and the material of each layer can be GaN, AlGaN, or AlInGaN, or other semiconductor materials including Ga atoms and N atoms, or a mixture of at least two of the above materials. In other embodiments of this disclosure, the material of the third semiconductor layer 3 may also include NiO, ITO, etc.

[0070] The surface of the third semiconductor layer 3 facing away from the second semiconductor layer 2 is conformally formed with a plurality of third protrusions 302, which correspond to the second protrusions 202. Of course, in other embodiments, the surface of the third semiconductor layer 3 facing away from the second semiconductor layer 2 can be a plane and fill the second groove 201, but this disclosure does not make any special limitation in this regard.

[0071] The number of third protrusions 302 can be multiple. Further, the number of third protrusions 302 can be the same as the number of second protrusions 202, but this embodiment does not specifically limit this. The horizontal projection of the third protrusion 302 can be strip-shaped. Taking multiple third protrusions 302 as an example, the multiple strip-shaped third protrusions 302 can be arranged in parallel and spaced apart. The horizontal width of the strip-shaped second protrusion 202 can be greater than the horizontal width of the strip-shaped third protrusion 302; of course, the horizontal width of the strip-shaped second protrusion 202 can also be less than the horizontal width of the strip-shaped third protrusion 302. In addition, a third groove 301 is formed between adjacent third protrusions 302.

[0072] The third semiconductor layer 3 can be formed by epitaxial growth, but this embodiment does not specifically limit it. Specifically, the third semiconductor layer 3 can be formed conformally during epitaxial growth to create the third protrusion 302.

[0073] The method for fabricating the semiconductor structure according to embodiments of this disclosure may further include:

[0074] Step S130: Etch a portion of the third semiconductor layer 3 to expose the top surface of the second protrusion 202.

[0075] Specifically, step S130 may include:

[0076] Step S1301, as follows Figure 3As shown, a mask layer 7 is formed covering the third semiconductor layer 3.

[0077] The mask layer 7 can be made of an insulating material, such as SiO2. The mask layer 7 can be prepared by vapor deposition. The mask layer 7 can conformally cover the third semiconductor layer 3, but this embodiment does not specifically limit its application.

[0078] Step S1302: A window 701 is formed on the mask layer 7, which exposes the portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202.

[0079] The window 701 can be formed by etching. The area of ​​the window 701 can be smaller than the top surface area of ​​the second protrusion 202, or it can be larger than or equal to the top surface area of ​​the second protrusion 202. This disclosure exposes the top surface of the second protrusion 202 by etching, which is highly efficient and reduces fabrication time.

[0080] Step S1303, as follows Figure 4 As shown, the portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202 is etched to expose the top surface of the second protrusion 202.

[0081] Using the mask layer 7 with the window 701 as a mask, the portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202 is etched. In embodiments of this disclosure, the mask layer 7 can be removed, or it can be retained.

[0082] This disclosure also provides a semiconductor structure, which can be fabricated by the semiconductor structure fabrication method described above. The semiconductor structure may include: a first semiconductor layer 1, comprising a first surface and a second surface facing each other, with a plurality of first protrusions 102 formed on the first surface; a second semiconductor layer 2, formed on the first semiconductor layer 1, with a plurality of second protrusions 202 conformally formed on the surface of the second semiconductor layer 2 facing away from the first semiconductor layer 1, the second protrusions 202 corresponding to the first protrusions 102, and a second groove 201 formed between adjacent second protrusions 202; the second semiconductor layer 2 and the first semiconductor layer 1 have the same conductivity type, and the doping concentration of the second semiconductor layer 2 is lower than that of the first semiconductor layer 1; and a third semiconductor layer 3, formed on the second semiconductor layer 2, exposing the second protrusions 202.

[0083] The method for preparing the semiconductor structure provided in this disclosure and the semiconductor structure belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other, and will not be repeated here.

[0084] Example 2

[0085] Figure 5 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 2 of this disclosure. The semiconductor structure and its preparation method in Embodiment 2 of this disclosure are generally the same as those in Embodiment 1 of this disclosure, except that, before step S110, the preparation method further includes: forming a buffer layer 9 covering the first surface of the first semiconductor layer 1, wherein the second semiconductor layer 2 is formed on the side of the buffer layer 9 facing away from the first semiconductor layer 1.

[0086] The conductivity type of the buffer layer 9 is the same as that of the first semiconductor layer 1. For example, the buffer layer 9 is an n-type buffer layer 9. The material of the buffer layer 9 can be GaN, AlGaN, or AlInGaN, or other semiconductor materials including Ga atoms, N atoms, or at least two of the above materials or a mixture thereof. A buffer layer groove 901 is formed on the surface of the buffer layer 9 facing away from the first semiconductor layer 1, and the buffer layer groove 901 corresponds to the first groove 101. The buffer layer 9 can be formed by epitaxial growth, but this embodiment of the present disclosure does not make any special limitation on this. In particular, the buffer layer groove 901 can be formed conformally during the epitaxial growth process.

[0087] The conductivity type of the buffer layer 9 is opposite to that of the first semiconductor layer 1. For example, the buffer layer 9 is a P-type buffer layer that provides electron replenishment between the first semiconductor layer 1 and the second semiconductor layer 2 to form a depletion layer. The buffer layer 9 can be an alloy layer or a superlattice structure layer, serving as a barrier layer against impurities and defects.

[0088] It should be noted that the buffer layer 9 can be a single-layer structure or a stacked structure.

[0089] Example 3

[0090] Figure 6 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 3 of this disclosure. The semiconductor structure and its preparation method of Embodiment 3 of this disclosure are generally the same as the semiconductor structure and its preparation method of Embodiment 1 or Embodiment 2 of this disclosure, except that the preparation method further includes: removing the mask layer 7; forming a source 4, a gate 5 and a drain 6, wherein the source 4 is disposed on the top surface of the second protrusion 202 to contact the second semiconductor layer 2, the gate 5 is disposed on the bottom surface of the third groove 301 to contact the third semiconductor layer 3, and the drain 6 is disposed on the second surface of the first semiconductor layer 1.

[0091] Example 4

[0092] Figure 7This is a schematic diagram of the semiconductor structure prepared according to Embodiment 4 of this disclosure. The semiconductor structure and its preparation method in Embodiment 4 of this disclosure are generally the same as those in Embodiment 1 or Embodiment 2 of this disclosure, except that the preparation method further includes: forming an opening in the mask layer 7, the opening exposing a portion of the third semiconductor layer 3 located on the bottom surface of the third groove 301; forming a source 4, a gate 5, and a drain 6, the source 4 being disposed on the top surface of the second protrusion 202, the gate 5 being disposed on the bottom surface of the third groove 301, and the drain 6 being disposed on the second surface of the first semiconductor layer 1. The opening can be formed by etching.

[0093] Example 5

[0094] Figure 8 This is a schematic diagram of the semiconductor structure prepared according to Embodiment 5 of this disclosure. The semiconductor structure and its preparation method of Embodiment 5 of this disclosure are generally the same as the semiconductor structure and its preparation method of any of Embodiments 1 to 4 of this disclosure, except that, before forming the source electrode 4, the preparation method of this semiconductor structure further includes: the third semiconductor layer 3 is mesh-like, with the mesh corresponding to the second protrusion 202, and a fourth semiconductor structure 8 is formed on the top surface of the second protrusion 202. The fourth semiconductor structure 8 has the same conductivity type as the first semiconductor layer 1 and the opposite conductivity type to the third semiconductor layer 3.

[0095] The aforementioned source 4 is formed on the side of the fourth semiconductor structure 8 facing away from the second protrusion 202. By providing the fourth semiconductor structure 8, the ohmic contact resistance can be reduced.

[0096] Example 6

[0097] Figure 9 This is a schematic diagram of the semiconductor structure prepared according to Embodiment Six of this disclosure. The semiconductor structure and its preparation method of Embodiment Six of this disclosure are generally the same as the semiconductor structure and its preparation method of Embodiment One or Embodiment Two of this disclosure, except that the preparation method further includes: forming a first electrode 10 in contact with the third semiconductor layer 3 on the top surface of the second protrusion 202; forming a second electrode 11 on the second surface of the first semiconductor layer 1, specifically the first electrode 10 is the anode, the second electrode 11 is the cathode, and the anode simultaneously contacts the second semiconductor layer 2 and the third semiconductor layer 3.

[0098] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to a preferred embodiment, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A first semiconductor layer (1) includes opposing first and second surfaces, wherein a plurality of first protrusions (102) are formed on the first surface. A second semiconductor layer (2) is formed on the first semiconductor layer (1). A plurality of second protrusions (202) are formed on the surface of the second semiconductor layer (2) facing away from the first semiconductor layer (1). The second protrusions (202) correspond to the first protrusions (102). A second groove (201) is formed between two adjacent second protrusions (202). The second semiconductor layer (2) has the same conductivity type as the first semiconductor layer (1). The doping concentration of the second semiconductor layer (2) is less than that of the first semiconductor layer (1). A third semiconductor layer (3) is formed on the second semiconductor layer (2), and the third semiconductor layer (3) has the opposite conductivity type to the first semiconductor layer (1); The surface of the third semiconductor layer (3) facing away from the second semiconductor layer (2) is conformally formed with a plurality of third protrusions (302) corresponding to the second protrusion (202).

2. The semiconductor structure according to claim 1, characterized in that, A buffer layer (9) is provided between the first semiconductor layer (1) and the second semiconductor layer (2).

3. The semiconductor structure according to claim 1, characterized in that, It also includes a fourth semiconductor structure (8), wherein the third semiconductor layer (3) is mesh-like, with the mesh corresponding to the second protrusion (202), the fourth semiconductor structure (8) is formed on the second protrusion (202), and the fourth semiconductor structure (8) has the same conductivity type as the first semiconductor layer (1) and the opposite conductivity type to the third semiconductor layer (3).

4. The semiconductor structure according to claim 1, characterized in that, The horizontal projection of the first protrusion (102) is circular, and after the second semiconductor layer (2) is grown, the horizontal projection of the second protrusion (202) is hexagonal.

5. The semiconductor structure according to claim 1, characterized in that, The first protrusion (102), the second protrusion (202) and the third protrusion (302) are strip-shaped.

6. The semiconductor structure according to claim 3, characterized in that, Also includes: The source (4), gate (5) and drain (6) are provided on the fourth semiconductor structure (8), the gate (5) is provided on the bottom surface of the third groove (301) between the third protrusions (302) of the third semiconductor layer (3), and the drain (6) is provided on the second surface of the first semiconductor layer (1).

7. The semiconductor structure according to claim 1, characterized in that, Also includes: The first electrode (10) is disposed on the top surface of the second protrusion (202); The second electrode (11) is disposed on the second surface of the first semiconductor layer (1).

8. A method for fabricating a semiconductor structure, characterized in that, include: A first semiconductor layer (1) is provided, the first semiconductor layer (1) includes opposing first and second surfaces, and the first surface forms a plurality of first protrusions (102). A second semiconductor layer (2) is formed covering the first surface. A plurality of second protrusions (202) are formed conformally on the surface of the second semiconductor layer (2) facing away from the first semiconductor layer (1). The second protrusions (202) correspond to the first protrusions (102). A second groove (201) is formed between two adjacent second protrusions (202). The second semiconductor layer (2) has the same conductivity type as the first semiconductor layer (1). The doping concentration of the second semiconductor layer (2) is less than that of the first semiconductor layer (1). A third semiconductor layer (3) is formed covering the second semiconductor layer (2); The third semiconductor layer (3) has a plurality of third protrusions (302) formed conformally on the surface opposite to the second semiconductor layer (2), and the third protrusions (302) correspond to the second protrusions (202).

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, It also includes, A mask layer (7) is formed covering the third semiconductor layer (3); A window (701) is formed on the mask layer (7), the window (701) exposing the portion of the third semiconductor layer (3) located on the top surface of the second protrusion (202); The portion of the third semiconductor layer (3) located on the top surface of the second protrusion (202) is etched to expose the top surface of the second protrusion (202).

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The method for preparing the semiconductor structure further includes: A fourth semiconductor structure (8) is formed on the top surface of the second protrusion (202).

11. The method for preparing a semiconductor structure according to claim 8, characterized in that, The first surface forms a plurality of first protrusions (102), including: Etch the first surface to form a plurality of first protrusions (102); or The first semiconductor layer (1) is conformally grown on the surface of a patterned substrate to form a plurality of first protrusions (102) on the first semiconductor layer (1).

12. The method for preparing a semiconductor structure according to claim 8, characterized in that, The method for preparing the semiconductor structure further includes: A source (4), a gate (5), and a drain (6) are formed. The source (4) is disposed on the top surface of the second protrusion (202) to contact the second semiconductor layer (2). The gate (5) is disposed on the bottom surface of the third groove (301) between the third protrusions (302) of the third semiconductor layer (3). The drain (6) is disposed on the second surface of the first semiconductor layer (1).

13. The method for preparing a semiconductor structure according to claim 8, characterized in that, The method for preparing the semiconductor structure further includes: A first electrode (10) is formed on the top surface of the second protrusion (202) to contact the third semiconductor layer (3); A second electrode (11) is formed on the second surface of the first semiconductor layer (1).

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