Silicon optical devices and methods of making the same

Abstract

The application provides a silicon optical device and a preparation method thereof. The silicon-based grating structure, the ridge waveguide and the strip waveguide are etched on the top layer of the SOI substrate in sequence according to different etching depths. Then, the two sides of the exposed ridge waveguide are doped. Next, the hard mask pattern is removed by adopting the chemical mechanical polishing (CMP) combined with the wet etching method. Finally, the modulator and the detector are prepared by the doping process. Since the remaining thickness of the hard mask pattern to be removed by the wet etching process is small, the buried oxygen layer is protected by the silicon dioxide layer, the damage to the optical waveguide device caused by directly using the wet etching process for a long time can be avoided, thus the defect that the buried oxygen layer is eroded to generate a lateral groove is not generated, and the transmission loss of the optical waveguide is effectively reduced, and the performance of the device is ensured.

Description

Technical Field

[0001] This invention belongs to the field of silicon-based optoelectronic technology, and in particular relates to a silicon photonic device and its fabrication method. Background Technology

[0002] In recent years, the research of high-performance, low-cost integrated chip systems using silicon-based optoelectronic technology has become a promising development direction. Silicon-based optoelectronic technology utilizes mature CMOS processes to connect active devices such as silicon modulators and photodetectors, as well as passive devices such as gratings, using silicon waveguides to achieve large-scale integration, thereby reducing the size and cost of devices and integrated systems. Silicon optoelectronic devices are mainly fabricated based on SOI wafers with a top silicon thickness of 220nm, and the devices are primarily formed into waveguide structures. Waveguide structures are generally formed through a three-step etching process: the first step forms a vertical grating structure, the second step forms a ridge waveguide structure, and the third step forms a strip waveguide structure. Silicon dioxide (SiO2) is commonly used as a hard mask during the etching process. To prevent the hard mask from being insufficient to block plasma bombardment during etching, annealing is typically used to ensure that the hard mask is not completely consumed after the three-step etching process. For silicon-based active optical devices such as modulators and detectors, the designed silicon region needs to be doped after etching to form the waveguide structure. Therefore, the remaining SiO2 hard mask needs to be removed. However, the hard mask becomes very difficult to remove after annealing. Simply increasing the wet etching time to remove the hard mask will erode the buried oxide layer (SiO2) on the side of the optical waveguide, causing undercuts 201. Figure 1 As shown, this has a significant impact on the transmission loss of the optical waveguide.

[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a silicon photonic device and its fabrication method, which solves the problem that the wet etching process in the silicon photonic device fabrication process causes lateral grooves, which in turn have a significant impact on the transmission loss of the optical waveguide.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon photonic device, the method comprising: 1) providing an SOI substrate, forming a hard mask layer on the SOI substrate, and patterning the hard mask layer to form a hard mask pattern; 2) etching the top silicon layer of the SOI substrate to form a ridge waveguide and a strip waveguide, wherein a portion of the thickness of the top silicon layer is retained on both sides of the ridge waveguide to form a connection region exposed outside the hard mask pattern, the ridge waveguide having a modulator region, and the strip waveguide having a detector region. 3) Doping the connection region located in the modulator region to form the connection portion of the modulator; 4) Depositing a silicon dioxide layer on the SOI substrate, the silicon dioxide layer covering the buried oxide layer exposed on the SOI substrate and the connection portion; 5) Removing a portion of the hard mask pattern by chemical mechanical polishing; 6) Removing the remaining portion of the hard mask pattern by wet etching to expose the modulator region and the detector region; 7) Doping the exposed modulator region and the detector region to form the modulator and the detector.

[0006] Optionally, step 1) further includes annealing the hard mask pattern to increase its hardness and density.

[0007] Optionally, steps 1) and 2) further include etching a silicon-based grating structure in the top silicon layer of the SOI substrate.

[0008] Optionally, step 2) includes: step 2-1), etching a silicon-based grating structure in the top silicon layer of the SOI substrate, wherein the thickness of the grating strips of the silicon-based grating structure is less than the thickness of the top silicon layer; step 2-2), etching a ridge waveguide in the top silicon layer of the SOI substrate, wherein a portion of the thickness of the top silicon layer is retained on both sides of the ridge waveguide to form a connection region exposed outside the hard mask pattern; and step 2-3), etching a strip waveguide in the top silicon layer of the SOI substrate, wherein the thickness of the strip waveguide is the same as the thickness of the top silicon layer.

[0009] Optionally, the material of the hard mask pattern includes silicon dioxide.

[0010] Optionally, in step 5), the thickness of the hard mask pattern is removed by chemical mechanical polishing to a degree of 70% to 95% of the total thickness of the hard mask pattern.

[0011] Optionally, step 3) doping the connection region located in the modulator region includes: step 3-1) heavily doping the connection region on one side of the ridge waveguide with P-type doping to form a P-type connection region; step 3-2) heavily doping the connection region on the other side of the ridge waveguide with N-type doping to form an N-type connection region.

[0012] Optionally, step 7) doping the modulator region and the detector region includes: step 7-1) performing P-type doping and N-type doping on both sides of the modulator region respectively to form a P-type doped region and an N-type doped region of the modulator, wherein the P-type doped region is connected to the P-type connection region and the N-type doped region is connected to the N-type connection region.

[0013] Optionally, step 7) of doping the modulator region and the detector region further includes: step 7-2) of heavily doping the detector region with P-type to form a P+ type doped region; and step 7-3) of heavily doping the detector region with P-type to form a P++ type contact region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P+ type doped region.

[0014] Optionally, step 7) of doping the modulator region and the detector region further includes: step 7-4), performing heavy P-type doping and heavy N-type doping on portions of the top silicon connected to the P-type connection region and the N-type connection region, respectively, to form a P++ type contact region connected to the P-type connection region and an N++ type contact region connected to the N-type connection region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P-type connection region, and the doping concentration of the N++ type contact region is greater than the doping concentration of the N-type connection region.

[0015] The present invention also provides a silicon photonic device, comprising an SOI substrate, wherein a ridge waveguide and a strip waveguide are formed in the top silicon layer of the SOI substrate, and a portion of the top silicon layer is retained on both sides of the ridge waveguide to form a connection portion, the connection portion comprising a P-type connection region and an N-type connection region respectively located on both sides of the ridge waveguide, the ridge waveguide is provided with a modulator, the modulator comprising a P-type doped region and an N-type doped region, the P-type doped region being connected to the P-type connection region, the N-type doped region being connected to the N-type connection region, and the strip waveguide is provided with a detector, the detector comprising a P+ type doped region disposed on the strip waveguide and a P++ type contact region located on the surface of the P+ type doped region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P+ type doped region.

[0016] Optionally, the modulator further includes a P++ type contact region connected to the P-type connection region and an N++ type contact region connected to the N-type connection region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P-type connection region, and the doping concentration of the N++ type contact region is greater than the doping concentration of the N-type connection region.

[0017] Optionally, a silicon-based grating structure is also formed in the top silicon layer of the SOI substrate.

[0018] Optionally, the thickness of the grating strips in the silicon-based grating structure is less than the thickness of the top silicon layer, and the thickness of the grating strips can be 10 to 100 nanometers.

[0019] Optionally, the width of the grating strips in the silicon-based grating structure is 300–400 nanometers, and the spacing between the grating strips is 300–400 nanometers.

[0020] Optionally, the height of the ridge waveguide is greater than the grating thickness of the silicon-based grating structure.

[0021] As described above, the silicon photonic device and its fabrication method of the present invention have the following beneficial effects:

[0022] This invention provides a method for fabricating silicon photonic devices. A silicon-based grating structure, a ridge waveguide, and a strip waveguide are sequentially etched onto the top silicon layer of an SOI substrate, according to different etching depths. First, the exposed sides of the ridge waveguide are doped. Then, a combination of chemical mechanical polishing (CMP) and wet etching is used to remove the hard mask pattern. Specifically, CMP is used to remove most of the hard mask pattern, followed by wet etching to remove the remaining pattern. Because the thickness of the remaining hard mask pattern removed by wet etching is relatively small, and the buried oxide layer is protected by a silicon dioxide layer, damage to the optical waveguide device caused by prolonged wet etching is avoided. Therefore, defects such as lateral trenches caused by erosion of the buried oxide layer are prevented, effectively reducing the transmission loss of the optical waveguide and ensuring device performance.

[0023] Based on the above preparation method, the present invention adjusts the doping order of each region. At the same time, the preparation method of the present invention is compatible with standard CMOS process and can be widely used in process flow that requires removal of hard mask. Attached Figure Description

[0024] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0025] Figure 1 The diagram shows a lateral groove caused by erosion of the buried oxide layer on the side of an optical waveguide in the prior art.

[0026] Figures 2 to 14 The diagram shows the structural schematics of each step in the fabrication method of the silicon photonic device according to an embodiment of the present invention.

[0027] Component designation explanation

[0028] 101 silicon substrate

[0029] 102 Buried Oxygen Layer

[0030] 103 Top-layer silicon

[0031] 104 Hard Mask Pattern

[0032] 105 Silicon-based grating structure

[0033] 106 Ridge Waveguide

[0034] 107 Connection Area

[0035] 108 strip waveguide

[0036] 109 P-type connection area

[0037] 110 N-type connection area

[0038] 111 Silicon Dioxide Layer

[0039] 112 P-type doped region

[0040] 113 N-type doped region

[0041] 114 P+ type doped regions

[0042] 115 P++ type contact area

[0043] 116 P++ type contact area

[0044] 117 N++ type contact area

[0045] 201 Side Groove Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0048] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0049] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0051] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] like Figures 2 to 14 As shown, this embodiment provides a method for fabricating a silicon photonic device, the method comprising:

[0054] like Figures 2-3 As shown, step 1) is performed first, an SOI substrate is provided, a hard mask layer is formed on the SOI substrate, and the hard mask layer is patterned to form a hard mask pattern 104.

[0055] In one embodiment, such as Figure 1 As shown, the SOI substrate includes a silicon substrate 101, a buried oxide layer 102 and a top silicon layer 103 stacked sequentially, and the thickness of the top silicon layer 103 can be, for example, 220 nanometers.

[0056] In one embodiment, step 1) includes:

[0057] Step 1-1): A silicon dioxide mask layer is deposited on the top silicon 103 by plasma-enhanced chemical vapor deposition (PECVD).

[0058] Steps 1-2): A photoresist layer is formed on the silicon dioxide mask layer by spin coating, and a photolithographic pattern is formed by exposure and development processes.

[0059] Steps 1-3) involve forming a hard mask pattern 104 in the silicon dioxide mask layer using an etching process. The material of the hard mask pattern 104 includes silicon dioxide, such as... Figure 3 As shown.

[0060] Steps 1-4) Anneal the hard mask pattern 104 to increase its hardness and density, so that it has sufficient blocking ability in subsequent etching processes and avoids premature consumption that could damage the waveguide structure.

[0061] like Figures 4-6 As shown, then step 2) is performed, etching the top silicon 103 of the SOI substrate to form a ridge waveguide 106 and a strip waveguide 108. The ridge waveguide 106 retains a portion of the thickness of the top silicon 103 on both sides to form a connection region 107 exposed outside the hard mask pattern 104. The ridge waveguide 106 has a modulator region, and the strip waveguide 108 has a detector region.

[0062] In one embodiment, step 2) includes:

[0063] like Figure 4 As shown, in step 2-1), a silicon-based grating structure 105 is etched in the top silicon layer 103 of the SOI substrate. The thickness of the grating strips in the silicon-based grating structure 105 is less than the thickness of the top silicon layer 103. Specifically, the corresponding grating period (including grating strip width and grating strip spacing) and grating strip thickness can be designed according to the required reflection parameters. For example, in one embodiment, the width of the grating strip can be 300-400 nanometers, the spacing of the grating strips can be 300-400 nanometers, and the thickness of the grating strips can be 10-100 nanometers.

[0064] like Figure 5 As shown, in step 2-2), a ridge waveguide 106 is etched in the top silicon 103 of the SOI substrate. The top silicon 103 with a partial thickness is retained on both sides of the ridge waveguide 106 to form a connection region 107 exposed outside the hard mask pattern 104. The height of the ridge waveguide 106 is greater than the grating thickness of the silicon grating structure 105.

[0065] like Figure 6 As shown, in steps 2-3), a strip waveguide 108 is etched in the top silicon 103 of the SOI substrate, and the thickness of the strip waveguide 108 is the same as the thickness of the top silicon 103.

[0066] It should be noted that the above etching processes can also be protected in the areas that do not need to be etched by preparing a photoresist layer.

[0067] like Figure 7 As shown, then step 3) is performed to dope the connection region 107 located in the modulator region to form the connection portion of the modulator.

[0068] In one embodiment, step 3) doping the connection region 107 located in the modulator region includes:

[0069] Step 3-1) P-type heavy doping is performed on the connection region 107 on one side of the ridge waveguide 106 to form a P-type connection region 109.

[0070] Step 3-2) The connection region 107 on the other side of the ridge waveguide 106 is heavily doped with N-type to form an N-type connection region 110.

[0071] like Figure 8 As shown, then step 4) is performed, depositing a silicon dioxide layer 111 on the SOI substrate, the silicon dioxide layer 111 covering the buried oxide layer 102 exposed on the SOI substrate and the connection portion.

[0072] For example, the silicon dioxide layer 111 can be deposited on the SOI substrate using plasma-enhanced chemical vapor deposition (PECVD). This silicon dioxide layer 111 provides a relatively smooth surface for subsequent chemical mechanical polishing (CMP) processes, facilitating the CMP process. Furthermore, the silicon dioxide layer 111 covers the exposed buried oxide layer 102, protecting it during subsequent wet etching processes.

[0073] like Figures 8-9 As shown, then step 5) is performed, in which a portion of the hard mask pattern 104 is removed by a chemical mechanical polishing process.

[0074] In one embodiment, step 5) removes 70% to 95% of the total thickness of the hard mask pattern 104 by chemical mechanical polishing (CMP). For example, CMP can remove 80% of the total thickness of the hard mask pattern 104. This step removes most of the thickness of the hard mask pattern 104 by mechanical polishing, which reduces the overall removal time of the hard mask pattern 104 and improves process efficiency. Furthermore, it significantly shortens the time required for subsequent wet etching to remove the hard mask pattern 104, avoiding damage to the optical waveguide device caused by prolonged wet etching. Therefore, it prevents the erosion of the buried oxide layer 102, thus avoiding lateral trench defects and effectively reducing the transmission loss of the optical waveguide, ensuring device performance.

[0075] like Figure 10 As shown, then step 6) is performed, in which the remaining portion of the hard mask pattern 104 is removed by a wet etching process to expose the modulator region and the detector region.

[0076] Since step 5) removes most of the thickness of the hard mask pattern 104, the time required for this wet etching process is greatly reduced. This avoids the damage to the optical waveguide device caused by directly using the wet etching process for a long time. Therefore, the defect of lateral grooves caused by the erosion of the buried oxide layer 102 will not occur, thereby effectively reducing the transmission loss of the optical waveguide and ensuring the performance of the device.

[0077] like Figures 11-14 As shown, step 7) is performed last to dope the exposed modulator region and detector region to form the modulator and detector.

[0078] Specifically, step 7) involves doping the modulator region and the detector region, including:

[0079] like Figure 11 As shown, in step 7-1), P-type doping and N-type doping are performed on both sides of the modulator region to form the P-type doped region 112 and the N-type doped region 113 of the modulator. The P-type doped region 112 is connected to the P-type connection region 109, and the N-type doped region 113 is connected to the N-type connection region 110.

[0080] like Figure 12 As shown, step 7-2) is performed to heavily dope the detector region with P-type doping to form a P+ type doped region 114.

[0081] like Figure 13As shown, in step 7-3), the detector region is heavily p-doped to form a p++ type contact region 115, wherein the doping concentration of the p++ type contact region 115 is greater than the doping concentration of the p+ type doped region 114.

[0082] like Figure 14 As shown, in step 7-4), the top silicon 103 connected to the P-type connection region 109 and the N-type connection region 110 is heavily doped with P-type and N-type respectively to form a P++ type contact region 116 connected to the P-type connection region 109 and an N++ type contact region 117 connected to the N-type connection region 110. The doping concentration of the P++ type contact region 116 is greater than that of the P-type connection region 109, and the doping concentration of the N++ type contact region 117 is greater than that of the N-type connection region 110. The N++ type contact region 117 of the present invention is connected to the N-type doped region 113 through the N-type connection region 110, which can effectively reduce the lead-out structure resistance while avoiding the influence of the high concentration of N++ type contact region 117 on the N-type doped region 113. Similarly, the P++ type contact region 116 of the present invention is connected to the P-type doped region 112 through the P-type connection region 109, which can effectively reduce the lead-out structure resistance while avoiding the influence of the high concentration of N++ type contact region 117 on the N-type doped region 113. It should be noted that the P++ type contact region 115 of the detector and the P++ contact region 116 of the modulator can be implemented in the same photolithography and ion implantation step, and both have the same doping concentration.

[0083] like Figure 14 As shown, this embodiment also provides a silicon photonic device, including an SOI substrate. A ridge waveguide 106 and a strip waveguide 108 are formed in the top silicon layer 103 of the SOI substrate. A portion of the top silicon layer is retained on both sides of the ridge waveguide 106 to form a connection portion. The connection portion includes a P-type connection region 109 and an N-type connection region 110 located on both sides of the ridge waveguide 106, respectively. The ridge waveguide 106 is provided with a modulator, which includes a P-type doped region 112 and an N-type doped region 113. The P-type doped region 112 is connected to the P-type connection region, and the N-type doped region is connected to the N-type connection region. The strip waveguide 108 is provided with a detector, which includes a P+ type doped region 114 disposed on the strip waveguide 108 and a P++ type contact region 115 located on the surface of the P+ type doped region 114, wherein the doping concentration of the P++ type contact region 115 is greater than the doping concentration of the P+ type doped region 114.

[0084] In one embodiment, the modulator further includes a P++ type contact region 116 connected to the P-type connection region and an N++ type contact region 117 connected to the N-type connection region, wherein the doping concentration of the P++ type contact region 116 is greater than the doping concentration of the P-type connection region 109, and the doping concentration of the N++ type contact region 117 is greater than the doping concentration of the N-type connection region 110.

[0085] In one embodiment, a silicon-based grating structure 105 is also formed in the top silicon layer of the SOI substrate.

[0086] In one embodiment, the thickness of the grating strips in the silicon-based grating structure 105 is less than the thickness of the top silicon layer, and the thickness of the grating strips can be 10 to 100 nanometers.

[0087] In one embodiment, the width of the grating strips of the silicon-based grating structure 105 is 300-400 nanometers, and the spacing between the grating strips is 300-400 nanometers.

[0088] In one embodiment, the height of the ridge waveguide 106 is greater than the grating thickness of the silicon-based grating structure 105.

[0089] The N++ type contact region 117 of the present invention is connected to the N-type doped region 113 through the N-type connection region 110, which can effectively reduce the lead-out structure resistance while avoiding the influence of the high concentration of N++ type contact region 117 on the N-type doped region 113. At the same time, the P++ type contact region 116 of the present invention is connected to the P-type doped region 112 through the P-type connection region 109, which can effectively reduce the lead-out structure resistance while avoiding the influence of the high concentration of N++ type contact region 117 on the N-type doped region 113.

[0090] As described above, the method for fabricating silicon photonic devices of the present invention has the following beneficial effects:

[0091] This invention provides a silicon photonic device and its fabrication method. A silicon-based grating structure 105, a ridge waveguide 106, and a strip waveguide 108 are sequentially etched on the top silicon layer 103 of an SOI substrate according to different etching depths. First, the exposed sides of the ridge waveguide 106 are doped. Then, a hard mask pattern 104 is removed using a combination of chemical mechanical polishing (CMP) and wet etching. Specifically, most of the hard mask pattern 104 is removed using CMP, and the remaining hard mask pattern 104 is completely removed using wet etching. Because the thickness of the remaining hard mask pattern 104 after wet etching is relatively small, and the buried oxide layer 102 is protected by a silicon dioxide layer 111, damage to the optical waveguide device caused by prolonged wet etching is avoided. Therefore, defects such as lateral trenches caused by erosion of the buried oxide layer 102 are not produced, effectively reducing the transmission loss of the optical waveguide and ensuring device performance.

[0092] Based on the above preparation method, the present invention adjusts the doping order of each region. At the same time, the preparation method of the present invention is compatible with standard CMOS process and can be widely used in process flow that requires removal of hard mask.

[0093] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon photonic device, characterized in that, The preparation method includes: 1) Provide an SOI substrate, form a hard mask layer on the SOI substrate, and perform patterning processing on the hard mask layer to form a hard mask pattern; 2) Etch the top silicon layer of the SOI substrate to form a ridge waveguide and a strip waveguide. The ridge waveguide has a portion of the thickness of the top silicon layer on both sides to form a connection region exposed outside the hard mask pattern. The ridge waveguide has a modulator region and the strip waveguide has a detector region. 3) The connection region located in the modulator region is doped to form the connection portion of the modulator; 4) A silicon dioxide layer is deposited on the SOI substrate, the silicon dioxide layer covering the buried oxide layer exposed on the SOI substrate and the interconnection portion; 5) A portion of the hard mask pattern is removed using a chemical mechanical polishing process; 6) Remove the remaining portion of the hard mask pattern using a wet etching process to expose the modulator region and the detector region; 7) The exposed modulator region and detector region are doped to form a modulator and a detector.

2. The method for fabricating a silicon photonic device according to claim 1, characterized in that: Step 1) also includes annealing the hard mask pattern to increase its hardness and density.

3. The method for fabricating a silicon photonic device according to claim 1, characterized in that: Steps 1) and 2) also include etching a silicon-based grating structure in the top silicon layer of the SOI substrate.

4. The method for fabricating a silicon photonic device according to claim 3, characterized in that: Step 2) includes: Step 2-1): A silicon-based grating structure is etched in the top silicon layer of the SOI substrate, wherein the thickness of the grating strips of the silicon-based grating structure is less than the thickness of the top silicon layer; Step 2-2): A ridge waveguide is etched in the top silicon layer of the SOI substrate, and a portion of the top silicon layer is retained on both sides of the ridge waveguide to form a connection region exposed outside the hard mask pattern. Steps 2-3) are used to etch a strip waveguide in the top silicon layer of the SOI substrate, wherein the thickness of the strip waveguide is the same as the thickness of the top silicon layer.

5. The method for fabricating a silicon photonic device according to claim 1, characterized in that: The material of the hard mask pattern includes silicon dioxide.

6. The method for fabricating a silicon photonic device according to claim 1, characterized in that: Step 5) Remove 70% to 95% of the total thickness of the hard mask pattern by chemical mechanical polishing.

7. The method for fabricating a silicon photonic device according to claim 1, characterized in that: Step 3) Doping the connection region located in the modulator region includes: Step 3-1) P-type heavy doping is performed on the connection region on one side of the ridge waveguide to form a P-type connection region; Step 3-2) involves N-type heavy doping of the connection region on the other side of the ridge waveguide to form an N-type connection region.

8. The method for fabricating a silicon photonic device according to claim 7, characterized in that: Step 7) Doping the modulator region and the detector region includes: Step 7-1): P-type doping and N-type doping are performed on both sides of the modulator region to form the P-type doped region and the N-type doped region of the modulator. The P-type doped region is connected to the P-type connection region, and the N-type doped region is connected to the N-type connection region.

9. The method for fabricating a silicon photonic device according to claim 8, characterized in that, Step 7) Doping the modulator region and the detector region further includes: Step 7-2), the detector region is heavily p-type doped to form a p+ type doped region; Step 7-3) involves P-type heavy doping of the detector region to form a P++ type contact region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P+ type doped region.

10. The method for fabricating a silicon photonic device according to claim 9, characterized in that: Step 7) Doping the modulator region and the detector region further includes: Step 7-4): The top silicon portion connected to the P-type connection region and the N-type connection region is heavily doped with P-type and N-type respectively to form a P++ type contact region connected to the P-type connection region and an N++ type contact region connected to the N-type connection region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P-type connection region, and the doping concentration of the N++ type contact region is greater than the doping concentration of the N-type connection region.

11. A silicon photonic device fabricated by the method for fabricating a silicon photonic device according to any one of claims 1 to 10, characterized in that, The device includes an SOI substrate, in which a ridge waveguide and a strip waveguide are formed in the top silicon layer. A portion of the top silicon layer is retained on both sides of the ridge waveguide to form a connection portion. The connection portion includes a P-type connection region and an N-type connection region located on both sides of the ridge waveguide. The ridge waveguide is equipped with a modulator, which includes a P-type doped region and an N-type doped region. The P-type doped region is connected to the P-type connection region, and the N-type doped region is connected to the N-type connection region. The strip waveguide is equipped with a detector, which includes a P+ type doped region disposed on the strip waveguide and a P++ type contact region located on the surface of the P+ type doped region. The doping concentration of the P++ type contact region is greater than the doping concentration of the P+ type doped region.

12. The silicon photonic device according to claim 11, characterized in that, The modulator further includes a P++ type contact region connected to the P-type connection region and an N++ type contact region connected to the N-type connection region, wherein the doping concentration of the P++ type contact region is greater than the doping concentration of the P-type connection region, and the doping concentration of the N++ type contact region is greater than the doping concentration of the N-type connection region.

13. The silicon photonic device according to claim 11, characterized in that, A silicon-based grating structure is also formed in the top silicon layer of the SOI substrate.

14. The silicon photonic device according to claim 13, characterized in that, The thickness of the grating strips in the silicon-based grating structure is less than the thickness of the top silicon layer, and the thickness of the grating strips is 10~100 nanometers.

15. The silicon photonic device according to claim 13, characterized in that, The width of the grating bars in the silicon-based grating structure is 300-400 nanometers, and the spacing between the grating bars is 300-400 nanometers.

16. The silicon photonic device according to claim 13, characterized in that, The height of the ridge waveguide is greater than the thickness of the grating strips in the silicon-based grating structure.

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