Clock delay circuit and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a clock delay circuit and a memory. The clock delay circuit comprises: a delay circuit configured to receive an initial clock signal and delay the initial clock signal to output a target clock signal; and a temperature control circuit connected to the delay circuit and configured to control the delay circuit to adjust a rising edge time and / or a falling edge time of the target clock signal according to temperature information. The rising edge time and / or the falling edge time of the clock signal is adjusted through the temperature information, so as to adjust a duty cycle of the clock signal and compensate for a duty cycle offset of the clock signal caused by temperature.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a clock delay circuit and a memory. Background Technology

[0002] With the development of semiconductor technology, various industries have increasingly higher requirements for the performance, power consumption and reliability of memory. The operation of memory is based on multiple clock signals with different phases, and these clock signals are generated by the memory's delay-locked loop (DLL).

[0003] For DLL structures, there are a large number of inverter transmission chains inside. If the DLL structure operates under high-frequency signals, the large number of inverter transmission chains will cause the accumulation of signal jitter, resulting in a duty cycle shift of the signal. If the duty cycle shift is too large, the signal may even be lost.

[0004] The applicant discovered in the research that different temperatures, different driving voltages, and different process flows can all cause duty cycle shifts in the signal in the DLL structure. While deviations in the process flow cannot be avoided artificially, the influence of temperature can be compensated for by adjusting the circuit structure and adapting the corresponding adjustment circuit. Summary of the Invention

[0005] This disclosure provides a clock delay circuit and a memory that adjusts the rise time and / or fall time of a clock signal based on temperature information, thereby adjusting the duty cycle of the clock signal to compensate for the duty cycle offset of the clock signal caused by temperature.

[0006] One embodiment of this disclosure provides a clock delay circuit, including: a delay circuit configured to receive an initial clock signal and delay the initial clock signal to output a target clock signal; and a temperature control circuit connected to the delay circuit, configured to control the delay circuit to adjust the rise time and / or fall time of the target clock signal according to temperature information.

[0007] As temperature increases, the duty cycle of the clock signal generated in the memory increases, meaning the duty cycle of the initial clock signal received by the temperature control circuit increases. For a target clock signal that is active at a high level, the duty cycle of the target clock signal is reduced by decreasing the rise time and / or increasing the fall time; for a target clock signal that is active at a low level, the rise time and / or fall time are increased, thus compensating for the effect of temperature on the clock signal's duty cycle. Conversely, as temperature decreases, the duty cycle of the clock signal generated in the memory decreases, meaning the duty cycle of the initial clock signal received by the temperature control circuit decreases. For a target clock signal that is active at a high level, the duty cycle of the target clock signal is increased by increasing the rise time and / or decreasing the fall time; for a target clock signal that is active at a low level, the duty cycle of the target clock signal is increased by decreasing the rise time and / or decreasing the fall time, thus compensating for the effect of temperature on the clock signal's duty cycle.

[0008] Additionally, the temperature control circuit includes: a first decoding unit configured to acquire temperature information and decode the temperature information to generate a first decoded signal; and a delay circuit configured to adjust the falling edge time of a target clock signal based on the first decoded signal.

[0009] Furthermore, the first decoded signal is set as a multi-bit binary signal, and each symbol in the first decoded signal corresponds to a different first adjustment time. The delay circuit obtains the first adjustment time corresponding to the first decoded signal based on the value of each symbol in the first decoded signal, and adjusts the falling edge time of the target clock signal based on the first adjustment time. By setting the first decoded signal as a multi-bit binary signal, the first adjustment time at different temperatures can be accurately controlled, thereby accurately adjusting the falling edge time of the target clock signal, thus improving the accuracy of the clock delay circuit in compensating for the duty cycle of the clock signal.

[0010] In addition, the temperature control circuit also includes: a second decoding unit configured to generate a second decoding signal from the temperature information; and a delay circuit configured to adjust the rise time of the target clock signal based on the second decoding signal.

[0011] Furthermore, the second decoded signal is set as a multi-bit binary signal, and each symbol in the second decoded signal corresponds to a different second adjustment time. The delay circuit obtains the second adjustment signal corresponding to the second decoded signal based on the value of each symbol in the second decoded signal, and adjusts the rise time of the target clock signal based on the second adjustment signal. By setting the second decoded signal as a multi-bit binary signal, the second adjustment time at different temperatures can be accurately controlled, thereby accurately adjusting the rise time of the target clock signal and improving the accuracy of the clock delay circuit in compensating for the duty cycle of the clock signal.

[0012] In addition, the first decoding unit and the second decoding unit are located in the same decoding unit.

[0013] In addition, the second decoding unit includes: a logic circuit, each input terminal for receiving different symbols in the first decoding signal, and an output terminal for outputting the second decoding signal.

[0014] In addition, the temperature control circuit also includes a temperature sensing unit configured to sense the temperature of the memory where the clock delay circuit is located and provide temperature information.

[0015] Additionally, the delay circuit includes at least one of a first time adjustment circuit and a second time adjustment circuit, and an adjustment circuit; the adjustment circuit is configured to receive an initial clock signal and delay the initial clock signal to output a target clock signal; the first time adjustment circuit is configured to control the delay circuit to adjust the falling edge time of the target clock signal according to temperature information; the second time adjustment circuit is configured to control the delay circuit to adjust the rising edge time of the target clock signal according to temperature information.

[0016] Additionally, the adjustment circuit includes: a first PMOS transistor, whose gate is used to receive an initial clock signal, whose source is used to receive a power supply signal, and whose drain is connected to the drain of a first NMOS transistor; the gate of the first NMOS transistor is used to receive a clock signal, and its source is used to ground; the drains of the first PMOS transistor and the drains of the first NMOS transistor are used to output a target clock signal.

[0017] In addition, the first-time adjustment circuit includes: a second PMOS transistor, the gate of which is connected to the gate of the first PMOS transistor, the source of which is connected to the first driving transistor group, and the drain of which is connected to the drain of the first PMOS transistor; the first driving transistor group includes: at least one driving PMOS transistor connected in parallel, wherein the gate of each driving PMOS transistor is used to receive temperature information, the source of which is used to receive power signals, and the drain of which is connected to the source of the first PMOS transistor.

[0018] In addition, the second timing adjustment circuit includes: a second NMOS transistor, the gate of which is connected to the gate of the first NMOS transistor, the source of which is connected to the second driving transistor group, and the drain of which is connected to the drain of the first NMOS transistor; the second driving transistor group includes: at least one driving NMOS transistor connected in parallel, wherein the gate of each driving NMOS transistor is used to receive temperature information, the source of which is used to ground, and the drain of which is connected to the source of the first NMOS transistor.

[0019] Furthermore, the size of the first PMOS transistor is three times that of the first NMOS transistor. By adjusting the sizes of the first PMOS transistor and the first NMOS transistor, the driving capabilities of the first PMOS transistor and the second NMOS transistor are made consistent under the same effective gate voltage, thereby improving the accurate control of the rise time and fall time of the generated target clock signal.

[0020] In addition, the multiple driving PMOS transistors are of the same size. By adjusting the size of the driving PMOS transistors, it is ensured that each driving PMOS transistor in the first driving transistor group adjusts the falling edge time of the target clock signal to the same degree, thereby improving the accurate control of the falling edge time of the generated target clock signal.

[0021] Another embodiment of this disclosure also provides a memory, including: a time-delay phase-locked loop (TDL) for providing multiple initial clock signals with different phases; and an output delay circuit, configured based on the clock delay circuit provided in the above embodiment, connected to the TLL, and configured to delay the initial clock signals to output a target clock signal, and adjust the rise time and / or fall time of the initial clock signals through temperature information to adjust the duty cycle of the clock signal generated by the TLL, so as to compensate for the influence of temperature on the duty cycle of the clock signal generated by the TLL. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a clock delay circuit provided in an embodiment of the present disclosure;

[0024] Figures 2-4 This is a schematic diagram illustrating the effect of temperature on the duty cycle of the clock signal in a memory.

[0025] Figures 5-8 This is a schematic diagram of the structure of a temperature control circuit provided in an embodiment of the present disclosure;

[0026] Figure 9 for Figure 6 A schematic diagram of a specific structure of the temperature control circuit shown;

[0027] Figure 10This is a schematic diagram of the structure of a delay circuit provided in an embodiment of the present disclosure;

[0028] Figure 11 A schematic diagram of the structure of a memory provided for another embodiment of this disclosure. Detailed Implementation

[0029] As the background technology shows, DLL structures contain a large number of inverter transmission chains. If the DLL structure operates under high-frequency signals, the large number of inverter transmission chains will cause the accumulation of signal jitter, resulting in a duty cycle offset. If the duty cycle offset is too large, the signal may even be lost. Different temperatures, different driving voltages, and different process flows will all cause duty cycle offsets in the DLL structure. While process flow deviations cannot be avoided artificially, the influence of temperature can be compensated for by adjusting the circuit structure and adapting the corresponding adjustment circuit.

[0030] One embodiment of this disclosure provides a clock delay circuit that adjusts the rise time and / or fall time of a clock signal based on temperature information, thereby adjusting the duty cycle of the clock signal to compensate for the duty cycle offset of the clock signal caused by temperature.

[0031] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0032] Figure 1 This is a schematic diagram of the structure of a clock delay circuit provided in an embodiment of the present disclosure. Figures 2-4 This is a schematic diagram illustrating the effect of temperature on the duty cycle of the clock signal in a memory. Figures 5-8 This is a schematic diagram of the structure of a temperature control circuit provided in an embodiment of the present disclosure. Figure 9 for Figure 6 The diagram shows a specific structure of a temperature control circuit. Figure 10 This is a schematic diagram of a delay circuit provided in an embodiment of the present disclosure. The clock delay circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0033] refer to Figure 1 The clock delay circuit 10 includes:

[0034] The delay circuit 100 is configured to receive an initial clock signal and delay the initial clock signal to output a target clock signal.

[0035] Temperature control circuit 200, connected to delay circuit 100, is configured to control delay circuit 100 to adjust the rise time and / or fall time of target clock signal according to temperature information.

[0036] For the clock signal transmitted in the memory, refer to Figure 2 If the input signal IN is a high-level active clock, the PMOS controls the falling edge of the output signal OUT based on the rising edge of the input signal IN, while the NMOS controls the rising edge of the output signal OUT based on the falling edge of the input signal IN; (Reference) Figure 3 If the input signal IN is a high-level active clock, the PMOS controls the falling edge of the output signal OUT based on the rising edge of the input signal IN, while the NMOS controls the rising edge of the output signal OUT based on the rising edge of the input signal IN; (Reference) Figure 4 Assume that the duty cycle of the initial clock signal generated by the memory at a preset temperature A is B.

[0037] When the temperature of the memory is less than A, based on Figure 4 It can be seen that as the threshold voltage Vth of the NMOS increases, the effective gate voltage decreases when the NMOS is driven based on the same gate voltage Vn. At this time, the source-drain current Ids of the NMOS decreases, weakening the driving capability and pull-down capability of the NMOS. Consequently, the falling edge time of the output signal OUT increases, exhibiting… Figure 2 L1 or shown Figure 3 As shown in K3; when the threshold voltage Vth of the PMOS decreases, and the PMOS is driven based on the same gate voltage Vp, the effective gate voltage decreases. At this time, the source-drain current Ids of the PMOS decreases, weakening the driving capability and pull-up capability of the PMOS. Consequently, the rise time of the output signal OUT increases, exhibiting… Figure 2 L3 or shown Figure 3 K3 as shown; and by Figure 4 The voltage V1 shown is greater than the voltage V2, meaning that the threshold voltage of the PMOS changes with temperature to a greater extent than the threshold voltage of the NMOS. This means the rise time of the output signal OUT increases more than the fall time, resulting in a decrease in the duty cycle of the output signal OUT. In other words, the duty cycle of the clock signal generated by the memory is less than B. In this embodiment, the temperature control circuit 200 adjusts the rise time of the target clock signal (output signal OUT) and / or increases the fall time of the target clock signal (output signal OUT) through the temperature information control delay circuit 100, thereby increasing the duty cycle of the target clock signal and compensating for the effect of temperature on the duty cycle of the clock signal generated by the memory.

[0038] When the temperature of the memory is greater than A, based on Figure 4 It can be seen that as the threshold voltage Vth of the NMOS decreases, when the NMOS is driven based on the same gate voltage Vn, the effective gate voltage increases. At this time, the source-drain current Ids of the NMOS increases, which enhances the driving capability and pull-up capability of the NMOS, and shortens the falling edge time of the output signal OUT. Figure 2 The L2 or shown Figure 3 As shown in L4, with the increase of the PMOS threshold voltage Vth, when the PMOS is driven based on the same gate voltage Vp, the effective gate voltage rises. At this time, the PMOS source-drain current Ids increases, enhancing the PMOS's driving capability and pull-up capability. This shortens the fall time of the output signal OUT, resulting in… Figure 2 L1 or shown Figure 3 K4 as shown; and by Figure 4 The voltage V1 shown is greater than the voltage V2, meaning that the threshold voltage of the PMOS changes with temperature to a greater extent than the threshold voltage of the NMOS. This means the rise time of the output signal OUT decreases more than the fall time, resulting in an increased duty cycle for the output signal OUT. Therefore, the duty cycle of the clock signal generated by the memory is greater than B. In this embodiment, the temperature control circuit 200 adjusts the rise time of the target clock signal (output signal OUT) and / or decreases the fall time of the target clock signal (output signal OUT) through the temperature information control delay circuit 100 to reduce the duty cycle of the target clock signal, thereby compensating for the effect of temperature on the duty cycle of the clock signal generated by the memory.

[0039] In summary, as temperature increases, the duty cycle of the clock signal generated in the memory increases, meaning the duty cycle of the initial clock signal received by the temperature control circuit increases. For a high-level active target clock signal, the duty cycle is reduced by decreasing the rise time and / or increasing the fall time; for a low-level active target clock signal, the rise time and / or fall time are increased, thus compensating for the temperature's effect on the clock signal's duty cycle. Conversely, as temperature decreases, the duty cycle of the clock signal generated in the memory decreases, meaning the duty cycle of the initial clock signal received by the temperature control circuit 200 decreases. For a high-level active target clock signal, the rise time and / or fall time are increased; for a low-level active target clock signal, the rise time and / or fall time are decreased, thus increasing the target clock signal's duty cycle, thereby compensating for the temperature's effect on the clock signal's duty cycle.

[0040] Regarding the temperature control circuit 200 provided in this embodiment, in some embodiments, refer to Figure 5 The temperature control circuit 200 includes: a first decoding unit 201 configured to acquire temperature information and decode the temperature information to generate a first decoding signal; and a delay circuit 100 configured to adjust the falling edge time of a target clock signal based on the first decoding signal.

[0041] In some embodiments, the temperature control circuit 200 further includes: a second decoding unit 202 configured to decode temperature information to generate a second decoded signal; and a delay circuit 100 configured to adjust the rise time of a target clock signal based on the second decoded signal; correspondingly, in some embodiments, reference... Figure 6 The second decoding unit 202 can also be configured to decode the first decoding signal to generate the second decoding signal.

[0042] In some embodiments, reference Figure 7 The temperature control circuit 200 may only have a second decoding unit 202, which is configured to decode the temperature information to generate a second decoding signal; the delay circuit 100 is configured to adjust the rise time of the target clock signal based on the second decoding signal.

[0043] In some embodiments, reference Figure 8 The temperature control circuit 200 is equipped with a first decoding unit 201 and a second decoding unit 202. The second decoding unit 202 is configured to decode the temperature information to generate a second decoding signal; the first decoding unit 201 is configured to decode the second decoding signal to generate a first decoding signal; the delay circuit 100 is configured to adjust the falling edge time of the target clock signal based on the first decoding signal and adjust the rising edge time of the target clock signal based on the second decoding signal.

[0044] It should be noted that generating a first decoding signal when the temperature information indicates a low temperature and generating a second decoding signal when the temperature information indicates a high temperature does not constitute a limitation of this embodiment. In other embodiments, it can be configured such that generating a first decoding signal when the temperature information indicates a low temperature and generating a second decoding signal when the temperature information indicates a high temperature, with the first decoding signal used to adjust the falling edge time and the second decoding signal used to adjust the rising edge time; or, generating a second decoding signal when the temperature information indicates a low temperature and generating a first decoding signal when the temperature information indicates a high temperature, with the first decoding signal used to adjust the rising edge time and the second decoding signal used to adjust the falling edge time.

[0045] for Figure 6 and Figure 8In some embodiments of the temperature control circuit 200 shown, the first decoding unit 201 and the second decoding unit 202 are disposed in the same decoding unit, that is, the first decoding signal and the second decoding signal are generated simultaneously based on the same decoding unit.

[0046] for Figures 5-8 In some embodiments, the first decoded signal generated by the temperature control circuit 200 is set as a multi-bit binary signal, and each symbol in the first decoded signal corresponds to a different first adjustment time. The delay circuit 100 obtains the first adjustment time corresponding to the first decoded signal based on the value of each symbol in the first decoded signal, and adjusts the falling edge time of the target clock signal based on the first adjustment time. By setting the first decoded signal as a multi-bit binary signal, the first adjustment time at different temperatures is accurately controlled, thereby accurately adjusting the falling edge time of the target clock signal, thus improving the accuracy of the clock delay circuit 10 in compensating for the duty cycle of the clock signal.

[0047] for Figures 5-8 In some embodiments, the second decoded signal generated by the temperature control circuit 200 is configured as a multi-bit binary signal, with each bit of the second decoded signal corresponding to a different second adjustment time. The delay circuit 100 obtains the second adjustment time corresponding to the second decoded signal based on the value of each bit of the second decoded signal, and adjusts the rise time of the target clock signal based on the second adjustment time. By configuring the second decoded signal as a multi-bit binary signal, the second adjustment time at different temperatures is accurately controlled, thereby accurately adjusting the rise time of the target clock signal, thus improving the accuracy of the clock delay circuit 10 in compensating for the duty cycle of the clock signal.

[0048] Accordingly, in some embodiments, the first decoding signal and the second decoding signal can be simultaneously set as multi-bit binary signals, thereby further improving the accuracy of the clock delay circuit 10 in compensating for the duty cycle of the clock signal.

[0049] In a specific example, refer to Figure 9 The first decoding signal is set as a multi-bit binary signal, with its code elements being J1. <0> J1 <1> and J1 <2> Accordingly, the second decoding unit 202 includes: a logic circuit, each input terminal for receiving different symbols in the first decoding signal, and an output terminal for outputting the second decoding signal J2.

[0050] In some embodiments, the temperature control circuit 200 further includes a temperature sensing unit 203, configured to sense the temperature of the memory where the clock delay circuit 10 is located and provide temperature information. Specifically, the temperature sensing unit 203 may be a temperature sensor disposed in the memory.

[0051] In another specific example, the second decoded signal is set as a multi-bit binary signal, with its code elements being J2. <0> J2 <1> and J2 <2> Accordingly, the first decoding unit includes: a logic circuit, each input terminal for receiving different symbols in the second decoding signal, and an output terminal for outputting the first decoding signal.

[0052] It should be noted that the above Figures 5-8 In the examples, the temperature control circuit 200 generates a first decoding signal and / or a second decoding signal based on the acquired temperature information, and controls the delay circuit 100 to adjust the rise time and / or fall time of the target clock signal through the first decoding signal and / or the second decoding signal; in other embodiments, the temperature control circuit can be directly configured to transmit the acquired temperature information, and the delay circuit can directly adjust the rise time and / or fall time of the target clock signal based on the temperature information.

[0053] For the delay circuit 100 provided in this embodiment, refer to... Figure 10 The delay circuit 100 includes at least one of a first time adjustment circuit 101 and a second time adjustment circuit 102, and an adjustment circuit 103.

[0054] The adjustment circuit 103 is configured to receive an initial clock signal and invert the initial clock signal to output a target clock signal; the first time adjustment circuit 101 is configured to control the delay circuit 103 to adjust the falling edge time of the target clock signal according to the temperature information; the second time adjustment circuit 102 is configured to control the delay circuit 103 to adjust the rising edge time of the target clock signal according to the temperature information.

[0055] In some embodiments, the adjustment circuit 103 includes: a first PMOS transistor <p1>The gate is used to receive the initial clock signal, the source is used to receive the power supply signal, and the drain is connected to the first NMOS transistor. <n1>The drain of the first NMOS transistor; <n1>The gate of the first PMOS transistor is used to receive the clock signal, and the source is used to ground. <p1>The drain and the first NMOS transistor <n1>The drain of the circuit is used to output the target clock signal. In this example, the adjustment circuit 103 is also used to invert the initial clock signal to output the target clock signal, referencing... Figure 2 and Figure 3 When the initial clock signal corresponds to the input signal IN, the target clock signal corresponds to the output signal OUT. In a specific example, the first PMOS transistor... <p1>The size of the first NMOS transistor <n1>Three times the size; by adjusting the first PMOS transistor <p1>Size and first NMOS transistor <n1>The size of the first PMOS transistor makes <p1>Second NMOS transistor <n1>Consistent drive capability at the same effective gate voltage improves accurate control over the rise and fall times of the generated target clock signal.

[0056] In some embodiments, the first-time adjustment circuit 101 includes: a second PMOS transistor. <p2>The gate is connected to the first PMOS transistor. <p1>The gate and source are connected to the first driving transistor group 110, and the drain is connected to the first PMOS transistor. <p1>The drain of the first driving transistor group 110 includes at least one driving PMOS transistor connected in parallel, wherein the gate of each driving PMOS transistor is used to receive temperature information, the source is used to receive a power supply signal, and the drain is connected to the first PMOS transistor. <p1>The source pole.

[0057] In some embodiments, the second timing adjustment circuit 102 includes: a second NMOS transistor. <n2>The gate is connected to the first NMOS transistor. <n1>The gate and source are connected to the second driving transistor group 120, and the drain is connected to the first NMOS transistor. <n1>The drain of the second driving transistor group 120 includes at least one driving NMOS transistor connected in parallel, wherein the gate of each driving NMOS transistor is used to receive temperature information, the source is used to ground, and the drain is connected to the first NMOS transistor. <n1>The source pole.

[0058] In a specific example, refer to Figure 10 In this example, the first driving transistor group 110 includes three driving PMOS transistors, combined with Figure 9 The gates of the three driving PMOS transistors are respectively used to receive symbol J1 in the first decoded signal. <0> J1 <1> and J1 <2> The second driving transistor group 120 includes a driving NMOS transistor, the gate of which is used to receive the second decoding signal J2.

[0059] Specifically, when the temperature is below -10℃, the first decoding signal is 000. At this time, all three driving PMOS transistors are turned on to maximize the effect of the second PMOS transistor in the first time adjustment circuit 101. <p2>The source and drain current Ids, thereby enhancing the second PMOS transistor. <p2>The driving capability is optimized to minimize the falling edge time of the target clock signal. When the temperature is between -10°C and 20°C, the first decoding signal is 001, at which point two of the three driving PMOS transistors are turned on, thus moderately increasing the driving capability of the second PMOS transistor in the first time adjustment circuit 101. <p2>The source and drain current Ids, thereby enhancing the second PMOS transistor. <p2>The driving capability is moderately reduced to decrease the falling edge time of the target clock signal; when the temperature is between 20 and 50°C, the first decoding signal is 011, at which time only one of the three driving PMOS transistors is turned on, so as to slightly increase the driving capability of the second PMOS transistor in the first time adjustment circuit 101. <p2>The source and drain current Ids, thereby enhancing the second PMOS transistor. <p2>The driving capability is adjusted to minimize the falling edge time of the target clock signal. When the temperature is greater than 50℃, the first decoding signal is 000, all three driving PMOS transistors are cut off, and the second decoding signal J2 is generated based on an AND gate. At this time, the second decoding signal J2 is 1, turning on the driving NMOS transistor, thereby increasing the driving capability of the second NMOS transistor in the second time adjustment circuit 102. <n2>The source and drain current Ids, thereby enhancing the second NMOS transistor. <n2>The driving capability is increased to reduce the rise time of the target clock signal.

[0060] It should be noted that the above temperature range examples are only for those skilled in the art to understand the generation methods of the first and second decoded signals in this embodiment, and do not constitute a limitation on this embodiment; furthermore, based on Figure 10 Based on the number of symbols in the first and second decoding signals mentioned above, those skilled in the art can adjust the number of driving PMOS transistors in the first driving transistor group 110 and the number of driving NMOS transistors in the second driving transistor group 120. Regardless of the specific number of driving PMOS transistors in the first driving transistor group 110 and the specific number of driving NMOS transistors in the second driving transistor group 120, they all fall within the protection scope of this disclosure.

[0061] In some embodiments, the multiple driving PMOS transistors in the first driving transistor group 110 are of the same size. By adjusting the size of the driving PMOS transistors, the degree of adjustment of the falling edge time of the target clock signal by each driving PMOS transistor in the first driving transistor group 110 is ensured to be the same, thereby improving the accurate control of the falling edge time of the generated target clock signal. Correspondingly, in some embodiments, the multiple driving NMOS transistors in the second driving transistor group 120 are of the same size. By adjusting the size of the driving NMOS transistors, the degree of adjustment of the rising edge time of the target clock signal by each driving NMOS transistor in the second driving transistor group 120 is ensured to be the same, thereby improving the accurate control of the rising edge time of the generated target clock signal.

[0062] For the clock delay circuit provided in this embodiment, as the temperature increases, the duty cycle of the clock signal generated in the memory increases, that is, the duty cycle of the initial clock signal received by the temperature control circuit increases. For a target clock signal that is active at a high level, the duty cycle of the target clock signal is reduced by decreasing the rise time and / or increasing the fall time of the target clock signal. For a target clock signal that is active at a low level, the duty cycle of the target clock signal is reduced by increasing the rise time and / or decreasing the fall time of the target clock signal, thereby compensating for the effect of temperature on the duty cycle of the clock signal. As the temperature decreases, the duty cycle of the clock signal generated in the memory decreases, that is, the duty cycle of the initial clock signal received by the temperature control circuit decreases. For a target clock signal that is active at a high level, the duty cycle of the target clock signal is increased by increasing the rise time and / or decreasing the fall time of the target clock signal. For a target clock signal that is active at a low level, the duty cycle of the target clock signal is increased by decreasing the rise time and / or decreasing the fall time of the target clock signal, thereby compensating for the effect of temperature on the duty cycle of the clock signal.

[0063] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0064] It should be noted that the features disclosed in the clock delay circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new clock delay circuit embodiments.

[0065] Another embodiment of this disclosure provides a memory that adjusts the rise time and / or fall time of an initial clock signal using temperature information, thereby adjusting the duty cycle of the clock signal generated by a time-locked loop (TLL) to compensate for the effect of temperature on the duty cycle of the clock signal generated by the TLL.

[0066] Figure 11 This is a schematic diagram of the memory structure provided in this embodiment, with reference to... Figure 11 The memory includes: a time-locked loop 20 for providing multiple initial clock signals with different phases; and an output delay circuit 30, which is connected to the time-locked loop 20 based on the clock delay circuit settings provided in the above embodiment. The output delay circuit 30 is configured to delay the initial clock signals to output a target clock signal.

[0067] Specifically, as the memory temperature increases, the duty cycle of the clock signal generated by the delay phase-locked loop 20 increases, and the duty cycle of the initial clock signal received by the output delay circuit 30 also increases. For a target clock signal that is active at a high level, the output delay circuit 30 reduces the rise time and / or increases the fall time of the target clock signal. For a target clock signal that is active at a low level, the output delay circuit 30 increases the rise time and / or decreases the fall time of the target clock signal to reduce the duty cycle of the target clock signal, thereby compensating for the effect of temperature on the duty cycle of the clock signal generated by the delay phase-locked loop 20. As the temperature of the memory decreases, the duty cycle of the clock signal generated by the delay phase-locked loop 20 decreases, and the duty cycle of the initial clock signal received by the output delay circuit 30 decreases. For a target clock signal that is active at a high level, the output delay circuit 30 increases the rising edge time and / or decreases the falling edge time of the target clock signal. For a target clock signal that is active at a low level, the output delay circuit 30 decreases the rising edge time and / or decreases the falling edge time of the target clock signal to increase the duty cycle of the target clock signal, thereby compensating for the effect of temperature on the duty cycle of the clock signal generated by the delay phase-locked loop 20.

[0068] It should be noted that memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0069] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A clock delay circuit, characterized in that, include: The delay circuit is configured to receive an initial clock signal and delay the initial clock signal to output a target clock signal; A temperature control circuit is connected to the delay circuit. The temperature control circuit includes: a first decoding unit configured to acquire temperature information and decode the temperature information to generate a first decoding signal; a second decoding unit configured to decode the temperature information to generate a second decoding signal; and the delay circuit configured to adjust the falling edge time of the target clock signal based on the first decoding signal and adjust the rising edge time of the target clock signal based on the second decoding signal.

2. The clock delay circuit according to claim 1, characterized in that, include: The first decoding signal is set as a multi-bit binary signal, and each bit in the first decoding signal corresponds to a different first adjustment time; The delay circuit obtains the first adjustment time corresponding to the first decoded signal based on the value of each bit in the first decoded signal, and adjusts the falling edge time of the target clock signal based on the first adjustment time.

3. The clock delay circuit according to claim 1, characterized in that, include: The second decoding signal is set as a multi-bit binary signal, and each bit in the second decoding signal corresponds to a different second adjustment time; The delay circuit obtains the second adjustment signal corresponding to the second decoded signal based on the value of each bit in the second decoded signal, and adjusts the rise time of the target clock signal based on the second adjustment signal.

4. The clock delay circuit according to claim 1, characterized in that, The first decoding unit and the second decoding unit are disposed in the same decoding unit.

5. The clock delay circuit according to claim 1, characterized in that, The second decoding unit includes: an AND logic circuit, each input terminal for receiving different symbols in the first decoding signal, and an output terminal for outputting the second decoding signal.

6. The clock delay circuit according to claim 1, characterized in that, The temperature control circuit further includes a temperature sensing unit configured to sense the temperature of the memory where the clock delay circuit is located and provide temperature information.

7. The clock delay circuit according to claim 1, characterized in that, The delay circuit includes: At least one of the first-time adjustment circuit and the second-time adjustment circuit, and the adjustment circuit; The adjustment circuit is configured to receive the initial clock signal and invert the initial clock signal to output the target clock signal; The first time adjustment circuit is configured to control the delay circuit to adjust the falling edge time of the target clock signal according to the temperature information; The second time adjustment circuit is configured to control the delay circuit to adjust the rise time of the target clock signal according to the temperature information.

8. The clock delay circuit according to claim 7, characterized in that, The adjustment circuit includes: The first PMOS transistor has a gate for receiving the initial clock signal, a source for receiving the power supply signal, and a drain connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is used to receive the clock signal, and the source is used to ground; The drain of the first PMOS transistor and the drain of the first NMOS transistor are used to output the target clock signal.

9. The clock delay circuit according to claim 8, characterized in that, The first time adjustment circuit includes: The second PMOS transistor has its gate connected to the gate of the first PMOS transistor, its source connected to the first driving transistor group, and its drain connected to the drain of the first PMOS transistor. The first driving transistor group includes at least one driving PMOS transistor connected in parallel, wherein the gate of each driving PMOS transistor is used to receive the temperature information, the source is used to receive the power supply signal, and the drain is connected to the source of the first PMOS transistor.

10. The clock delay circuit according to claim 8, characterized in that, The second time adjustment circuit includes: The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, its source connected to the second driving transistor group, and its drain connected to the drain of the first NMOS transistor. The second driving transistor group includes at least one driving NMOS transistor connected in parallel, wherein the gate of each driving NMOS transistor is used to receive the temperature information, the source is used to ground, and the drain is connected to the source of the first NMOS transistor.

11. The clock delay circuit according to claim 8, characterized in that, The size of the first PMOS transistor is three times the size of the first NMOS transistor.

12. The clock delay circuit according to claim 9, characterized in that, The multiple driving PMOS transistors are of the same size.

13. A memory, characterized in that, include: A time-delay phase-locked loop (TLL) is used to provide multiple initial clock signals with different phases. An output delay circuit, based on the clock delay circuit of any one of claims 1 to 11, is connected to the delay phase-locked loop and configured to delay the initial clock signal to output a target clock signal.

Images