A data transmission method, device, system, slave device and storage medium

Abstract

The embodiment of the application discloses a data transmission method, device, system, slave device and storage medium, wherein the data transmission method comprises: in response to a target interaction instruction signal, initiating a DMA request signal to a local DMA controller; wherein the target interaction instruction signal comprises an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system; data interaction is carried out with the local DMA controller through the DMA request signal, and DMA interaction data is obtained; in the case that it is determined that the handshake process with the host device is completed, the DMA interaction data is sent to the host device. The technical scheme of the embodiment of the application can improve the robustness of I2C data communication, and further improve the data transmission quality between the master and slave devices in the I2C-based data transmission system.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data transmission method, apparatus, system, slave device, and storage medium. Background Technology

[0002] I2C (Inter-Integrated Circuit, bidirectional two-wire synchronous serial bus) is a general-purpose bus protocol, commonly used as a communication interface IP, such as in bootloaders and inter-system bus expansion. I2C can complete communication with a small number of buses, saving design space, and has low power consumption, making it widely applicable and practical.

[0003] The I2C interface can achieve stable and reliable data transmission for various application scenarios through a small number of buses, mainly relying on selectable address modes and operating modes. I2C address modes include 7-bit and 10-bit addresses, and operating modes include Standard Mode (typically 100kHz), Fast Mode (typically 400kHz), Fast Mode Plus (typically 1MHz), and High Speed ​​Mode (3.4MHz). I2C also supports two modes: Clock Stretching Mode and Clock Nostretch Mode, with Clock Nostretch Mode being more widely used.

[0004] In the process of developing this invention, the inventors discovered that with technological iteration and innovation, the market has placed higher demands on the speed and data reliability of commonly used I2C communication, requiring real-time and fast data communication with the host in different address modes without any issues affecting communication quality. However, the system's main frequency is limited by process technology, operating temperature, power consumption, and critical path, restricting the product's maximum operating frequency. Therefore, when the product's operating frequency is relatively low, and I2C selects ClkNostrech Mode, the coordination between the slave device and DMA (Direct Memory Access) becomes a challenge. During data interaction between the host and slave devices based on I2C, some bytes of data are easily discarded in High Speed ​​Mode or Fast Mode Plus, affecting the data communication quality between the host and slave devices, and in severe cases, affecting the success or failure of the product. Summary of the Invention

[0005] This invention provides a data transmission method, apparatus, system, slave device, and storage medium, which can improve the robustness of I2C data communication and thus improve the data transmission quality between master and slave devices in an I2C-based data transmission system.

[0006] According to one aspect of the present invention, a data transmission method is provided, applied to a slave device in an I2C-based data transmission system, wherein the slave device is in Clk No Stretch Mode; the method includes:

[0007] In response to a target interaction indication signal, a DMA request signal is initiated to the local DMA controller; wherein, the target interaction indication signal includes an address match signal or an IRQ (Interrupt ReQuest) signal; the address match signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system;

[0008] The DMA request signal is used to interact with the local DMA controller to obtain DMA interaction data.

[0009] Once it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device.

[0010] According to another aspect of the present invention, a data transmission apparatus is provided, configured in a slave device of an I2C-based data transmission system, the slave device being in Clk No Stretch Mode; the apparatus includes:

[0011] A DMA request signal initiation module is used to initiate a DMA request signal to the local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system;

[0012] The DMA interaction data acquisition module is used to interact with the local DMA controller through the DMA request signal to obtain DMA interaction data;

[0013] The DMA interaction data sending module is used to send the DMA interaction data to the host device after determining that the handshake process with the host device has been completed.

[0014] According to another aspect of the present invention, a slave device is provided, the slave device comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the data transmission method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a data transmission system is provided, including a host device, a slave device, and an I2C bus; the host device and the slave device are communicatively connected via the I2C bus, and the slave device is in ClkNo Stretch Mode; wherein: the host device is used for:

[0020] Send a slave device address signal to the slave device to perform a handshake process with the slave device through the slave device address signal;

[0021] The slave device is used to initiate a DMA request signal to the local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the master device in the I2C communication system;

[0022] The DMA request signal is used to interact with the local DMA controller to obtain DMA interaction data.

[0023] Once the handshake process with the host device is completed, the DMA interaction data is sent to the host device via the I2C bus.

[0024] In this embodiment of the invention, a slave device in Clk No Stretch Mode responds to a target interaction indication signal, such as an address matching signal or an IRQ signal, by initiating a DMA request signal to its local DMA controller. This allows for data interaction with the local DMA controller via the DMA request signal, obtaining DMA interaction data. After confirming the handshake process with the master device is complete, the acquired DMA interaction data is sent to the master device. Specifically, the address matching signal is triggered by the slave device at the falling edge of the last address pulse signal sent by the master device in the I2C communication system, earlier than the triggering time of the existing address matching signal. The IRQ signal, however, can be triggered at any time according to the slave device's data interaction needs, without being limited by the triggering restriction of the address matching signal. Therefore, by triggering the target interaction indication signal in advance, the above technical solution can improve the speed at which the slave device acquires DMA interaction data, thereby solving the problem of poor data communication quality between master and slave devices in Clk No Stretch Mode in existing I2C-based data transmission systems. This improves the robustness of I2C data communication and ultimately enhances the data transmission quality between master and slave devices in I2C-based data transmission systems.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of an I2C-based data transmission system provided in Embodiment 1 of the present invention;

[0029] Figure 3 This is a schematic diagram illustrating the data communication process between a host device and a slave device in an I2C-based data transmission system provided in Embodiment 1 of the present invention.

[0030] Figure 4 This is a schematic diagram illustrating the interaction between the I2C bus interface and the DMA of the slave device in the existing technology.

[0031] Figure 5 This is a schematic diagram illustrating the interaction effect between an I2C bus interface and a slave device DMA, as provided in Embodiment 1 of the present invention.

[0032] Figure 6 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention;

[0033] Figure 7 This is a schematic diagram illustrating the interaction effect between an I2C bus interface and a slave device DMA, as provided in Embodiment 2 of the present invention.

[0034] Figure 8 This is a schematic diagram of a data transmission device provided in Embodiment 3 of the present invention;

[0035] Figure 9 This is a schematic diagram of the structure of a data transmission system provided in Embodiment 4 of the present invention;

[0036] Figure 10 This is a schematic diagram of a slave device provided in Embodiment 5 of the present invention. Detailed Implementation

[0037] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] Example 1

[0040] Figure 1This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where a slave device in an I2C-based data transmission system acquires DMA interaction data based on an address matching signal or IRQ signal and transmits data with the host. This method can be executed by a data transmission device, which can be implemented in software and / or hardware, and is generally integrated into the slave device. The slave device can be various types of terminal devices or server devices, etc., used in conjunction with the host device in the I2C-based data transmission system. This embodiment of the present invention does not limit the specific device type of the slave device. Correspondingly, as... Figure 1 As shown, the method includes the following operations:

[0041] S110. In response to the target interaction indication signal, initiate a DMA request signal to the local DMA controller; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system.

[0042] The target interaction indication signal can be a signal used to indicate that the slave device has started interacting with the local DMA controller. Optionally, the target interaction indication signal can be a software-triggered signal or a hardware-triggered signal, as long as it can be used to indicate that the slave device has started interacting with the local DMA controller. This embodiment of the invention does not limit the signal type of the target interaction indication signal. The local DMA controller, that is, the DMA controller in the slave device that executes the data transfer method, can perform DMA operations and provide high-speed data transfer between the peripherals and memory of the slave device or between the memory of the slave device and memory. The DMA request signal can be used to indicate that a handshake has started with the local DMA controller and that interactive data has been obtained. The address pulse signal, that is, the address signal sent by the master device to the slave device, can be used to perform a handshake process with the slave device.

[0043] Figure 2 This is a schematic diagram of the structure of an I2C-based data transmission system provided in Embodiment 1 of the present invention. Figure 3 This is a schematic diagram illustrating the data communication process between a host device and a slave device in an I2C-based data transmission system according to Embodiment 1 of the present invention. In a specific example, such as... Figure 1 and Figure 2As shown, the technical solution of this invention is mainly applicable to the following application scenario: In an I2C-based data transmission system, the host device and each slave device maintain a communication connection through the I2C bus. The number of slave devices can be one or more. All the SDA (Serial Data Line) lines of the master and slave devices are connected to a single line, and these devices use this common data line in a time-sharing manner to achieve pairwise data transmission. Therefore, SDA conforms to the characteristics of a data bus. All the SCL (Serial Clock Line) lines of the master and slave devices are connected to a single line, and they use this common clock line in a time-sharing manner to achieve pairwise clock transmission. Therefore, SCL conforms to the characteristics of a clock bus.

[0044] like Figure 3 As shown, when the slave device is in Clk Nostrech Mode, before the master device M0 initiates a read data request to the slave, it can first send the corresponding slave address to the target slave device to complete the handshake process. After the master device and the target slave device complete the handshake process, the master device M0 can initiate a read data request to the target slave device in Clk Nostrech Mode. The target slave device responds to the read data request by handshaking with its local DMA controller. After the target slave device completes the handshake process with the DMA controller, it can obtain the data sent by the DMA controller and feed the obtained data back to the master device M0. Therefore, the DMA state of the slave device will affect the correctness of the data received by the master device M0. In practical applications, products often choose slave Clk Nostrech Mode to maintain high communication efficiency. Therefore, the I2C bus in the I2C-based data transmission system needs to have high robustness; otherwise, the communication efficiency and quality between the master and slave devices will be severely affected.

[0045] Figure 4 This is a schematic diagram illustrating the interaction between the I2C bus interface and the slave device's DMA in existing technology. Taking the 7-bit address mode in I2C as an example... Figure 4 The diagram shows the waveforms of I2C working with the slave DMA controller to acquire slave data and initiate data transmission. For example... Figure 4As shown, in the prior art, after the master device and slave device complete the handshake via slave address pulse signals A0-A6 sent by the master device, the master device sends a W / R signal (read / write flag signal) to the slave device. The W / R signal can indicate the type of interaction between the master device and the slave device, such as reading data from the slave device or writing data to the slave device. Correspondingly, when the slave device detects the rising edge of the W / R signal, it triggers the generation of an address matching signal, i.e., the ADDR_MATCH signal, indicating confirmation that the handshake process with the master device has been completed, and the slave device can begin interacting with the local DMA controller. After the slave device triggers the generation of the ADDR_MATCH signal, it begins the handshake process with the local DMA controller, sending a DMA request signal, i.e., the DMA_TX_REQ signal, to the local DMA controller. Correspondingly, after receiving the DMA_TX_REQ signal, the slave device's DMA controller can send back a DMA_TX_ACK signal to the slave device, indicating that the DMA has confirmed receipt of the DMA request signal and can interact with the slave device for data. At this point, the slave device completes the handshake process with the local DMA controller. Once the slave device completes the handshake process with the local DMA controller, it can obtain the interaction data from the local DMA controller and fill the transmit buffer in preparation for sending it to the host device.

[0046] like Figure 4 As can be seen, in the current I2C-based data transmission system, the system reserves less than one SCL time for the DMA handshake process between the slave device and the host device. If the DMA_TX_REQ is not responded to by the DMA controller of the slave device in time, the slave device will lose the first few bits of the first byte of data, and in severe cases, the entire byte will be lost, thus affecting the communication quality between the slave device and the host device.

[0047] To address the aforementioned issues, this embodiment of the invention preprocesses the timing of triggering interaction between the slave device and the local DMA controller. Specifically, the slave device can trigger the generation of an address matching signal or an IRQ signal as a target interaction indication signal. When using the address matching signal, i.e., the ADDR_MATCH signal, as the target interaction indication signal, the generation of the address matching signal can be triggered in advance, such as at the falling edge of the last address pulse signal sent by the master device, instead of after the master device sends the W / R signal. This allows for earlier timing of the address matching signal triggering. When using the IRQ signal as the target interaction indication signal, the master device can trigger the generation of the IRQ signal at any time as needed, without being limited by the handshake process with the master device or the W / R signal detection process.

[0048] In an optional embodiment of the present invention, if the target interaction indication signal includes the address matching signal, then before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method may further include: detecting the moment when the last address pulse signal sent by the host device changes from a high-level signal to a low-level signal; and triggering the generation of the address matching signal at the same time as detecting the change from a high-level signal to a low-level signal of the last address pulse signal sent by the host device.

[0049] Figure 5 This is a schematic diagram illustrating the interaction between an I2C bus interface and a slave device DMA, as provided in Embodiment 1 of the present invention. Figure 5 As shown, optionally, if the slave device selects the address matching signal as the target interaction indication signal, the slave device can detect the signal information sent by the master device in real time to trigger the generation of the address matching signal via software. Once the slave device detects that the master device has started sending address pulse signals, it can begin preparing to trigger the generation of the address matching signal. Specifically, after the slave device detects that the master device has sent all address pulse signals, it determines the moment when the last address pulse signal sent by the master device changes from a high-level signal to a low-level signal, i.e., determines the falling edge moment of the last address pulse signal sent by the master device, and simultaneously triggers the generation of the address matching signal via software at this moment. In this case, the triggering time of the address matching signal is advanced from the rising edge moment of the read / write flag signal to the falling edge moment of the last address pulse signal. Because the address matching signal is triggered earlier, the interaction time between the slave device and the local DMA controller is also advanced accordingly. Consequently, the interaction time reserved by the data communication system for the slave device and the local DMA controller is extended, and the slave device has more time to prepare DMA interaction data.

[0050] In an optional embodiment of the present invention, if the target interaction indication signal includes the address matching signal, then initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal may include: reading internal configuration information to obtain a preset signal trigger interval between the address matching signal and the DMA request signal; determining the trigger time of the rising edge of the address matching signal in response to the address matching signal; calculating the current trigger duration of the address matching signal based on the trigger time of the rising edge of the address matching signal; and initiating the DMA request signal to the local DMA controller if it is determined that the current trigger duration of the address matching signal reaches the preset signal trigger interval.

[0051] The preset signal trigger interval can be the interval between the trigger time of the address matching signal and the trigger time of the DMA request signal. The current trigger duration can be the statistical duration after the address matching signal is triggered.

[0052] In this embodiment of the invention, when the address matching signal is triggered in software, in order to further extend the interaction time reserved by the data communication system for the slave device and the local DMA controller, the timing of triggering the interaction between the slave device and the local DMA controller based on the address matching signal can be configured as needed. Specifically, before the slave device interacts with the master device, the user can configure the internal configuration information of the slave device, determine the parameter of the preset signal trigger interval between the address matching signal and the DMA request signal, and modify the parameter of the preset signal trigger interval as needed.

[0053] like Figure 5 As shown, the minimum value for the preset signal trigger interval (in the Can.config stage) is 0, indicating that the slave device can begin handshaking with the local DMA controller when the address matching signal is triggered. The maximum value for the preset signal trigger interval is 2.5 SCLs to prevent insufficient time for the slave device to handshake with the local DMA controller, which could lead to handshake failure and consequently, failure of the slave device's interaction with the local DMA. If the user has not configured the preset signal trigger interval, the default value can be used.

[0054] Accordingly, during communication, the slave device can read its internal configuration information to obtain the preset signal trigger interval between the address matching signal and the DMA request signal. When the slave device also detects the address matching signal, it can determine the trigger time of the rising edge of the address matching signal and use that trigger time as the starting point to calculate the accumulated duration of the address matching signal from that starting point as the current trigger duration. Simultaneously, the slave device calculates in real time whether the current trigger duration has reached the preset signal trigger interval. If the slave device determines that the current trigger duration of the address matching signal has reached the preset signal trigger interval, it can initiate a DMA request signal to the local DMA controller to begin the handshake process with the local DMA controller.

[0055] The above technical solution modifies the address matching signal in software to bring it to the falling edge of the last address pulse signal sent by the master device. Simultaneously, it configures the interval between the address matching signal and the DMA request signal as needed. This allows the slave device to complete the DMA data filling preparation during the period from the last address pulse signal to the ACK response from the master device. By relying on the address matching signal to initiate the handshake between the DMA and the slave device, the data retrieval margin for DMA interaction data is increased from 1 SCL to a selectable 2.5 SCL. This ensures sufficient data interaction time between the slave device and the local DMA controller, improving the stability and reliability of the slave device's DMA interaction data processing, thereby enhancing the robustness of I2C data communication and improving the data transmission quality between the master and slave devices.

[0056] In an optional embodiment of the present invention, if the target interaction indication signal includes the IRQ signal, then before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method may further include: detecting the local device status or software event through the device driver or the local operating system kernel; and triggering the generation of the IRQ signal if it is determined that the local device status is the target device status or that a target software event has been generated.

[0057] S120. Data interaction is performed with the local DMA controller through the DMA request signal to obtain DMA interaction data.

[0058] DMA interaction data can be data obtained by the slave device after interacting with the DMA controller.

[0059] S130. If it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device.

[0060] Accordingly, when the slave device initiates a DMA request signal to its local DMA controller, it can begin a handshake process with the local DMA controller. After completing the handshake, the slave device acquires the data to be exchanged with the DMA controller. Once the slave device acquires the DMA exchange data, it can fill the transmit buffer with the DMA exchange data and needs to wait for the handshake process with the master device. If the slave device determines that the handshake process with the master device is complete, it can send the DMA exchange data stored in the transmit buffer to the master device.

[0061] Optionally, the above data transmission method can be applied to NFC (Near Field Communication) products, and can be used in many application scenarios to speed up communication between the BootLoader and the interface.

[0062] In this embodiment of the invention, a slave device in Clk No Stretch Mode responds to a target interaction indication signal, such as an address matching signal or an IRQ signal, by initiating a DMA request signal to its local DMA controller. This allows for data interaction with the local DMA controller via the DMA request signal, obtaining DMA interaction data. After confirming the handshake process with the master device is complete, the acquired DMA interaction data is sent to the master device. Specifically, the address matching signal is triggered by the slave device at the falling edge of the last address pulse signal sent by the master device in the I2C communication system, earlier than the triggering time of the existing address matching signal. The IRQ signal, however, can be triggered at any time according to the slave device's data interaction needs, without being limited by the triggering restriction of the address matching signal. Therefore, by triggering the target interaction indication signal in advance, the above technical solution can improve the speed at which the slave device acquires DMA interaction data, thereby solving the problem of poor data communication quality between master and slave devices in Clk No Stretch Mode in existing I2C-based data transmission systems. This improves the robustness of I2C data communication and ultimately enhances the data transmission quality between master and slave devices in I2C-based data transmission systems.

[0063] Example 2

[0064] Figure 6 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention. Based on the above embodiments, this embodiment of the present invention uses the IRQ signal as a target interaction indication signal to specifically illustrate the overall flow of the data transmission method. Accordingly, as... Figure 6 As shown, the method in this embodiment may include:

[0065] S210: Detect local device status or software events through device drivers or the local operating system kernel.

[0066] S220. If the local device status is determined to be the target device status, or if the target software event is determined to be generated, the IRQ signal is triggered to be generated.

[0067] The target device status and target software event can be set according to the specific application scenario or business requirements of the I2C-based data transmission system. For example, when the slave device is used to monitor temperature, the target software event could be that the monitored temperature has reached the warning temperature value. When the slave device detects that its local memory is about to be full, the state of its local memory about to overflow can be used as the target device status.

[0068] It should be noted that the current scheme of using address matching signals as target interaction indication signals is only applicable to scenarios where the master device sends a data request to the slave device, and the slave device passively feeds back data to the master device. This limits its application scope. In many application scenarios, such as monitoring, detection, or security protection, slave devices often need to report collected information to the master device in real time so that the master device can make immediate decisions based on the reported information. For example, when the slave device detects that the current temperature has reached a warning value, it needs to report an alarm to the master device in real time; or when the slave device detects malicious attack data, it needs to report an alarm to the master device in real time.

[0069] In the aforementioned application scenarios where the host device needs to report information in real time, if the address matching signal is used as the target interaction indication signal, the slave device can only trigger the address matching signal at the falling edge of the last address pulse signal sent by the host device. This causes a certain delay and cannot guarantee the real-time nature of the reported information. To solve this problem and expand the application scope of the aforementioned data transmission method, this embodiment of the invention adds a separate IRQ signal to the slave device. When the slave device needs to actively report information to the host device in real time, it generates a target interaction indication signal by triggering the IRQ signal. In response to the real-time triggered target interaction indication signal, it initiates a DMA request signal to the local DMA controller.

[0070] In this embodiment of the invention, a target interaction indication signal can be generated for the slave device by triggering an IRQ signal via hardware. Optionally, in scenarios where the slave device actively reports data to the master device in real time, an IRQ pin can be added to the slave device configuration. The slave device can then monitor its status in real time through its internal device driver or the local operating system kernel. If the slave device detects that its current status is the target device status or detects that it has generated a target software event, it can proactively trigger a hardware interrupt through its internal device driver or the local operating system kernel to generate an IRQ signal. When the slave device detects the IRQ signal, it can use it as a target interaction indication signal and, based on the triggering time of the IRQ signal, trigger the generation of a DMA request signal according to the default timing. The DMA request signal is then sent to the local DMA controller to begin the handshake process with the local DMA controller.

[0071] Figure 7 This is a schematic diagram illustrating the interaction between an I2C bus interface and a slave device DMA, as provided in Embodiment 2 of the present invention. Figure 7As shown, when a slave device needs to actively report data to a master device, it can trigger a hardware interrupt, adding an IRQ signal to record the current moment when the slave device requests data from the master device. When the slave device detects the new IRQ signal, it can follow the default timing sequence, i.e. Figure 7 In the Config phase shown, a DMA request signal is initiated to the local DMA controller. This enables the DMA request to obtain the interaction data from the local DMA controller and fill the transmit buffer before the host device's address pulse signal is sent after the rising edge of the IRQ, so that it can be sent to the host device.

[0072] S230, in response to the IRQ signal, initiates a DMA request signal to the local DMA controller.

[0073] S240. Data interaction is performed with the local DMA controller through the DMA request signal to obtain DMA interaction data.

[0074] S250. If it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device.

[0075] Accordingly, when the slave device initiates a DMA request signal to its local DMA controller, it can begin a handshake process with the local DMA controller. After completing the handshake, the slave device acquires the data exchanged with the DMA controller. Once the slave device acquires the DMA exchange data, it can fill the transmit buffer with the DMA exchange data and needs to wait for the handshake process with the master device. If the slave device determines that the handshake process with the master device is complete, it can send the DMA exchange data stored in the transmit buffer to the master device in real time.

[0076] Optionally, the above data transmission method can be applied to NFC series products, and can be used in many application scenarios to speed up communication between the BootLoader and the interface.

[0077] The above technical solution, by adding an IRQ signal in hardware, enables the slave device to complete the DMA interaction data filling preparation work before the address pulse signal is sent and before the master device responds with an ACK. Relying on a customized signal, the DMA and slave devices handshake in real time. In the 7-bit address mode of I2C, the data retrieval margin for DMA interaction data can be increased from 1 SCL to 9 SCLs. In the 10-bit address mode of I2C, the data retrieval margin for DMA interaction data can be increased from 1 SCL to 18 SCLs. Therefore, adding an IRQ signal in hardware can also ensure sufficient data interaction time between the slave device and the local DMA controller, improving the real-time performance, stability, and reliability of the slave device in processing DMA interaction data, thereby improving the robustness of I2C data communication and enhancing the data transmission quality and real-time performance between the master and slave devices.

[0078] In this embodiment of the invention, a slave device in Clk No Strike Mode responds to a target interaction indication signal of the IRQ signal type by initiating a DMA request signal to its local DMA controller. This allows for data interaction with the local DMA controller via the DMA request signal, obtaining DMA interaction data. After confirming the handshake process with the master device is complete, the acquired DMA interaction data is sent to the master device. Since the IRQ signal can be triggered at any time according to the slave device's data interaction needs, it is not limited by the triggering restrictions of the address matching signal. Therefore, by triggering the target interaction indication signal in advance, the above technical solution can improve the speed at which the slave device obtains DMA interaction data, thereby solving the problem of poor data communication quality between master and slave devices in Clk No Strike Mode in existing I2C-based data transmission systems. This improves the robustness of I2C data communication, and consequently enhances the data transmission quality and real-time performance between master and slave devices in I2C-based data transmission systems.

[0079] Example 3

[0080] Figure 8 This is a schematic diagram of a data transmission device provided in Embodiment 3 of the present invention. The device is configured as a slave device in an I2C-based data transmission system, and the slave device is in Clk No Stretch Mode, such as... Figure 8 As shown, the device includes: a DMA request signal initiation module 310, a DMA interaction data acquisition module 320, and a DMA interaction data transmission module 330, wherein:

[0081] The DMA request signal initiation module 310 is used to initiate a DMA request signal to the local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system;

[0082] The DMA interaction data acquisition module 320 is used to interact with the local DMA controller through the DMA request signal to obtain DMA interaction data.

[0083] The DMA interaction data sending module 330 is used to send the DMA interaction data to the host device when it is determined that the handshake process with the host device has been completed.

[0084] In this embodiment of the invention, a slave device in Clk No Stretch Mode responds to a target interaction indication signal, such as an address matching signal or an IRQ signal, by initiating a DMA request signal to its local DMA controller. This allows for data interaction with the local DMA controller via the DMA request signal, obtaining DMA interaction data. After confirming the handshake process with the master device is complete, the acquired DMA interaction data is sent to the master device. Specifically, the address matching signal is triggered by the slave device at the falling edge of the last address pulse signal sent by the master device in the I2C communication system, earlier than the triggering time of the existing address matching signal. The IRQ signal, however, can be triggered at any time according to the slave device's data interaction needs, without being limited by the triggering restriction of the address matching signal. Therefore, by triggering the target interaction indication signal in advance, the above technical solution can improve the speed at which the slave device acquires DMA interaction data, thereby solving the problem of poor data communication quality between master and slave devices in Clk No Stretch Mode in existing I2C-based data transmission systems. This improves the robustness of I2C data communication and ultimately enhances the data transmission quality between master and slave devices in I2C-based data transmission systems.

[0085] Optionally, if the target interaction indication signal includes the address matching signal, the data transmission device may further include an address matching signal generation module, configured to: detect the moment when the last address pulse signal sent by the host device changes from a high-level signal to a low-level signal; and trigger the generation of the address matching signal at the same time as detecting the change from a high-level signal to a low-level signal in the last address pulse signal sent by the host device.

[0086] Optionally, if the target interaction indication signal includes the address matching signal, the DMA request signal initiation module 310 is specifically configured to: read internal configuration information to obtain a preset signal trigger interval between the address matching signal and the DMA request signal; in response to the address matching signal, determine the trigger time of the rising edge of the address matching signal; calculate the current trigger duration of the address matching signal based on the trigger time of the rising edge of the address matching signal; and, if it is determined that the current trigger duration of the address matching signal reaches the preset signal trigger interval, initiate the DMA request signal to the local DMA controller.

[0087] Optionally, if the target interaction indication signal includes the IRQ signal, the data transmission device may further include an IRQ signal generation module, used to: detect the local device status or software event through a device driver or the local operating system kernel; and trigger the generation of the IRQ signal when it is determined that the local device status is the target device status or that a target software event has been generated.

[0088] The aforementioned data transmission device can execute the data transmission method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the data transmission method provided in any embodiment of the present invention.

[0089] Since the data transmission device described above is capable of executing the data transmission method in the embodiments of the present invention, those skilled in the art can understand the specific implementation and various variations of the data transmission device in this embodiment based on the data transmission method described in the embodiments of the present invention. Therefore, how the data transmission device implements the data transmission method in the embodiments of the present invention will not be described in detail here. Any device used by those skilled in the art to implement the data transmission method in the embodiments of the present invention falls within the scope of protection of this application.

[0090] Example 4

[0091] Figure 9 This is a schematic diagram of the structure of a data transmission system provided in Embodiment 4 of the present invention, as shown below. Figure 9 As shown, the structure of this data transmission system includes: a host device 410, a slave device 420, and an I2C bus 430; the host device 410 and the slave device 420 are connected via the I2C bus 430, and the slave device 420 is in Clk No Stretch Mode; wherein:

[0092] The master device 410 is used to send a slave device address signal to the slave device 420, so as to perform a handshake process with the slave device 420 through the slave device address signal.

[0093] The slave device address signal can be an address pulse signal.

[0094] Slave device 420 is used to initiate a DMA request signal to its local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system; data interaction is performed with the local DMA controller through the DMA request signal to obtain DMA interaction data; if it is determined that the handshake process with the host device 410 is completed, the DMA interaction data is sent to the host device 410 through the I2C bus 430.

[0095] Optionally, if the target interaction indication signal includes the address matching signal, the slave device 410 can also be used to: detect the moment when the last address pulse signal sent by the host device changes from a high-level signal to a low-level signal; and trigger the generation of the address matching signal at the same time as detecting the change from a high-level signal to a low-level signal of the last address pulse signal sent by the host device.

[0096] Optionally, if the target interaction indication signal includes the address matching signal, the slave device 410 can also be used to: read internal configuration information to obtain a preset signal trigger interval between the address matching signal and the DMA request signal; determine the trigger time of the rising edge of the address matching signal in response to the address matching signal; calculate the current trigger duration of the address matching signal based on the trigger time of the rising edge of the address matching signal; and, if it is determined that the current trigger duration of the address matching signal reaches the preset signal trigger interval, initiate the DMA request signal to the local DMA controller.

[0097] Optionally, if the target interaction indication signal includes the IRQ signal, the slave device 410 can also be used to: detect the local device status or software event through the device driver or the local operating system kernel; and trigger the generation of the IRQ signal when it is determined that the local device status is the target device status or that a target software event has been generated.

[0098] This invention provides a data transmission system comprising a host device, a slave device, and an I2C bus. In this system, the host device and the slave device are connected via the I2C bus, with the slave device operating in Clk No Strike Mode. Correspondingly, in Clk No Strike Mode, the slave device, responding to a target interaction indication signal such as an address match signal or an IRQ signal, initiates a DMA request signal to its local DMA controller. This allows for data interaction with the local DMA controller, obtaining DMA interaction data. After confirming the handshake process is complete with the host device, the slave device sends the acquired DMA interaction data to the host device. This addresses the problem of poor data communication quality between master and slave devices in Clk No Strike Mode in existing I2C-based data transmission systems, improving the robustness of I2C data communication and thus enhancing the data transmission quality between master and slave devices in I2C-based data transmission systems.

[0099] The slave device in the above data transmission system can execute the data transmission method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the data transmission method provided in any embodiment of the present invention.

[0100] Since the slave device in the data transmission system described above is a device capable of executing the data transmission method in the embodiments of the present invention, those skilled in the art can understand the specific implementation and various variations of the data transmission system of this embodiment based on the data transmission method described in the embodiments of the present invention. Therefore, how the slave device in this data transmission system implements the data transmission method in the embodiments of the present invention will not be described in detail here. Any slave device in the data transmission system used by those skilled in the art to implement the data transmission method in the embodiments of the present invention falls within the scope of protection of this application.

[0101] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0102] Example 5

[0103] Figure 10A schematic diagram of a slave device 10, which can be used to implement embodiments of the present invention, is shown. The slave device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The slave device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0104] like Figure 10 As shown, the slave device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from storage unit 18. The RAM 13 can also store various programs and data required for the operation of the slave device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0105] Multiple components in slave device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows slave device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0106] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data transfer methods.

[0107] Optionally, the data transmission method is applied to a slave device in an I2C-based data transmission system, wherein the slave device is in a clock no-stretch mode; the method includes:

[0108] In response to a target interaction indication signal, a DMA request signal is initiated to the local DMA controller; wherein, the target interaction indication signal includes an address match signal or an interrupt request IRQ signal; the address match signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system;

[0109] The DMA request signal is used to interact with the local DMA controller to obtain DMA interaction data.

[0110] Once it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device.

[0111] In some embodiments, the data transfer method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on slave device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the data transfer method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the data transfer method by any other suitable means (e.g., by means of firmware).

[0112] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0113] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0114] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0115] To provide interaction with a user, the systems and techniques described herein can be implemented on a slave device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the slave device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0116] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0117] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

Claims

1. A data transmission method, characterized in that, A method for a slave device in an I2C-based data transmission system, wherein the slave device is in Clock No Stretch Mode; the method includes: In response to a target interaction indication signal, a DMA request signal is initiated to the local DMA controller; wherein, the target interaction indication signal includes an address match signal or an interrupt request IRQ signal; the address match signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system; The DMA request signal is used to interact with the local DMA controller to obtain DMA interaction data. Once it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device; If the target interaction indication signal includes the address matching signal, then the step of initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal includes: Read internal configuration information to obtain the preset signal trigger interval between the address matching signal and the DMA request signal; In response to the address matching signal, determine the trigger time of the rising edge of the address matching signal; Based on the triggering time of the rising edge of the address matching signal, calculate the current triggering duration of the address matching signal; If it is determined that the current trigger duration of the address matching signal has reached the preset signal trigger interval duration, the DMA request signal is initiated to the local DMA controller.

2. The method according to claim 1, characterized in that, If the target interaction indication signal includes the address matching signal, then before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method further includes: The moment when the last address pulse signal sent by the host device changes from a high-level signal to a low-level signal is detected; The address matching signal is generated simultaneously with the detection that the last address pulse signal sent by the host device changes from a high level signal to a low level signal.

3. The method according to claim 1, characterized in that, If the target interaction indication signal includes the IRQ signal, then before initiating a DMA request signal to the local DMA controller in response to the target interaction indication signal, the method further includes: Detect the status of local devices or software events through device drivers or the local operating system kernel; The IRQ signal is triggered when the local device status is determined to be the target device status, or when a target software event is determined to be generated.

4. A data transmission device, characterized in that, A slave device configured in an I2C-based data transmission system, the slave device being in Clk No Stretch Mode; the device includes: A DMA request signal initiation module is used to initiate a DMA request signal to the local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the host device in the I2C communication system; The DMA interaction data acquisition module is used to interact with the local DMA controller through the DMA request signal to obtain DMA interaction data; The DMA interaction data sending module is used to send the DMA interaction data to the host device when it is determined that the handshake process with the host device has been completed. If the target interaction indication signal includes the address matching signal, then the DMA request signal initiation module is specifically used for: Read internal configuration information to obtain the preset signal trigger interval between the address matching signal and the DMA request signal; In response to the address matching signal, determine the trigger time of the rising edge of the address matching signal; Based on the triggering time of the rising edge of the address matching signal, calculate the current triggering duration of the address matching signal; If it is determined that the current trigger duration of the address matching signal has reached the preset signal trigger interval duration, the DMA request signal is initiated to the local DMA controller.

5. A slave device, characterized in that, The slave device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method according to any one of claims 1-3.

6. A data transmission system, characterized in that, It includes a master device, a slave device, and an I2C bus; the master device and the slave device are connected via the I2C bus, and the slave device is in Clk No Stretch Mode; wherein: the master device is used for: Send a slave device address signal to the slave device to perform a handshake process with the slave device through the slave device address signal; The slave device is used to initiate a DMA request signal to the local DMA controller in response to a target interaction indication signal; wherein, the target interaction indication signal includes an address matching signal or an IRQ signal; the address matching signal is triggered at the falling edge of the last address pulse signal sent by the master device in the I2C communication system; The DMA request signal is used to interact with the local DMA controller to obtain DMA interaction data. Once it is determined that the handshake process with the host device has been completed, the DMA interaction data is sent to the host device via the I2C bus; If the target interaction indication signal includes the address matching signal, the slave device is further configured to: Read internal configuration information to obtain the preset signal trigger interval between the address matching signal and the DMA request signal; In response to the address matching signal, determine the trigger time of the rising edge of the address matching signal; Based on the triggering time of the rising edge of the address matching signal, calculate the current triggering duration of the address matching signal; If it is determined that the current trigger duration of the address matching signal has reached the preset signal trigger interval duration, the DMA request signal is initiated to the local DMA controller.

7. The system according to claim 6, characterized in that, If the target interaction indication signal includes the address matching signal, the slave device is further configured to: The moment when the last address pulse signal sent by the host device changes from a high-level signal to a low-level signal is detected; The address matching signal is generated simultaneously with the detection that the last address pulse signal sent by the host device changes from a high level signal to a low level signal.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute and perform the data transmission as described in any one of claims 1-3.

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