A channel estimation method, apparatus, device, and communication base station

Abstract

The application discloses a channel estimation method, device and equipment and a communication base station in the technical field of computer communication, which divides the channel estimation process into several calculation stages by the FPGA, and performs parallelly "elimination of upper triangular elements of real parts", "calculation of the first product of the inverse matrix of real parts and the imaginary part in a complex matrix" and "calculation of the matrix sum of real parts and a target matrix" in the second calculation stage; and performs parallelly "elimination of upper triangular elements of the matrix sum" and "calculation of the second product of the first product and the inverse matrix of the matrix sum" in the fourth calculation stage, so that the time cost of matrix inversion and the time cost of channel estimation can be reduced, and the channel estimation efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer communication technology, and in particular to a channel estimation method, apparatus, device and communication base station. Background Technology

[0002] Currently, the accuracy and real-time performance of channel estimation have a significant impact on the overall system performance. Most current channel estimation methods are implemented in software, which is time-consuming; moreover, the matrix inversion process is complex and time-consuming, resulting in a large time overhead for channel estimation.

[0003] Therefore, how to reduce the time overhead of channel estimation is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a channel estimation method, apparatus, device, and communication base station to reduce the time overhead of channel estimation. The specific solution is as follows:

[0005] In a first aspect, this application provides a channel estimation method applied to FPGA, including:

[0006] Receive the target signal through the target channel and acquire the pilot signal of the antenna element;

[0007] In the first calculation stage, when the covariance matrix of the pilot signal is a complex matrix, the lower triangular elements of the real part of the complex matrix are eliminated;

[0008] In the second calculation stage, the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix are calculated in parallel; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part.

[0009] In the third calculation stage, the lower triangular elements of the sum of the matrices are eliminated;

[0010] In the fourth calculation stage, the elimination of the upper triangular elements of the sum of matrices and the second product of the first product and the inverse matrix of the sum of matrices are calculated in parallel.

[0011] During the channel estimation stage, the inverse of the covariance matrix is ​​calculated from the second product; based on the inverse of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel, the channel state information of the target channel is estimated.

[0012] Optionally, calculating the inverse matrix of the covariance matrix from the second product includes:

[0013] The inverse of the covariance matrix is ​​constructed based on the real part of the inverse of the covariance matrix calculated by the second product and the imaginary part of the inverse of the covariance matrix.

[0014] Optionally, it also includes:

[0015] Between the fourth calculation stage and the channel estimation stage, the real part of the inverse of the complex matrix and the imaginary part of the inverse of the complex matrix are calculated in parallel.

[0016] Optionally, the elimination process of the upper or lower triangular elements of any matrix includes:

[0017] Take each column of the current matrix as the target column, and take the element in the target column located on the diagonal of the matrix as the pivot element;

[0018] Divide all elements in the row containing the pivot by the pivot.

[0019] Set all elements below or above the diagonal in the target column to zero.

[0020] Optionally, it also includes:

[0021] Before the first calculation stage, the real part of the complex matrix is ​​read from the first memory in the FPGA; simultaneously, the complex matrix is ​​read from the first memory.

[0022] Accordingly, during the channel estimation stage, the real part of the inverse of the complex matrix and the imaginary part of the inverse of the complex matrix are stored in the first memory.

[0023] Optionally, it also includes:

[0024] Prior to the first calculation stage, the covariance matrix of the pilot signal is determined.

[0025] Optionally, receiving the target signal through the target channel includes:

[0026] The target signal is received through the target channel using MIMO technology.

[0027] Secondly, this application provides a channel estimation apparatus applied to an FPGA, comprising:

[0028] The signal acquisition module is used to receive the target signal through the target channel and acquire the pilot signal of the antenna element;

[0029] The first execution module is used to eliminate the lower triangular elements of the real part of the complex matrix when the covariance matrix of the pilot signal is a complex matrix during the first calculation stage.

[0030] The second execution module is used in the second calculation stage to perform parallel calculations of the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part.

[0031] The third execution module is used to eliminate the lower triangular elements of the matrix sum in the third calculation stage;

[0032] The fourth execution module is used to perform parallel calculations in the fourth calculation stage of eliminating the upper triangular elements of the sum of matrices and the second product of the first product and the inverse matrix of the sum of matrices.

[0033] The channel estimation module is used to calculate the inverse matrix of the covariance matrix from the second product during the channel estimation stage; and to estimate the channel state information of the target channel based on the inverse matrix of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel.

[0034] Thirdly, this application provides a channel estimation device, including an FPGA, wherein the FPGA is used to implement the method described in any of the preceding descriptions.

[0035] Fourthly, this application provides a channel estimation device, including: an FPGA;

[0036] The FPGA is used to acquire the target signal and the pilot signal of the antenna unit received by the antenna unit through the target channel, and to estimate the channel state information of the target channel based on the target signal and the pilot signal.

[0037] Specifically, the FPGA is used for:

[0038] In the first calculation stage, when the covariance matrix of the pilot signal is a complex matrix, the lower triangular elements of the real part of the complex matrix are eliminated;

[0039] In the second calculation stage, the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix are calculated in parallel; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part.

[0040] In the third calculation stage, the lower triangular elements of the sum of the matrices are eliminated;

[0041] In the fourth calculation stage, the elimination of the upper triangular elements of the sum of matrices and the second product of the first product and the inverse matrix of the sum of matrices are calculated in parallel.

[0042] During the channel estimation stage, the inverse of the covariance matrix is ​​calculated from the second product; based on the inverse of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel, the channel state information is estimated.

[0043] Optionally, the FPGA includes: a first computing module, a second computing module, a third computing module, a fourth computing module, and a fifth computing module;

[0044] In the first calculation stage, the first calculation module eliminates the lower triangular elements of the real part of the complex matrix;

[0045] In the second calculation stage, the first calculation module, the second calculation module, and the third calculation module run in parallel; wherein, the first calculation module eliminates the upper triangular elements of the real part to obtain the inverse matrix of the real part; simultaneously, the second calculation module calculates the first product of the inverse matrix of the real part and the imaginary part of the complex matrix; simultaneously, the third calculation module calculates the matrix sum of the real part and the target matrix;

[0046] In the third calculation stage, the fourth calculation module eliminates the lower triangular elements of the matrix sum;

[0047] In the fourth calculation stage, the fourth calculation module and the fifth calculation module run in parallel; wherein, the fourth calculation module eliminates the upper triangular elements of the sum of matrices to obtain the inverse matrix of the sum of matrices; simultaneously, the fifth calculation module calculates the second product of the first product and the inverse matrix of the sum of matrices.

[0048] Optionally, the FPGA further includes: a result generation module;

[0049] In the channel estimation stage, the result generation module constructs the inverse of the covariance matrix based on the real part and the imaginary part of the inverse of the covariance matrix calculated by the second product; and estimates the channel state information based on the inverse of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel.

[0050] Optionally, between the fourth calculation stage and the channel estimation stage, the fourth calculation module and the fifth calculation module run in parallel;

[0051] Specifically, the fourth calculation module calculates the real part of the inverse of the complex matrix based on the second product and transmits the real part of the inverse of the complex matrix to the result generation module; simultaneously, the fifth calculation module calculates the imaginary part of the inverse of the complex matrix based on the second product and transmits the imaginary part of the inverse of the complex matrix to the result generation module.

[0052] Optionally, both the first computing module and the fourth computing module include:

[0053] The pivot element determination unit is used to take each column of the current input matrix as the target column and take the element located on the diagonal of the matrix in the target column as the pivot element.

[0054] The first transformation unit is used to divide all elements in the row containing the pivot by the pivot.

[0055] The second transformation unit is used to set each element below or above the diagonal in the target column to zero.

[0056] Optionally, the FPGA further includes a first memory storing the complex matrix;

[0057] Prior to the first calculation phase, the first calculation module, the second calculation module, and the third calculation module operate in parallel.

[0058] The first calculation module reads the real part of the complex matrix from the first memory; simultaneously, the second calculation module and the third calculation module read the complex matrix from the first memory.

[0059] During the channel estimation stage, the result generation module outputs the real part and the imaginary part of the inverse of the complex matrix to the first memory, so that the first memory stores the real part and the imaginary part of the inverse of the complex matrix.

[0060] Optionally, the FPGA further includes: a matrix determination module;

[0061] Prior to the first calculation stage, the matrix determination module determines the covariance matrix of the pilot signal.

[0062] Optionally, the antenna unit is specifically used to receive the target signal using MIMO technology.

[0063] A communication base station includes: at least one channel estimation device.

[0064] As can be seen, the channel estimation method provided in this application is applied to FPGA. The channel estimation process is divided into several calculation stages. In the second calculation stage, the "elimination of the upper triangular elements of the real part", "calculation of the first product of the inverse matrix of the real part and the imaginary part of the complex matrix" and "calculation of the matrix sum of the real part and the target matrix" are executed in parallel. In the fourth calculation stage, the "elimination of the upper triangular elements of the matrix sum" and "calculation of the second product of the first product and the inverse matrix of the matrix sum" are executed in parallel. This can reduce the time overhead of matrix inversion and channel estimation, thereby improving the efficiency of channel estimation.

[0065] Correspondingly, the channel estimation device, equipment, communication base station, and others provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0066] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0067] Figure 1 This is a schematic diagram of the operational logic for inverting a complex matrix as disclosed in this application;

[0068] Figure 2 A schematic diagram illustrating the operational logic for inverting another complex matrix disclosed in this application;

[0069] Figure 3 This is a schematic diagram of the operational logic for inverting a real matrix as disclosed in this application;

[0070] Figure 4 This is a schematic diagram of a logic module reading RAM as disclosed in this application;

[0071] Figure 5 A schematic diagram of the computation process in the first parallel computation cycle of the second computation stage of complex matrix inversion disclosed in this application;

[0072] Figure 6 A schematic diagram of the computation process in the second parallel computation cycle of the second computation stage of complex matrix inversion disclosed in this application;

[0073] Figure 7 A schematic diagram of the calculation process in the N+1th parallel calculation cycle of the second calculation stage of complex matrix inversion disclosed in this application;

[0074] Figure 8 A schematic diagram of the computation process in the N+2th parallel computation cycle of the second computation stage of complex matrix inversion disclosed in this application;

[0075] Figure 9 A schematic diagram of the computation process in the 2N+1th parallel computation cycle of the second computation stage of complex matrix inversion disclosed in this application;

[0076] Figure 10 A schematic diagram of the calculation process in the 2N+2th parallel calculation cycle of the second calculation stage of complex matrix inversion disclosed in this application;

[0077] Figure 11 A schematic diagram of the computation process of the first parallel computation cycle of the fourth computation stage of complex matrix inversion disclosed in this application;

[0078] Figure 12 A schematic diagram of the computation process in the second parallel computation cycle of the fourth computation stage of complex matrix inversion disclosed in this application;

[0079] Figure 13 A schematic diagram of the calculation process in the N+1th parallel calculation cycle of the fourth calculation stage of complex matrix inversion disclosed in this application;

[0080] Figure 14 A schematic diagram of the computation process in the N+2th parallel computation cycle of the fourth computation stage of complex matrix inversion disclosed in this application;

[0081] Figure 15 This is a schematic diagram of a channel estimation device disclosed in this application;

[0082] Figure 16 This is a schematic diagram of a communication system disclosed in this application;

[0083] Figure 17 This is a schematic diagram of another channel estimation device disclosed in this application;

[0084] Figure 18 This is a flowchart of a channel estimation method disclosed in this application;

[0085] Figure 19 This is a schematic diagram of a channel estimation device disclosed in this application. Detailed Implementation

[0086] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0087] Currently, the accuracy and real-time performance of channel estimation have a significant impact on the overall system performance. Most current channel estimation methods are implemented in software, which is time-consuming; moreover, the matrix inversion process is complex and time-consuming, resulting in a large time overhead for channel estimation.

[0088] Please see Figure 18 This application discloses a channel estimation method applied to an FPGA, comprising:

[0089] S101. Receive the target signal through the target channel and obtain the pilot signal of the antenna element.

[0090] In one example, receiving a target signal through a target channel includes receiving the target signal through the target channel using MIMO technology. That is, the antenna element receives the target signal on the target channel using MIMO technology.

[0091] S102. In the first calculation stage, when the covariance matrix of the pilot signal is a complex matrix, the lower triangular elements of the real part of the complex matrix are eliminated.

[0092] S103. In the second calculation stage, the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part in the complex matrix, and the matrix sum of the real part and the target matrix are calculated in parallel. The target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part.

[0093] S104. In the third calculation stage, eliminate the lower triangular elements of the matrix sum.

[0094] S105. In the fourth calculation stage, the elimination of the upper triangular elements of the matrix sum and the second product of the first product and the inverse matrix of the matrix sum are calculated in parallel.

[0095] S106. In the channel estimation stage, the inverse of the covariance matrix is ​​calculated by the second product; based on the inverse of the covariance matrix, the signal matrix obtained by converting the target signal, the pilot matrix obtained by converting the pilot signal, and the channel matrix of the target channel, the channel state information of the target channel is estimated.

[0096] In one example, the inverse of the covariance matrix is ​​calculated from the second product by: constructing the inverse of the covariance matrix based on the real part and the imaginary part of the inverse of the covariance matrix calculated from the second product.

[0097] In one example, the calculation also includes: between the fourth calculation stage and the channel estimation stage, parallel computation of the real part and the imaginary part of the inverse of the complex matrix. This enables parallel computation of the "real part of the inverse of the complex matrix" and the "imaginary part of the inverse of the complex matrix".

[0098] In one example, the process of eliminating upper or lower triangular elements of any matrix includes: taking each column of the current matrix as the target column, taking the element in the target column located on the diagonal of the matrix as the pivot; dividing all elements in the row containing the pivot by the pivot; and setting all elements below or above the diagonal of the target column to zero.

[0099] In one example, the method further includes: before the first calculation stage, reading the real part of the complex matrix from a first memory in the FPGA; simultaneously, reading the complex matrix from the first memory; correspondingly, during the channel estimation stage, storing the real part of the inverse matrix of the complex matrix and the imaginary part of the inverse matrix of the complex matrix into the first memory.

[0100] In one example, the method further includes determining the covariance matrix of the pilot signal prior to the first calculation stage.

[0101] For the specific implementation of the relevant steps in this embodiment, please refer to other embodiments of this application.

[0102] As can be seen, the channel estimation method provided in this embodiment is applied to an FPGA. The FPGA divides the channel estimation process into several computational stages. In the second computational stage, it executes in parallel the "elimination of the upper triangular elements of the real part", "calculation of the first product of the inverse matrix of the real part and the imaginary part of the complex matrix", and "calculation of the matrix sum of the real part and the target matrix". In the fourth computational stage, it executes in parallel the "elimination of the upper triangular elements of the matrix sum" and "calculation of the second product of the first product and the inverse matrix of the matrix sum". This reduces the time overhead of matrix inversion and channel estimation, thereby improving the efficiency of channel estimation. The FPGA can also provide high-performance computing for algorithms such as target recognition and target tracking.

[0103] Please see Figure 19 This application discloses a channel estimation device applied to an FPGA, comprising:

[0104] The signal acquisition module is used to receive the target signal through the target channel and acquire the pilot signal of the antenna element;

[0105] The first execution module is used to eliminate the lower triangular elements of the real part of the complex matrix when the covariance matrix of the pilot signal is a complex matrix during the first calculation stage.

[0106] The second execution module is used in the second calculation stage to perform parallel calculations of the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part.

[0107] The third execution module is used to eliminate the lower triangular elements of the matrix sum in the third calculation stage;

[0108] The fourth execution module is used in the fourth computation stage to perform parallel computation of the elimination of the upper triangular elements of the matrix sum, and the second product of the first product and the inverse matrix of the matrix sum;

[0109] The channel estimation module is used to calculate the inverse of the covariance matrix from the second product during the channel estimation stage; and to estimate the channel state information of the target channel based on the inverse of the covariance matrix, the signal matrix obtained from the target signal conversion, the pilot matrix obtained from the pilot signal conversion, and the channel matrix of the target channel.

[0110] In one example, the channel estimation module is specifically used to construct the inverse of the covariance matrix based on the real part and the imaginary part of the inverse of the covariance matrix calculated by the second product.

[0111] In one example, the system further includes a parallel computation module for the real and imaginary parts of the inverse of a complex matrix, used to compute the real part and the imaginary part of the inverse of the complex matrix in parallel between the fourth computation stage and the channel estimation stage. This enables the parallel computation of the "real part of the inverse of the complex matrix" and the "imaginary part of the inverse of the complex matrix".

[0112] In one example, the process of eliminating upper or lower triangular elements of any matrix includes: taking each column of the current matrix as the target column, taking the element in the target column located on the diagonal of the matrix as the pivot; dividing all elements in the row containing the pivot by the pivot; and setting all elements below or above the diagonal of the target column to zero.

[0113] In one example, the system further includes: a read module for reading the real part of the complex matrix from a first memory in the FPGA before the first calculation stage; and a storage module for reading the complex matrix from the first memory; correspondingly, during the channel estimation stage, the real part of the inverse matrix of the complex matrix and the imaginary part of the inverse matrix of the complex matrix are stored in the first memory.

[0114] This application also provides a channel estimation device, including an FPGA, which is used to implement the channel estimation method provided in this application.

[0115] This application also provides a communication base station, including: at least one channel estimation device.

[0116] Please see Figure 15This application discloses a channel estimation device, including an active antenna unit and a baseband processing unit connected to the active antenna unit. The active antenna unit is used to receive a target signal through a target channel; the baseband processing unit includes a CPU and an FPGA; the CPU is used to acquire the pilot signal and the target signal of the active antenna unit; the FPGA is used to estimate the channel state information of the target channel based on the pilot signal and the target signal.

[0117] Specifically, the active antenna unit is used to receive the target signal using MIMO (Multiple Input Multiple Output) technology. MIMO improves the performance of the communication system by increasing the number of antennas at both the transmitting and receiving ends and using higher frequencies. Large-scale MIMO can fully utilize spatial resources, enhance spatial resolution, and improve the spectral efficiency and power efficiency of communication without increasing the number of base stations. However, the channel estimation process under large-scale MIMO is very complex, especially the matrix inversion operation involved. Therefore, this embodiment uses an FPGA to improve the efficiency of matrix inversion operation in the channel estimation process.

[0118] In this process, the FPGA is used for the following: When the covariance matrix of the pilot signal is a complex matrix, in the first calculation stage, it eliminates the lower triangular elements of the real part of the complex matrix; in the second calculation stage, it eliminates the upper triangular elements of the real part; it calculates the first product of the inverse matrix of the real part and the imaginary part of the complex matrix; it calculates the matrix sum of the real part and the target matrix, where the target matrix is ​​the product of the imaginary part, the inverse matrix of the real part, and the imaginary part; in the third calculation stage, it eliminates the lower triangular elements of the matrix sum; in the fourth calculation stage, it eliminates the upper triangular elements of the matrix sum and calculates the second product of the first product and the inverse matrix of the matrix sum; in the channel estimation stage, it calculates the inverse matrix of the covariance matrix from the second product; and based on the inverse matrix of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel, it estimates the channel state information. The FPGA divides the complex matrix inversion operation into several calculation stages, enabling parallel execution of related operations within the same calculation stage. Therefore, while adhering to the computational logic of complex matrix inversion, parallel execution of related operations can reduce the time overhead of matrix inversion and channel estimation, thereby improving the timeliness of channel estimation. This FPGA can also provide high-performance computing for algorithms such as target recognition and target tracking.

[0119] The FPGA includes: a matrix determination module, a first calculation module, a second calculation module, a third calculation module, a fourth calculation module, a fifth calculation module, and a result generation module. Therefore, the FPGA implements a complex matrix inversion circuit comprising the matrix determination module, the first calculation module, the second calculation module, the third calculation module, the fourth calculation module, the fifth calculation module, and the result generation module.

[0120] The FPGA utilizes five computation modules and one result generation module to perform complex matrix inversion operations, which reduces the time overhead of matrix inversion and channel estimation, thereby improving the channel estimation efficiency of the channel estimation device. In the FPGA, the matrix determination module is used to determine the covariance matrix of the pilot signal.

[0121] See Figure 1 As shown, the first calculation module is used to: if the covariance matrix is ​​a complex matrix, then in the first calculation stage, eliminate the lower triangular elements of the real part A in the complex matrix C = A + iB; in the second calculation stage, eliminate the upper triangular elements of the real part A to obtain the inverse matrix A of the real part A. -1 .

[0122] The second calculation module is used to: calculate the inverse matrix A of the real part A in the second calculation stage. -1 The first product A with the imaginary part B in the complex matrix -1 B.

[0123] The third calculation module is used to: in the second calculation stage, calculate the matrix sum A+Q = A+BA of the real part A and the target matrix Q. -1 B, the objective matrix Q is the inverse matrix A of the imaginary part B and the real part A. -1 The product of B and the imaginary part B is BA. -1 B, that is: Q = BA -1 B.

[0124] The fourth calculation module is used to: eliminate matrices and A+BA in the third calculation stage. -1 The lower triangular elements of B; in the fourth calculation stage, eliminate the matrix and A+BA. -1 The upper triangular elements of B yield the matrix and A+BA. -1 The inverse matrix of B (A+BA) -1 B) -1 .

[0125] The fifth calculation module is used to: calculate the first product and matrix sum A+BA in the fourth calculation stage. -1 The inverse matrix of B (A+BA) -1 B) -1 The second product A -1 B(A+BA -1 B) -1 .

[0126] The result generation module is used to output the second product A. -1 B(A+BA -1 B) -1 The inverse matrix C of the calculated complex matrix C -1 The real part of the complex matrix C and the inverse of the complex matrix C -1The imaginary part of the covariance matrix. In the channel estimation stage, the result generation module constructs the inverse of the covariance matrix based on the real and imaginary parts of the inverse of the covariance matrix calculated by the second product. Based on the inverse of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel, the channel state information is estimated. Specifically, the result generation module performs least squares estimation, minimum mean square error estimation, maximum expectation estimation, and / or maximum likelihood estimation on the inverse of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel to obtain the channel state information. A common feature of these estimation methods is that they all require calculating the inverse of the covariance matrix of the pilot signal. Especially when the antenna array is large, the inversion operation of a large-scale matrix is ​​very time-consuming, significantly impacting the system's real-time performance; therefore, it is necessary to accelerate the matrix inversion process.

[0127] Among them, the channel state information is estimated based on the inverse of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel, including: according to the formula Obtain channel state information. Among them, The covariance matrix R X The inverse matrix, and the covariance matrix R of the pilot matrix X obtained by pilot signal conversion. X =X H X, R X The subscript X represents the pilot signal, Y is the signal matrix obtained by converting the target signal, and H is the channel matrix of the target channel. The covariance matrix R... X =C=A+iB.

[0128] In this embodiment, when calculating the inverse matrix of the covariance matrix of the pilot signal, the FPGA utilizes five calculation modules and one result generation module to perform complex matrix inversion operations, which can improve the efficiency of complex matrix inversion; simultaneously, matrix multiplication X can also be calculated in parallel. H Y saves computation time by performing matrix multiplication last. Obtain the channel state information of the channel.

[0129] In one example, the received target signal is represented as Y = XH + Z, where, The signal matrix obtained by converting the received target signal. Represents T×N R A set of 3D complex matrices The pilot matrix is ​​obtained by converting the pilot signal, where T is the length of the pilot signal and N is the length of the pilot signal. R and N T These represent the number of receiving and transmitting antennas, respectively. The channel matrix of the target channel. It is a noise matrix and vec(·) denotes the vectorization operator. The expected value is 0, and the covariance matrix is... The complex Gaussian distribution, This represents the variance of each component of the random noise vector. If the channel is estimated using the least squares method, the estimated channel state information is represented as: If the channel is estimated using the minimum mean square error, then the estimated channel state information is represented as follows: E{·} represents expectation.

[0130] Please see Figure 2 The fourth calculation module is also used for: based on the second product A -1 B(A+BA -1 B) -1 The inverse matrix C of the complex matrix C is calculated. -1 The real part of the complex matrix C, and the inverse matrix C of the complex matrix C. -1 The real part is transmitted to the result generation module; simultaneously, the fifth calculation module is also used to: based on the second product A -1 B(A+BA -1 B) -1 The inverse matrix C of the complex matrix C is calculated. -1 The imaginary part of the complex matrix C, and the inverse of the complex matrix C. -1 The imaginary part is transmitted to the result generation module.

[0131] In one implementation, the FPGA further includes a first memory storing a complex matrix C = A + iB (e.g., ...). Figure 2 The first calculation module is configured to read the real part of the complex matrix from the first memory; the second calculation module and the third calculation module are configured to read the complex matrix from the first memory; and the result generation module is configured to output the real part of the inverse matrix and the imaginary part of the inverse matrix of the complex matrix to the first memory, so that the first memory stores the real part of the inverse matrix and the imaginary part of the inverse matrix of the complex matrix.

[0132] In this embodiment, the FPGA provided by the PFGA utilizes five computation modules and one result generation module to perform complex matrix inversion operations. The complex matrix inversion operation is divided into several computation stages, allowing different computation modules to execute related operations in parallel within the same stage. For example, the first, second, and third computation modules execute in parallel during the second computation stage; the fourth and fifth computation modules execute in parallel during the fourth computation stage. Thus, while adhering to the computational logic of complex matrix inversion, the parallel execution of related operations by each computation module reduces the time overhead of matrix inversion and channel estimation. This PFGA is expected to provide high-performance computing for algorithms such as target recognition and target tracking.

[0133] Please see Figure 3 The FPGA further includes: a second memory (such as...) Figure 3 RAM_A in the middle), third memory (such as RAM_A ...) Figure 3 The system consists of a RAM (RAM_E) and an arithmetic module. The second memory stores the real matrix, and the third memory stores the identity matrix. The arithmetic module transforms the real matrix in the second memory into the identity matrix and the identity matrix in the third memory into the inverse of the real matrix using Gaussian-Jordan elimination. The arithmetic module comprises n logic modules, where n is the number of columns in the real matrix. These n logic modules are used to eliminate non-pivot elements in the corresponding columns of the real matrix using Gaussian-Jordan elimination. In other words, each logic module eliminates non-pivot elements in one column. The n logic modules are identical; changing the number of columns n in the real matrix simply requires increasing the number of logic modules, making it easy to expand and implement. The n logic modules operate serially.

[0134] In one example, the computation module includes a logic module used to sequentially eliminate non-pivoting elements from each column of the real matrix using Gaussian-Jordan elimination. That is, the computation module reuses the same logic module to sequentially eliminate non-pivoting elements from each column of the real matrix. When the number of columns n of the real matrix changes, the number of repetitions of the computation logic only needs to be increased accordingly.

[0135] As mentioned earlier, this embodiment focuses on real matrix inversion. A logic module is designed based on Gaussian-Jordan elimination to perform elementary row operations on the data matrix (real matrix) and the identity matrix stored in RAM. This eliminates all elements except the pivot in a column of the data matrix. Multiple logic modules then perform column-by-column elimination on the data matrix, while simultaneously performing the same elementary operations on the identity matrix. Finally, the inverse of the data matrix is ​​obtained in RAM_E. When implementing the real matrix inversion circuit using an FPGA, only n logic modules need to be set up in parallel. Two RAM memories are used to store the data matrix and the identity matrix, respectively. The matrix inversion process using a single logic module based on Gaussian-Jordan elimination involves elementary row operations on the matrix. The multiplication and division operations involved can be implemented using the FPGA's built-in IP cores. Both RAM memories are dual-port RAMs. Initially, each RAM stores the data matrix and the identity matrix, respectively. During the inversion process, the same read and write operations are performed on both RAMs. When the value in RAM_A becomes the identity matrix, the value in RAM_E becomes the inverse of the data matrix.

[0136] It should be noted that the element 1 in the identity matrix needs to be quantized to ensure precision in subsequent calculations; the quantized value is 2. t The final result can be easily shifted according to the requirements of the scenario.

[0137] The principle of finding the inverse of a real matrix is: if matrix D is the inverse of matrix A, then DA = E, where E is the identity matrix. According to this formula, for the extended matrix [A,E], D[A,E] = [E,D]. The process of D[A,E] is essentially performing elementary transformations on the extended matrix [A,E]. Therefore, the entire matrix inversion process becomes transforming matrix A into the identity matrix through elementary transformations, and then performing the same elementary transformations on E. The result is the inverse matrix A. -1 To ensure computational accuracy, especially in division operations, the element 1 in matrix E needs to be quantized; the actual value used is 2. t E, and finally the inverse matrix A. -1 Then, perform the corresponding shift operation.

[0138] Specifically, eliminating the element a below the diagonal of the j-th column of the N×N real matrix A j+1,j a j+2,j ... a N,j First, find the pivot element, taking the element on the diagonal of each column as the pivot. Then, divide all elements in the row containing the pivot by the pivot element, making the pivot value 1. Finally, let element ak... ,j The row containing the pivot element minus the row containing the pivot element multiplied by a k,j a k,jLet k represent the element in the k-th row and j-th column, where k = j+1, j+2, ..., N. The elements below the diagonal of the column containing the pivot are changed to 0. This process eliminates elements below the diagonal of a given column. Correspondingly, the same elementary row operations are performed on the identity matrix E.

[0139] Based on the above process, a logic module is designed and implemented. To invert an N×N matrix, N unit logic modules are needed. Different logic modules operate on different columns; therefore, it is only necessary to identify the different column numbers at the interface of the logic module. Each unit logic module includes 2 multipliers, 2 dividers, and 2 adders. Therefore, inverting an N×N matrix requires 2N multipliers, 2N dividers, and 2N adders.

[0140] The RAM read / write logic module is used to operate on RAM_A and RAM_E. Please refer to [link / reference]. Figure 4 The operations of different logic modules on RAM_A and RAM_E are as follows: Figure 4 As shown. Inside the logic module, since read and write operations are required on data in different RAM addresses, address operations are standardized to make them applicable to column operations. Therefore, real matrix inversion is characterized by ease of expansion and implementation, greatly shortening engineering development time.

[0141] In one example, when inverting a complex matrix, the inversion formula is used to transform the process into operations on real matrices. The entire computation process is then divided into four stages. In the second and fourth stages, multiple computation modules process the matrix inversion in parallel, thereby shortening the processing time and allowing the complex matrix inversion circuit to be applied to high real-time systems. This effectively avoids the significant transmission delay caused by calculating the matrix inversion on the PC. For the inverse matrix C = A + iB, the inverse matrix C... -1 C -1 The real part can be equivalent to (A+BA) -1 B) -1 The imaginary part can be equivalent to A. -1 B(A+BA -1 B) -1 Therefore, we should try to parallelize the operations in the formula to reduce processing time. The inverse of a complex invertible matrix C = A + iB can be represented as C -1 = (A + iB) -1 = (A+BA) -1 B) -1 -iA - 1 B(A+BA -1 B) -1 Note that the above formula involves two inversions of the real matrix A. -1 and(A+BA -1 B)-1 And 3rd matrix multiplication A -1 ×B、B×A -1 B and A -1 B×(A+BA -1 B) -1 The above steps have a dependency relationship (corresponding to the computational logic of complex matrix inversion). If we follow A... -1 A -1 ×B、B×A -1 B, (A+BA) -1 B) -1 and A -1 B×(A+BA -1 B) -1 The steps involved in calculating the complex matrix inverse sequentially are time-consuming. Therefore, this embodiment further decomposes the matrix calculation into parallel steps, significantly reducing the time overhead of complex matrix inversion.

[0142] Please see Figure 2 The first calculation stage of complex matrix inversion completes the function of eliminating the lower triangular elements of matrix A in the first calculation module. The first calculation module uses multipliers and adders. The first calculation module then transmits the calculation result to the second calculation stage.

[0143] The second calculation stage has three calculation modules that can run in parallel. The first calculation module eliminates the upper triangular elements of matrix A to obtain the inverse matrix A. -1 The second calculation module calculates A. -1 ×B, the second calculation module uses multipliers and adders; the reason why the lower triangular elements and upper triangular elements of matrix A are eliminated separately is for A -1 and A -1 ×B can perform parallel computation.

[0144] Note that the multiplication of any P×Q dimensional matrix X and Q×S dimensional matrix Y can be expressed as: Where x p Let X be the p-th row of matrix X. Assume X is obtained through row-by-row calculations using other mathematical processes, and Y is a known matrix. Then, it's clear that we don't need to wait for all elements of matrix X to be calculated before calculating the multiplication Z = X × Y; instead, we only need to obtain one row x of matrix X. p The corresponding row z of matrix Z can then be calculated. p =x p Y. Based on the above principle, in the second calculation stage, the first calculation module obtains the inverse matrix A row by row through upper triangular elimination. -1 Each calculation yields matrix A. -1 A can be calculated in the second calculation module from a single line. -1 The row corresponding to B.

[0145] It is also noted that the multiplication of any P×Q dimensional matrix X and Q×S dimensional matrix Y can be expressed as in Let y be the q-th column of matrix X. q Let Y be the q-th row of matrix Y. Therefore, matrix multiplication can be divided into q steps, with each step calculating a vector product. Suppose Y is obtained through row-by-row calculations using other mathematical processes, and X is a known matrix. Then it's clear that we don't need to wait for all elements of matrix Y to be calculated before we can calculate the multiplication Z = X × Y. Instead, we only need to obtain one row y of matrix Y. q This allows us to calculate the corresponding vector multiplication. Based on the above principles, in the second calculation stage, for matrix multiplication B×A... -1 B, when the second calculation module calculates A -1 After the q-th row of B, the third calculation module can then perform the vector product b. q (A -1 B) q The calculation, where b q Let q be the q-th column of matrix B, (A -1 B) q A represents -1 The qth row of B. This parallel design effectively shortens the overall computation time and quickly yields the results of matrix multiplication.

[0146] The third computation stage is similar in principle to the first computation stage, and the parallel computation principle of the fourth computation stage is similar to that of the second stage, so it will not be described again.

[0147] For the complex matrix C = A + iB, the inverse of the real matrix A is calculated using Gaussian-Jordan elimination in the first calculation stage. During the elimination process, elements below the main diagonal are first eliminated; specifically...

[0148] Eliminating the element 'a' below the j-th column diagonal of the N×N real matrix A j+1,j a j+2,j ... a N,j First, designate the element at the diagonal position as the pivot. Then, divide all elements in the row containing the pivot by the pivot, making the pivot value 1. Finally, set element ak... ,j The row containing the pivot element minus the row containing the pivot element multiplied by ak ,j a k,jLet $k$ represent the element in the $k$-th row and $j$-th column, where $k = j+1, j+2, ..., N$. The elements below the diagonal of the column containing the pivot are changed to 0. This process eliminates elements below the diagonal of a given column. The same operation is performed on the identity matrix $E$. Finally, the extended matrix $[A, E]$ is transformed into the form $[U, L]$ through elementary row operations, where $U$ is an upper triangular matrix with diagonal elements of 1, and $L$ is a lower triangular matrix.

[0149] After completing the first computational phase, the second phase of parallel computation begins. After the first phase, the extended matrix [A,E] is transformed into the form [U,L] through elementary row operations, where U is an upper triangular matrix with diagonal elements of 1, and L is a lower triangular matrix. Then, Gaussian elimination is used to eliminate the elements above the diagonal of the upper triangular matrix U. However, it's important to note that this process differs from eliminating the elements below the diagonal of matrix A. Specifically, when eliminating the elements above the diagonal of the upper triangular matrix U, the first iteration starts from the Nth row at the bottom of the extended matrix [U,L], multiplying the Nth row by -u. kN (u kN Let the element in the k-th row and N-th column of matrix U (k = 1, 2, ..., N-1) be added to the k-th row of the extended matrix [U, L], thereby eliminating the N-th element in the k-th row of the extended matrix [U, L]. In other words, the N-th row of matrix L remains unchanged during this process, which is the same as the element in matrix A. -1 The Nth row. Similarly, when eliminating the (N-1)th column elements above the diagonal of matrix U, the operation only affects rows 1 to N-2 of the extended matrix [U,L]. The (N-1)th row of matrix L remains unchanged, which is the same as matrix A. -1 The (N-1)th row. Using this property, A can be computed in parallel. -1 A -1 ×B、B×A -1 B and A+BA -1 B consists of these four processes.

[0150] Figure 5 and Figure 6 This illustrates the parallel computation A after entering the second computation stage. -1 and A -1 The process of multiplying by B. For ease of representation, a 4th-order matrix is ​​used as an example; this process applies to Nth-order matrices. Parallel computation of A. -1 and A -1 The specific process of ×B includes: In the first parallel computing cycle of the second computing stage, the first computing module eliminates the elements u in the upper triangular matrix U through N multiplications and N subtractions. N-1,N Meanwhile, the second calculation module runs in parallel, that is, the second calculation module calculates the matrix F = A through N multiplications and N-1 additions. -1 The element f in the Nth row and 1st column of ×BN,1 After N-1 parallel computation cycles, all elements above the diagonal of the Nth column of the upper triangular matrix U are eliminated. After another parallel computation cycle, matrix F = A is completed. -1 Calculation of the Nth row element of ×B.

[0151] Figures 7 to 10 This illustrates that parallel computation of A begins from the (N+1)th parallel computation cycle of the second computation stage. -1 F = A -1 ×B and H=A+BA -1 The process of B. Starting from the (N+1)th parallel computing cycle of the second computing phase, A is computed in parallel. -1 F = A -1 ×B and H=A+BA -1 B. Starting from the (N+1)th parallel computing cycle of the second computing phase, F = A -1 The Nth row element of ×B has been calculated. Note the matrix operations. a k Let b represent the k-th row of matrix A, where k = 1, 2, ..., N. j Let A represent the j-th column of matrix B, where j = 1, 2, ..., N, (A -1 B) j Representing matrix A -1 The j-th row of B, b kj Let represent the element in the k-th row and j-th column of matrix B. In addition to the two parallel computing modules mentioned above, a third parallel computing module is added. Then, in each parallel computing cycle, the sum of the last vector multiplication result of the summation term in the last row of matrix H and the sum of the N-th row of matrix A is calculated through N multiplications and N additions. N +b NN (A -1 B) N Repeating the above process, after N parallel computing cycles, at the end of the 2Nth parallel computing cycle, the third computing module can obtain A+b in matrix H. N (A -1 B) N As a result, the first and second calculation modules can respectively provide A -1 The last 3 lines and F=A -1 The last two lines of ×B.

[0152] It is worth noting that the elimination process in the first calculation module requires N(N-1) / 2 parallel computing cycles to complete because the number of elements to be eliminated in each column decreases. The second and third calculation modules require a total of N cycles to complete the matrix multiplication. 2 Each parallel computing cycle.

[0153] The third calculation stage is similar to the first calculation stage, also using the Gaussian-Jordan elimination method to calculate the inverse matrix H. -1 = (A+BA) -1 B) -1 The third calculation stage ends when the lower triangular elements of the matrix are completely eliminated and the extended matrix [H,E] is transformed into [U,L], where U is an upper triangular matrix with diagonal elements of 1 and L is a lower triangular matrix.

[0154] After transforming the extended matrix [H,E] into [U,L], the fourth calculation stage continues, and the inverse matrix H is calculated in parallel. -1 Matrix multiplication K = F × H -1 =A -1 B×(A+BA -1 B) -1 . Figures 11 to 14 This illustrates the parallel computing process in the fourth computing stage.

[0155] The fourth computation stage involves parallel computation of the inverse matrix H. -1 = (A+BA) -1 B) -1 Matrix multiplication K = F × H -1 =A -1 B×(A+BA -1 B) -1 In the first parallel computing cycle of the fourth computing stage, the fourth computing module eliminates the element u in the upper triangular matrix U through N multiplications and N subtractions. N-1,N (u N-1,N (This refers to the element in the (N-1)th row and Nth column of matrix U), while also noting matrix operations. , (A - 1 B) j Representing matrix A -1 Column j of B, ((A+BA -1 B) -1 ) j Representing the matrix (A+BA) -1 B) -1 The j-th row, (A -1 B) kj Representing matrix A -1 B is in the k-th row and j-th column, where k = 1, 2, ..., N. Therefore, the last term (A) of the summation term in the first row of matrix K can be obtained in parallel through N multiplications in the fifth calculation module. -1 B) 1N ((A+BA -1 B) -1 ) N After N-1 parallel computation cycles, all elements in the last column of the upper triangular matrix U are eliminated. After another parallel computation cycle, the vector product (A) is completed.-1 B) N ((A+BA -1 B) -1 ) N The calculation.

[0156] In the (N+1)th parallel computation cycle of the fourth computation stage, the fourth computation module continues to eliminate other off-diagonal elements in the upper triangular matrix U through N multiplications and N subtractions. Simultaneously, the fifth computation module calculates the remaining vector products in matrix K through N multiplications and N additions. This process repeats continuously, requiring a total of N(N-1) / 2 parallel computation cycles to complete the inverse matrix H. -1 The calculation yields the real part of the inverse of the complex matrix C = A + iB. Simultaneously, a total of N... 2 One calculation cycle is needed to complete matrix multiplication K = F × H -1 The calculation yields the imaginary part of the inverse of the complex matrix C = A + iB.

[0157] As can be seen, this embodiment utilizes multiple computing modules to rapidly calculate the inverse of a complex matrix in parallel, significantly reducing computation time. This greatly shortens the computation time for channel estimation in large-scale MIMO systems, effectively improving the real-time performance of communication systems. Furthermore, it has broad application prospects in fields with high computational performance requirements, such as target tracking and real-time communication. The complex matrix inversion circuit can be implemented using an FPGA.

[0158] In addition, this application also provides a communication system, including: at least one of the aforementioned communication base stations.

[0159] Please see Figure 16 A communication system includes: a communication base station, the communication base station including a channel estimation device consisting of an active antenna element and a baseband processing unit, the active antenna element receiving signals from a terminal through channel H.

[0160] Please see Figure 17 This application discloses a channel estimation device, which includes an FPGA. The FPGA is used to acquire the target signal received by the antenna element through the target channel and the pilot signal of the antenna element, and to estimate the channel state information of the target channel based on the target signal and the pilot signal.

[0161] Specifically, the FPGA is used for: in the first calculation stage, when the covariance matrix of the pilot signal is a complex matrix, eliminating the lower triangular elements of the real part of the complex matrix; in the second calculation stage, parallelly calculating the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix; the target matrix is ​​the product of the imaginary part, the inverse matrix of the real part, and the imaginary part; in the third calculation stage, eliminating the lower triangular elements of the matrix sum; in the fourth calculation stage, parallelly calculating the elimination of the upper triangular elements of the matrix sum, and the second product of the first product and the inverse matrix of the matrix sum; in the channel estimation stage, calculating the inverse matrix of the covariance matrix from the second product; and estimating the channel state information based on the inverse matrix of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel.

[0162] As can be seen, the FPGA in this embodiment divides the channel estimation process into several computational stages. In the second computational stage, it executes in parallel the "elimination of the upper triangular elements of the real part", "calculation of the first product of the inverse matrix of the real part and the imaginary part of the complex matrix", and "calculation of the matrix sum of the real part and the target matrix". In the fourth computational stage, it executes in parallel the "elimination of the upper triangular elements of the matrix sum" and "calculation of the second product of the first product and the inverse matrix of the matrix sum". This reduces the time overhead of matrix inversion and channel estimation, thereby improving the efficiency of channel estimation. The FPGA can also provide high-performance computing for algorithms such as target recognition and target tracking.

[0163] In one example, the FPGA includes: a first computing module, a second computing module, a third computing module, a fourth computing module, and a fifth computing module; in a first computing stage, the first computing module eliminates the lower triangular elements of the real part of the complex matrix; in a second computing stage, the first, second, and third computing modules operate in parallel; wherein, the first computing module eliminates the upper triangular elements of the real part to obtain the inverse matrix of the real part; simultaneously, the second computing module calculates the first product of the inverse matrix of the real part and the imaginary part of the complex matrix; simultaneously, the third computing module calculates the matrix sum of the real part and the target matrix; in the third computing stage, the fourth computing module eliminates the lower triangular elements of the matrix sum; in the fourth computing stage, the fourth and fifth computing modules operate in parallel; wherein, the fourth computing module eliminates the upper triangular elements of the matrix sum to obtain the inverse matrix of the matrix sum; simultaneously, the fifth computing module calculates the second product of the first product and the inverse matrix of the matrix sum.

[0164] In one example, the FPGA further includes: a result generation module; during the channel estimation stage, the result generation module constructs the inverse of the covariance matrix based on the real part and the imaginary part of the inverse of the covariance matrix calculated by the second product; and estimates the channel state information based on the inverse of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel.

[0165] In one example, between the fourth calculation stage and the channel estimation stage, the fourth calculation module and the fifth calculation module run in parallel; wherein, the fourth calculation module calculates the real part of the inverse of the complex matrix based on the second product and transmits the real part of the inverse of the complex matrix to the result generation module; at the same time, the fifth calculation module calculates the imaginary part of the inverse of the complex matrix based on the second product and transmits the imaginary part of the inverse of the complex matrix to the result generation module.

[0166] In one example, both the first and fourth calculation modules include: a pivot determination unit, used to take each column of the current input matrix as the target column and the element located on the diagonal of the target column as the pivot; a first transformation unit, used to divide all elements in the row containing the pivot by the pivot; and a second transformation unit, used to set all elements below or above the diagonal of the target column to zero. The first and fourth calculation modules eliminate non-pivotal elements according to the Gaussian-Jordan elimination method.

[0167] In one example, the FPGA also includes a first memory storing a complex matrix; prior to the first calculation stage, a first calculation module, a second calculation module, and a third calculation module operate in parallel; wherein, the first calculation module reads the real part of the complex matrix from the first memory; simultaneously, the second and third calculation modules read the complex matrix from the first memory; during the channel estimation stage, the result generation module outputs the real part of the inverse matrix and the imaginary part of the inverse matrix of the complex matrix to the first memory, so that the first memory stores the real part of the inverse matrix and the imaginary part of the inverse matrix of the complex matrix.

[0168] In one example, the FPGA also includes a matrix determination module; prior to the first calculation stage, the matrix determination module determines the covariance matrix of the pilot signal.

[0169] In one example, the antenna element is specifically used to receive target signals using MIMO technology.

[0170] The terms “first,” “second,” “third,” “fourth,” etc., used in this application (if applicable) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, or apparatus.

[0171] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0172] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0173] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the art.

[0174] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A channel estimation method, characterized in that, Applied to FPGAs, including: Receive the target signal through the target channel and acquire the pilot signal of the antenna element; In the first calculation stage, when the covariance matrix of the pilot signal is a complex matrix, the lower triangular elements of the real part of the complex matrix are eliminated; In the second calculation stage, the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix are calculated in parallel; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part. In the third calculation stage, the lower triangular elements of the sum of the matrices are eliminated; In the fourth calculation stage, the elimination of the upper triangular elements of the sum of matrices and the second product of the first product and the inverse matrix of the sum of matrices are calculated in parallel. During the channel estimation stage, the inverse of the covariance matrix is ​​calculated from the second product; based on the inverse of the covariance matrix, the signal matrix obtained from the target signal, the pilot matrix obtained from the pilot signal, and the channel matrix of the target channel, the channel state information of the target channel is estimated.

2. The method according to claim 1, characterized in that, The inverse matrix of the covariance matrix calculated from the second product includes: The inverse of the covariance matrix is ​​constructed based on the real part of the inverse of the covariance matrix calculated by the second product and the imaginary part of the inverse of the covariance matrix.

3. The method according to claim 1, characterized in that, Also includes: Between the fourth calculation stage and the channel estimation stage, the real part of the inverse of the complex matrix and the imaginary part of the inverse of the complex matrix are calculated in parallel.

4. The method according to claim 1, characterized in that, The process of eliminating the upper or lower triangular elements of any matrix includes: Take each column of the current matrix as the target column, and take the element in the target column located on the diagonal of the matrix as the pivot element; Divide all elements in the row containing the pivot by the pivot. Set all elements below or above the diagonal in the target column to zero.

5. The method according to claim 1, characterized in that, Also includes: Before the first calculation stage, the real part of the complex matrix is ​​read from the first memory in the FPGA; simultaneously, the complex matrix is ​​read from the first memory. Accordingly, during the channel estimation stage, the real part of the inverse of the complex matrix and the imaginary part of the inverse of the complex matrix are stored in the first memory.

6. The method according to claim 1, characterized in that, Also includes: Prior to the first calculation stage, the covariance matrix of the pilot signal is determined.

7. The method according to any one of claims 1 to 6, characterized in that, Receiving the target signal through the target channel includes: The target signal is received through the target channel using MIMO technology.

8. A channel estimation device, characterized in that, Applied to FPGAs, including: The signal acquisition module is used to receive the target signal through the target channel and acquire the pilot signal of the antenna element; The first execution module is used to eliminate the lower triangular elements of the real part of the complex matrix when the covariance matrix of the pilot signal is a complex matrix during the first calculation stage. The second execution module is used in the second calculation stage to perform parallel calculations of the elimination of the upper triangular elements of the real part, the first product of the inverse matrix of the real part and the imaginary part of the complex matrix, and the matrix sum of the real part and the target matrix; the target matrix is ​​the result of the product of the imaginary part, the inverse matrix of the real part, and the imaginary part. The third execution module is used to eliminate the lower triangular elements of the matrix sum in the third calculation stage; The fourth execution module is used to perform parallel calculations in the fourth calculation stage of eliminating the upper triangular elements of the sum of matrices and the second product of the first product and the inverse matrix of the sum of matrices. The channel estimation module is used to calculate the inverse matrix of the covariance matrix from the second product during the channel estimation stage; and to estimate the channel state information of the target channel based on the inverse matrix of the covariance matrix, the signal matrix converted from the target signal, the pilot matrix converted from the pilot signal, and the channel matrix of the target channel.

9. A channel estimation device, characterized in that, Includes: an FPGA, said FPGA being used to implement the method as described in any one of claims 1 to 7.

10. A communication base station, characterized in that, include: At least one channel estimation device as described in claim 9.

Images