A method for fabricating a ferroelectric memory
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2023-11-21
- Publication Date
- 2026-07-21
Smart Images
Figure CN117641936B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor memory technology, and specifically relates to a method for preparing a ferroelectric memory. Background Technology
[0002] Memory is an indispensable component of electronic information processing systems. In the past, thanks to continuous advancements in CMOS technology, memory performance has been constantly improved. However, in recent years, on the one hand, the leakage current problem of transistors caused by miniaturization has become increasingly serious, increasing memory power consumption and deteriorating the retention characteristics of memory cells, thus encountering a significant bottleneck in memory development; on the other hand, the rapid development of fields such as artificial intelligence and the Internet of Things has placed higher demands on the capacity, speed, and power consumption of memory. Against this backdrop, embedded ferroelectric random access memory (eFeRAM) has attracted much attention in recent years due to its non-volatility, high density, low power consumption, and fast read speed, which can improve the overall performance of the system.
[0003] Ferroelectric memories (FE-Ms) possess two distinct polarization states, both of which are retained after the voltage excitation is removed. Applying an external voltage excitation to a FE-M results in different response charges for the two polarization states. By defining these two polarization states as "0" and "1," non-volatile data storage can be achieved. Integrating FE-Ms onto an array, by applying voltages to the FE-Ms in different polarization states and collecting the voltage changes resulting from the response charges, storage functionality can be implemented at a very low cost and high speed. However, FE-M fabrication often employs photolithography and etching for patterning. The copper interconnects in CMOS back-end processes, along with almost all the reactants generated by etching gases, are non-volatile, leading to contamination of the metal interconnects. Furthermore, after each layer of metal interconnects is fabricated in CMOS back-end processes, the surface is planarized using chemical mechanical polishing, resulting in a lack of alignment points to assist photolithography in subsequent FE-M fabrication. Therefore, how to integrate FE-Ms in CMOS back-end processes has become a pressing issue. Summary of the Invention
[0004] This invention proposes a method for fabricating ferroelectric memory. Through a specially designed process, the fabrication of ferroelectric memory is integrated into the traditional CMOS back-end process, which not only solves the problems of etching contamination and alignment loss, but also does not affect the fabrication of conventional metal interconnects and vias.
[0005] The technical solution adopted in this invention is as follows:
[0006] A method for fabricating a ferroelectric memory specifically includes the following steps:
[0007] (1) Select a silicon wafer that has been fabricated with CMOS array and circuit as a substrate;
[0008] (2) A barrier layer and a fill layer are grown on the substrate using chemical vapor deposition (CVD);
[0009] (3) Photolithography and etching of the electrode contact area. The specific method is to etch the filling layer by reactive ion etching (RIE), then rinse the residual filling layer and etching reactants with buffered hydrofluoric acid, then etch the barrier layer exposed on the surface with hot phosphoric acid, and then rinse the etching reactants with buffered hydrofluoric acid.
[0010] (4) Fill the lower electrode layer and make the surfaces of the lower electrode layer and the filling layer flat by chemical mechanical polishing or reactive ion etching.
[0011] (5) Forming the alignment, specifically by growing the alignment material using chemical vapor deposition (CVD) and then patterning the alignment using photolithography and reactive ion etching (RIE);
[0012] (6) Grow the lower electrode layer, ferroelectric layer, and upper electrode layer;
[0013] (7) The ferroelectric capacitor stack is patterned by photolithography and reactive ion etching (RIE) and the alignment is removed during the reactive ion etching (RIE) process;
[0014] (8) A barrier layer material is grown by chemical vapor deposition (CVD), and then a protective layer for a ferroelectric capacitor is formed by photolithography and reactive ion etching (RIE).
[0015] (9) A filler layer is grown by chemical vapor deposition (CVD) and the surface is smoothed by chemical mechanical polishing.
[0016] (10) The location of the metal interconnects of the ferroelectric memory is patterned by photolithography and reactive ion etching (RIE);
[0017] (11) A deposited layer is grown, a metal layer is filled, and the surface is smoothed by chemical mechanical polishing.
[0018] (12) The locations of metal interconnects and vias in the non-ferroelectric memory portion are patterned using photolithography and reactive ion etching (RIE).
[0019] (13) A deposited layer is grown, a metal layer is filled, and the surface is smoothed by chemical mechanical polishing.
[0020] (14) The barrier layer was grown using chemical vapor deposition (CVD);
[0021] (15) Annealing;
[0022] (16) Enter the CMOS back-end process.
[0023] Furthermore, the filling layer material is silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or other dielectric materials with a dielectric constant not greater than that of silicon dioxide, and the thickness is between 5 nm and 400 nm.
[0024] Furthermore, the calibration material is silicon nitride, carbon-doped silicon nitride, boron-doped silicon nitride, or silicon nitride material doped with other elements.
[0025] Furthermore, the barrier layer material is silicon nitride, carbon-doped silicon nitride, boron-doped silicon nitride, or silicon nitride material doped with other elements.
[0026] Furthermore, the metal layer material is copper or tungsten.
[0027] Furthermore, the deposited layer material is a titanium, titanium nitride, and copper multilayer material, or a tantalum, tantalum nitride, and tungsten multilayer material.
[0028] Furthermore, the upper electrode material is a metallic material such as titanium nitride, tantalum nitride, or tungsten, or a multilayer material composed of titanium and titanium nitride, or a multilayer material composed of tantalum and tantalum nitride.
[0029] Furthermore, the lower electrode material is a metallic material such as titanium nitride, tantalum nitride, or tungsten, or a multilayer material composed of titanium and titanium nitride, or a multilayer material composed of tantalum and tantalum nitride.
[0030] Furthermore, the ferroelectric layer material is zirconium oxide or hafnium oxide doped with impurities: hafnium zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, or a multilayer material composed of zirconium oxide and hafnium oxide doped with impurities.
[0031] Furthermore, the method for growing the deposited layer material in the above steps is magnetron sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0032] Furthermore, the method for growing and filling the lower electrode layer and upper electrode layer materials in the above steps is magnetron sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0033] Furthermore, the method for growing ferroelectric materials in the aforementioned steps is atomic layer deposition (ALD).
[0034] Furthermore, the method for filling the metal layer material in the above step is electroplating.
[0035] Furthermore, the annealing in the above step can be one or a combination of several of the following annealing methods: rapid thermal annealing (RTA), furnace tube annealing, laser annealing, or spike annealing.
[0036] This invention proposes a method for fabricating ferroelectric memory, integrating the fabrication of ferroelectric memory into the traditional CMOS back-end process. Before growing the ferroelectric memory stack material (i.e., the lower electrode layer, ferroelectric layer, and upper electrode layer), a filler layer is formed to isolate the metal interconnects from the ferroelectric memory. Therefore, subsequent alignment fabrication and patterning of the ferroelectric memory both use the filler layer as an etch stop layer, solving the problems of etching contamination and alignment loss. Furthermore, the above method does not affect the fabrication of conventional metal interconnects and vias. Attached Figure Description
[0037] Figures 1-15 A schematic diagram illustrating the steps of forming a ferroelectric memory monolithically integrated with a CMOS circuit according to the fabrication method proposed in this invention, wherein:
[0038] Figure 1 A substrate diagram for the preparation of the embedded ferroelectric memory;
[0039] Figure 2 This is a rear view showing the growth barrier layer and the filler layer;
[0040] Figure 3 This is a rear view of the electrode contact area after photolithography and etching.
[0041] Figure 4 Image showing the result after filling and polishing the lower electrode layer;
[0042] Figure 5 To create a diagram after alignment;
[0043] Figure 6 This is a diagram showing the growth of the lower electrode layer, ferroelectric layer, and upper electrode layer.
[0044] Figure 7 Image showing the patterned ferroelectric capacitor stack and alignment after photolithography and etching;
[0045] Figure 8 Image after photolithography and etching of the growth barrier layer;
[0046] Figure 9 Image showing the growth of the filler layer and subsequent polishing;
[0047] Figure 10 The image shows the location of the metal interconnects in the ferroelectric memory section after photolithography and etching.
[0048] Figure 11Image showing the growth of the deposited layer, the filling of the metal layer, and the polishing process;
[0049] Figure 12 The image shows the location of metal interconnects and vias in the non-ferroelectric memory section after photolithography and etching.
[0050] Figure 13 Image showing the growth of the deposited layer, the filling of the metal layer, and the polishing process;
[0051] Figure 14 Image showing the growth barrier layer;
[0052] Figure 15 This is a diagram showing the process after entering the CMOS back-end manufacturing process;
[0053] In the picture:
[0054] 1—Barrier layer; 2—Filling layer;
[0055] 3 – Deposition layer; 4 – Metal layer;
[0056] 5—Lower electrode layer; 6—Ferroelectric layer;
[0057] 7—Top electrode layer; 8—Substrate;
[0058] 9 — Align with the target. Detailed Implementation
[0059] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.
[0060] Figures 1-15 This is a schematic diagram illustrating the steps of a specific embodiment of the fabrication method proposed according to the present invention to form a ferroelectric memory monolithically integrated with a CMOS circuit. The specific steps are as follows:
[0061] First, such as Figure 1 As shown, a wafer with a CMOS circuit already fabricated is prepared as a substrate for subsequent fabrication of ferroelectric memory.
[0062] Secondly, such as Figure 2 As shown, a 30 nm thick silicon nitride (Si3N4) layer and a 40 nm thick silicon oxide (SiO2) layer were grown on the substrate using plasma-enhanced chemical vapor deposition (PECVD).
[0063] Next, as Figure 3As shown, SiO2 is etched using photolithography and reactive ion etching (RIE), then residual SiO2 and etching products are rinsed with buffered hydrofluoric acid, then exposed Si3N4 is removed by hot phosphoric acid etching, and then metal oxides generated during the etching process are rinsed with buffered hydrofluoric acid.
[0064] Next, as Figure 4 As shown, 40 nm TiN was grown using magnetron sputtering, and then the surface was planarized using chemical mechanical polishing (CMP).
[0065] Next, as Figure 5 As shown, 40 nm Si3N4 was grown using plasma-enhanced chemical vapor deposition (PECVD), and then patterned to form alignments using photolithography and reactive ion etching (RIE).
[0066] Next, as Figure 6 As shown, 20 nm TiN was grown using the Sputter method, 8 nm Hafnium Zirconium Oxide (HZO) was grown using the Atomic Layer Deposition (ALD) method, and 20 nm TiN was grown using the Sputter method as the lower electrode layer, ferroelectric layer, and upper electrode layer.
[0067] Next, as Figure 7 As shown, the ferroelectric capacitor stack is patterned using photolithography and reactive ion etching (RIE), and the alignment is removed during the reactive ion etching (RIE) process.
[0068] Next, as Figure 8 As shown, a 30 nm thick silicon nitride (Si3N4) layer was grown as a barrier layer using plasma-enhanced chemical vapor deposition (PECVD), and then a protective layer for the ferroelectric capacitor was formed by photolithography and reactive ion etching (RIE).
[0069] Next, as Figure 9 As shown, a 200 nm thick silicon oxide (SiO2) layer was grown using plasma-enhanced chemical vapor deposition (PECVD) as a filler layer, and then the surface was planarized by chemical mechanical polishing.
[0070] Next, as Figure 10 As shown, the locations of the metal interconnects in the ferroelectric memory are patterned using photolithography and reactive ion etching (RIE).
[0071] Next, as Figure 11As shown, a 30 nm Ti / TiN / Cu layer was grown by magnetron sputtering, and then Cu was filled as a metal layer using the Electroplate method. The surface was then smoothed by chemical mechanical polishing.
[0072] Next, as Figure 12 As shown, the locations of metal interconnects and vias in a non-ferroelectric memory portion are patterned using photolithography and reactive ion etching (RIE).
[0073] Next, as Figure 13 As shown, a 30 nm Ti / TiN / Cu layer was grown by magnetron sputtering, and then Cu was filled as a metal layer using the Electroplate method. The surface was then smoothed by chemical mechanical polishing.
[0074] Next, as Figure 14 As shown, a 30 nm thick silicon nitride (Si3N4) layer was grown as a barrier layer using plasma-enhanced chemical vapor deposition (PECVD).
[0075] Next, rapid thermal annealing (RTA) was used to crystallize the ferroelectric layer 6 and give it ferroelectric properties;
[0076] Next, as Figure 15 As shown, it enters the CMOS back-end process.
[0077] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A method for fabricating a ferroelectric memory, characterized in that, Specifically, the following steps are included: 1) Select a silicon wafer that has already been used to fabricate a CMOS array and circuit as a substrate; 2) Barrier layer material and filler layer material are grown on the substrate using chemical vapor deposition; 3) Photolithography and etching of the electrode contact area: Specifically, reactive ion etching is used to etch the filler layer material, followed by rinsing with buffered hydrofluoric acid to remove the residual filler layer and etching reactants, and then hot phosphoric acid etching is used to expose the barrier layer on the surface. Then rinse the corrosive reactants with buffered hydrofluoric acid; 4) Fill the lower electrode layer and then use chemical mechanical polishing or reactive ion etching to separate the lower electrode layer from the filling layer. Smooth surface; 5) Forming the alignment: The specific method is to grow the alignment material using chemical vapor deposition, and then pattern the alignment using photolithography and reactive ion etching. 6) Grow the lower electrode layer, ferroelectric layer, and upper electrode layer; 7) Pattern the ferroelectric capacitor stack using photolithography and reactive ion etching, and remove the alignment marks during the reactive ion etching process; 8) The barrier layer material is grown by chemical vapor deposition, and then the protective layer of the ferroelectric capacitor is formed by photolithography and reactive ion etching. 9) A filler layer is grown using chemical vapor deposition, and the surface is smoothed using chemical mechanical polishing. 10) The locations of the metal interconnects in the ferroelectric memory are patterned using photolithography and reactive ion etching methods; 11) Grow a deposited layer, fill with a metal layer, and smooth the surface using chemical mechanical polishing; 12) The positions of metal interconnects and vias in the non-ferroelectric memory portion are patterned using photolithography and reactive ion etching methods; 13) Grow a deposited layer, fill with a metal layer, and smooth the surface using chemical mechanical polishing; 14) A barrier layer is grown using chemical vapor deposition; 15) Annealing; 16) Enter the CMOS back-end process.
2. The method as described in claim 1, characterized in that, The filling layer material is silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, or other dielectric materials with a dielectric constant not greater than that of silicon dioxide, and the thickness is between 5 nm and 400 nm.
3. The method as described in claim 1, characterized in that, The calibration material is silicon nitride, carbon-doped silicon nitride, boron-doped silicon nitride, or silicon nitride material doped with other elements.
4. The method as described in claim 1, characterized in that, The barrier layer material is silicon nitride, carbon-doped silicon nitride, boron-doped silicon nitride, or silicon nitride material doped with other elements.
5. The method as described in claim 1, characterized in that, The metal layer material is copper or tungsten.
6. The method as described in claim 1, characterized in that, The deposited layer material is a titanium, titanium nitride, and copper multilayer material, or a tantalum, tantalum nitride, and tungsten multilayer material.
7. The method as described in claim 1, characterized in that, The upper electrode material is a metallic material such as titanium nitride, tantalum nitride, or tungsten, or a multilayer material composed of titanium and titanium nitride, or a multilayer material composed of tantalum and tantalum nitride.
8. The method as described in claim 1, characterized in that, The lower electrode material is a metallic material such as titanium nitride, tantalum nitride, or tungsten, or a multilayer material composed of titanium and titanium nitride, or a multilayer material composed of tantalum and tantalum nitride.
9. The method as described in claim 1, characterized in that, The ferroelectric layer material is zirconium oxide or hafnium oxide doped with impurities: hafnium zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, or a multilayer material composed of zirconium oxide and hafnium oxide doped with impurities.