Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a pixel array, the number of sub-pixels in two adjacent pixel rows and / or pixel columns in the pixel array is not equal, a plurality of steps are formed at the edge of the pixel array, a plurality of multiplexing circuits are arranged corresponding to the plurality of steps, a plurality of data signal line groups are connected with the pads at one end and connected with the plurality of multiplexing circuits at the other end, a gate drive circuit comprises a plurality of gate drive units connected in cascade, a gate drive signal line comprises a first signal line and a second signal line, the first signal line is connected with the pad and the first end of the second signal line, the second end of the second signal line is connected with the gate drive circuit, the first signal line extends along the column direction, the second signal line extends along the row direction, the first signal line is arranged between two adjacent data signal line groups, and the second signal line is arranged at the step between two multiplexing circuits corresponding to two adjacent data signal line groups.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and display device. Background Technology

[0002] In OLED display panels, in order to drive the pixel array to emit light for display, various types of circuits need to be set in the display panel to provide various signals to the sub-pixels in the pixel array, such as gate drive signals, multiplexed circuit signals, data signals and power signals. The above-mentioned various types of signals are usually provided by multiple signal lines set in the non-display area. These multiple signal lines are connected to the driver chip through pads and flexible circuit boards set in the non-display area.

[0003] With the development of wearable electronic devices such as smartwatches or smart bracelets, users have put forward higher demands for the screen ratio of display panels. The signal lines of the above-mentioned types in the display panel are all located in the lead area on one side of the pixel array. In order to reduce the screen ratio, it is necessary to arrange the signal lines of various types in the lead area in a reasonable manner.

[0004] In related technologies, the aforementioned display panel typically has a third metal film layer; data signal lines used to provide data signals to the multiplexing circuit occupy two of these film layers; gate drive signal lines, multiplexing circuit signal lines, and power signal lines are typically located in another metal film layer. The lateral traces of these multiple types of signal lines are arranged sequentially along the longitudinal direction of the display area on this film layer and maintain a certain distance. This results in the lead area occupying a larger width in the longitudinal direction, thereby increasing the width of the bezel. Summary of the Invention

[0005] This application provides a display panel and a display device. The various aspects related to the embodiments of this application are described below.

[0006] In a first aspect, a display panel is provided, comprising: a pixel array, wherein the number of sub-pixels in two adjacent pixel rows and / or two adjacent pixel columns in the pixel array is unequal, forming multiple steps at the edge of the pixel array; a plurality of multiplexing circuits, corresponding to the plurality of steps; a plurality of data signal line groups, one end of which is connected to a pad (COFPAD), and the other end of which is respectively connected to the plurality of multiplexing circuits; a gate driving circuit, including a plurality of cascaded gate driving units; and a gate driving signal line, including a first signal line and a second signal line, one end of which is connected to the pad, and the other end of which is connected to a first end of the second signal line, and the second end of which is connected to the gate driving circuit, wherein the first signal line extends along a column direction, the second signal line extends along a row direction, the first signal line is disposed between two adjacent data signal line groups, and the second signal line is disposed at a step between two multiplexing circuits corresponding to the two adjacent data signal line groups.

[0007] As one possible implementation, the display panel further includes: multiplexed circuit signal lines connected to the pads and the plurality of multiplexed circuits, including a plurality of third signal lines disposed on the side of the plurality of multiplexed circuits away from the sub-pixel array and corresponding to the plurality of multiplexed circuits, and a plurality of fourth signal lines connecting two adjacent third signal lines; a first distance between the second signal line and the pad is greater than or equal to a second distance between the target third signal line and the pad; wherein the target third signal line is the one of the plurality of third signal lines closest to the pad.

[0008] As one possible implementation, the multiplexed circuit signal line further includes a fifth signal line, the first end of which is connected to the pad and the second end of which is connected to the target third signal line.

[0009] As one possible implementation, the third signal line and the fourth signal line are located in the same metal film layer, but in a different metal film layer than the fifth signal line.

[0010] As one possible implementation, the first signal line and the fifth signal line are located in the same metal film layer, and the second signal line and the third signal line are located in the same metal film layer.

[0011] As one possible implementation, each of the data signal line groups includes at least one first data signal line and at least one second data signal line extending along the column direction, wherein the first data signal line and the second data signal line are located in different metal film layers, and the first data signal line and the second data signal line are located in different metal film layers from the second signal line, the third signal line and the fourth signal line.

[0012] As one possible implementation, the first signal line is disposed between the first data signal line group and the second data signal line group; wherein, the first data signal line group is a data signal line group connected to the first multiplexing circuit, the first multiplexing circuit is the one among the plurality of multiplexing circuits closest to the pad, and the second multiplexing circuit is a multiplexing circuit adjacent to the first multiplexing circuit.

[0013] As one possible implementation, the display panel further includes power signal lines, which include a plurality of first power signal lines respectively disposed between the plurality of multiplexed circuits and the plurality of steps, and a second power signal line connecting two adjacent first power signal lines; the power signal lines also include a third power signal line, one end of which is connected to the pad and the other end of which is connected to a target first power signal line; wherein, the target first power signal line is one or more of the plurality of first power signal lines that are closest to the pad.

[0014] As one possible implementation, the power signal line is located in the same metal film layer as the first signal line and the third signal line.

[0015] In a second aspect, a display device is provided, comprising a display panel as described in the first aspect.

[0016] In the display panel provided in this application embodiment, by leading out the first signal line arranged vertically from the gate drive signal line between two adjacent data signal line groups, the second signal line arranged horizontally can be set at the step between two adjacent multiplexing circuits, thereby avoiding the problem of the display panel bezel being wide due to the horizontal trace of the gate drive signal line occupying the width of the lead area between the multiplexing circuit and the pad at the bottom of the pixel array. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the display panel provided in an embodiment of this application.

[0018] Figure 2 yes Figure 1 A magnified view of a portion of region B.

[0019] Figure 3 This is a partial enlarged view of a display panel provided in another embodiment of this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] This application provides a display panel and a display device. The display panel provided in the embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 A schematic diagram of a display panel 100 provided in an embodiment of this application is shown. This display panel is an irregularly shaped display panel with a circular display area AA. It should be noted that... Figure 1 The circular display area shown is only an example; the display area can also be other shapes, such as semicircles, ellipses, polygons, and other non-rectangular shapes. Figure 2 for Figure 1 A magnified view of a portion of area B in the middle. Figure 2 The image shows the three rows of sub-pixels at the bottom of the display area and the circuitry surrounding the display area. The following section combines... Figure 2 Further explanation is needed.

[0023] like Figure 2 As shown, the display panel 100 includes a pixel array 110, which includes a plurality of sub-pixels 111. The pixel array also includes a plurality of gate lines 112 and a plurality of data lines 113. The plurality of gate lines 112 and the plurality of data lines 113 are insulated and intersected to define the setting area of ​​the plurality of sub-pixels 111.

[0024] Continue reading Figure 2 The pixel array 110 includes multiple pixel rows 114 and multiple pixel columns 115. The periphery of the pixel array 110 includes multiple steps. The number of sub-pixels in two adjacent pixel rows 114 is unequal or the number of pixels in two adjacent pixel columns is unequal, forming the aforementioned steps.

[0025] In some embodiments, the number of multiple gate lines 112 in the pixel array 110 is the same as the number of pixel rows 114 in the pixel array 110, that is, each pixel row 114 is provided with a corresponding gate line 112, and multiple sub-pixels in each pixel row 114 are connected to the corresponding gate line 112 to receive gate signals.

[0026] In some embodiments, the number of multiple data lines 113 in the pixel array 110 is the same as the number of pixel columns 115 in the pixel array 110, that is, one data line 113 is set for each pixel column 115, and multiple sub-pixels in each pixel column 115 are connected to the corresponding data line 115 to receive data signals.

[0027] The display panel 100 also includes pads 120 with multiple pins (not shown) for connection to the display panel's driver chip via a flexible circuit board.

[0028] The display panel 100 also includes a plurality of multiplexed circuits 130, which are correspondingly arranged with a plurality of steps in the pixel array 110. The corresponding arrangement here may mean that the plurality of multiplexed circuits 130 are located below the plurality of steps; each multiplexed circuit 130 includes a plurality of output terminals, which are connected to data lines of multiple columns of pixels in each step, for providing data signals to each column of pixels; for example, in... Figure 2 In the technical solution shown, each multiplexer circuit 130 is connected to three data lines.

[0029] It should also be noted that, Figure 2 The multiplexing circuit 130 also includes multiple input terminals. These multiple input terminals are connected to the pad 120 through multiple data signal line groups 140. Each data signal line group may include multiple data signal lines. These data signal lines are disposed between the pad 120 and the multiple input terminals of the multiplexing circuit 130 and are used to transmit data signals to the multiplexing circuit 130.

[0030] It is understood that the first number of input terminals in the above-mentioned multiplexing circuit is usually greater than the second number of output terminals; the embodiments of this application do not limit the specific values ​​of the first and second numbers, for example, the ratio of the first number and the second number can be 2:1 or 3:1.

[0031] During the operation of this multiplexing circuit, signals are provided to multiple data lines through one data signal line in the data signal line group 140. This data signal line is connected to the multiple data lines through a switch, which controls the reception of data signals on the corresponding data lines. By setting up a multiplexing circuit in the display panel 100, data signals can be provided to more pixel columns using a smaller number of data signal lines, thereby increasing the density of sub-pixels in the pixel array and increasing the resolution of the display panel under the condition of the same number of pins.

[0032] Figure 2The display panel 100 also includes a gate driving circuit 150, comprising a plurality of cascaded gate driving units 151; these gate driving units 151 are disposed in the peripheral area of ​​the pixel array 110. The plurality of gate driving units 151 in the gate driving circuit 150 are respectively connected to a plurality of gate lines 112 of a plurality of pixel rows. These gate driving units are used to generate and output GIP signals; wherein, a first-level GIP signal is provided to a first pixel row, a second-level GIP signal is provided to a second pixel row, and so on, with the nth-level GIP signal provided to the nth pixel row.

[0033] Multiple gate driving units 151 in the gate driving circuit 150 are cascaded in the order of pixel rows. The output signal of the previous driving unit is used as the input signal of the next driving unit. At the same time, the output signal of each driving unit is used as the light emission control signal of the sub-pixel. The output signals of two adjacent driving units have a fixed time relationship. The frequency of the output signals of the multiple driving units is the same as the frequency of the initial input signal of the first driving unit, so that the refresh frequency of each pixel row is the same.

[0034] The first-stage gate driving unit among the multiple gate driving units 151 is connected to the pad 120 via the gate driving signal line 160, such as Figure 2 As shown, the gate drive signal line 160 includes a first signal line 161 and a second signal line 162. One end of the first signal line 161 is connected to the pad 120, and the other end is connected to the first end of the second signal line 162. The second end of the second signal line 162 is connected to the gate drive circuit 150. Specifically, the second end of the second signal line 162 can be connected to the input terminal of the first-stage gate drive unit.

[0035] The first signal line 161 in the gate drive signal line 160 extends along the column direction, and the second signal line 162 extends along the row direction. The first signal line 161 is disposed between two adjacent data signal line groups, and the second signal line 162 is disposed at the step between the two multiplexing circuits corresponding to the two adjacent data signal line groups. The two adjacent data signal line groups mentioned here can refer to any two adjacent data signal line groups.

[0036] In the display panel 100 provided in this application embodiment, by leading out the first signal line 161 from between two adjacent data signal line groups, the second signal line 162 in the horizontal direction can be set at the step between two adjacent multiplexing circuits, thereby avoiding the problem that the horizontal trace of the gate drive signal line 160 occupies the width of the lead area between the multiplexing circuit and the pad at the bottom of the pixel array, resulting in a wide display panel bezel.

[0037] Figure 3This is a schematic diagram of a display panel provided in a further embodiment of this application. (As shown...) Figure 3 As shown, the display panel also includes multiplexed circuit signal lines 170, which are connected to pads 120 and multiple multiplexed circuits 130. The multiplexed circuit signal lines include multiple third signal lines 171 that are disposed on the side of the multiple multiplexed circuits 130 away from the pixel array and corresponding to the multiple multiple multiplexed circuits 130, and multiple fourth signal lines 172 that connect two adjacent third signal lines.

[0038] The aforementioned multiple third signal lines 171 and multiple fourth signal lines 172 together constitute the multiplexed circuit signal line 170, such as... Figure 3 As shown, the signal line 170 of the multiplexing circuit is located close to the multiple multiplexing circuits 130 and is arranged in a stepped manner.

[0039] The first distance H1 of the second signal line 162 in the above gate drive signal lines from the pad is greater than or equal to the second distance H2 of the target third signal line from the pad, wherein the target third signal line is one or more of the above plurality of third signal lines 171 that are closest to the pad 120.

[0040] By setting the first distance H1 to be greater than or equal to the second distance H2, the lateral traces in the gate drive signal line are at the same horizontal level or higher than the lateral traces at the bottom of the multiplexed circuit signal line 170. This ensures that the lateral traces in the gate drive signal line do not occupy additional width of the border portion, which is more conducive to reducing the width of the border.

[0041] Continue reading Figure 3 The multiplexed signal line 170 also includes a fifth signal line 173, the first end of which is connected to the pad 120 and the second end of which is connected to the aforementioned target third signal line; the fifth signal line 173 is used to connect the third signal line and the fourth signal line to the pad 120.

[0042] In the multiplexed signal lines, the third signal line 171 and the fourth signal line 172 are located in the same metal film layer, but in a different film layer than the fifth signal line 173. A cable switching via needs to be provided at the connection between the fifth signal line 173 and the target third signal line to enable conduction.

[0043] It should be noted that the display panel provided in this application embodiment typically has three metal film layers, wherein the first signal line 161 and the fifth signal line 173 in the gate drive signal line 160 are located in the same metal film layer, and the second signal line 162 and the third signal line 171 are located in the same metal film layer.

[0044] In some embodiments, each data signal line group 140 in the display panel includes at least one first data signal line 141 and at least one second data signal line 142 extending in the column direction. The first data signal line 141 and the second data signal line 142 are in different metal film layers, and the first data signal line 141 and the second signal line 162 in the gate driving signal line 160, the third signal line 171 in the multiplexing circuit signal line 170, and the fourth signal line 172 are in different metal film layers.

[0045] Continue to participate Figure 3 , the display panel provided by the embodiment of the present application further includes a power supply signal line 180, which is used to provide a power supply signal for the pixel array, and the power supply signal may be, for example, a VDD signal. The power supply signal line 180 includes a first power supply signal line 181 respectively disposed between multiple steps 116 of multiple multiplexing circuits 130 and the pixel array 110, and a second power supply signal line 182 connecting two adjacent first power supply signal lines.

[0046] The power supply signal line 180 further includes a third power supply signal line 183, one end of which is connected to the pad 120 and the other end is connected to the target first power supply signal line, where the target first power supply signal line is one or more of the first power supply signal lines 181 closest to the pad 120. The third power supply signal line 183 has a "冂" - shaped routing.

[0047] In some embodiments, the power supply signal line 180 is in the same metal film layer as the second signal line, the third signal line, and the fourth signal line.

[0048] As mentioned above, the first signal line 161 in the gate driving signal line 160 is disposed between any two adjacent data signal line groups; further, in some embodiments, the first signal line is disposed between the first data signal line group and the second data signal line group, where the first data signal line group is the data signal line group connected to the first multiplexing circuit, and the first multiplexing circuit is one or more of the multiple multiplexing circuits closest to the pad, and the second data signal line group is the data signal line group adjacent to the first data signal line group.

[0049] The embodiment of the present application further provides a display device, and the display device includes the display panel of any one of the above embodiments.

[0050] It should be noted that the display device can be various electronic display products, specifically including but not limited to at least one of mobile phones, tablet computers, e-book readers, media players, digital cameras, laptops, in-vehicle computers, desktop computers, set-top boxes, smart TVs, and wearable devices. Furthermore, depending on actual needs, the display device may also include other structures such as a touch function layer, a polarizer, and a cover plate.

[0051] It should be noted that, in the embodiments of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0053] It should be understood that the term "and / or" used in the embodiments of this application is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. In addition, the character " / " in the embodiments of this application generally indicates that the preceding and following associated objects have an "or" relationship.

[0054] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: A pixel array in which the number of sub-pixels in two adjacent pixel rows and / or two adjacent pixel columns are not equal, forming multiple steps at the edge of the pixel array; Multiple multiplexing circuits are configured corresponding to the multiple steps; Multiple data signal line groups, one end of which is connected to the pad, and the other end of which is connected to the multiple multiplexed circuits respectively; Gate drive circuit, including multiple cascaded gate drive units; A gate drive signal line includes a first signal line and a second signal line. One end of the first signal line is connected to the pad and the other end is connected to the first end of the second signal line. The second end of the second signal line is connected to the gate drive circuit. The first signal line extends along the column direction and the second signal line extends along the row direction. The first signal line is disposed between two adjacent data signal line groups and the second signal line is disposed at the step between two multiplexing circuits corresponding to the two adjacent data signal line groups. Multiplexed circuit signal lines are connected to the pads and the plurality of multiplexed circuits, including a plurality of third signal lines disposed on the side of the plurality of multiplexed circuits away from the pixel array and corresponding to the plurality of multiplexed circuits, and a plurality of fourth signal lines connecting two adjacent third signal lines. The first distance between the second signal line and the pad is greater than or equal to the second distance between the target third signal line and the pad; The target third signal line is one or more of the plurality of third signal lines that are closest to the pad.

2. The display panel according to claim 1, characterized in that, The multiplexed circuit signal line also includes a fifth signal line, the first end of which is connected to the pad and the second end of which is connected to the target third signal line.

3. The display panel according to claim 2, characterized in that, The third signal line and the fourth signal line are located in the same metal film layer, but are located in a different metal film layer than the fifth signal line.

4. The display panel according to claim 3, characterized in that, The first signal line and the fifth signal line are located in the same metal film layer, and the second signal line and the third signal line are located in the same metal film layer.

5. The display panel according to claim 4, characterized in that, Each of the data signal line groups includes at least one first data signal line and at least one second data signal line extending along the column direction. The first data signal line and the second data signal line are located in different metal film layers, and the first data signal line and the second data signal line are located in different metal film layers from the second signal line, the third signal line and the fourth signal line.

6. The display panel according to claim 4, characterized in that, It also includes power signal lines, which include a plurality of first power signal lines respectively disposed between the plurality of multiplexed circuits and the plurality of steps, and a second power signal line connecting two adjacent first power signal lines; The power signal line also includes a third power signal line, one end of which is connected to the pad and the other end of which is connected to the target first power signal line. The target first power signal line is the one among the plurality of first power signal lines that is closest to the pad.

7. The display panel according to claim 6, characterized in that, The power signal line is located in the same metal film layer as the first signal line and the third signal line.

8. The display panel according to any one of claims 1-7, characterized in that, The first signal line is disposed between the first data signal line group and the second data signal line group; Wherein, the first data signal line group is a data signal line group connected to the first multiplexing circuit, the first multiplexing circuit is the one among the plurality of multiplexing circuits that is closest to the pad, and the second data signal line group is a data signal line group adjacent to the first data signal line group.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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