Magnetic memory device

Abstract

Embodiments provide a magnetic memory device that can reduce a write current. The magnetic memory device of the embodiments includes a first conductive layer, a second conductive layer, a third conductive layer extending in a first direction, and a three-terminal memory cell connected to the first conductive layer, the second conductive layer, and the third conductive layer. The memory cell includes a fourth conductive layer extending in the first direction, and a magnetoresistive effect element disposed between the fourth conductive layer and the third conductive layer. The magnetoresistive effect element includes a first ferromagnetic layer in contact with the fourth conductive layer in a second direction intersecting the first direction, a second ferromagnetic layer disposed on a side opposite the fourth conductive layer with respect to the first ferromagnetic layer, a dielectric layer between the first ferromagnetic layer and the second ferromagnetic layer, a third ferromagnetic layer disposed on a side opposite the first ferromagnetic layer with respect to the second ferromagnetic layer, and a non-magnetic layer disposed between the second ferromagnetic layer and the third ferromagnetic layer and containing oxygen and magnesium. A concentration of a first noble metal in the first ferromagnetic layer is higher than a concentration of a second noble metal in the second ferromagnetic layer.

Description

[0001] [Reference to relevant applications]

[0002] This application claims priority to Japanese Patent Application No. 2022-138459 (filed on August 31, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation relates to a magnetic storage device. Background Technology

[0004] Magnetic memory devices that use magnetoresistive elements as storage elements are known. Various methods have been proposed for writing data to the magnetoresistive elements. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a magnetic memory device that can reduce write current.

[0006] A magnetic memory device according to an embodiment includes: a first conductive layer; a second conductive layer; a third conductive layer extending along a first direction; and a three-terminal memory cell connected to the first conductive layer, the second conductive layer, and the third conductive layer. The memory cell includes: a fourth conductive layer extending along the first direction; and a magnetoresistive element disposed between the fourth conductive layer and the third conductive layer. The magnetoresistive element includes: a first ferromagnetic layer connected to the fourth conductive layer in a second direction intersecting the first direction; a second ferromagnetic layer disposed on a side opposite to the fourth conductive layer relative to the first ferromagnetic layer; a dielectric layer located between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer disposed on a side opposite to the first ferromagnetic layer relative to the second ferromagnetic layer; and a non-magnetic layer disposed between the second ferromagnetic layer and the third ferromagnetic layer, comprising oxygen and magnesium. The concentration of the first noble metal in the first ferromagnetic layer is higher than the concentration of the second noble metal in the second ferromagnetic layer. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a magnetic memory device according to an embodiment.

[0008] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a storage cell array according to an implementation method.

[0009] Figure 3 This is a top view illustrating an example of the planar layout of the storage cell array in an embodiment.

[0010] Figure 4This is an example of the cross-sectional structure of the storage cell array in the embodiment. Figure 3 A cross-sectional view along line IV-IV.

[0011] Figure 5 This is the first example illustrating the cross-sectional structure of the magnetoresistive element and its peripheral wiring in the embodiment. Figure 4 A cross-sectional view of region W.

[0012] Figure 6 This is the second example illustrating the cross-sectional structure of the magnetoresistive element and its peripheral wiring in the embodiment. Figure 4 A cross-sectional view of region W.

[0013] Figure 7 This is a circuit diagram illustrating an example of a write operation in a magnetic memory device according to an embodiment.

[0014] Figure 8 This is a line graph illustrating an example of the VCMA (Voltage Control of Magnetic Anisotropy) effect generated on the storage layer of a storage cell in a magnetic memory device according to an embodiment.

[0015] Figure 9 This is a line graph showing an example of the magnetization curve of the storage layer of the storage cell in a magnetic memory device according to an embodiment.

[0016] Figure 10 This is a line graph showing an example of the magnetization curve of the storage layer of the storage cell in a magnetic memory device according to an embodiment.

[0017] Figure 11 This is a line graph showing an example of the magnetization curve of the storage layer of the storage cell in a magnetic memory device according to an embodiment.

[0018] Figure 12 This is a line graph showing an example of the magnetization curve of the storage layer of the storage cell in a magnetic memory device according to an embodiment.

[0019] Figure 13 (A) to (B) are cross-sectional views showing an example of a write operation in the magnetic memory device of the embodiment.

[0020] Figure 14 (A) to (B) are cross-sectional views showing an example of a write operation in the magnetic memory device of the embodiment.

[0021] Figure 15 This is a circuit diagram illustrating an example of the circuit configuration of the storage cell array in the first variation.

[0022] Figure 16This is a circuit diagram illustrating an example of the circuit configuration of the storage cell array in the second variation.

[0023] Figure 17 This is a circuit diagram illustrating an example of the circuit configuration of the storage cell array in the third variation.

[0024] Figure 18 This is a circuit diagram illustrating an example of the circuit configuration of the storage cell array in the fourth variation.

[0025] Figure 19 This is a cross-sectional view of the first example showing the cross-sectional structure of the magnetoresistive effect element and its peripheral wiring in the fifth variation.

[0026] Figure 20 This is a cross-sectional view of the second example showing the cross-sectional structure of the magnetoresistive effect element and its peripheral wiring in the fifth variation. Detailed Implementation

[0027] Hereinafter, several embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and structure will be marked with common reference symbols. Additionally, when it is necessary to distinguish multiple constituent elements with common reference symbols, a suffix will be added to the common reference symbol for differentiation. Furthermore, when it is not necessary to specifically distinguish multiple constituent elements, only the common reference symbol will be marked for the multiple constituent elements without adding a suffix. Suffixes are not limited to subscripts or superscripts, and may include, for example, lowercase letters added to the end of the reference symbol, symbols, and indexes indicating sequences.

[0028] In this specification, a magnetic memory device is, for example, an MRAM (Magnetoresistive Random Access Memory). A magnetic memory device includes magnetoresistive elements as storage elements. A magnetoresistive element is a resistive switching element that exhibits a magnetoresistance effect through a magnetic tunnel junction (MTJ). Magnetoresistive elements are also called MTJ elements.

[0029] 1. Implementation Method

[0030] The implementation method is described below.

[0031] 1.1 Composition

[0032] First, the configuration of the magnetic memory device according to the embodiment will be explained.

[0033] 1.1.1 Magnetic storage devices

[0034] Figure 1This is a block diagram illustrating an example of the configuration of a magnetic memory device according to an embodiment. The magnetic memory device 1 includes a storage cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0035] The storage cell array 10 is the data storage unit in the magnetic memory device 1. The storage cell array 10 has multiple storage cells MC. The multiple storage cells MC are respectively associated with groups consisting of rows and columns. Storage cells MC located in the same row are connected to the same word line WL, and storage cells MC located in the same column are connected to the first bit line BL1 and the second bit line BL2 of the same group.

[0036] Row selection circuit 11 is a circuit that selects rows of memory cell array 10. Row selection circuit 11 is connected to memory cell array 10 via word line WL. The decoding result (row address) of address ADD from decoding circuit 13 is supplied to row selection circuit 11. Row selection circuit 11 selects the word line WL corresponding to the row determined based on the decoding result of address ADD. Hereinafter, the selected word line WL will be referred to as the selected word line WL. In addition, word lines WL other than the selected word line WL will be referred to as non-selected word lines WL.

[0037] Column selection circuit 12 is a circuit that selects columns of memory cell array 10. Column selection circuit 12 is connected to memory cell array 10 via first bit line BL1 and second bit line BL2. The decoding result (column address) of address ADD from decoding circuit 13 is supplied to column selection circuit 12. Column selection circuit 12 selects the first bit line BL1 and second bit line BL2 corresponding to the column determined based on the decoding result of address ADD. Hereinafter, the selected first bit line BL1 and second bit line BL2 will be referred to as selected bit line BL1 and selected bit line BL2, respectively. In addition, the first bit line BL1 other than selected bit line BL1 and the second bit line BL2 other than selected bit line BL2 will be referred to as non-selected bit line BL1 and non-selected bit line BL2, respectively.

[0038] Decoding circuit 13 is a decoder that decodes the address ADD from input / output circuit 17. Decoding circuit 13 supplies the decoding result of address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes column address and row address.

[0039] The write circuit 14 includes, for example, a write driver (not shown). The write circuit 14 writes data to the storage cell MC.

[0040] The readout circuit 15 includes, for example, a sense amplifier (not shown). The readout circuit 15 reads data from the storage cell MC.

[0041] The voltage generation circuit 16 utilizes a power supply voltage supplied from an external source (not shown) to the magnetic memory device 1 to generate voltages for various operations of the storage cell array 10. For example, the voltage generation circuit 16 generates various voltages required to perform a write operation and outputs them to the write circuit 14. Additionally, for example, the voltage generation circuit 16 generates various voltages required to perform a read operation and outputs them to the read circuit 15.

[0042] Input / output circuit 17 is responsible for communication with the external environment of magnetic memory device 1. Input / output circuit 17 transmits address ADD from the external environment of magnetic memory device 1 to decoding circuit 13. Input / output circuit 17 transmits instruction CMD from the external environment of magnetic memory device 1 to control circuit 18. Input / output circuit 17 sends and receives various control signals CNT between the external environment of magnetic memory device 1 and control circuit 18. Input / output circuit 17 transmits data DAT from the external environment of magnetic memory device 1 to write circuit 14, and outputs data DAT transmitted from read circuit 15 to the external environment of magnetic memory device 1.

[0043] The control circuit 18 includes, for example, a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). Based on control signals CNT and instructions CMD, the control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16, and input / output circuit 17 within the magnetic memory device 1.

[0044] 1.1.2 Storage Cell Array

[0045] Next, the configuration of the storage cell array of the magnetic memory device according to the embodiment will be explained.

[0046] (Circuit configuration)

[0047] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a storage cell array according to an implementation method. Figure 2 The word line WL, the first bit line BL1, and the second bit line BL2 are distinguished by suffixes with index symbols ("<>").

[0048] The memory cell array 10 includes multiple memory cells MC, multiple word lines WL, multiple first bit lines BL1, and multiple second bit lines BL2. Figure 2In the example, multiple storage cells MC contain (M+1)×(N+1) storage cells MC<0,0>, MC<0,1>, ..., MC<0,N>, MC<1,0>, ..., and MC<M,N> (where M and N are integers greater than 2). Furthermore, although... Figure 2 The examples shown depict the cases where M and N are integers greater than 2, but are not limited to this. M and N can also be 0 or 1. Multiple word lines WL comprise (M+1) word lines WL<0>, WL<1>, ..., and WL<M>. Multiple first-bit lines BL1 comprise (N+1) first-bit lines BL1<0>, WBL<1>, ..., and WBL<N>. Multiple second-bit lines BL2 comprise (N+1) second-bit lines BL2<0>, RBL<1>, ..., and RBL<N>.

[0049] Multiple storage cells MC are arranged in a matrix within the storage cell array 10. Each storage cell MC corresponds to one of the multiple word lines WL, and to a group of first-bit lines BL1 and second-bit lines BL2. That is, a storage cell MC<i,j> (0≦i≦M, 0≦j≦N) is connected to word line WL, first-bit line BL1<j>, and second-bit line BL2<j>.

[0050] The memory cell MC<i,j> is a three-terminal type memory cell with a first terminal connected to word line WL, a second terminal connected to the first bit line BL1<j>, and a third terminal connected to the second bit line BL2<j>. The memory cell MC<i,j> includes switching elements SEL1<i,j> and SEL2<i,j>, a magnetoresistive element MTJ<i,j>, and wiring SOTL<i,j>.

[0051] Wiring SOTL<i,j> comprises a first part, a second part, and a third part between the first and second parts. The first part of wiring SOTL<i,j> is connected to the word line WL. The second part of wiring SOTL<i,j> is connected to the first bit line BL1<j>. The third part of wiring SOTL<i,j> is connected to the second bit line BL2<j>. Switching element SEL1<i,j> is connected between the second part of wiring SOTL<i,j> and the first bit line BL1<j>. Magnetoresistive element MTJ<i,j> is connected between the third part of wiring SOTL<i,j> and the second bit line BL2<j>. Switching element SEL2<i,j> is connected between the magnetoresistive element MTJ<i,j> and the second bit line BL2<j>.

[0052] Switching elements SEL1 and SEL2 are two-terminal switching elements. Two-terminal switching elements differ from three-terminal switching elements such as transistors in that they do not have a third terminal. When the voltage applied between the two terminals is less than the threshold voltages Vth1 and Vth2, respectively, switching elements SEL1 and SEL2 are in a "high impedance" state or an "off" state, for example, a non-conductive state. When the voltage applied between the two terminals is greater than or equal to the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 become in a "low impedance" state or an "on" state, for example, a conductive state. More specifically, for example, when the voltage applied to the corresponding memory cell MC is lower than the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 act as insulators with higher impedance values, blocking current (becoming an off state). When the voltage applied to the corresponding memory cell MC is higher than the threshold voltages Vth1 and Vth2, switching elements SEL1 and SEL2 act as conductors with lower impedance values, allowing current to flow (becoming an on state). Regardless of the polarity of the voltage applied between the two terminals (regardless of the direction of the current flowing), the switching elements SEL1 and SEL2 switch between allowing current to flow or blocking current based on the magnitude of the voltage applied to the corresponding memory cell MC.

[0053] The SOTL wiring is the current path within the memory cell MC. For example, when switch element SEL1 is on and switch element SEL2 is off, the SOTL wiring functions as the current path between word line WL and bit line BL1. Additionally, when switch element SEL1 is off and switch element SEL2 is on, a portion of the SOTL wiring functions as the current path between word line WL and bit line BL2.

[0054] The magnetoresistive element (MTJ) is a resistive switching element. Based on the current controlled by switching elements SEL1 and SEL2, the impedance of the MTJ switches between low and high impedance states. The MTJ functions as a storage element that stores data through changes in its impedance state rather than volatilely.

[0055] (Floor plan layout)

[0056] Next, the planar layout of the memory cell array in the embodiment will be described. Hereinafter, the plane parallel to the substrate surface will be designated as the XY plane. The direction in which the magnetic memory device 1 is disposed relative to the substrate surface will be designated as the Z direction or the upward direction. The directions intersecting each other within the XY plane will be designated as the X direction and the Y direction.

[0057] Figure 3 This is a top view illustrating an example of the planar layout of the storage cell array in an embodiment. Figure 3The diagrams of structures such as the insulating layer are omitted.

[0058] The storage cell array 10 also includes multiple vertical structures V1, multiple vertical structures V2, and multiple vertical structures V3. Each of the multiple vertical structures V1 includes a switching element SEL1. Each of the multiple vertical structures V2 includes a magnetoresistive element MTJ and a switching element SEL2.

[0059] Multiple first-order lines BL1 are arranged along the X direction. Multiple first-order lines BL1 extend along the Y direction respectively.

[0060] Multiple word lines WL are positioned above multiple first bit lines BL1. The multiple word lines WL are arranged along the Y direction. The multiple word lines WL extend along the X direction.

[0061] Above multiple word lines (WL) are multiple routing lines (SOTLs). Viewed from above, each SOTL has a rectangular shape that is longer in the Y direction than in the X direction. The SOTLs extend along the Y direction. Viewed from above, the SOTLs correspond to positions overlapping with one word line (WL) and one first bit line (BL1), arranged in a matrix.

[0062] Multiple second-position lines BL2 are positioned above multiple wiring SOTLs. These second-position lines BL2 are arranged along the X-direction. Each second-position line BL2 extends along the Y-direction. Viewed from above, the second-position lines BL2 are positioned overlapping with multiple first-position lines BL1.

[0063] Multiple vertical structures V1 extend along the Z-direction. Viewed from above, the multiple vertical structures V1 have a circular shape. Each of the multiple vertical structures V1 connects a corresponding first-position line BL1 to a wiring SOTL. That is, each of the multiple vertical structures V1 is connected to the second part of its corresponding wiring SOTL.

[0064] Multiple vertical structures V2 extend along the Z-direction. Viewed from above, the multiple vertical structures V2 have a circular shape. Each of the multiple vertical structures V2 connects a corresponding second-position line BL2 to a wiring SOTL. That is, each of the multiple vertical structures V2 is connected to the third part of its corresponding wiring SOTL.

[0065] Multiple vertical structures V3 extend along the Z-direction. Viewed from above, the multiple vertical structures V3 have a circular shape. Each of the multiple vertical structures V3 connects a corresponding word line WL to a wiring SOTL. That is, each of the multiple vertical structures V3 is connected to the first part of its corresponding wiring SOTL.

[0066] In the above-described configuration, a group consisting of a wiring SOTL and a vertical structure V1, a vertical structure V2 and a vertical structure V3 connected to the wiring SOTL functions as a storage cell MC.

[0067] (Cross-section structure)

[0068] Next, the cross-sectional structure of the storage cell array in the embodiment will be described.

[0069] Figure 4 This is an example of the cross-sectional structure of the storage cell array in the embodiment. Figure 3 A cross-sectional view along line IV-IV. The memory cell array 10 includes a semiconductor substrate 20 and layer structures L1 and L2. Layer structure L1 includes conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and device layers 22_1, 27_1, and 28_1. Layer structure L2 includes conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and device layers 22_2, 27_2, and 28_2. If a configuration is marked with the suffix "_x", it indicates that the configuration belongs to layer structure Lx (x is an integer greater than or equal to 1).

[0070] A layered structure L1 and L2 are sequentially deposited along the Z direction above the semiconductor substrate 20. The layered structures L1 and L2 correspond to... Figure 3 The plan layout shown.

[0071] Peripheral circuits such as row selection circuit 11 and column selection circuit 12 can be provided between the semiconductor substrate 20 and the layer structure L1. Alternatively, no circuit may be formed between the semiconductor substrate 20 and the layer structure L1. If no circuit is formed between the semiconductor substrate 20 and the layer structure L1, STI (Shallow Trench Isolation) may be formed in the portion of the semiconductor substrate 20 located below the layer structure L1.

[0072] The hierarchical structure L1 is explained.

[0073] A conductive layer 21_1 is disposed above the semiconductor substrate 20. The conductive layer 21_1 is used as the first bit line BL1. The conductive layer 21_1 extends along the Y direction.

[0074] A component layer 22_1 is disposed on the upper surface of the conductor layer 21_1. The component layer 22_1 is used as a switching component SEL1.

[0075] A conductive layer 23_1 is disposed on the upper surface of component layer 22_1. Conductive layer 23_1 is used as a connector. Component layer 22_1 and conductive layer 23_1 constitute a vertical structure V1.

[0076] A conductive layer 24_1 is disposed on the upper surface of conductive layer 23_1. Conductive layer 24_1 is used as a wiring SOTL. The portion of conductive layer 24_1 that is in contact with conductive layer 23_1 corresponds to the second part of wiring SOTL. Conductive layer 24_1 extends along the Y direction.

[0077] A conductive layer 25_1 is disposed on the lower surface of a portion of conductive layer 24_1 that differs from the portion where conductive layer 23_1 is disposed. The portion of conductive layer 24_1 that connects to conductive layer 25_1 corresponds to the first part of wiring SOTL. Conductive layer 25_1 is used as a connector. Conductive layer 25_1 constitutes a vertical structure V3.

[0078] A conductive layer 26_1 is disposed on the lower surface of conductive layer 25_1. Conductive layer 26_1 is used as a word line WL. Conductive layer 26_1 extends along the X direction.

[0079] A component layer 27_1 is disposed on the upper surface of the portion of conductor layer 24_1 between the portion where conductor layer 23_1 is disposed and the portion where conductor layer 25_1 is disposed. The portion of conductor layer 24_1 that is connected to component layer 27_1 corresponds to the third part of wiring SOTL. Component layer 27_1 is used as a magnetoresistive element MTJ.

[0080] Component layer 28_1 is disposed on the upper surface of component layer 27_1. Component layer 28_1 is used as a switching component SEL2. Component layers 27_1 and 28_1 constitute a vertical structure V2.

[0081] A conductive layer 29_1 is disposed on the upper surface of the component layer 28_1. The conductive layer 29_1 is used as the second bit line BL2. The conductive layer 29_1 extends along the Y direction.

[0082] With the above-described configuration, the set of conductive layers 24_1 in the layered structure L1, as well as the vertical structures V1, V2 and V3, function as a storage cell MC with three terminals respectively connected to conductive layers 21_1, 29_1 and 26_1.

[0083] The layer structure L2 has the same configuration as the layer structure L1. That is, the conductor layers 21_2, 23_2, 24_2, 25_2, 26_2, and 29_2, and the element layers 22_2, 27_2, and 28_2 have the same structure and function as the conductor layers 21_1, 23_1, 24_1, 25_1, 26_1, and 29_1, and the element layers 22_1, 27_1, and 28_1, respectively. Therefore, the group of conductor layers 24_2 and the vertical structures V1, V2, and V3 within the layer structure L2 function as a storage cell MC with three terminals connected to the conductor layers 21_2, 29_2, and 26_2, respectively.

[0084] 1.1.3 Magnetoresistive element and peripheral wiring

[0085] Next, the configuration of the magnetoresistive effect element and peripheral wiring of the magnetic memory device of the embodiment will be explained.

[0086] Figure 5 This is the first example illustrating the cross-sectional structure of the magnetoresistive element and its peripheral wiring in the embodiment. Figure 4 A cross-sectional view of region W. Figure 6 This is a second example illustrating the cross-sectional structure of the magnetoresistive element and its peripheral wiring in the first embodiment. Figure 4 A cross-sectional view of region W. For example... Figure 5 and Figure 6 As shown, the component layer 27 includes a stacked body 27a, a non-magnetic layer 27b, a ferromagnetic layer 27c, a non-magnetic layer 27d, and a ferromagnetic layer 27e. The stacked body 27a includes a ferromagnetic layer 27a-1, a dielectric layer 27a-2, and a ferromagnetic layer 27a-3.

[0087] First, the structure of the conductive layer 24 will be explained.

[0088] The conductive layer 24 is a conductive film containing a non-magnetic heavy metal. The conductive layer 24 may contain at least one element selected from tantalum (Ta), tungsten (W), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), copper (Cu), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), manganese (Mn), lead (Pb), and bismuth (Bi) as the heavy metal. The element contained in the conductive layer 24 as a heavy metal may also include oxides. Furthermore, when tantalum (Ta) or tungsten (W) is contained, the structure of this element is preferably a β structure. The conductive layer 24 generates a spin-orbit torque (SOT) primarily due to the bulk spin Hall effect when an internal current flows through it. Additionally, a spin effect due to spin splitting may also occur. The spin-orbit torque acts on the ferromagnetic layer 27a-1.

[0089] Next, the structure of component layer 27 will be explained.

[0090] A ferromagnetic layer 27a-1 is disposed in the central portion of the upper surface of the conductive layer 24. The ferromagnetic layer 27a-1 is a conductive film exhibiting ferromagnetism. The ferromagnetic layer 27a-1 has, for example, a film thickness of 0.5 nanometers (nm) to 3.0 nanometers (nm). The ferromagnetic layer 27a-1 has an easy magnetization axis in a direction perpendicular to the film surface (Z-direction). A spin-orbit moment generated in the conductive layer 24 acts on the ferromagnetic layer 27a-1. The configuration is such that when a specified size of spin-orbit moment is applied, the magnetization direction of the ferromagnetic layer 27a-1 is reversed.

[0091] Generally, the ferromagnetic layer 27a-1 is a ferromagnetic layer using any element selected from cobalt (Co), iron (Fe), and nickel (Ni). Cobalt-iron (CoFe) alloys, iron (Fe), cobalt-iron-boron (CoFeB), iron-boron (FeB), cobalt-boron (CoB), and cobalt-iron-nickel-boron (CoFeNiB) are representative ferromagnetic layers that exhibit perpendicular magnetization. They possess a body-centered cubic (BCC) structure. Additionally, phosphorus (P) and carbon (C) can be used as alternatives to boron (B). The magnetic materials such as CoFeB generate perpendicular magnetic anisotropy at the interface through contact with oxides having a NaCl (001) structure. MgO (001) / CoFeB laminates are typical examples. Furthermore, the ferromagnetic layer 27a-1 may also contain noble metals. The ferromagnetic layer 27a-1 contains, for example, at least one element selected as a noble metal from ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au). Among these, osmium (Os), iridium (Ir), platinum (Pt), and gold (Au), being 5d noble metal elements, are preferred. Furthermore, from the viewpoint of improving the VCMA effect described below, iridium (Ir) is most preferred. The noble metal is preferably 50 at% or less in the ferromagnetic layer 27a-1. Furthermore, "at%" represents atomic percentage. When the ferromagnetic layer 27a-1 contains multiple noble metals, the total amount of the noble metals contained is only required to be 50 at% or less. This is because if the ferromagnetic layer 27a-1 contains more than 50 at% of the noble metals, the magnetic properties of the ferromagnetic layer 27a-1 may deteriorate. In other words, if the ferromagnetic layer 27a-1 contains more than 50 at% of the noble metal, the saturation magnetization Ms and magnetic anisotropy energy Ku of the ferromagnetic layer 27a-1 may be extremely low. Furthermore, a concentration gradient with a higher concentration near the dielectric layer 27a-2 is preferable. This concentration gradient can be detected using nano-EDX (Energy Dispersive X-ray spectroscopy) analysis or nano-EELS (Electron Energy Loss Spectroscopy).

[0092] Alternatively, at least one alloy film selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd), or a Co / Pt laminated film, a Co / Pd laminated film, or a Co / Ni laminated film, can be used for the ferromagnetic layer 27a-1. When using these laminated films, from the viewpoint of efficiently improving the VCMA effect described below, it is desirable that more than half of the magnetic anisotropy of the ferromagnetic layer 27a-1 originates from the interfacial magnetic anisotropy at the interface between the ferromagnetic layer 27a-1 and the dielectric layer 27a-2.

[0093] The ferromagnetic layer 27a-1 can be formed by inserting noble metal layers between the multiple layers constituting the ferromagnetic layer 27a-1. The ferromagnetic layer 27a-1 can also be formed by adding noble metal to at least one layer constituting the ferromagnetic layer 27a-1.

[0094] The ferromagnetic layer 27a-1 will be the topmost layer, that is, the layer connected to the dielectric layer 27a-2 is a ferromagnetic layer containing cobalt (Co), iron (Fe), or nickel (Ni). The same applies when using laminated films such as the Co / Pt laminated film.

[0095] A dielectric layer 27a-2 is disposed on the upper surface of the ferromagnetic layer 27a-1. The dielectric layer 27a-2 has a film thickness of, for example, less than 2.0 nm. The dielectric layer 27a-2 has, for example, a NaCl crystal structure with the film surface orientation of the (001) plane, a cubic crystal system, or a tetragonal crystal system. In order to maintain the crystal system, it is expected that a stack of more than three atomic layers is required, therefore the film thickness of the dielectric layer 27a-2 is preferably more than 0.5 nm. The purpose is to improve the strength of the ferromagnetic electrostatic coupling and interlayer exchange coupling between the ferromagnetic layer 27a-1 and the ferromagnetic layer 27a-3. The ferromagnetic layer 27a-1 and the ferromagnetic layer 27a-3 are ferromagnetically electrostatically coupled via the dielectric layer 27a-2, and are ferromagnetically exchange-coupled. As a result, the ferromagnetic layer 27a-1 and the ferromagnetic layer 27a-3 exhibit integrated magnetization reversal behavior. The dielectric constant of dielectric layer 27a-2 is greater than or equal to the dielectric constant of non-magnetic layer 27b. For example, dielectric layer 27a-2 preferably has a dielectric constant of magnesium oxide (MgO) or greater.

[0096] Examples of dielectric layers 27a-2 with a NaCl crystal structure include magnesium oxide (MgO), calcium oxide (CaO), nickel oxide (NiO), cobalt oxide (CoO), iron oxide (FeO), chromium oxide (CrO), strontium oxide (SrO), vanadium oxide (VO), manganese oxide (MnO), barium oxide (BaO), and cadmium oxide (CdO). Examples of cubic or tetragonal dielectric layers 27a-2 include Al₂O₃ and AO₂ rutile structures. Examples of element A suitable for the structural film include ytterbium (Yb), yttrium (Y), gallium (Ga), europium (Eu), erbium (Er), holmium (Ho), lutetium (Lu), iron (Fe), zirconium (Zr), neodymium (Nd), scandium (Sc), chromium (Cr), terbium (Tb), tin (Sn), samarium (Sm), cerium (Ce), dysprosium (Dy), thulium (Tm), gadolinium (Gd), bismuth (Bi), hafnium (Hf), lanthanum (La), praseodymium (Pr), titanium (Ti), indium (In), ruthenium (Ru), iridium (Ir), and osmium (Os). Examples of tetragonal dielectric layer 27a-2 include tri-elemental materials such as ABO3. Examples of such tri-elemental materials include SrRuO3, SrTiO3, and LaAlO3.

[0097] Furthermore, the dielectric layer 27a-2 only needs to have a strong dielectric and is not limited to being non-magnetic; it may also be ferromagnetic or ferrimagnetic. Examples of compounds contained in the ferromagnetic or ferrimagnetic dielectric layer 27a-2 include Fe3O4, CoFe2O4, MnFe2O4, NiFe2O4, CuFe2O4, and MgFe2O4. These compounds have a spinel structure. In this case, the ferromagnetic layers 27a-1 and 27a-3 have magnetic interlayer interactions, thereby increasing the magnetization coupling force. This is preferable from the viewpoint of the integrity and uniformity of the magnetization reversal between the ferromagnetic layers 27a-1 and 27a-3.

[0098] The ferromagnetic layer 27a-1, as described above, exhibits the VCMA (Voltage Control of Magnetic Anisotropy) effect at its interface with the dielectric layer 27a-2. The VCMA effect refers to the phenomenon where the energy barrier ΔE required to reverse the magnetization of a magnetic material by applying a voltage changes. Furthermore, while physically the VCMA effect involves a change in the energy barrier ΔE, the measurement parameter for the VCMA effect is the change in the coercivity Hc of the ferromagnetic layer 27a-1. A decrease in coercivity Hc indicates a decrease in the energy barrier ΔE. The noble metals contained in the ferromagnetic layer 27a-1 can amplify the VCMA effect.

[0099] From the viewpoint of increasing the VCMA effect, the noble metal contained in the ferromagnetic layer 27a-1 is ideally an element containing at least one of the following: osmium (Os), iridium (Ir), platinum (Pt), and gold (Au), all selected as 5d noble metal elements. To further increase the VCMA effect through dielectric polarization, it is desirable that the dielectric constant of the dielectric layer 27a-2 be higher (e.g., higher than that of magnesium oxide (MgO)). Furthermore, from the viewpoint of both increasing the VCMA effect and obtaining magnetic anisotropy, the average concentration of the noble metal contained in the ferromagnetic layer 27a-1 is preferably 50 at% or less. This is because if the ferromagnetic layer 27a-1 contains more than 50 at% of the noble metal, the magnetic properties of the ferromagnetic layer 27a-1 may deteriorate. In other words, if the ferromagnetic layer 27a-1 contains more than 50 at% of the aforementioned noble metal, the saturation magnetization Ms and magnetic anisotropy energy Ku of the ferromagnetic layer 27a-1 may be extremely low. From the perspective of the interfacial magnetic anisotropy at the interface between the ferromagnetic layer 27a-1 and the dielectric layer 27a-2, the local noble metal coating rate at the interface between the ferromagnetic layer 27a-1 and the dielectric layer 27a-2 can also be 100%. Since a magnetoresistance effect is not required at the interface between the ferromagnetic layer 27a-1 and the dielectric layer 27a-2, an interface coating rate that maximizes the efficiency of the VCMA effect is chosen. However, even if the coating rate reaches 100%, when using feasible analytical methods (EDX or EELS), the concentration can only be estimated to be around 50% to 90% due to the influence of the upper and lower layers caused by the electron beam spot size.

[0100] A ferromagnetic layer 27a-3 is disposed on the upper surface of the dielectric layer 27a-2. The ferromagnetic layer 27a-3 has a film thickness of, for example, 0.5 nanometers (nm) to 3.0 nanometers (nm). The ferromagnetic layer 27a-3 is a conductive film having ferromagnetic static coupling or ferromagnetic interlayer exchange coupling with the ferromagnetic layer 27a-1. The ferromagnetic layer 27a-3 has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). Therefore, the magnetization direction of the ferromagnetic layer 27a-3 is parallel to the magnetization direction of the ferromagnetic layer 27a-1 under static conditions. In the following description, the magnetization directions of the ferromagnetic layers 27a-1 and 27a-3 are also referred to as the magnetization direction of the stack 27a.

[0101] The ferromagnetic layer 27a-3 contains iron (Fe). The ferromagnetic layer 27a-3 may also contain at least one element selected from cobalt (Co) and nickel (Ni). Additionally, the ferromagnetic layer 27a-3 may also contain boron (B). More specifically, the ferromagnetic layer 27a-3 may contain, for example, cobalt-iron-boron (CoFeB), iron-boron (FeB), cobalt-boron (CoB), or cobalt-iron-nickel-boron (CoFeNiB).

[0102] Furthermore, the amount of noble metal contained in the ferromagnetic layer 27a-3 is less than the amount of noble metal contained in the ferromagnetic layer 27a-1. If possible, the concentration of noble metal contained in the ferromagnetic layer 27a-3 is preferably so low as to be negligible. That is, the concentration of noble metal contained in the ferromagnetic layer 27a-3 is significantly lower than the concentration of noble metal contained in the ferromagnetic layer 27a-1. In physical analyses such as TEM-EDX (Transmission Electron Microscope-Energy Dispersive X-ray Spectroscopy) or EELS, it is preferable to be below the detection limit. This is important as it reduces the degradation of the tunneling magneto resistance (TMR) ratio. The dielectric layer 27a-2 functions as a diffusion barrier layer, inhibiting the diffusion of noble metal contained in the ferromagnetic layer 27a-1 into the ferromagnetic layer 27a-3.

[0103] The stack 27a comprising the ferromagnetic layer 27a-1, dielectric layer 27a-2 and ferromagnetic layer 27a-3 as described above is used as a storage layer.

[0104] A non-magnetic layer 27b is disposed on the upper surface of the ferromagnetic layer 27a-3. The non-magnetic layer 27b is a non-magnetic insulating film. The non-magnetic layer 27b is used as a tunnel barrier layer. The non-magnetic layer 27b is disposed between the ferromagnetic layer 27a-3 and the ferromagnetic layer 27c, forming a magnetic tunnel junction together with these two ferromagnetic layers. That is, a magnetoresistance effect is generated in the magnetic tunnel junction portion. In addition, when an initial amorphous layer such as cobalt iron boron (CoFeB) is used as the interface layer between the ferromagnetic layer 27a-3 and the ferromagnetic layer 27c, the non-magnetic layer 27b functions as a seed material in the crystallization process of the ferromagnetic layer 27a-3, and this seed material becomes the nucleus for growing a crystalline film from the interface with the ferromagnetic layer 27a-3. Similarly, when cobalt iron boron (CoFeB) is used as the interface layer of the ferromagnetic layer 27c, the non-magnetic layer 27b also functions as a seed material for the ferromagnetic layer 27c. Here, the term "initial amorphous layer" refers to a layer that is amorphous immediately after film formation and crystallizes after annealing. The nonmagnetic layer 27b has a tetragonal or cubic crystal structure with the film surface oriented at the (001) plane. For example, magnesium oxide (MgO) can be used as an oxide in the nonmagnetic layer 27b. Magnesium oxide (MgO) has a NaCl structure. When magnesium oxide (MgO) is used in the nonmagnetic layer 27b, the (001) interface of magnesium oxide (MgO) matches the (001) interface of cobalt iron boron (CoFeB), and crystallizes and grows through annealing. Therefore, cobalt iron boron (CoFeB) becomes a body-centered cubic structure with (001) orientation.

[0105] A ferromagnetic layer 27c is disposed on the upper surface of the non-magnetic layer 27b. The ferromagnetic layer 27c is a conductive film with ferromagnetic properties. The ferromagnetic layer 27c is used as a reference layer. The ferromagnetic layer 27c has an easy magnetization axis in a direction perpendicular to the film surface (Z direction). The magnetization direction of the ferromagnetic layer 27c is fixed. That is, during normal component operation, the magnetization of the reference layer remains unchanged. Figure 5In the example, the magnetization direction of the ferromagnetic layer 27c is oriented towards the stack 27a. Furthermore, "fixed magnetization direction" means that the magnetization direction remains unchanged under a torque large enough to reverse the magnetization direction of the stack 27a. Typically, an interface layer is used for the ferromagnetic layer 27c. As the interface layer for the ferromagnetic layer 27c, an initial amorphous layer such as cobalt-iron-boron (CoFeB) can be used. Furthermore, an auxiliary ferromagnetic layer is provided such that it is in contact with the side opposite to the side in contact with the magnesium oxide (MgO) layer of the CoFeB layer. This auxiliary ferromagnetic layer may, for example, comprise at least one alloy film selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). This auxiliary ferromagnetic layer becomes a Co / Pt stacked film, a Co / Pd stacked film, or a similar stacked film. This is used for stacking the initial amorphous cobalt-iron-boron (CoFeB) layer with CoPt, CoPd, Co / Pt stacked films, Co / Pd stacked films, etc. In this case, the interface layer in the ferromagnetic layer 27c, such as the CoFeB layer, has MgO that has been oriented (001) at a position closer to the nonmagnetic layer 27b compared to other layers.

[0106] A non-magnetic layer 27d is disposed on the upper surface of the ferromagnetic layer 27c. The non-magnetic layer 27d is a non-magnetic conductive film. The non-magnetic layer 27d is used as a spacer layer. The non-magnetic layer 27d is composed, for example, of elements selected from ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), and chromium (Cr), or alloys thereof. For example, the film thickness of the non-magnetic layer 27d is less than 2 nm.

[0107] A ferromagnetic layer 27e is disposed on the upper surface of the non-magnetic layer 27d. The ferromagnetic layer 27e is a conductive film with ferromagnetism. The ferromagnetic layer 27e is used as a shift canceling layer. The ferromagnetic layer 27e has an easy magnetization axis orientation in a direction perpendicular to the film surface (Z direction). The ferromagnetic layer 27e may, for example, comprise at least one alloy layer selected from cobalt-platinum (CoPt), cobalt-palladium (CoPd), cobalt-palladium-platinum (CoPdPt), and cobalt-chromium-platinum (CoCrPt). Alternatively, the ferromagnetic layer 27e may also be a laminated film such as a Co / Pt laminated film, a Co / Pd laminated film, or a Co / Ni laminated film.

[0108] Ferromagnetic layer 27c and ferromagnetic layer 27e are antiferromagnetically coupled through nonmagnetic layer 27d. That is, ferromagnetic layer 27c and ferromagnetic layer 27e are coupled with mutually antiparallel magnetization directions. This antiferromagnetic magnetic coupling of ferromagnetic layer 27c, nonmagnetic layer 27d, and ferromagnetic layer 27e is called SAF (Synthetic Anti-Ferromagnetic) coupling. Through SAF coupling, ferromagnetic layer 27e can counteract the influence of the leakage magnetic field of ferromagnetic layer 27c on the change in magnetization direction of the laminate 27a, thereby reducing the substantial impact of the leakage magnetic field of ferromagnetic layer 27c on the laminate 27a.

[0109] The magnetoresistive element (MTJ) can determine whether it is in a low-impedance or high-impedance state based on whether the magnetization directions of the storage layer and the reference layer are parallel or antiparallel. In this implementation, the relationship between the magnetization direction of the storage layer and the magnetization direction of the reference layer is controlled by not flowing a write current into the MTJ. Specifically, a writing method utilizing the spin-orbit torque generated by flowing current into the SOTL wiring is employed.

[0110] If a write current Ic0 of a certain magnitude is flowed into the SOTL wiring along the Y direction, the relative magnetization directions of the storage layer and the reference layer become parallel. In this parallel state, the impedance of the magnetoresistive element MTJ is at its lowest, and the magnetoresistive element MTJ is set to a low-impedance state. This low-impedance state is called the "P (Parallel) state," and for example, it is defined as the state of data "0".

[0111] Furthermore, if a write current Ic1 flows into the SOTL wiring in the opposite direction to the write current Ic0, the relative magnetization directions of the storage layer and the reference layer become antiparallel. In this antiparallel state, the magnetoresistive element MTJ has the highest impedance value, and the magnetoresistive element MTJ is set to a high-impedance state. This high-impedance state is called the "AP (Anti-Parallel) state," and for example, it is defined as the state of data "1".

[0112] Furthermore, the method of specifying data "1" and data "0" is not limited to the example described above. For example, the P state can also be specified as data "1" and the AP state as data "0".

[0113] The shape of the magnetoresistive element (MTJ) as seen when viewed from the Z-direction is elliptical or circular. From the viewpoint of high-density integrated memory cell (MC), a circular shape is preferred when viewed from the Z-direction. From the viewpoint of reducing area and power consumption, the shorter side length of the MTJ when it is elliptical and the radius of the MTJ when it is circular are preferably 100 nm or less. Furthermore, when performing high-speed magnetization reversal of the stacked layer 27a in 5 nsec or less, a radius of 30 nm or less is preferred. When the radius of the magnetoresistive element (MTJ) is 10 nm or less, it approximates simultaneous magnetization reversal along a single magnetic axis, resulting in a magnetization reversal mode that does not form a defined magnetic wall. This achieves high-speed magnetization reversal.

[0114] 1.2 Write Action

[0115] Next, the writing operation of the magnetic memory device according to the embodiment will be explained.

[0116] 1.2.1 Voltage application

[0117] Figure 7 This is a circuit diagram illustrating an example of a write operation in a magnetic memory device according to an embodiment. Figure 7 The example shows the voltage applied to various wirings when writing data to storage cells MC<m, n> in multiple storage cells MC (0 < m < M, 0 < n < N).

[0118] When writing data to memory cell MC<m, n>, voltages VDD or VSS are applied to word line WL<m> and the first bit line BL1<n>, respectively. When VDD is applied to word line WL<m>, voltage VSS is applied to the first bit line BL1<n>. When VSS is applied to word line WL<m>, voltage VDD is applied to the first bit line BL1<n>. Voltage Vvcma (=VDD / 2+α) is applied to the second bit line BL2<n>. Voltage VDD / 2 is applied to all word lines WL (excluding word line WL<m>), all first bit lines BL1 (excluding the first bit line BL1<n>), and all second bit lines BL2 (excluding the second bit line BL2<n>).

[0119] Therefore, a potential difference VDD is generated between the word line WL<m> and the first bit line BL1<n>. In this case, the potential at the connection between the wiring SOTL<m,n> and the magnetoresistive element MTJ<m,n> becomes VDD / 2. Therefore, a potential difference α is generated between the wiring SOTL<m,n> and the second bit line BL2<n>.

[0120] Additionally, a potential difference VDD / 2 is generated between word line WL<m> and any first bit line BL1 other than the first bit line BL1<n>. A potential difference VDD / 2 is generated between any word line WL other than word line WL<m> and the first bit line BL1<n>. Furthermore, no potential difference is generated between any word line WL other than word line WL<m> and any first bit line BL1 other than the first bit line BL1<n>. The potential difference generated between any group of wiring SOTL and second bit line BL2, other than the group formed by wiring SOTL<m,n> and the second bit line BL2<n>, is less than the potential difference α.

[0121] Here, voltage VSS is the reference potential. For example, voltage VSS is 0V. The difference between voltage VDD and voltage VSS (potential difference VDD) turns switching elements SEL1 and SEL2 on. Potential difference VDD / 2 turns switching element SEL1 off. The potential difference α between voltage Vvcma and voltage VDD / 2 turns switching element SEL2 on. Potential differences generated between any group of wiring SOTL and BL2 (excluding the group formed by wiring SOTL<m,n> and the second-position line BL2<n>) turn switching element SEL2 off.

[0122] Therefore, switching elements SEL1<m,n> and SEL2<m,n> are in the ON state. All switching elements SEL1 except SEL1<m,n> are in the OFF state. All switching elements SEL2 except SEL2<m,n> are in the OFF state.

[0123] Therefore, a potential difference VDD can be applied to the wiring SOTL<m,n> while a potential difference α can be applied to the magnetoresistive element MTJ<m,n>. By applying a potential difference VDD to the conductive layer 24, a current can flow to change the impedance state of the magnetoresistive element MTJ. By applying a potential difference α to the magnetoresistive element MTJ, a significant VCMA effect can be generated in the ferromagnetic layer 24a-1. Furthermore, because the switching element SEL2 is in the ON state, current also flows to the magnetoresistive element MTJ<m,n>, but the amount of current is negligible.

[0124] During the write operation, the state of storage cell MC<m,n> is also called the selected state. The states of storage cells MC<0,n> to MC<m-1,n>, MC<m+1,n> to MC<M,n>, MC<m,0> to MC<m,n-1>, and MC<m,n+1> to MC<m,N> are also called the semi-selected states. All storage cells MC that are not in the selected state or semi-selected state are also called the non-selected states.

[0125] 1.2.2 VCMA effect

[0126] Figure 8 This is a line diagram illustrating an example of the VCMA effect generated on the storage layer of a storage cell in a magnetic memory device according to an embodiment. Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a line graph showing an example of the magnetization curve of the storage layer of the storage cell in a magnetic memory device according to an embodiment. Figure 8 In the figure, lines Q1 and Q2 represent the changes in coercivity Hc of ferromagnetic layers 27a-3 and 27a-1 relative to the potential difference V caused by the VCMA effect. Figure 9 The figure shows an example of the magnetization curve of the ferromagnetic layer 27a-3 of the storage cell MC when there is no potential difference. Figure 10 The figure shows an example of the magnetization curve of the ferromagnetic layer 27a-3 of the storage cell MC when there is a potential difference. Figure 11 The figure shows an example of the magnetization curve of the ferromagnetic layer 27a-1 of the storage cell MC when there is no potential difference. Figure 12 The figure shows an example of the magnetization curve of the ferromagnetic layer 27a-1 of the storage cell MC when there is a potential difference.

[0127] As described above, the amount of noble metal contained in the ferromagnetic layer 27a-3 is significantly less than the amount of noble metal contained in the ferromagnetic layer 27a-1. Therefore, as Figure 8 As shown by line Q1, the slope of the coercivity Hc of the ferromagnetic layer 27a-3 relative to the potential difference V is so small that it can be considered as 0.

[0128] Therefore, as Figure 9 and Figure 10 As shown, the coercivity Hc of the ferromagnetic layer 27a-3 remains almost unchanged under static conditions (Hc1) where no potential difference is generated, such as in a standby state, and under conditions where a significant potential difference, such as α, is generated, such as during a write operation (Hc1'). The standby state refers to a state in which neither write nor read operations are performed. Furthermore, the saturation magnetization Ms of the ferromagnetic layer 27a-3 remains almost unchanged under static conditions (Ms1) where no potential difference is generated, such as in a standby state, and under conditions where a significant potential difference, such as α, is generated, such as during a write operation (Ms1').

[0129] In contrast, the ferromagnetic layer 27a-1 is constructed by incorporating noble metals. Therefore, as shown in line Q2, the slope of the coercivity Hc of the ferromagnetic layer 27a-1 relative to the potential difference V becomes a large negative value.

[0130] Therefore, as Figure 11 and Figure 12As shown, the coercivity (Hc2') of the ferromagnetic layer 27a-1 when a potential difference of a significant magnitude, similar to the potential difference α during a write operation, is significantly lower than that in the static case (Hc2) where no potential difference is generated, similar to the standby state. In other words, the overall coercivity of the ferromagnetic layers 27a-1 and 27a-3 when a potential difference of a significant magnitude, similar to the potential difference α during a write operation, is lower than that in the static case where no potential difference is generated, similar to the standby state. Furthermore, the saturation magnetization Ms of the ferromagnetic layer 27a-1 remains almost unchanged between the static case (Ms2) where no potential difference is generated and, for example, the case (Ms2') where a potential difference of a significant magnitude, similar to the potential difference α during a write operation, is generated.

[0131] Here, the energy barrier ΔE of the ferromagnetic layer can be expressed by the saturation magnetization Ms and the coercivity Hc as shown in Equation (1).

[0132] ΔE=KuV=(MsHk / 2)·V≒(MsHc / 2)·V=MsVHc / 2…(1)

[0133] In equation (1) above, Ku is the magnetic anisotropic energy. V is the volume, V = the product of the element area S and the film thickness t. Hk is the anisotropic magnetic field.

[0134] Thus, without a potential difference, the energy barriers ΔE of ferromagnetic layers 27a-1 and 27a-3 remain almost unchanged. Therefore, without a potential difference, the overall energy barrier ΔE of the storage layer remains almost unchanged. On the other hand, with a potential difference as significant as α, the energy barrier ΔE of ferromagnetic layer 27a-3 remains unchanged, but the energy barrier ΔE of ferromagnetic layer 27a-1 decreases significantly. In other words, it is preferable to have a larger decrease in the energy barrier ΔE of ferromagnetic layer 27a-1. Therefore, with a potential difference as significant as α, the overall energy barrier ΔE of the storage layer decreases significantly. Thus, the overall energy barrier ΔE of the storage layer decreases only when a significant potential difference is generated. Therefore, the selected state storage cell MC during the write operation becomes easier to write than when the VCMA effect is not utilized.

[0135] 1.2.3 Magnetization Reversal

[0136] Figure 13 and Figure 14 This is a cross-sectional view illustrating an example of a write operation in a magnetic memory device according to an embodiment. Figure 13 and Figure 14 The diagram schematically illustrates the current flowing to the storage cell MC in the selected state and the magnetization direction of the magnetoresistive element MTJ. Figure 13 This corresponds to the write action when writing the data "1". Figure 14 This corresponds to the write action when writing data "0".

[0137] First, refer to Figure 13 The writing action of the data "1" is explained. Figure 13 The example shows the write current Ic1 flowing from word line WL (right side of the paper) to bit line BL1 (left side of the paper).

[0138] like Figure 13 As shown in (A), a potential difference VDD is generated across the conductive layer 24 to turn on the switching element SEL1. By controlling the potential difference VDD, a write current Ic1 flows into the conductive layer 24. The flow of the write current Ic1 within the conductive layer 24 generates a spin orbital moment that aims to make the magnetization direction of the ferromagnetic layer 27a-1 antiparallel to the magnetization direction of the ferromagnetic layer 27c. This spin orbital moment acts on the ferromagnetic layer 27a-1, which is close to the conductive layer 24. Furthermore, Figure 13 Although not illustrated, a bias magnetic field in the Y direction was applied to the ferromagnetic layer 27a-1.

[0139] Furthermore, a potential difference α is generated at both ends of the element layer 27 such that the reference layer side is at a higher potential relative to the storage layer side. As a result, the VCMA effect occurs, and the energy barrier ΔE of the ferromagnetic layer 27a-1 decreases.

[0140] Therefore, the magnetization direction of the ferromagnetic layer 27a-1 is reversed to an antiparallel direction to the magnetization direction of the ferromagnetic layer 27c by the application of spin orbital moment, bias magnetic field, and VCMA effect.

[0141] As described above, the ferromagnetic layer 27a-3 and the ferromagnetic layer 27a-1 are ferromagnetically statically coupled or exchange-coupled. Thus, as... Figure 13 As shown in (B), the magnetization direction of the ferromagnetic layer 27a-3 is reversed in such a way that it becomes parallel to the magnetization direction of the ferromagnetic layer 27a-1.

[0142] Through the actions described above, the magnetization direction of the stack 27a is reversed to be antiparallel to the magnetization direction of the ferromagnetic layer 27c, and the writing of the data "1" is completed.

[0143] Secondly, refer to Figure 14 This section explains the action of writing the data "0". Figure 14 The example shows the write current Ic0 flowing from bit line BL1 (left side of the paper) to word line WL (right side of the paper).

[0144] like Figure 14As shown in (A), a potential difference VDD is generated across the conductive layer 24 to turn on the switching element SEL1. By controlling the potential difference VDD, a write current Ic0 flows into the conductive layer 24. The flow of the write current Ic0 within the conductive layer 24 generates a spin orbital moment that aims to make the magnetization direction of the ferromagnetic layer 27a-1 parallel to the magnetization direction of the ferromagnetic layer 27c. This spin orbital moment acts on the ferromagnetic layer 27a-1, which is close to the conductive layer 24. Furthermore, Figure 14 Although not illustrated, a bias magnetic field in the Y direction was applied to the ferromagnetic layer 27a-1.

[0145] Furthermore, a potential difference α is generated at both ends of the element layer 27 such that the reference layer side is at a higher potential relative to the storage layer side. As a result, the VCMA effect occurs, and the energy barrier ΔE of the ferromagnetic layer 27a-1 decreases.

[0146] Therefore, the magnetization direction of the ferromagnetic layer 27a-1 is reversed to a direction parallel to the magnetization direction of the ferromagnetic layer 27c by means of the spin orbital moment, the bias magnetic field, and the VCMA effect.

[0147] As described above, the ferromagnetic layer 27a-3 and the ferromagnetic layer 27a-1 are ferromagnetically statically coupled or exchange-coupled. Thus, as... Figure 14 As shown in (B), the magnetization direction of the ferromagnetic layer 27a-3 is reversed in such a way that it becomes parallel to the magnetization direction of the ferromagnetic layer 27a-1.

[0148] Through the actions described above, the magnetization direction of the stack 27a is reversed to be parallel to the magnetization direction of the ferromagnetic layer 27c, and the writing of the data "0" is completed.

[0149] Furthermore, if the saturation magnetization Ms·t of ferromagnetic layer 27a-1 is greater than that of ferromagnetic layer 27a-3, then as the magnetization direction of ferromagnetic layer 27a-1 reverses, the magnetization direction of ferromagnetic layer 27a-3 becomes easier to reverse. Therefore, it is preferable to select a material in such a way that the saturation magnetization Ms·t of ferromagnetic layer 27a-1 is greater than that of ferromagnetic layer 27a-3. In addition, in this case, ferromagnetic layer 27a-1 and ferromagnetic layer 27a-3 are both statically coupled and interlayer exchange coupled, so the saturation magnetization Ms of ferromagnetic layer 27a-1 is preferably greater than that of ferromagnetic layer 27a-3, and the film thickness t of ferromagnetic layer 27a-1 is preferably greater than that of ferromagnetic layer 27a-3. After adjusting the film thickness t and the saturation magnetization Ms, the magnetic anisotropy energy Ku of the ferromagnetic layer 27a-1 will inevitably become greater than that of the ferromagnetic layer 27a-3. For example, when using a cobalt-iron-boron (CoFeB) film, the film thickness t and the saturation magnetization Ms can be adjusted by the boron (B) content. In this case, the aforementioned relationship can be achieved by making the boron (B) content of the ferromagnetic layer 27a-1 less than that of the ferromagnetic layer 27a-3.

[0150] 1.3 Effects of the Implementation Method

[0151] In the magnetic memory device 1 of this embodiment, a writing method utilizing spin-orbit torque is used. In this case, there is a risk of a higher write current compared to a writing method utilizing spin-transfer torque. According to this embodiment, the write current can be reduced. The advantages of this embodiment will be explained below.

[0152] According to the embodiment, the stack 27a, which functions as a storage layer, includes a ferromagnetic layer 27a-1, a ferromagnetic layer 27a-3, and a dielectric layer 27a-2 between the ferromagnetic layers 27a-1 and 27a-3, all connected to the conductive layer 24. The ferromagnetic layer 27a-1 contains a noble metal. Therefore, during write operations, the energy barrier ΔE of the ferromagnetic layer 27a-1 in the selected state can be significantly reduced. Consequently, during write operations, the spin-orbit moment acting on the ferromagnetic layer 27a-1 can be reduced. Thus, the write current can be reduced.

[0153] Furthermore, in standby mode or other states where no write operation is performed, or in a non-selected or semi-selected state during a write operation, the energy barrier ΔE of the ferromagnetic layer 27a-1 does not decrease but remains unchanged. Therefore, in standby mode or other states, the magnetization direction of the ferromagnetic layer 27a-1 is less likely to reverse compared to the selected state during a write operation.

[0154] Furthermore, the concentration of noble metals in ferromagnetic layer 27a-1 is higher than that in ferromagnetic layer 27a-3. This suppresses the degradation of the tunnel magnetoresistance (TMR) ratio caused by the presence of noble metals in ferromagnetic layer 27a-3. Therefore, it is possible to maintain the TMR ratio while reducing the write current.

[0155] Furthermore, the concentration of noble metal contained in the ferromagnetic layer 27a-1 is less than 50 at%. The coverage of noble metal contained in the ferromagnetic layer 27a-1 at the interface between the ferromagnetic layer 27a-1 and the dielectric layer 27a-2 is less than 70%. Therefore, the VCMA effect can be generated without compromising the interfacial magnetic anisotropy of the ferromagnetic layer 27a-1.

[0156] Furthermore, the thickness of each of the ferromagnetic layers 27a-1 and 27a-3 is designed to be 0.5 nm or more. This allows the ferromagnetic layers 27a-1 and 27a-3 to be formed without causing the loss of saturation magnetization Ms and magnetic anisotropy energy Ku. Additionally, the thickness of each of the ferromagnetic layers 27a-1 and 27a-3 is designed to be 3.0 nm or less. This allows the ferromagnetic layers 27a-1 and 27a-3 to be formed without causing the loss of the anisotropic magnetic field Hk, which is a perpendicular magnetic characteristic.

[0157] 2. Examples of variations, etc.

[0158] Furthermore, the embodiments described are not limited to the example described above, but various variations can be applied.

[0159] In the described embodiment, a case where two-terminal switching elements are used for switching elements SEL1 and SEL2 is illustrated, but the embodiment is not limited to this. For example, such as... Figure 15 As shown, three-terminal switching elements can also be used for switching elements SEL1 and SEL2. Specifically, for example, a transistor such as an SGT (Surrounding Gate Transistor) can be used as a three-terminal switching element. In this case, the first part of all wiring SOTL is commonly connected to the source line SL. The source line SL is grounded, for example. Moreover, the gate of switching element SEL1<i,j> is connected to word line WL1<i,j>. The gate of switching element SEL2<i,j> is connected to word line WL2<i,j>. In this way, one memory cell MC can be selected by controlling each switching element SEL1 and SEL2 separately using individual word lines WL1 and WL2.

[0160] In addition, Figure 15 The example illustrates the case where both switching elements SEL1 and SEL2 are three-terminal switching elements, but it is not limited to this. For example, as... Figure 16As shown, a three-terminal switching element can also be used for switching element SEL1, and a two-terminal switching element can be used for switching element SEL2.

[0161] Furthermore, the described embodiment uses a selector as a two-terminal switching element for the application of switching element SEL2, but it is not limited to this. For example, such as Figure 17 As shown, a selector can also be applied to the switching element SEL1, and a diode can be applied to the switching element SEL2.

[0162] In addition, Figure 17 The example illustrates the application of a selector to the switching element SEL1, but is not limited to this. For example, as... Figure 18 As shown, a three-terminal switching element can also be used for switching element SEL1, and a diode can be used for switching element SEL2. In this case, with Figure 15 and Figure 16 Similarly, in this example, the first part of all wiring SOTL is commonly connected to the source line SL. The source line SL is grounded, for example. Moreover, the gate of the switching element SEL1<i,j> is connected to the word line WL1<i,j>. In this way, one memory cell MC can be selected by controlling each switching element SEL1 using the individual word line WL1.

[0163] Furthermore, the embodiment described herein illustrates a case where the magnetoresistive element MTJ is configured such that the storage layer is located below the reference layer, but it is not limited to this. For example, such as Figure 19 and Figure 20 As shown, the magnetoresistive element MTJ can also be configured with the storage layer located above the reference layer. In this case, the portion of the lower surface of the conductive layer 24 that connects to the ferromagnetic layer 27a-1 protrudes downwards from the lower surface compared to other portions of the lower surface of the conductive layer 24. Figure 19 In the example shown, one side of the connection portion of the conductive layer 24 with the ferromagnetic layer 27a-1 is aligned with one side of the ferromagnetic layer 27a-1. Figure 20 In the example shown, the connection portion between the conductive layer 24 and the ferromagnetic layer 27a-1 is tapered.

[0164] Furthermore, in the described embodiment, the magnetoresistive element MTJ has been described as having an easy magnetization axis direction in a direction perpendicular to the film surface, but it is not limited to this. For example, the magnetoresistive element MTJ may also have an easy magnetization axis direction in a direction parallel to the film surface. More specifically, for example, the magnetoresistive element MTJ may also have an easy magnetization axis direction along the Y-axis. In this case, during the write operation, a bias magnetic field is applied to the ferromagnetic layer 27a-1 along the Z-direction together with the spin-orbit moment. Alternatively, for example, the magnetoresistive element MTJ may also have an easy magnetization axis direction along the X-axis. In this case, during the write operation, a bias magnetic field is not required to be applied to the ferromagnetic layer 27a-1 along with the spin-orbit moment.

[0165] Furthermore, the embodiment shown illustrates a case where two layered structures L1 and L2 are deposited above the semiconductor substrate 20, but it is not limited to this. For example, three or more layered structures with the same structure may also be deposited above the semiconductor substrate 20. Alternatively, for example, a single layered structure may be deposited above the semiconductor substrate 20.

[0166] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention and its equivalents as set forth in the claims.

[0167] [Explanation of Symbols]

[0168] 1: Magnetic storage device

[0169] 10: Storage Cell Array

[0170] 11: Row selection circuit

[0171] 12: Column Selection Circuit

[0172] 13: Decoding Circuit

[0173] 14: Writing Circuit

[0174] 15: Readout Circuit

[0175] 16: Voltage generation circuit

[0176] 17: Input / output circuit

[0177] 18: Control Circuit

[0178] 20: Semiconductor substrate

[0179] 21,23,24,25,26,29: Conductor layer

[0180] 22, 27, 28: Component Layer

[0181] 27a: Laminated body

[0182] 27b, 27d: Non-magnetic layers

[0183] 27a-1, 27a-3, 27c, 27e: Ferromagnetic layers

[0184] 27a-2: Dielectric layer.

Claims

1. A magnetic storage device comprising: First conductor layer; Second conductive layer; The third conductive layer extends along the first direction; and A three-terminal memory cell is connected to the first conductor layer, the second conductor layer, and the third conductor layer; The storage cell has: A fourth conductive layer extends along the first direction; and A magnetoresistive element is disposed between the fourth conductor layer and the third conductor layer; The magnetoresistive effect element includes: The first ferromagnetic layer is connected to the fourth conductive layer in a second direction that intersects with the first direction; The second ferromagnetic layer is disposed on the side opposite to the fourth conductive layer, relative to the first ferromagnetic layer; A dielectric layer is located between the first ferromagnetic layer and the second ferromagnetic layer; The third ferromagnetic layer is disposed on the side opposite to the first ferromagnetic layer, relative to the second ferromagnetic layer; and A non-magnetic layer, disposed between the second and third ferromagnetic layers, comprises oxygen and magnesium; and The concentration of the first noble metal in the first ferromagnetic layer is higher than the concentration of the second noble metal in the second ferromagnetic layer.

2. The magnetic memory device according to claim 1, The magnetoresistive element further comprises: A fourth ferromagnetic layer is disposed on the side opposite to the second ferromagnetic layer, relative to the third ferromagnetic layer; and A second non-magnetic layer is disposed between the third ferromagnetic layer and the fourth ferromagnetic layer; and The third ferromagnetic layer and the fourth ferromagnetic layer have mutually antiparallel magnetic directions. The coupling of the third ferromagnetic layer, the second nonmagnetic layer, and the fourth ferromagnetic layer constitutes a synthetic antiferromagnetic SAF structure.

3. The magnetic memory device according to claim 1, wherein... The first ferromagnetic layer comprises at least one element selected from osmium, iridium, platinum and gold as the first noble metal.

4. The magnetic memory device according to claim 1, wherein... The first ferromagnetic layer contains iridium as the first noble metal.

5. The magnetic memory device according to claim 1, wherein... The first ferromagnetic layer comprises at least one element selected from ruthenium, rhodium, palladium and silver as the first noble metal.

6. The magnetic memory device according to claim 1, wherein... The concentration of the first noble metal contained in the first ferromagnetic layer is less than 50 at%.

7. The magnetic memory device according to claim 1, wherein... The first ferromagnetic layer is connected to the dielectric layer.

8. The magnetic memory device according to claim 1, wherein The thickness of the first ferromagnetic layer is 0.5 nm or more and 3.0 nm or less.

9. The magnetic memory device according to claim 1, wherein... The thickness of the second ferromagnetic layer is 0.5 nm or more and 3.0 nm or less.

10. The magnetic memory device according to claim 1, wherein The saturation magnetization of the first ferromagnetic layer is greater than that of the second ferromagnetic layer.

11. The magnetic memory device according to claim 1, wherein The dielectric layer has a thickness of less than 2.0 nm.

12. The magnetic memory device according to claim 1, wherein... The fourth conductive layer contains at least one element selected from tantalum, tungsten, ruthenium, rhodium, palladium, silver, copper, osmium, iridium, platinum, gold, manganese, lead, and bismuth.

13. The magnetic memory device according to claim 1, wherein The fourth conductive layer is such that a portion of it protrudes in the second direction.

14. The magnetic memory device according to claim 1, wherein The dielectric constant of the dielectric layer is greater than or equal to the dielectric constant of the non-magnetic layer.

15. The magnetic memory device according to claim 14, wherein... The dielectric layer is non-magnetic.

16. The magnetic memory device of claim 14, wherein... The dielectric layer is ferromagnetic or ferrimagnetic.

17. The magnetic memory device according to claim 16, wherein The dielectric layer comprises at least one compound selected from Fe3O4, CoFe2O4, MnFe2O4, NiFe2O4, CuFe2O4 and MgFe2O4.

18. The magnetic memory device according to claim 1, wherein... It also includes a control circuit for controlling the write operation of the memory cell, and The fourth conductor layer includes: a first portion connected to the first conductor layer; a second portion connected to the second conductor layer; and a third portion located between the first portion and the second portion, connected to the magnetoresistive effect element, and connected to the third conductor layer via the magnetoresistive effect element. During the write operation, the control circuit... A first voltage is applied to the first conductor layer. A second voltage is applied to the second conductor layer. A third voltage is applied to the third conductor layer, the third voltage being higher than half the difference between the first voltage and the second voltage.

19. The magnetic memory device according to claim 18, wherein The first conductor layer is a word line. The second conductor layer is the first bit line. The third conductor layer is the second bit line.

20. The magnetic memory device of claim 18, wherein... The overall coercivity of the first and second ferromagnetic layers during the write operation is lower than that of the first and second ferromagnetic layers in the standby state.

21. The magnetic memory device according to claim 18, further comprising: The first switching element is connected to the magnetoresistive effect element and the third conductive layer; and The second switching element is connected to either the first portion or the second portion of the fourth conductive layer.

22. A magnetic memory device comprising: First conductor layer; Second conductive layer; Third conductor layer; A three-terminal memory cell is connected to the first conductive layer, the second conductive layer, and the third conductive layer; and The control circuit controls the write operation of the storage cell; The storage cell contains: A fourth conductor layer has a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion connected to the third conductor layer and located between the first portion and the second portion; and A magnetoresistive element is connected between the third conductive layer and the fourth conductive layer; The magnetoresistive effect element includes: The first ferromagnetic layer contains a first noble metal and is in contact with the fourth conductive layer; The second ferromagnetic layer is disposed on the side opposite to the fourth conductive layer, relative to the first ferromagnetic layer; and A dielectric layer is located between the first ferromagnetic layer and the second ferromagnetic layer; and During the write operation, the control circuit... A first voltage is applied to the first conductor layer. A second voltage is applied to the second conductor layer. A third voltage is applied to the third conductor layer, the third voltage being higher than half the difference between the first voltage and the second voltage.

23. The magnetic memory device according to claim 22, wherein... The second ferromagnetic layer contains a second noble metal, and The concentration of the first noble metal contained in the first ferromagnetic layer is higher than the concentration of the second noble metal contained in the second ferromagnetic layer.

24. The magnetic memory device according to claim 22, wherein... The first ferromagnetic layer comprises at least one element selected from osmium, iridium, platinum and gold as the first noble metal.

25. The magnetic memory device according to claim 22, wherein... The first ferromagnetic layer contains iridium as the first noble metal.

26. The magnetic memory device of claim 22, wherein... The first ferromagnetic layer comprises at least one element selected from ruthenium, rhodium, palladium and silver as the first noble metal.

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