Display substrate, manufacturing method thereof and display device

Abstract

The display substrate, the manufacturing method thereof and the display device of the present disclosure comprise a substrate, an alignment layer on the substrate, a first electrode between the substrate and the alignment layer and in contact with the alignment layer, and a pattern layer between the substrate and the alignment layer and in contact with the alignment layer, the orthographic projection of the pattern layer on the substrate and the orthographic projection of the first electrode on the substrate do not overlap each other, and the ratio of the contact angle of the pattern layer to the contact angle of the first electrode is greater than or equal to 7 / 12 and less than 3 / 2.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the substrate, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) have advantages such as light weight, low power consumption, high image quality, low radiation, and portability. They have gradually replaced traditional cathode ray tube displays (CRTs) and are widely used in modern information equipment, such as virtual reality (VR) headsets, laptops, televisions, mobile phones, and digital products. Summary of the Invention

[0003] This disclosure provides a display substrate, its manufacturing method, and a display device, the specific solutions of which are as follows:

[0004] On one hand, an embodiment of this disclosure provides a display substrate, comprising:

[0005] Substrate;

[0006] The alignment layer is located on the substrate.

[0007] The first electrode is located between the substrate and the alignment layer and is in contact with the alignment layer;

[0008] A patterned layer is located between the substrate and the alignment layer and is in contact with the alignment layer. The orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate. The ratio of the contact angle of the patterned layer to the contact angle of the first electrode is greater than or equal to 7 / 12 and less than 3 / 2.

[0009] In some embodiments, in the display substrate provided in the present disclosure, the pattern layer is disposed on the same layer and made of the same material as the first electrode.

[0010] In some embodiments, in the display substrate provided in the present disclosure, there are multiple first electrodes, and the multiple first electrodes are arranged in an array on the substrate.

[0011] The orthographic projection of the patterned layer on the substrate lies within the orthographic projection of the row spacing of each of the first electrodes on the substrate.

[0012] In some embodiments, in the display substrate provided in the present disclosure, the first electrode includes a first strip electrode and a second strip electrode integrally disposed therein. The extension direction of the first strip electrode intersects with the row direction, the column direction and the extension direction of the second strip electrode. The extension direction of the second strip electrode intersects with the row direction and the column direction.

[0013] The patterned layer extends along the extension direction of the first strip electrode and / or the extension direction of the second strip electrode.

[0014] In some embodiments, in the display substrate provided in the present disclosure, the extension directions of the pattern layer at the gaps between two adjacent rows are different.

[0015] In some embodiments, in the display substrate provided in the present disclosure, the linewidth of the pattern layer is the same as the linewidth of the first strip electrode or the second strip electrode that extends in the same direction, and the line spacing of the pattern layer is the same as the line spacing of the first strip electrode or the second strip electrode that extends in the same direction.

[0016] In some embodiments, in the display substrate provided in the present disclosure, the pattern layer includes a plurality of block patterns spaced apart at the same row gap of each of the first electrodes, and the block patterns extend along the row direction.

[0017] In some embodiments, the display substrate provided in the present disclosure further includes a first signal line, wherein the orthographic projection of the first signal line on the substrate is located within the orthographic projection of the column gap of each of the first electrodes on the substrate.

[0018] The orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

[0019] In some embodiments, the display substrate provided in this disclosure further includes a transistor, and at least a portion of the first signal line is electrically connected to the transistor;

[0020] The orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the transistor on the substrate.

[0021] In some embodiments, in the display substrate provided in the present disclosure, the pattern layer includes a strip pattern extending in the row direction at the row gap of each of the first electrodes, the length of the strip pattern in the row direction being the same as the length of the row gap of each of the first electrodes.

[0022] In some embodiments, the display substrate provided in the present disclosure further includes a second signal line, wherein the orthographic projection of the second signal line on the substrate is located within the orthographic projection of the row spacing of each of the first electrodes on the substrate.

[0023] The orthographic projection of the patterned layer on the substrate lies within the orthographic projection of the second signal line on the substrate.

[0024] In some embodiments, in the display substrate provided in the present disclosure, the ratio of the width of the pattern layer in the column direction to the width of the second signal line in the column direction is greater than or equal to 3 / 5 and less than or equal to 1.

[0025] In some embodiments, the display substrate provided in the present disclosure further includes a second signal line. The orthographic projection of the second signal line on the substrate is located within the orthographic projection of the row gap of each of the first electrodes on the substrate. Two second signal lines are correspondingly provided at the same row gap of each of the first electrodes.

[0026] At the same row gap between each of the first electrodes, the orthographic projection of the two second signal lines on the substrate lies within the orthographic projection of the patterned layer on the substrate.

[0027] In some embodiments, the display substrate provided in the present disclosure further includes a first signal line and a second signal line that are intersected and insulated from each other. The orthographic projection of the first signal line on the substrate is located within the orthographic projection of the column gap of each first electrode on the substrate. The first signal line includes an island-shaped structure at the intersection of the column gap of each first electrode and the gap between the two second signal lines.

[0028] The orthographic projection of the patterned layer on the substrate coincides with the orthographic projection of the island structure on the substrate.

[0029] In some embodiments, the display substrate provided in the present disclosure further includes a second signal line and a gate, wherein the second signal line and the gate are integrally formed and the gate protrudes relative to the second signal line;

[0030] The pattern layer includes a plurality of first portions that are intersected with both the row and column directions, and a second portion that extends along the row direction. The orthographic projection of the first portion on the substrate is located within the orthographic projection of the gate on the substrate, and the orthographic projection of the second portion on the substrate is located within the orthographic projection of the second signal line on the substrate.

[0031] In some embodiments, the display substrate provided in this disclosure further includes a second electrode located between the layer containing the first electrode and the substrate, wherein the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate overlap each other.

[0032] In some embodiments, the display substrate provided in this disclosure further includes an insulating layer located between the layer containing the first electrode and the layer containing the second electrode. The first electrode partially blocks the insulating layer, and the portion of the insulating layer not blocked by the first electrode is reused as the pattern layer.

[0033] In some embodiments, in the display substrate provided in the present disclosure, the alignment layer includes a stationing area for setting spacers, and the orthographic projection of the stationing area on the substrate is located within the orthographic projection of the pattern layer on the substrate.

[0034] On the other hand, this disclosure provides a method for manufacturing the above-mentioned display substrate, including:

[0035] Provide a substrate;

[0036] A patterned layer and a first electrode are formed on the substrate, wherein the orthographic projection of the patterned layer on the substrate and the orthographic projection of the first electrode on the substrate do not overlap, and the ratio of the contact angle of the patterned layer to the contact angle of the first electrode is greater than or equal to 7 / 12 and less than or equal to 3 / 2.

[0037] An alignment liquid is applied to the patterned layer and the layer containing the first electrode.

[0038] The alignment liquid is cured to form an alignment layer.

[0039] In some embodiments, the fabrication method provided in the present disclosure, wherein forming a pattern layer and a first electrode on the substrate, specifically includes:

[0040] Using the same photomask, a patterned layer and a first electrode of the same material are formed on the substrate.

[0041] In some embodiments, in the fabrication method provided in the present disclosure, the same mask is used to form a patterned layer and a first electrode of the same material on the substrate, specifically including:

[0042] A conductive layer and a photoresist layer are sequentially formed on the substrate.

[0043] A photomask is provided, the photomask having only a pattern for fabricating the first electrode;

[0044] The pattern of the mask is offset relative to the area where the first electrode is to be fabricated, such that the pattern of the mask overlaps with both the area where the first electrode is to be fabricated and the area where the pattern layer is to be fabricated.

[0045] Under the cover of the photomask, the photoresist layer in the area where the first electrode is to be formed and the photoresist layer in the area where the pattern layer is to be formed are exposed in a time-division manner.

[0046] The photoresist layer is developed to retain the photoresist layer in the area where the first electrode is to be fabricated and the photoresist layer in the area where the pattern layer is to be fabricated.

[0047] Under the cover of the photoresist layer, the conductive layer is etched to form the patterned layer and the first electrode, which are of the same layer and material but disconnected.

[0048] In some embodiments, in the fabrication method provided in the present disclosure, the same mask is used to form a patterned layer and a first electrode of the same material on the substrate, specifically including:

[0049] A conductive layer and a photoresist layer are sequentially formed on the substrate.

[0050] A photomask is provided having a first pattern for fabricating a first electrode and a second pattern for fabricating a patterned layer, wherein the first pattern and the second pattern are disconnected.

[0051] Under the cover of the photomask, the photoresist layer in the area where the first electrode is to be formed and the photoresist layer in the area where the pattern layer is to be formed are exposed simultaneously.

[0052] The photoresist layer is developed to retain the photoresist layer in the area where the first electrode is to be fabricated and the photoresist layer in the area where the pattern layer is to be fabricated.

[0053] Under the cover of the photoresist layer, the conductive layer is etched to form the patterned layer and the first electrode, which are of the same layer and material but disconnected.

[0054] In some embodiments, the fabrication method provided in the present disclosure, wherein forming a pattern layer and the first electrode on the substrate, specifically includes:

[0055] An insulating layer is formed by using ammonia and silane as the reaction source gases, with the flow ratio of ammonia to silane being greater than or equal to 2 and less than or equal to 8.

[0056] A first electrode is formed on the insulating layer of the pixel opening region contained in the substrate, and the insulating layer outside the pixel opening region is reused as a pattern layer.

[0057] On the other hand, this disclosure provides a display device including the display substrate described above. Attached Figure Description

[0058] Figure 1 This is a schematic diagram illustrating the breakage and aggregation of the wet film formed by the alignment liquid in related technologies;

[0059] Figure 2 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0060] Figure 3 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0061] Figure 4 This is a schematic diagram showing the accumulation of a wet film formed by the alignment liquid due to the overlap between the first electrode and the patterned layer.

[0062] Figure 5 A flowchart for testing the contact angle provided in an embodiment of this disclosure;

[0063] Figure 6 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0064] Figure 7 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0065] Figure 8 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0066] Figure 9 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0067] Figure 10 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0068] Figure 11 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0069] Figure 12 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0070] Figure 13 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0071] Figure 14This is a schematic diagram of a transistor structure in a display substrate provided in an embodiment of the present disclosure;

[0072] Figure 15 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0073] Figure 16 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0074] Figure 17 This is a schematic diagram illustrating the uneven cell thickness caused by alignment layer aggregation.

[0075] Figure 18 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0076] Figure 19 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0077] Figure 20 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0078] Figure 21 This is a schematic diagram of a pixel structure of a display substrate provided in an embodiment of the present disclosure;

[0079] Figure 22 for Figure 21 A schematic diagram of the structure of the second signal line and the gate of the transistor;

[0080] Figure 23 for Figure 21 A schematic diagram of the structure of the third signal line and the second electrode;

[0081] Figure 24 for Figure 21 A schematic diagram of the structure of the first signal line, the first and second terminals of the transistor, the connecting electrode, and the limiting structure;

[0082] Figure 25 for Figure 21 A schematic diagram of the structure of the first electrode, the first transition electrode, and the patterned layer;

[0083] Figure 26 This is a schematic diagram of a structure in which the connecting electrode is connected to the second electrode via a first adapter electrode.

[0084] Figure 27 A schematic diagram of yet another pixel structure of a display substrate provided in an embodiment of this disclosure;

[0085] Figure 28 for Figure 27 A schematic diagram of the stacking of the first and second electrodes;

[0086] Figure 29 for Figure 27 A schematic diagram of the structure of the first electrode in the middle;

[0087] Figure 30 for Figure 27 A schematic diagram of the structure of the second signal line, the gate of the transistor, and the third signal line;

[0088] Figure 31 for Figure 27 A schematic diagram of the structure of the first signal line, the first electrode, and the second electrode of the transistor;

[0089] Figure 32 for Figure 27 A schematic diagram of the structure of the second electrode, the second transfer electrode, and the patterned layer;

[0090] Figure 33 A schematic diagram of yet another pixel structure of a display substrate provided in an embodiment of this disclosure;

[0091] Figure 34 for Figure 33 A schematic diagram of the structure of the second signal line and the gate of the transistor;

[0092] Figure 35 for Figure 33 A schematic diagram of the structure of the first signal line, the first electrode, and the second electrode of the transistor;

[0093] Figure 36 for Figure 33 Schematic diagram of the structure of the first electrode and the patterned layer;

[0094] Figure 37 This is a flowchart illustrating the manufacturing process of a display substrate provided in an embodiment of this disclosure. Detailed Implementation

[0095] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0096] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0097] During product development, this disclosure discovered that the liquid crystal display device repeatedly exhibited clumped stains at the L127 grayscale, affecting the display effect. After disassembling and analyzing the screen, it was found that alignment layer (PI) aggregation occurred in the clumped stain areas, and the more severe the clumped stains, the higher the alignment layer accumulation.

[0098] The fabrication process of the alignment layer mainly includes two steps: First, using an inkjet coating device, alignment droplets are spread onto the surface of the display substrate to form a wet film 102'; second, in a pre-curing device, heating is used to evaporate the solvent from the wet film 102', thus forming the alignment layer. In both processes, the contact angle of the display substrate plays a decisive role. Generally, it is believed that the smaller the interfacial tension between the solid and the liquid, the smaller the contact angle, the better the wettability of the liquid on the solid, and the less likely the liquid and solid are to separate; conversely, the greater the interfacial tension between the solid and the liquid, the larger the contact angle, the worse the wettability of the liquid on the solid, and the easier the liquid and solid are to separate.

[0099] Further research revealed that the film layers beneath the alignment layer, in contact with it, include a first electrode located in the pixel aperture region and an insulating layer located in the non-pixel aperture region, such as the insulating layer corresponding to the grid lines of the display panel. The contact angle of the first electrode is 60°, while the contact angle of the insulating layer is 20°–30°. It can be seen that the contact angle of the insulating layer is 1 / 3 to 1 / 2 of the contact angle of the first electrode. This significant difference in contact angles results in a much greater interfacial tension between the alignment liquid and the first electrode than between the alignment liquid and the insulating layer. Therefore, the first electrode and the insulating layer exert a "pulling effect" on the alignment liquid, causing the wet film 102' formed by the alignment liquid to break and aggregate. Figure 1 As shown. Furthermore, although a smaller contact angle is beneficial for the wetting and diffusion of the alignment liquid, the solvent evaporation rate is inconsistent during the pre-curing process. The alignment liquid is not easy to transfer at interfaces with good wettability, and is prone to breakage, shrinkage and accumulation. Therefore, the alignment layer has poor accumulation on the insulating layer with a smaller contact angle.

[0100] Based on this, in order to improve the aforementioned technical problems existing in related technologies, this disclosure provides a display substrate, such as... Figure 2 and Figure 3 As shown, it includes:

[0101] Substrate 101;

[0102] The alignment layer 102 is located on the substrate 101;

[0103] The first electrode 103 is located between the substrate 101 and the alignment layer 102 and is in contact with the alignment layer 102.

[0104] The pattern layer 104 is located between the substrate 101 and the alignment layer 102 and is in contact with the alignment layer 102. The orthographic projection of the pattern layer 104 on the substrate 101 does not overlap with the orthographic projection of the first electrode 103 on the substrate 101. The ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 is greater than or equal to 7 / 12 and less than 3 / 2.

[0105] In the display substrate provided in the embodiments of this disclosure, the staggered pattern layer 104 and the first electrode 103 are both in contact with the alignment layer 102, which is equivalent to the alignment liquid being coated on the surfaces of the pattern layer 104 and the first electrode 103. This disclosure sets the ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 to be greater than or equal to 7 / 12 and less than 3 / 2. For example, the contact angle of the first electrode 103 is 60°, and the contact angle of the pattern layer 104 is greater than or equal to 35° and less than 90°. This makes the difference between the contact angles of the pattern layer 104 and the first electrode 103 smaller. Correspondingly, the difference between the interfacial tension between the alignment liquid and the first electrode 103 and the interfacial tension between the alignment liquid and the pattern layer 104 is smaller, thereby effectively weakening the "pulling effect" of the first electrode 103 and the pattern layer 104 on the alignment liquid, reducing the risk of breakage and aggregation of the wet film 102' formed by the diffusion of the alignment liquid. Furthermore, the contact angle of the untreated insulating layer is greater than or equal to 1 / 3 and less than or equal to 1 / 2 of the contact angle of the first electrode 103. In this disclosure, the contact angle of the pattern layer 104 is greater than or equal to 7 / 12 and less than 3 / 2 of the contact angle of the first electrode 103. Therefore, the contact angle of the pattern layer 104 in this disclosure is greater than that of the untreated insulating layer. Since a larger contact angle indicates poorer wettability, the wettability of the alignment liquid on the pattern layer 104 is slightly worse than that on the untreated insulating layer. Combined with the aforementioned statement that "the alignment liquid is not easily transferred at interfaces with good wettability, and is prone to breakage, shrinkage, and accumulation," it can be concluded that the alignment liquid is more easily transferred on the pattern layer 104, which has slightly poorer wettability, and is less prone to breakage, shrinkage, and accumulation. Based on these two reasons, this disclosure can significantly improve the aggregation phenomenon of the alignment layer 102 and enhance the display effect.

[0106] In addition, such as Figure 4 As shown, if the first electrode 103 overlaps with the pattern layer 104, on the one hand, the alignment layer 102 at the overlap position N will accumulate higher; on the other hand, the pattern layer 104 may change the interface resistance of the first electrode 103 at the first via V1, affecting signal transmission and display quality. In this disclosure, the orthographic projection of the pattern layer 104 on the substrate 101 and the orthographic projection of the first electrode 103 on the substrate 101 are not overlapped, so that the pattern layer 104 and the first electrode 103 are disconnected, avoiding the pattern layer 104 and the first electrode 103 from overlapping. Therefore, the pattern layer 104 will not affect signal transmission and display quality, and at the same time, it avoids the alignment layer 102 from accumulating at the overlap position N.

[0107] In some embodiments, it can be achieved through Figure 5 The method shown is to test the contact angle. The specific process is as follows: a hydrophilic droplet l (e.g., deionized water) of a preset volume (e.g., 1 μL) is dropped onto the pattern layer 104 or the first electrode 103. The droplet l begins to expand on the pattern layer 104 or the first electrode 103. After waiting until the droplet l stops expanding, the droplet l and the pattern layer 104 or the first electrode 103 are photographed, and the angle θ between the droplet-air interface (lg) and the droplet-solid interface (ls) in the photographed image is measured. This angle θ is the contact angle of the pattern layer 104 or the first electrode 103.

[0108] Regarding the adhesion of the alignment layer 102 to the first electrode 103 and the unimproved insulating layer, this disclosure presents an adhesion measurement experiment of the alignment layer 102 on the first electrode 103 and the insulating layer. Specifically, the alignment layer 102 was rubbed with an eraser using the same force, and then the residue of the alignment layer 102 was observed under a microscope. The results showed that after rubbing, the alignment layer 102 remaining on the first electrode 103 was more intact than the alignment layer 102 remaining on the insulating layer, indicating a tighter bond between the alignment layer 102 and the first electrode 103. Furthermore, this disclosure found that the surface roughness of the first electrode 103 is small, and no aggregation of the alignment layer 102 occurred on the first electrode 103. Therefore, as... Figure 3 As shown, in the above-mentioned display substrate provided in the embodiments of this disclosure, the pattern layer 104 and the first electrode 103 can be disposed in the same layer and with the same material. This not only allows the alignment layer 102 to be tightly bonded to the pattern layer 104, but also ensures that the alignment layer 102 does not aggregate on the pattern layer 104.

[0109] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 6 to 8As shown, there are multiple first electrodes 103, which are arranged in an array on the substrate 101. The orthographic projection of the pattern layer 104 on the substrate 101 lies within the orthographic projection of the row spacing of each first electrode 103 onto the substrate 101. Typically, a black matrix (BM) is provided on the opposing substrate opposite the display substrate to block the row spacing of each first electrode 103. In this disclosure, where the orthographic projection of the pattern layer 104 on the substrate 101 lies within the orthographic projection of the row spacing of each first electrode 103 onto the substrate 101, the pattern layer 104 is blocked by the black matrix, preventing light leakage. Furthermore, since the area containing the black matrix does not display an image, the pattern layer 104 does not affect the display effect.

[0110] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 2 , Figures 6 to 8 As shown, the first electrode 103 includes an integrally formed first strip electrode 31 and a second strip electrode 32. The extension direction D1 of the first strip electrode 31 intersects the row direction X, the column direction Y, and the extension direction D2 of the second strip electrode 32. The extension direction D2 of the second strip electrode 32 intersects the row direction X and the column direction Y. The pattern layer 104 extends along the extension direction D1 of the first strip electrode 31 and / or the extension direction D2 of the second strip electrode 32, for example, in... Figure 6 In each row gap of the first electrode 103, the pattern layer 104 extends along the extending direction D1 of the first strip electrode 31. Figure 7 The pattern layer 104 at each row gap of the first electrode 103 extends along the extension direction D2 of the second strip electrode 32. Figure 8 The extension directions of the pattern layer 104 at the adjacent row gaps of each first electrode 103 are different; that is, the extension directions of the pattern layer 104 at the adjacent row gaps are the same as the extension direction D1 of the first strip electrode 31 and the extension direction D2 of the second strip electrode 32, respectively. This allows the morphology of the pattern layer 104 to be similar to the local morphology of the first electrode 103, which is beneficial for forming a uniform alignment layer 104 on the first electrode 103 and the pattern layer 104. It should be noted that... Figure 6 The first strip electrode 31 and the second strip electrode 32 shown in the diagram can be referenced. Figure 21 and Figure 25 Specifically, in Figure 21 and Figure 25 The middle part is a strip electrode formed by opening a slit in a plate-shaped electrode; or Figure 6 The first strip electrode 31 and the second strip electrode 32 shown in the diagram can also be referenced. Figure 27 , Figure 32 , Figure 33 and Figure 36 , specifically, Figure 27 , Figure 32 , Figure 33 and Figure 36 The middle part consists of strip electrodes that directly form multiple electrical connections, among which, Figure 27 and Figure 32 The strip electrode shown is a dual-domain electrode and the included angle between the domain-directed electrodes is an obtuse angle. In some embodiments, the included angle between the domain-directed electrodes can also be an acute angle. Figure 33 and Figure 36 The strip electrode shown is a single-domain electrode.

[0111] In some embodiments, the pattern layer 104 can be fabricated using a mask for fabricating the first electrode 103, as described in related technologies. For example, it can be fabricated along... Figure 6 The mask for fabricating the first electrode 103 is moved along direction A to the gap between the rows of the first electrodes 103. By controlling the light source to illuminate only the local mask corresponding to the gap between the rows of the first electrodes 103, or by blocking the mask corresponding to the first electrode 103 while the light source illuminates the entire mask, only the gaps between the rows of the first electrodes 103 are exposed and developed, thereby creating a pattern layer 104 at the gap between the rows of the first electrodes 103 with an extension direction D1 that is the same as the extension direction D1 of the first strip electrode 31. Similarly, along... Figure 7 When the mask for fabricating the first electrode 103 is moved along the A' direction to the inter-row gap of each first electrode 103, a pattern layer 104 with an extension direction D2 of the second strip electrode 32 can be fabricated at the inter-row gap of each first electrode 103. Additionally, along... Figure 8 The mask for the first electrode 103 is moved along direction A to the gap between the rows of the first electrodes 103. By controlling the light source to only illuminate the partial mask corresponding to the odd-numbered row gaps of the first electrodes 103, or by blocking the mask corresponding to the first electrode 103 and the partial mask corresponding to the even-numbered row gaps while the light source illuminates the entire mask, exposure and development are performed only on the odd-numbered row gaps. This creates a pattern layer 104 at the odd-numbered row gaps, with its extension direction being the same as the extension direction D1 of the first strip electrode 31. It can also be used along... Figure 8 The mask for the first electrode 103 is moved in the A' direction to the gap between the rows of the first electrode 103. By controlling the light source to only illuminate the local mask corresponding to the even-numbered row gap of the first electrode 103, or by blocking the mask corresponding to the first electrode 103 and the local mask corresponding to the odd-numbered row gap while the light source illuminates the entire mask, exposure and development are performed only on the even-numbered row gap. This creates a pattern layer 104 at the even-numbered row gap with an extension direction that is the same as the extension direction D2 of the second strip electrode 32. This allows the extension directions of the pattern layer 104 at two adjacent row gaps to be different.

[0112] When the pattern layer 104 is fabricated using the mask of the first electrode 103, it is possible to avoid providing an additional mask for fabricating the pattern layer 104, thus saving costs. Furthermore, as... Figures 6 to 8 As shown, the linewidth of the patterned layer 104 is the same as the linewidth of the first strip electrode 31 or the second strip electrode 32 with the same extension direction, and the line spacing of the patterned layer 104 is the same as the line spacing of the first strip electrode 31 or the second strip electrode 32 with the same extension direction. That is, the morphology of the patterned layer 104 is the same as the local morphology of the first electrode 103, which is more conducive to forming a uniform alignment layer 102 on the first electrode 103 and the patterned layer 104.

[0113] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 9 As shown, the pattern layer 104 includes multiple block patterns 41 spaced apart at the same row gap of each of the first electrodes 103, and the block patterns 41 extend along the row direction X. The structure of the pattern layer 104 composed of block patterns 41 is relatively simple, and the corresponding manufacturing difficulty is relatively low.

[0114] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 2 , Figures 6 to 9 As shown, it may also include a first signal line 105. Optionally, the first signal line 105 is located between the substrate 101 and the layer containing the first electrode 103, and is insulated from the first electrode 103 by an insulating layer 106. The first signal line 105 may be entirely a data line V. data It may also include a data cable V. data and common electrode line V com This may also include touch signal lines, etc., and is not limited here. The orthographic projection of the first signal line 105 on the substrate 101 lies within the orthographic projection of the column gaps of each first electrode 103 on the substrate 101; the orthographic projection of the pattern layer 104 on the substrate 101 does not overlap with the orthographic projection of the first signal line 105 on the substrate 101. Since the material of the first electrode 103 is a conductive material, the pattern layer 104, which is made of the same layer and material as the first electrode 103, is also conductive. If the pattern layer 104 and the first signal line 105 overlap, a parasitic capacitance will be formed between them, causing the pattern layer 104 to interfere with the signal of the first signal line 105. Therefore, in order to avoid the pattern layer 104 interfering with the signal of the first signal line 105, this disclosure sets the orthographic projection of the pattern layer 104 on the substrate 101 to not overlap with the orthographic projection of the first signal line 105 on the substrate 101.

[0115] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 10 and Figure 11As shown, it may also include a transistor 107, with at least a portion of the first signal line 105 electrically connected to the transistor 107. Optionally, all of the first signal line 105 may be a data line V. data In this case, the first signal line 105 is electrically connected to the transistor 107; the first signal line 105 includes a data line V. data and common electrode line V com In this case, the data line V in the first signal line 105 data It is electrically connected to transistor 107. In some embodiments, the data line V can be formed via a single patterning process. data The first terminal of the transistor 107, which is electrically connected to the pattern layer 104, can optionally be the source or the drain. Optionally, in order to avoid the pattern layer 104 and the first signal line 105 overlapping to form parasitic capacitance and affect the stability of the transistor 107, the orthographic projection of the pattern layer 104 on the substrate 101 and the orthographic projection of the transistor 107 on the substrate 101 can be configured not to overlap.

[0116] It should be understood that, because there is an insulating layer 106 between the layer containing the first signal line 105 and the layer containing the pattern layer 104, they will not be short-circuited. Based on this, in some embodiments, such as... Figure 1 and Figure 12 As shown, the orthographic projections of the pattern layer 104 onto the substrate 101 and the orthographic projections of the transistors 107 onto the substrate 101 can also overlap; in other embodiments, such as Figure 13 As shown, the pattern layer 104 includes a strip pattern 42 extending along the row direction X at the row gap. The length of the strip pattern 42 in the row direction X is the same as the length of the row gap. At this time, the orthographic projection of the pattern layer 104 on the substrate 101 and the orthographic projection of the first signal line 105 on the substrate 101 can overlap with each other. Figure 13 In the case shown, the pattern layer 104 is composed of multiple strip structures 42 extending at the row gaps. The structure is simpler and the manufacturing difficulty is lower. Optionally, the length of the strip pattern 42 in the row direction X is not the same as the length of the row gap. For example, the extension direction of the strip pattern 42 in the row direction X is the same as the extension direction of the grid line. The specific length and width are not limited.

[0117] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 10 and Figure 11 As shown, it may also include a second signal line 108. Optionally, the second signal line 108 may be a gate line V integrally formed with the gate 71 of the transistor 107. gFurthermore, the second signal line 108 is located between the layer containing the first signal line 105 and the substrate 101. In this disclosure, the orthographic projection of the second signal line 108 onto the substrate 101 can be located within the orthographic projection of the row spacing of each first electrode 103 onto the substrate 101. Simultaneously, the orthographic projection of the pattern layer 104 onto the substrate 101 can be located within the orthographic projection of the second signal line 108 onto the substrate 101. Since this disclosure discovers that the aggregation region of the alignment layer 102 is located within the region containing the second signal line 108, this disclosure provides a pattern layer 104 within the region containing the second signal line 108 to help prevent the aggregation of the alignment layer 102.

[0118] Furthermore, this disclosure reveals that when the aggregation width of the alignment layer 102 on the second signal line 108 is 60% or more of the linewidth of the second signal line 108, macroscopic defects may occur. Therefore, to avoid these defects, in the display substrate provided in the embodiments of this disclosure, the ratio of the width of the pattern layer 104 in the column direction Y to the width of the second signal line 108 in the column direction Y can be greater than or equal to 3 / 5 and less than or equal to 1.

[0119] In some embodiments, such as Figure 10 and Figure 11 As shown, the gate line V g The portion can be reused as the gate 71 of transistor 107; or, as... Figure 14 , Figure 27 , Figure 30 , Figure 33 and Figure 34 As shown, gate 71 can also be relative to gate line V. g Protruding settings. See also Figure 13 To prevent the alignment layer 102 from being used on the second signal line 108 (i.e., gate line V), g The positions of the gate 71 and the gate 71 are aligned, and the pattern layer 104 can be configured including a plurality of first portions 43 that are intersected by both the row direction X and the column direction Y, and a second portion 44 extending along the row direction X. The orthographic projection of the first portion 43 on the substrate 101 lies within the orthographic projection of the gate 71 on the substrate 101, and the orthographic projection of the second portion 44 on the substrate 101 lies within the orthographic projection of the second signal line 108 on the substrate 101. It can be seen that... Figure 13 The first portion 43 shown is a diagonal strip structure, that is, it can be a strip electrode with the same width and direction of extension as the pixel electrode domain. The second portion 44 is a block structure. Of course, in some embodiments, the first portion 43 and the second portion 44 can be both block structures or diagonal strip structures. Alternatively, the first portion 43 can be a block structure and the second portion 44 can be a diagonal strip structure. That is, the structure of the first portion 43 and the structure of the second portion 44 can be the same or different. No specific limitation is made here.

[0120] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 15 As shown, two second signal lines 108 are provided at the same row gap of each first electrode 103. At the same row gap of each first electrode 103, the orthographic projection of the two second signal lines 108 on the substrate 101 is located within the orthographic projection of the pattern layer 104 on the substrate 101, so as to prevent the alignment layer 102 from accumulating in the area where the second signal lines 108 are located by the pattern layer 104.

[0121] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 16 As shown, the first signal line 105 includes an island structure 51 located at the intersection of the column gaps of each first electrode 103 and the gaps of the two second signal lines 108; the orthographic projection of the pattern layer 104 on the substrate 101 coincides with the orthographic projection of the island structure 51 on the substrate 101. It should be noted that in the embodiments provided in this disclosure, due to limitations in process conditions or the influence of other factors such as measurement, the "coincidence" may be exactly the same, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the "coincidence" relationship between related features meets the allowable error, it falls within the protection scope of this disclosure. It should be noted that the orthographic projection of the pattern layer 104 on the substrate 101 being within or partially exceeding the orthographic projection of the island structure 51 on the substrate 101 is also within the protection scope of this disclosure. Furthermore, in Figure 15 When the pattern layer 104 simultaneously covers two second signal lines 108 at the same row gap, because the island structure 51 is located at the intersection of the column gap of each first electrode 103 and the gap of the two second signal lines 108, Figure 15 The pattern layer 104 also covers the island structure 51, that is, the pattern layer 104 is provided on both the second signal line 108 and the island structure 51.

[0122] Typically, a spacer PS is provided on the opposing substrate, which is positioned opposite the display substrate, to maintain a stable cell thickness (Gap) between the display substrate and the opposing substrate. The spacer PS is in contact with the alignment layer 102 at the location of the island structure 51. For example... Figure 17As shown, if the alignment layer 102 accumulates at the location of the island structure 51, the spacer PS will press against the accumulated alignment layer 102, which will cause the cell thickness at the location of the island structure 51 to increase, resulting in a display unevenness (Mura) problem caused by uneven cell thickness. In this disclosure, a patterned layer 104 is provided at the position of the island structure 51 to prevent the alignment layer 102 from agglomerating. This ensures that at the position of the island structure 51, the spacer PS contacts the alignment layer 102 with uniform film thickness. Therefore, the abnormal phenomenon of increased cell thickness will not occur, thus effectively solving the problem of uneven display. Optionally, for the liquid crystal display panel, which includes a color filter substrate (such as the aforementioned opposing substrate) and an array substrate (such as the aforementioned display substrate) and liquid crystal disposed between the color filter substrate and the array substrate, the spacer PS can be disposed on one side of the color filter substrate, with the other end of the spacer PS facing the island structure 51 of the array substrate. Alternatively, the spacer PS can be disposed on one side of the array substrate, i.e., directly disposed at the position corresponding to the island structure 51. Here, the island structure 51 can be directly fabricated with the same layer and material as the data cable. When the spacer PS is positioned on top of the island structure 51, the compressive strength of the liquid crystal display panel can be increased.

[0123] It should be noted that the position of the spacer PS in this disclosure is not limited to corresponding to the position of the island structure 51. In some embodiments, such as Figure 18 As shown, the spacer PS can also be positioned in the area where the second signal line 108 is located. That is, after the display substrate and the opposing substrate are aligned, the spacer PS contacts the alignment layer PI in the area where the second signal line 108 is located. However, since the uppermost film layer of the display substrate is the alignment layer PI, regardless of the specific position of the spacer PS, the spacer PS is in contact with the alignment layer 102. That is, the alignment layer 102 includes a stationing area for setting the spacer PS. In order to prevent the local cell thickness increase caused by the aggregation of the alignment layer 102, the orthographic projection of the stationing area of ​​the spacer PS on the substrate 101 can be set within the orthographic projection of the pattern layer 104 on the substrate 101.

[0124] See also Figure 16 In the first signal line 105, the data line V data In this case, at one row gap of each first electrode 103, an island-shaped structure 51 can be electrically connected to the first electrode of two transistors 107 respectively, and the gate of one transistor 107 is electrically connected to a second signal line 108, the gate of the other transistor 107 is electrically connected to another second signal line 108, the second electrode of one transistor 107 is electrically connected to the first electrode 103 of the odd-numbered column on one side of the row gap, and the second electrode of the other transistor 107 is electrically connected to the first electrode 103 of the even-numbered column on the other side of the row gap. In this way, a data line V can be used to transmit signals. data Signals are applied to the two columns of first electrodes 103, thereby saving data lines V.data The quantity and wiring space saved. Optionally, the saved wiring space can be used to install the common electrode line V. com The common electrode line V com It can be electrically connected to the second electrode 109, thereby reducing the overall resistance of the second electrode 109 and improving the voltage uniformity and stability on the second electrode 109.

[0125] In some embodiments, such as Figure 16 As shown, the second electrode 109 can be located between the layer containing the first electrode 103 and the substrate 101, and the orthographic projection of the first electrode 103 on the substrate 101 and the orthographic projection of the second electrode 109 on the substrate 101 overlap each other, so that an electric field for driving liquid crystal deflection can be formed between the first electrode 103 and the second electrode 109. Optionally, the second electrode 109 can be disposed in the same layer as the gate 71 of the transistor 107. However, in order to ensure transmittance, the second electrode 109 is made of transparent conductive materials such as indium tin oxide (ITO), indium tin oxide (IZO), and zinc oxide (ZnO). In order to make the resistance of the gate 71 low, the gate 71 can be made of metal materials, alloy materials, etc. Optionally, the material of the gate 71 can include molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), etc. The gate 71 can be a single-layer metal structure or a multi-layer metal structure. For example, the multi-layer metal structure can be composed of stacked titanium metal layers / aluminum metal layers / titanium metal layers. In addition, to meet the transmittance requirements, the first electrode 103 can also be made of transparent conductive materials such as indium tin oxide (ITO), indium tin oxide (IZO), and zinc oxide (ZnO). When the first electrode 103 is a slit electrode composed of a first strip electrode 31 and a second strip electrode 32, the transmittance can be further improved through the slit.

[0126] It is worth noting that, such as Figure 21 , Figure 23 , Figure 25 , Figure 33 and Figure 36 As shown, the first electrode 103 can be a pixel electrode, and the second electrode 109 is a common electrode. In some embodiments, such as... Figures 27 to 29 , Figure 32 As shown, the first electrode 103 can also be set as a common electrode and the second electrode 109 as a pixel electrode, i.e. Figure 21 , Figure 23 , Figure 25 , Figure 33 and Figure 36 As shown, the pixel electrode can be a strip electrode formed by a slit design, and the common electrode can be a plate electrode; or, as... Figures 27 to 29 , Figure 32As shown, the common electrode can be a strip electrode with a slit design, and the pixel electrode can be a plate electrode; no specific limitation is made here. Furthermore, this disclosure shows that both the first electrode 103 and the second electrode 109 are located on the display substrate; however, in some embodiments, the first electrode 103 and the second electrode 109 can also be disposed on the display substrate and the opposing substrate respectively; no specific limitation is made here.

[0127] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 19 and Figure 20 As shown, the insulating layer 106 can be located between the layer containing the first electrode 103 and the layer containing the second electrode 109. The first electrode 103 partially obscures the insulating layer 106, and the portion of the insulating layer 106 not obscured by the first electrode 103 is reused as the pattern layer 104. Therefore, it is unnecessary to fabricate an additional pattern layer 104. In other words, this invention allows for the adjustment of the insulating layer without setting a pattern of the same material as the first electrode 103. In this case, the film quality of the insulating layer 106 can be optimized to make it denser, with reduced roughness and increased contact angle, thus enabling its reuse as the pattern layer 104. Specifically, the film quality of the insulating layer 106 can be changed by adjusting the ratio of the reaction source gases used to fabricate the insulating layer 106. In some embodiments, ammonia (NH3) and silane (SiH4) can be used as the reaction source gases, and when the flow ratio of ammonia to silane is greater than or equal to 2 and less than or equal to 8, the contact angle of the produced insulating layer 106 can satisfy greater than or equal to 35° and less than 90°, for example, the contact angle of the insulating layer 106 is 37.5°, 52°, 58.7°, etc.

[0128] It should be noted that in this disclosure, not only can the patterned layer 104 be fabricated solely using the material of the first electrode 103, or the insulating layer 106 be reused as the patterned layer 104 solely by adjusting the film quality of the insulating layer 106; these two methods can also be combined, that is, in addition to using the insulating layer 106 as the patterned layer 104, the patterned layer 104 can also be fabricated using the material of the first electrode 103. Furthermore, it should be understood that when the morphology of the patterned layer 104 fabricated using the material of the first electrode 103 is the same as the local morphology of the first electrode 103, the inclined strip structure of the patterned layer 104 and the insulating layer 106 at the gaps in the inclined strip structure can be used simultaneously to prevent the alignment layer 102 from agglomerating.

[0129] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 21 to 25As shown, at the intersection of the first signal line 105 and the second signal line 108, the line width of both the first signal line 105 and the second signal line 108 is reduced. This reduces the area of ​​the first signal line 105 and the second signal line 108 facing each other, thereby ensuring that the parasitic capacitance between the first signal line 105 and the second signal line 108 is small, or that the width of one of the first signal line 105 and the second signal line 108 is reduced.

[0130] See also Figures 21 to 25 Two adjacent second electrodes 109 in the same column are electrically connected through a connecting electrode 110, so as to improve the voltage uniformity and stability of the second electrodes 109 in the same column, and to achieve electrical connection between the second electrodes 109 in adjacent rows. Optionally, as Figure 24 As shown, the connecting electrode 110 is in the same layer and made of the same material as the first electrode 72 and the second electrode 73 of the transistor 107. Figure 3 As shown, a gate insulating layer 111 is provided between the second electrode 109 and the first electrode 72 and the second electrode 73 of the transistor 107. Therefore, the electrical connection between the connecting electrode 110 and the second electrode 109 can be achieved by drilling a hole in the gate insulating layer 111. However, since the gate insulating layer 111 in related technologies is fabricated using an open mask, no patterning process is required. If a hole is drilled in the gate insulating layer 111 in this disclosure to connect the transition electrode 110 and the second electrode 109, an additional patterning process is required. Considering that the first electrode 103 is electrically connected to the second electrode 73 of the transistor 107 through a first via V1 penetrating the insulating layer 106, and that there is an insulating layer 106 and a gate insulating layer 111 between the second electrode 109 and the first electrode 103, the electrical connection between the connecting electrode 110 and the second electrode 109 can be achieved through a first transition electrode 112 that is in the same layer and material as the second electrode 109 and is mutually insulated from the second electrode 109. Specifically, as shown... Figure 3 and Figure 26 As shown, during the process of forming the first via V1 for connecting the first electrode 103 and the second electrode 73 of the transistor 107, a second via V2 that penetrates the insulating layer 106 and is used to realize the electrical connection between the connecting electrode 110 and the first transition electrode 112, and a third via V3 that penetrates the insulating layer 106 and the gate insulating layer 111 and is used to realize the electrical connection between the second electrode 109 and the first transition electrode 112 can be formed simultaneously, thus avoiding the need for additional patterning processes for the gate insulating layer 111.

[0131] In some embodiments, such as Figure 23 , Figure 27 , Figure 30 and Figure 32 As shown, two adjacent second electrodes 109 in the same row can be electrically connected via a third signal line 113, and... Figure 23The third signal line 113 is integrally disposed with each of the second electrodes 109 in the same row. Figure 27 , Figure 30 and Figure 32 The third signal line 113 and the second signal line 108 are disposed in the same layer and made of the same material. Two adjacent second electrodes 109 in the same row are electrically connected via the third signal line 113, which ensures good voltage uniformity and stability for all second electrodes 109 in the same row. As described above, in some embodiments, the second electrodes 109 in the same column can also be connected together via connecting electrodes 110. In this case, the second electrodes 109 in each row and column form an electrically connected whole, thereby ensuring excellent voltage uniformity and stability for all second electrodes 109. Optionally, at the intersection of the first signal line 105 and the third signal line 113, the line width of both the first signal line 105 and the third signal line 113 is reduced. This reduces the facing area of ​​the first signal line 105 and the third signal line 113, thereby ensuring a small parasitic capacitance between them.

[0132] In some embodiments, such as Figure 24 As shown, within the layer containing the first electrode 72 and the second electrode 73 of transistor 107, two positioning structures 114 are also provided. These two positioning structures 114 are used to position the spacer PS. For example, the orthogonal projection of the spacer PS onto the display substrate is located at the midpoint between the two positioning structures 114. Additionally, by Figure 25 As can be seen, in this disclosure, the first electrode 103 is a slit electrode, and the pattern between each two adjacent slits can be a first strip electrode 31 or a second strip electrode 32.

[0133] In some embodiments, such as Figure 21 and Figure 24 As shown, the first signal line 105 can be a straight line extending along the column gaps of each first electrode 103, or, as... Figure 27 , Figures 31 to 33 , Figure 35 , Figure 36 As shown, the first signal line 105 can have the same extension direction and shape as the strip electrode of the first electrode 103 or the second electrode 109, and is not limited here. Additionally, as... Figure 27 , Figure 29 , Figure 31 and Figure 32 As shown, it may also include a second transfer electrode 115 disposed on the same layer and of the same material as the second electrode 109, so as to realize the electrical connection between the second electrode 73 of the transistor 107 and the first electrode 103 through the second transfer electrode 115.

[0134] In some implementations, the transistor 107 provided in this disclosure can be a top-gate transistor or a bottom-gate transistor. The transistor 107 can be an oxide transistor, an amorphous silicon transistor, a polycrystalline silicon transistor, etc. The transistor 107 can be a P-type transistor or an N-type transistor, wherein the voltage difference V between the gate and source of the P-type transistor is... gs Its threshold voltage V th Satisfying relation V gs <V th When it is turned on, the voltage difference V between its gate and its source is... gs Its threshold voltage V th Satisfying relation V gs ≥V th Time cutoff; the voltage difference V between the gate and source of an N-type transistor. gs Its threshold voltage V th Satisfying relation V gs >V th When it is turned on, the voltage difference V between its gate and its source is... gs Its threshold voltage V th Satisfying relation V gs ≤V th Deadline. Additionally, if... Figure 3 As shown, transistor 107 may further include an active layer 74, and has a contact layer 75 between the active layer 74 and the first electrode 72, and between the active layer 74 and the second electrode 73, to improve the electrical connection between the active layer 74 and the first electrode 72, and between the active layer 74 and the second electrode 73.

[0135] Based on the same inventive concept, this disclosure provides a method for manufacturing the above-mentioned display substrate, such as... Figure 37 As shown, the following steps may be included:

[0136] S3701, Provide a substrate 101;

[0137] S3702. A pattern layer 104 and a first electrode 103 are formed on a substrate 101, wherein the orthographic projection of the pattern layer 104 on the substrate 101 and the orthographic projection of the first electrode 103 on the substrate 101 do not overlap, and the ratio of the contact angle of the pattern layer 104 to the contact angle of the first electrode 103 is greater than or equal to 7 / 12 and less than or equal to 3 / 2.

[0138] S3703, Apply alignment liquid to the layer where the pattern layer 104 and the first electrode 103 are located;

[0139] S3704. The alignment liquid is cured to form alignment layer 102.

[0140] In some embodiments, in the fabrication method provided in this disclosure, step S3702, forming a pattern layer and a first electrode on the substrate, can be implemented in two ways: First, using the same photomask to form a pattern layer and a first electrode of the same layer and material on the substrate. Second, using two photomasks to form a pattern layer and a first electrode on the substrate respectively, wherein the pattern layer and the first electrode are located on the same layer, and the material of the pattern layer and the material of the first electrode are the same.

[0141] In some embodiments, in the fabrication method provided in this disclosure, the same mask is used to form a patterned layer 104 and a first electrode 103 of the same layer and material on the substrate 101. This can be achieved in the following two possible ways:

[0142] The first possible implementation may include the following steps:

[0143] The first step is to sequentially form a conductive layer and a photoresist layer on the substrate 101.

[0144] The second step is to provide a mask with only the pattern used to fabricate the first electrode 103.

[0145] The third step is to offset the pattern of the mask relative to the area where the first electrode is to be fabricated, so that the pattern of the mask overlaps with both the area where the first electrode 103 is to be fabricated and the area where the pattern layer 104 is to be fabricated.

[0146] The fourth step involves exposing the photoresist layer in the area where the first electrode 103 is to be fabricated and the photoresist layer in the area where the pattern layer 104 is to be fabricated, in a time-sequential manner, under the cover of the photomask.

[0147] Optionally, by controlling the light source to only illuminate the photoresist layer in the area to be fabricated for the first electrode 103 or the area to be fabricated for the pattern layer 104, time-division exposure processing of the photoresist layer in the area to be fabricated for the first electrode 103 and the area to be fabricated for the pattern layer 104 can be achieved; or, when the light source illuminates the entire photomask, time-division exposure processing of the photoresist layer in the area to be fabricated for the first electrode 103 and the area to be fabricated for the pattern layer 104 can be achieved by blocking the photoresist layer in the area to be fabricated for the pattern layer 104 or the area to be fabricated for the first electrode 103.

[0148] The fifth step is to develop the photoresist layer, retaining the photoresist layer in the area where the first electrode 103 is to be fabricated and the photoresist layer in the area where the pattern layer 104 is to be fabricated.

[0149] The sixth step involves etching the conductive layer under the cover of the photoresist layer to form a patterned layer 104 and a first electrode 103 that are of the same layer and material but are disconnected.

[0150] The second possible implementation may include the following steps:

[0151] The first step is to sequentially form a conductive layer and a photoresist layer on the substrate 101.

[0152] The second step is to provide a mask having a first pattern for fabricating the first electrode 103 and a second pattern for fabricating the pattern layer 104, wherein the first pattern and the second pattern are disconnected.

[0153] The third step involves simultaneously exposing the photoresist layer in the area where the first electrode 103 is to be fabricated and the photoresist layer in the area where the pattern layer 104 is to be fabricated, under the cover of the photomask.

[0154] The fourth step is to develop the photoresist layer, retaining the photoresist layer in the area where the first electrode 103 is to be fabricated and the photoresist layer in the area where the pattern layer 104 is to be fabricated.

[0155] The fifth step involves etching the conductive layer under the cover of the photoresist layer to form a patterned layer 104 and a first electrode 103 that are of the same layer and material but are disconnected.

[0156] Alternatively, in the two possible implementations described above, after forming the patterned layer 104 and the first electrode 103 of the same layer and material but disconnected, a step of stripping the photoresist layer can also be performed.

[0157] In some embodiments, in the fabrication method provided in this disclosure, step S2602, forming the pattern layer 104 and the first electrode 103 on the substrate, can also be implemented in the following ways:

[0158] An insulating layer 106 is formed by using ammonia and silane as the reaction source gases. The flow ratio of ammonia to silane is greater than or equal to 2 and less than or equal to 8. For example, the flow ratio of ammonia to silane can be 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, etc.

[0159] A first electrode 103 is formed on the insulating layer 106 of the pixel opening region contained in the substrate 101, and the insulating layer 106 outside the pixel opening region is reused as a pattern layer 104.

[0160] Optionally, after providing a substrate 101 and before forming an insulating layer 106 that is disposed over the entire surface using ammonia and silane as reaction source gases, a gate 71, a second electrode 109, a gate insulating layer 111, an active layer 74 of the transistor 107, a first electrode 72, a second electrode 73 of the transistor disposed in the same layer, and a connecting electrode 110 of the transistor 107 may be sequentially formed on the substrate 101. After forming the entire insulating layer 106 using ammonia and silane as reaction source gases, and before forming the first electrode on the insulating layer 106 in the pixel opening region, a first via V1, a second via V2 penetrating the insulating layer 106, and a third via V3 penetrating the insulating layer 106 and the gate insulating layer 111 can be formed simultaneously. The first via V1 is used to electrically connect the second electrode 73 of the transistor 107 to the first electrode 103; the second via V2 is used to electrically connect the connecting electrode 110 to the transition electrode 112; and the third via V3 is used to electrically connect the transition electrode 112 to the second electrode 109. In some embodiments, the transition electrode 112 can be fabricated simultaneously with the formation of the first electrode 103.

[0161] It should be noted that in the fabrication method provided in the embodiments of this disclosure, the patterning process involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and is not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0162] Based on the same inventive concept, this disclosure provides a display device including the display substrate described above. Since the principle by which this display device solves the problem is similar to that of the display substrate, the implementation of the display device provided in this disclosure can refer to the implementation of the display substrate described above, and repeated details will not be described again.

[0163] In some embodiments, the display device provided in this disclosure can be applied to any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, smartwatches, fitness wristbands, and personal digital assistants. Optionally, the display device provided in this disclosure is a liquid crystal display screen. The liquid crystal display screen may include a backlight module and a display panel located on the light-emitting side of the backlight module. The display panel includes a display substrate and a counter substrate placed opposite each other, a liquid crystal layer located between the display substrate and the counter substrate, a sealant surrounding the liquid crystal layer between the display substrate and the counter substrate, a first alignment layer located on the display substrate near the liquid crystal layer, a second alignment layer located on the counter substrate near the liquid crystal layer, a first polarizer located on the display substrate away from the liquid crystal layer, and a second polarizer located on the counter substrate away from the liquid crystal layer. The backlight module may be a direct-lit backlight module or an edge-lit backlight module. The backlight module may include a light source, a stacked reflector, a light guide plate, a diffuser, a prism assembly, etc. The light source can be a light-emitting diode (LED), such as a miniature light-emitting diode (Mini LED, MicroLED, etc.).

[0164] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0165] In some embodiments, the display device provided in this disclosure may include, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip may be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and implement power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code, etc. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0166] Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0167] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A display substrate, wherein, include: Substrate; The alignment layer is located on the substrate. A first electrode is located between the substrate and the alignment layer and is in contact with the alignment layer. The first electrode is disposed in the pixel opening region. A patterned layer is located between and in contact with the alignment layer, wherein the orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate, and the ratio of the contact angle of the patterned layer to the contact angle of the first electrode is greater than or equal to 7 / 12 and less than 3 / 2; the patterned layer and the first electrode are disposed in the same layer and of the same material; there are multiple first electrodes, which are arranged in an array on the substrate; the orthographic projection of the patterned layer on the substrate is located within the orthographic projection of the row spacing of each first electrode on the substrate; the first electrode includes an integrally disposed first strip electrode and a second strip electrode, wherein the extension direction of the first strip electrode intersects with the row direction, the column direction, and the extension direction of the second strip electrode, and the extension direction of the second strip electrode intersects with the row direction and the column direction; the patterned layer extends along the extension direction of the first strip electrode and / or the extension direction of the second strip electrode, and the morphology of the patterned layer is the same as the local morphology of the first electrode.

2. The display substrate as claimed in claim 1, wherein, The patterned layers at the gaps between two adjacent rows of each of the first electrodes extend in different directions.

3. The display substrate as described in claim 1 or 2, wherein, The linewidth of the patterned layer is the same as the linewidth of the first or second strip electrode that extends in the same direction as the pattern, and the line spacing of the patterned layer is the same as the line spacing of the first or second strip electrode that extends in the same direction as the pattern.

4. The display substrate as claimed in claim 1, wherein, The pattern layer includes multiple block patterns spaced apart at the same row gap of each of the first electrodes, and the block patterns extend along the row direction.

5. The display substrate as claimed in claim 1, wherein, It also includes a first signal line, the orthographic projection of which is located within the orthographic projection of the column gap of each of the first electrodes on the substrate. The orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the first signal line on the substrate.

6. The display substrate as claimed in claim 5, wherein, It also includes a transistor, and at least a portion of the first signal line is electrically connected to the transistor; The orthographic projection of the patterned layer on the substrate does not overlap with the orthographic projection of the transistor on the substrate.

7. The display substrate as claimed in claim 1, wherein, The patterned layer includes strip patterns extending in the row direction at the row gaps of each of the first electrodes, the length of the strip patterns in the row direction being the same as the length of the row gaps.

8. The display substrate as claimed in claim 1, wherein, It also includes a second signal line, the orthographic projection of which is located within the orthographic projection of the row spacing of each of the first electrodes on the substrate. The orthographic projection of the patterned layer on the substrate lies within the orthographic projection of the second signal line on the substrate.

9. The display substrate as claimed in claim 8, wherein, The ratio of the width of the pattern layer in the column direction to the width of the second signal line in the column direction is greater than or equal to 3 / 5 and less than or equal to 1.

10. The display substrate as claimed in claim 1, wherein, It also includes a second signal line, the orthographic projection of the second signal line on the substrate is located within the orthographic projection of the row gap of each of the first electrodes on the substrate, and two second signal lines are correspondingly provided at the same row gap; At the same row gap between each of the first electrodes, the orthographic projection of the two second signal lines on the substrate lies within the orthographic projection of the patterned layer on the substrate.

11. The display substrate as claimed in claim 1, wherein, It also includes first and second signal lines that are intersected and insulated from each other, wherein the orthographic projection of the first signal line on the substrate is located within the orthographic projection of the column gap of each first electrode on the substrate, and the first signal line includes an island-shaped structure located at the intersection of the column gap and the gap of the two second signal lines. The orthographic projection of the patterned layer on the substrate coincides with the orthographic projection of the island structure on the substrate.

12. The display substrate as claimed in claim 1, wherein, It also includes a second signal line and a gate, wherein the second signal line and the gate are integrally formed and the gate protrudes relative to the second signal line; The pattern layer includes a plurality of first portions that are intersected with both the row and column directions, and a second portion that extends along the row direction. The orthographic projection of the first portion on the substrate is located within the orthographic projection of the gate on the substrate, and the orthographic projection of the second portion on the substrate is located within the orthographic projection of the second signal line on the substrate.

13. The display substrate as claimed in claim 1, wherein, It also includes a second electrode located between the layer containing the first electrode and the substrate, wherein the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate overlap each other.

14. The display substrate as claimed in claim 13, wherein, It also includes an insulating layer located between the layer containing the first electrode and the layer containing the second electrode, wherein the first electrode partially blocks the insulating layer, and the portion of the insulating layer not blocked by the first electrode is reused as the pattern layer.

15. The display substrate as claimed in claim 1, wherein, The alignment layer includes a stationing area for setting spacers, wherein the orthographic projection of the stationing area on the substrate lies within the orthographic projection of the patterned layer on the substrate.

16. A method for manufacturing a display substrate as described in any one of claims 1 to 15, wherein, include: Provide a substrate; A patterned layer and a first electrode are formed on the substrate, wherein the orthographic projection of the patterned layer on the substrate and the orthographic projection of the first electrode on the substrate do not overlap, and the ratio of the contact angle of the patterned layer to the contact angle of the first electrode is greater than or equal to 7 / 12 and less than or equal to 3 / 2. An alignment liquid is applied to the patterned layer and the layer containing the first electrode. The alignment liquid is cured to form an alignment layer.

17. The manufacturing method as described in claim 16, wherein, Forming a patterned layer and a first electrode on the substrate specifically includes: Using the same photomask, a patterned layer and a first electrode of the same material are formed on the substrate.

18. The manufacturing method as described in claim 17, wherein, Using the same photomask, a patterned layer and a first electrode of the same material are formed on the substrate, specifically including: A conductive layer and a photoresist layer are sequentially formed on the substrate. A photomask is provided, the photomask having only a pattern for fabricating the first electrode; The pattern of the mask is offset relative to the area where the first electrode is to be fabricated, such that the pattern of the mask overlaps with both the area where the first electrode is to be fabricated and the area where the pattern layer is to be fabricated. Under the cover of the photomask, the photoresist layer in the area where the first electrode is to be formed and the photoresist layer in the area where the pattern layer is to be formed are exposed in a time-division manner. The photoresist layer is developed to retain the photoresist layer in the area where the first electrode is to be fabricated and the photoresist layer in the area where the pattern layer is to be fabricated. Under the cover of the photoresist layer, the conductive layer is etched to form the patterned layer and the first electrode, which are of the same layer and material but disconnected.

19. The manufacturing method as described in claim 17, wherein, Using the same photomask, a patterned layer and a first electrode of the same material are formed on the substrate, specifically including: A conductive layer and a photoresist layer are sequentially formed on the substrate. A photomask is provided having a first pattern for fabricating a first electrode and a second pattern for fabricating a patterned layer, wherein the first pattern and the second pattern are disconnected. Under the cover of the photomask, the photoresist layer in the area where the first electrode is to be formed and the photoresist layer in the area where the pattern layer is to be formed are exposed simultaneously. The photoresist layer is developed to retain the photoresist layer in the area where the first electrode is to be fabricated and the photoresist layer in the area where the pattern layer is to be fabricated. Under the cover of the photoresist layer, the conductive layer is etched to form the patterned layer and the first electrode, which are of the same layer and material but disconnected.

20. The manufacturing method as described in claim 17, wherein, Forming a patterned layer and the first electrode on the substrate specifically includes: An insulating layer is formed by using ammonia and silane as the reaction source gases, with the flow ratio of ammonia to silane being greater than or equal to 2 and less than or equal to 8. A first electrode is formed on the insulating layer of the pixel opening region contained in the substrate, and the insulating layer outside the pixel opening region is reused as a pattern layer.

21. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 15.

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