Display driver system with embedded non-volatile memory

Abstract

A circuit structure (320, 420, 520) for adjusting the brightness of a display device (200). The circuit structure (320, 420, 520) includes: a non-volatile memory array (321, 421, 521) having multiple storage cells for storing brightness data of the display device (200); and a brightness adjustment circuit (322, 422, 522) for receiving image data to be displayed on the display device (200). The brightness adjustment circuit (322, 422, 522) is directly connected to the non-volatile memory array (321, 421, 521) to receive the brightness data of the display device (200) from the non-volatile memory array (321, 421, 521) and adjust the image data according to the brightness data of the display device (200).

Description

Technical Field

[0001] This invention relates generally to integrated circuits, and more particularly to display drivers. Background Technology

[0002] Display driver integrated circuits (DDICs) comprise a class of integrated circuits used to provide interface functionality between a specific microprocessor / microcontroller / application-specific integrated circuit (ASIC) / interface and a specific display device. These display devices include, but are not limited to, liquid crystal displays (LCDs), light-emitting diode (LED) displays, and organic light-emitting diode (OLED) displays. Display drivers typically use industry-standard, universal interfaces to receive commands and data and generate signals with appropriate voltage / current / timing to enable the display to show the desired image.

[0003] OLED displays are entering mainstream mobile devices. For such applications, the expectation is for low-cost, small-size, and high-performance DDICs. Figure 1 A block diagram of a conventional display driver system 100 is shown. The display driver system 100 includes a Mobile Industrial Processor Interface (MIPI) 102, a Digital Signal Compression (DSC) encoder 104, a Data Buffer (Dbuf) 106, Static Random Access Memory (SRAM) 108, a DSC decoder 110, a Screen Color Management (SCM) module 112, an Edge Adjustment module 114, a Subpixel Rendering (SPR) module 116, a De-Mura module 118, Flash memory 120, another SRAM 122, an Anti-Gamma (Gamma Correction) module 124, a Timing Control (T-con) module 126, analog circuitry 128, a General Purpose Input / Output (GPIO) interface 130, and a display panel 132.

[0004] MIPI 102 defines the serial bus and communication protocol between the host (source of image data) and the display system 100 (destination of image data). MIPI 102 can forward received image / pixel data to DSC encoder 104 and data buffer 106. DSC encoder 104 is used to encode / compress pixel data according to the DSC standard and send the encoded pixel data to data buffer 106. Data buffer 106 temporarily stores the pixel data compressed according to the DSC standard in SRAM 108. The compressed pixel data is then forwarded sequentially to DSC decoder 110, which decodes the next available pixel data into pixel / RGB data according to the DSC standard. Screen color management module 112 receives RGB data / signals and converts the colors in the original color space to colors in a specified color space (specified by the designer or user) associated with the display panel 132 (e.g., OLED display).

[0005] Edge adjustment module 114 processes pixel data based on the specific shape (e.g., border / notch portion) of display panel 132 (e.g., a display for a mobile device). For example, edge adjustment module 114 can remove some pixel data at the edges / periphery portions of an image, allowing the image to be displayed correctly on a mobile phone. Subpixel rendering block 116 increases the resolution of display panel 132 by rendering RGB pixels separately using the underlying physical properties of display panel 132.

[0006] The demura module 118 is used to calibrate the brightness data across the entire screen and uses this data to calculate corrections for each pixel to achieve a more uniform brightness / appearance on the display panel 132. Due to manufacturing variations, each pixel on the display panel 132 may have slight brightness differences from one another under the same driving conditions. For example, when the same driving voltage or current is applied to the individual pixels of the display panel 132, the individual pixels may exhibit different brightness levels, thus reducing the user's visual experience. The demura module 118 is designed to correct for this difference. To achieve this, the display system 100 also includes flash memory 120 and SRAM 122. Flash memory 120 is used to store mura information for the display panel 132. For example, mura information is generated based on the brightness measurement of each individual display panel. The mura information is written to flash memory 120 via input / output 120-1. When the display panel 132 is powered on, data is read from flash memory 120 into SRAM 122. When image data is read at the demura module 118, mura information is output to the demura module 118 via SRAM input / output 122-1. The demura module 118 then uses this mura information to calibrate the brightness data of the image data.

[0007] The degamma module 124 is used to transform frame / image data and provide a non-linear relationship between brightness and input voltage. The image data is then sent to the T-Con module 126 and analog circuitry 128. The T-Con module 126 is a control circuit for the analog circuitry 128, which generates the voltage / current to drive the pixels of the display panel 132. Drive signals from the analog circuitry 128 are sent to the display panel 132 via the GPIO interface 130 to drive the pixels of the display panel 132. Summary of the Invention

[0008] In general, one aspect of this disclosure relates to an apparatus comprising: a circuit structure for adjusting the brightness of a display device, the circuit structure including: a non-volatile memory array having a plurality of storage cells for storing brightness data of the display device; a brightness adjustment circuit for receiving image data to be displayed on the display device and adjusting the image data according to the brightness data of the display device; and a unified controller for providing: (i) a memory control signal for controlling the operation of the non-volatile memory array; and (ii) a brightness control signal for controlling the operation of the brightness adjustment circuit.

[0009] Embodiments of the device may include one or more of the following features. In some embodiments, the unified controller includes a single finite state machine, wherein the finite state machine is used to generate: (i) the memory control signal; and (ii) the brightness control signal. In some embodiments, the circuit structure for adjusting the brightness of the display device further includes: another non-volatile memory array having an additional plurality of memory cells, wherein the additional plurality of memory cells are used to buffer the image data before the brightness adjustment circuit adjusts the image data; and the unified controller is further used to provide (iii) other memory control signals to control the operation of the other non-volatile memory array. In some embodiments, the unified controller includes a single finite state machine, wherein the finite state machine is used to generate: (i) the memory control signal; (ii) the brightness control signal; and (iii) the other memory control signals. Some embodiments include a single integrated circuit having the device.

[0010] In some embodiments, the non-volatile memory array includes one of resistive random access memory, phase-change random access memory, ferroelectric random access memory, or spin torque transfer magnetic random access memory. In some embodiments, the non-volatile memory array is a one-time programmable memory. In some embodiments, the non-volatile memory array includes a redundant memory portion for correcting errors in the brightness data after the one-time programmable memory has been programmed with the brightness data. In some embodiments, the non-volatile memory array includes a plurality of memory banks, wherein the brightness adjustment circuit is configured to receive a set of data in parallel from the plurality of memory banks and serially output pixel data corresponding to the set of data. In some embodiments, the unified controller includes: a non-volatile memory, wherein the unified controller is configured to provide the memory control signal and the brightness control signal based on data stored in the non-volatile memory.

[0011] In general, one aspect of this disclosure relates to an apparatus comprising: a circuit structure for adjusting the brightness of a display device, the circuit structure comprising: a non-volatile memory array having a plurality of storage cells for storing brightness data of the display device; and a brightness adjustment circuit for receiving image data to be displayed on the display device and adjusting the image data according to the brightness data of the display device; a brightness controller including a first non-volatile memory, wherein the brightness controller is configured to provide a brightness control signal according to first data stored in the first non-volatile memory to control the operation of the brightness adjustment circuit; and a memory controller including a second non-volatile memory, wherein the memory controller is configured to provide a memory control signal according to second data stored in the second non-volatile memory to control the operation of the non-volatile memory array.

[0012] Embodiments of the device may include one or more of the following features. In some embodiments, the brightness controller includes a single finite state machine for generating the brightness control signal. In some embodiments, the memory controller includes a single finite state machine for generating the memory control signal. In some embodiments, the circuit structure for adjusting the brightness of the display device further includes another non-volatile memory array having an additional plurality of memory cells, wherein the additional plurality of memory cells are used to buffer the image data before the brightness adjustment circuit adjusts the image data; and the memory controller is further used to provide additional memory control signals to control the operation of the additional non-volatile memory array. In some embodiments, the memory controller includes a single finite state machine for generating the memory control signal and the additional memory control signals. Some embodiments include a single integrated circuit having the device.

[0013] In some embodiments, the non-volatile memory array includes one of resistive random access memory, phase-change random access memory, ferroelectric random access memory, or spin torque transfer magnetic random access memory. In some embodiments, the non-volatile memory array is a one-time programmable memory. In some embodiments, the non-volatile memory array includes a redundant memory portion for correcting errors in the brightness data after the one-time programmable memory has been programmed with the brightness data. In some embodiments, the non-volatile memory array includes a plurality of memory banks, wherein the brightness adjustment circuit is configured to receive a set of data in parallel from the plurality of memory banks and serially output pixel data corresponding to the set of data.

[0014] One aspect of this disclosure provides a circuit structure for adjusting the brightness of a display device. The circuit structure includes: a non-volatile memory array having a plurality of storage cells for storing brightness data of the display device; and a brightness adjustment circuit for receiving image data to be displayed on the display device. The brightness adjustment circuit is directly connected to the non-volatile memory array to obtain the brightness data of the display device from the non-volatile memory array and adjust the image data based on the brightness data of the display device.

[0015] Embodiments of the circuit structure may include one or more of the following features. In some embodiments, the circuit structure further includes a memory control circuit connected to and used to control the operation of the non-volatile memory array. In some embodiments, the circuit structure further includes an input / output interface connected to the memory control circuit and used to receive brightness data from outside the circuit structure. In some embodiments, both the memory control circuit and the input / output interface are embedded in a brightness adjustment circuit. In some embodiments, the non-volatile memory array includes one of: resistive random access memory, phase-change random access memory, ferroelectric random access memory, and spin torque transfer magnetic random access memory.

[0016] In some embodiments, the non-volatile memory array is a one-time programmable memory. In some embodiments, the non-volatile memory array includes a redundant memory portion for correcting errors in the brightness data after the one-time programmable memory has been programmed with the brightness data. In some embodiments, the non-volatile memory array includes a plurality of memory banks, wherein the brightness adjustment circuitry is configured to receive a set of data in parallel from the plurality of memory banks and serially output pixel data corresponding to the set of data.

[0017] In another aspect, a display control circuit is provided. The display control circuit includes: an input interface for receiving image data to be displayed on a display device; a circuit structure for adjusting the image data to generate adjusted image data; and an output interface for outputting a display signal generated based on the adjusted image data to the display device. The circuit structure includes: a non-volatile memory array having multiple storage units for storing brightness data of the display device; and a brightness adjustment circuit for receiving the image data to be displayed on the display device. The brightness adjustment circuit is directly connected to the non-volatile memory array to obtain the brightness data of the display device from the non-volatile memory array and adjust the image data based on the brightness data of the display device.

[0018] In some embodiments, the display control circuit further includes: a digital signal compression encoder connected to the input interface and used to encode image data received from the input interface to generate encoded image data; a data buffer connected to the digital signal compression encoder and the input interface and used to store the encoded image data and the image data; and a digital signal compression decoder connected to the data buffer and used to decode the encoded image data.

[0019] In some embodiments, the data buffer includes non-volatile memory. In some embodiments, the non-volatile memory is a multiple-programmable memory. In some embodiments, the non-volatile memory includes one of resistive random access memory, phase-change random access memory, ferroelectric random access memory, and spin torque transfer magnetic random access memory.

[0020] The above and other features of the apparatus, system, and method of invention herein, as well as the operation and function of related elements of the structure, will become more readily understood after considering the following description and claims with reference to the accompanying drawings, all of which form part of this specification. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to limit the invention. It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only and do not limit the invention. Attached Figure Description

[0021] Non-limiting embodiments of the present invention can be more easily understood by referring to the following figures.

[0022] Figure 1 This is a block diagram of a traditional display driving system.

[0023] Figure 2 This is a block diagram of a display device according to an example embodiment.

[0024] Figure 3 This is a block diagram of a display control device for controlling the brightness of a display device according to an example embodiment.

[0025] Figure 4 This is a block diagram of another display control device for controlling the brightness of a display device according to an example embodiment.

[0026] Figure 5 This is a block diagram of another display control device for controlling the brightness of a display device according to an example embodiment.

[0027] Figure 6 This is a block diagram of yet another display control device for controlling the brightness of a display device according to an example embodiment.

[0028] Figure 7This is a block diagram of a display control device for controlling the brightness of a display device according to an example embodiment, wherein the control display device has a display data buffer.

[0029] Figure 8 is a block diagram of a conventional display system with a single controller according to an example embodiment.

[0030] Figure 9 This is a block diagram of a display system with two controllers according to an example embodiment.

[0031] Figure 10 This is a block diagram of a display system with a unified DDIC / NVM controller according to an example embodiment.

[0032] Figure 11 This is a block diagram of a display system with two controllers equipped with NVM, according to an example embodiment.

[0033] Figure 12 This is a block diagram of a display system with a unified DDIC / NVM controller with NVM according to an example embodiment. Detailed Implementation

[0034] Non-limiting embodiments of the invention will now be described with reference to the accompanying drawings. It should be understood that specific features and aspects of any embodiment of the invention may be used and / or combined with specific features and aspects of any other embodiment of the invention. It should also be understood that such embodiments are merely examples and illustrations of a limited number of embodiments within the scope of the invention. Any modifications or alterations made by those skilled in the art to the technical solutions and content disclosed in this invention shall still fall within the spirit, scope of protection, and concept of the invention as further defined in the appended claims.

[0035] Brightness inhomogeneity / mura is common in display devices. For example, in OLED displays, each pixel is an individual emitter, and differences between pixels can cause brightness inhomogeneity across the entire screen / panel, known as mura. This effect causes visual unevenness for the user and needs to be mitigated. Typically, during OLED manufacturing / testing, brightness data on the screen can be measured and recorded. This data can be used to calculate individual corrections to the voltage / current applied to each pixel, thereby making the display appear more uniform. This process is called mura correction or demura. Brightness inhomogeneity is recorded only once per screen and typically does not change significantly over the screen's lifespan. The memory capacity used for demura purposes is proportional to the total number of pixels on the screen.

[0036] The technology invented in this paper provides a solution in which the memory of the demura module can be quickly programmed and read and has good data retention (at least 10 years at 85°C), as well as low power consumption and small size during mobile application reading.

[0037] Example embodiments will now be described with reference to the accompanying drawings. Figure 2 . Figure 2 This is a block diagram of a display device 200 according to an example embodiment. The display device 200 is similar to... Figure 1 The display device 100. Besides using a first non-volatile memory (NVM) 210 connected to a data buffer 106 and a second non-volatile memory (NVM) 220 connected to a demura module 118, the display device 200 and... Figure 1 The devices are similar. Since other components of display device 200 are similar to those of display device 100, detailed descriptions of these components will not be provided further. The mura module 118 and the second non-volatile memory (NVM) 220 form a circuit 250 for adjusting the brightness of the display device. For example, circuit 250 is used to correct the mura effect of the display panel 132 of display device 200.

[0038] Figure 3 A block diagram of a display control device 300 for controlling the brightness of a display device according to an example embodiment is shown. The display control device 300 includes one or more upstream modules 310, a circuit structure 320, and one or more downstream modules 330. The upstream module 310 is used to receive and process image data for pixels of the display device. The display device may be an LCD, LED, or OLED panel, or other display panels currently known or developed below. The circuit structure 320 is used to adjust the brightness of the display device. In some embodiments, the circuit structure 320 is used to adjust the brightness of the display device to correct for the mura effect on the display device. The downstream module 330 is used to further process the image data from the circuit structure 320 and to generate drive signals for driving the display device based on the image data.

[0039] In some embodiments, circuit structure 320 includes a non-volatile memory array 321 with multiple memory cells for storing brightness / mura data of the display device. In some embodiments, the brightness data of the display device includes brightness measurements of the pixels of the display device. For example, the brightness data may include brightness measurements of all pixels on the display device. Circuit structure 320 also includes a brightness adjustment circuit 322. The brightness adjustment circuit 322 is used to receive image data to be displayed on the display device from the upstream module 310. In the illustrated embodiment, the brightness adjustment circuit 322 may be demura logic. When the brightness adjustment circuit 322 receives image data, it obtains brightness / mura data from the memory array 321 and calibrates the image data to compensate for uneven brightness across the entire display device, thereby displaying an improved image on the display device. Figure 3 As shown, the brightness adjustment circuit 322 is directly connected to the non-volatile memory array 321 to receive brightness data from the display device and adjust the image data based on the brightness data. Brightness / mura data is unidirectionally transmitted from the non-volatile memory array 321 to the brightness adjustment circuit 322.

[0040] In some embodiments, circuit structure 320 further includes control circuitry 323 connected to and used to control the operation of non-volatile memory array 321. Circuit 320 also includes input / output (I / O) 324 connected to memory control circuitry and used to receive brightness data from outside the circuit structure 320. For example, brightness / mura data of a display device is measured and written to memory array 321 via I / O 324. Compared to a demura function that includes a demura module 118, flash memory 120 (with its I / O 120-1), and SRAM 122 (with I / O 122-1), circuit structure 320 for adjusting brightness / mura effects eliminates the interface between memory (e.g., memory array 321) and demura logic 322. Furthermore, circuit structure 320 includes one I / O interface 324 instead of two. Figure 1 The I / O pins 120-1 and 122-1 in the circuit are used to obtain the luminance / mura data from the mura-reducing logic 322. This reduces the complexity of the circuitry used to correct the mura effect.

[0041] In some embodiments, the non-volatile memory array 321 includes one of resistive random access memory (RRAM), phase-change random access memory (PCM), ferroelectric random access memory (FeRAM), and spin torque-transfer magnetic random access memory (STT-MRAM). In some embodiments, the non-volatile memory array 321 is a one-time programmable memory. That is, data can only be written to the non-volatile memory array 321 once. In some embodiments, the non-volatile memory array 321 is a multiple-programmable memory that can be programmed multiple times.

[0042] In some embodiments, when the memory array 321 includes resistive random access memory, each memory cell on the memory array 321 may include a transistor (T) and a resistor (R) (1T1R). Compared to conventional demura functions that typically require six transistors in a memory cell, the memory array 321 consumes less chip area. Furthermore, since SRAM operation requires standby power, circuitry 320 also uses less power because the non-volatile memory array 321 has no standby power. The non-volatile memory array 321 requires a read current comparable to or lower than that of an SRAM array. Additionally, the non-volatile memory array 321 has a faster response time than an SRAM array because conventional demura functions require reading luminance / mura data from flash memory to the SRAM array. Another advantage of circuitry 320 is that it does not include flash memory.

[0043] Figure 4 A block diagram of a display control device 400 for controlling the brightness of a display device according to an example embodiment is shown. The display control device 400 includes one or more upstream modules 410, a circuit structure 420, and one or more downstream modules 430. The upstream modules 410 and downstream modules 430 are similar to... Figure 3 The upstream module 310 and downstream module 330 have functions that will not be described in detail here. Circuit structure 420 is used to adjust the brightness of the display device. In some embodiments, circuit structure 420 is used to adjust the brightness of the display device to correct the mura effect on the display device.

[0044] In some embodiments, circuit structure 420 includes a non-volatile memory array 421 with multiple storage cells and a brightness adjustment circuit 422. The multiple storage cells are used to store brightness / mura data of the display device, and the brightness adjustment circuit 422 is directly connected to the non-volatile memory array 421 via a communication channel 423. The brightness adjustment circuit 422 includes demura logic for correcting image data to compensate for uneven brightness across the entire display device. Furthermore, control circuitry and I / O interfaces for the non-volatile memory array 421 are embedded within the brightness adjustment circuit 422. Brightness / mura data of the display device is written to the non-volatile memory array 421 via the brightness adjustment circuit 422, which includes control circuitry and I / O interfaces for the non-volatile memory array 421. When the demura logic of the brightness adjustment circuit 422 receives image data from the upstream module 410, it obtains the brightness / mura data from the memory array 421 to calculate the corrected pixel brightness values ​​for the pixels of the display device.

[0045] In circuit structure 420, since the control circuitry and I / O interface for the non-volatile memory array 421 are both embedded in the brightness adjustment circuit 422, there is no external I / O for the memory array 421. Furthermore, the non-volatile memory array 421 can be programmed using the I / O interface in the brightness adjustment circuit 422. This structure eliminates the need for external I / O for the non-volatile memory array 421 and saves on the cost of implementing the display control device 400. Therefore, bidirectional transmission is achieved on the communication channel 423.

[0046] Figure 5 A block diagram of another display control device 500 for controlling the brightness of a display device according to an example embodiment is shown. The display control device 500 includes one or more upstream modules 510, a circuit structure 520 for adjusting brightness, and one or more downstream modules 530. The circuit structure 520 includes a non-volatile memory array 521, a brightness adjustment circuit 522, a control circuit 523 for controlling the non-volatile memory array 521, and an I / O interface 524.

[0047] The display control device 500 is similar to Figure 3The display control device 300, in addition to the non-volatile memory array 521 of the display control device 500, also includes a redundant memory section 521a. The redundant memory section 521a is used to correct the luminance / mura data after the one-time programmable memory 521 has been programmed with luminance / mura data. In some cases, luminance / mura data may be incorrectly written to the non-volatile memory array 521, or luminance / mura data in some cells of the non-volatile memory array 521 may be lost due to, for example, a faulty cell. When this occurs, the error can be corrected using the data stored in the redundant memory section 521a after the luminance / mura data has been programmed into the non-volatile memory array 521. In some embodiments, algorithms can be used to correct the error, including but not limited to low-density parity-check (LDPC), cyclic codes, Hamming codes, etc.

[0048] Because the pixels of the display device are arranged in an array including rows and columns, the luminance / mura data for the pixels of the display device can be stored in a similar manner in a non-volatile memory array (e.g., 321, 421, and 521). In some embodiments, the non-volatile memory array storing the luminance / mura data for the pixels of the display device is accessed sequentially during read and write operations. In some embodiments, the non-volatile memory array can be divided into multiple memory banks to store the luminance / mura data, such that the luminance adjustment circuitry can obtain a set of luminance data in parallel from the multiple memory banks and output pixel data corresponding to the set of data in series.

[0049] Figure 6A block diagram of another display control device 600 for controlling the brightness of a display device according to an example embodiment is shown. The display control device 600 includes a non-volatile memory array 621 and demura logic 622 for providing color difference correction for the display device. The non-volatile memory array 621 is divided into four banks: 621a (bank0), 621b (bank1), 621c (bank2), and 621d (bank3). It should be understood that the non-volatile memory array 621 may be divided into more or fewer than four banks. For example, data entries 0-7 are the brightness / mura data of pixels 1-8 located in the display device rows. Data entries 0 and 4 (corresponding to pixels 1 and 5) are stored in bank 621a; data entries 1 and 5 (corresponding to pixels 2 and 6) are stored in bank 621b; data entries 2 and 6 (corresponding to pixels 3 and 7) are stored in bank 621c; and data entries 3 and 7 (corresponding to pixels 4 and 8) are stored in bank 621d. During a write operation, entries 0-3 can be written to memory banks 621a-621d in parallel or serially. That is, four luminance data entries can be written to four memory banks in parallel or serially. In the next write operation, entries 4-7 can be written to memory banks 621a-621d in parallel or serially.

[0050] During the read operation, demura logic 622 is used to obtain data entries 0-3 in parallel from memory banks 621a-621d and use the luminance data stored therein to calibrate the image luminance data of pixels 1-4. Then, demura logic circuit 622 serially outputs the pixel luminance data of pixels 1-4. That is, demura logic 622 is used to read luminance data for mura correction in parallel from memory banks and serially output the pixel luminance data. This technique allows for low-speed parallel access to multiple luminance data entries and reads or writes data at the normal chip clock frequency to match throughput requirements. In some embodiments, these techniques contribute to improving the speed and / or design margin of the display control device.

[0051] Figure 7 A block diagram of another display control device 700 for controlling the brightness of a display device according to an example embodiment is shown. This other display control device 700 includes a display data buffer. The display control device 700 includes one or more upstream modules 710, a display data buffer 720, and one or more downstream modules 730. For example, the upstream module 710 may include a connection to an input interface (e.g., ...). Figure 2 The MIPI 102 digital signal compression encoder (e.g., Figure 2The encoder 104 in the display data buffer 720 is used to encode image data received from the input interface to generate encoded image data. The display data buffer 720 is connected to the digital signal compression encoder and the input interface, and is used to store encoded image data and image data. The downstream module 730 may include a digital signal compression decoder (e.g., a digital signal compression decoder) connected to the display data buffer 720. Figure 2 The decoder 110 in the middle is used to decode the encoded image data.

[0052] The display data buffer device 720 includes a display data buffer 721, a non-volatile memory array 722, and control circuitry 723 for controlling the non-volatile memory array 722. The display data buffer 721 can write frame data to and read frame data from the non-volatile memory array 722. For this purpose, the non-volatile memory array 722 is a multiple-programmable memory. In some embodiments, the non-volatile memory array 722 includes one of a resistive random access memory device, a phase-change random access memory device, a ferroelectric random access memory device, and a spin torque transfer magnetic random access memory.

[0053] As mentioned above, in some traditional systems, such as Figure 1 In the display driver system 100, the memory in the DDIC is typically implemented as SRAM. Such systems require only a single controller to control only the DDIC functional modules. Figure 8 is a block diagram of a conventional display system 800 with a single controller according to an example embodiment. Referring to Figure 8, the conventional display system 800 includes a DDIC 802, wherein the DDIC 802 includes a DDIC functional module 810 and an SRAM 812. The system 800 includes a DDIC controller 814 for generating a brightness control signal 816.

[0054] System 800 includes a DDIC 802, which generates an output signal 806 to drive a display panel 804. The DDIC includes a DDIC functional module 810. The DDIC functional module 810 may include... Figure 1 The conventional display driver system 100 includes one or more functional modules. The DDIC functional module 810 generates an output signal 806 based on the input signal 808, according to the brightness control signal 816 generated by the DDIC controller 814. The DDIC functional module 810 employs SRAM 812.

[0055] As mentioned above, in some systems, such as Figure 2 In the display driver system 200, the memory in the DDIC is implemented in the form of NVM. Such systems typically use two controllers: a DDIC controller for controlling the DDIC functional modules and an NVM controller for controlling the NVM. Figure 9 This is a block diagram of a display system 900 with two controllers according to an example embodiment. (See reference) Figure 9 The display system 900 includes a DDIC 902, which includes a DDIC functional module 910 and an NVM 912. The system 900 includes a DDIC controller 914 that generates a brightness control signal 916 and an NVM controller 918 that generates an NVM control signal 920.

[0056] System 900 includes a DDIC 902 that generates an output signal 906 to drive a display panel 904. The DDIC 902 includes a DDIC function module 910. The DDIC function module 910 may include... Figure 2 The display driver system 200 includes one or more functional modules. The DDIC functional module 910 generates an output signal 906 based on an input signal 908, according to a brightness control signal 916 generated by a DDIC controller 914. The DDIC functional module 910 employs an NVM 912. The NVM 912 operates according to an NVM control signal 920 generated by an NVM controller 918.

[0057] The DDIC controller 914 includes digital logic 922 implementing a finite state machine (FSM) 924. The FSM 924 determines the current operating state of the DDIC 902 (e.g., powered on, idle, data flow, powered off, etc.) and selects a specific set of logic functions to generate brightness control signals 916 for other modules in the current operating state. The DDIC controller 914 may also include a register 926, an I / O interface 928, and an OTP memory 930. The DDIC controller 914 may also include a controller interface 942 for exchanging inter-controller control signals 946 with the NVM controller 918.

[0058] The NVM controller 918 includes digital logic 932 implementing an FSM 934. The FSM 934 determines the current operating state of the NVM module (e.g., initialization, write, read, etc.) and selects a specific set of logic functions to generate NVM control signals 920 for other modules in the current operating state. The NVM controller 918 may also include registers 936, I / O interfaces 938, and OTP memory 940. The NVM controller 918 may also include a controller interface 944 for exchanging inter-controller control signals 946 with the DDIC controller 914.

[0059] Based on the input signals and data read from registers, OTP memory, and I / O interfaces, the state machine will also determine whether to switch to another state in the next clock cycle. Once a state is switched, a set of logic functions used to generate control signals can also be switched. The various signals generated by the two controllers can include: analog circuit configuration signals (e.g., voltage values, current values, etc.), clock signals for various modules (which can also be used to synchronize the two controllers), selection signals for the memory array (e.g., word line address, bit line address, etc.), and timing signals (e.g., pulse duration, pulse width, pulse count, etc.).

[0060] Using two controllers has some drawbacks. An additional controller, the NVM controller 918, is required. Many components, including registers 926 and 936, I / O interfaces 928 and 938, and OTP memories 930 and 940, are redundant. Furthermore, additional components such as controller interfaces 942 and 944 are also needed.

[0061] Some embodiments of the present disclosure improve these systems by providing a single unified controller for simultaneously controlling the DDIC functional modules and the NVM. Figure 10 This is a block diagram of a display system 1000 with a unified DDIC / NVM controller according to an example embodiment. (Refer to...) Figure 10 The display system 1000 includes a DDIC 1002 with a DDIC function module 1010 and an NVM 1012. The system 1000 includes a unified DDIC / NVM controller 1014 that generates both a brightness control signal 1016 and an NVM control signal 1020.

[0062] System 1000 includes a DDIC 1002 that generates an output signal 1006 to drive a display panel 1004. DDIC 1002 includes a DDIC functional module 1010. The DDIC functional module 1010 may include... Figure 2 The display driver system 200 comprises one or more functional modules. The DDIC functional module 1010 generates an output signal 1006 based on the input signal 1008 according to the brightness control signal 1016 generated by the unified DDIC / NVM controller 1014. The DDIC functional module 1010 employs an NVM 1012. The NVM 1012 operates according to the NVM control signal 1020 generated by the unified DDIC / NVM controller 1014.

[0063] The unified DDIC / NVM controller 1014 includes digital logic 1022 implementing a finite state machine (FSM) 1024. The FSM 1024 determines the current operating state of the DDIC 1002 (e.g., powered on, idle, data flow, powered off, etc.) and selects a specific set of logic functions to generate brightness control signals 1016 for other modules in the current operating state. The FSM 1024 also determines the current operating state of the NVM module (e.g., initialization, write, read, etc.) and selects a specific set of logic functions to generate NVM control signals 1020 for other modules in the current operating state. The unified DDIC / NVM controller 1014 may also include registers 1026, I / O interfaces 1028, and an OTP memory 1030.

[0064] and Figure 9 Compared to the 900 display system, Figure 10 The 1000 display system offers several advantages. Compared to Figure 9 The display system has multiple controllers. Figure 10 The display system 1000 requires only a single controller, namely the unified DDIC / NVM controller 1014. Therefore, only one state machine is needed. All control signals are generated by this state machine. Furthermore, there are no redundant components. The advantages of this approach include smaller footprint, lower cost, and faster control.

[0065] As mentioned above, in some dual-controller systems, such as Figure 9 In the display driver system 900, the memory in the controller is implemented as an OTP memory. In some embodiments, the OTP memory in one or both controllers is replaced by an NVM. Figure 11 This is a block diagram of a display system 1100 with two controllers equipped with NVM, according to an example embodiment. (Refer to...) Figure 11 The memories in DDIC controller 1114 and NVM controller 1118 are replaced by NVM 1130 and NVM 1140, respectively. For example, the NVM can be resistive random access memory (RRAM), phase-change memory (PCM), ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), or spin-transfer torque RAM (STRAM). NVM 1130 in DDIC controller 1114 can be controlled by DDIC FSM 1124 or other logic. NVM 1140 in NVM controller 1118 can be controlled by NVM FSM 1134 or other logic. Figure 11 Other components of the display system 1100 can be referenced from [the relevant documentation]. Figure 9The description of the corresponding components of System 900. Using NVM instead of OTP memory provides a more cost-effective solution with lower cost and lower operating power. Furthermore, NVM can be reprogrammed if needed. Moreover, the memory control logic is simplified because all memory modules can be controlled in the same way.

[0066] In some embodiments with a unified DDIC / NVM controller, the OTP memory in the unified DDIC / NVM controller is replaced by an NVM. Figure 12 This is a block diagram of a display system 1200 with a unified DDIC / NVM controller having NVM according to an example embodiment. (Refer to...) Figure 12 The OTP memory in the unified DDIC / NVM controller 1214 has been replaced by the NVM 1230. For example, the NVM can be RRAM, PCM, FeRAM, MRAM, or STRAM. The NVM 1230 in the unified DDIC / NVM controller 1214 can be controlled by the DDIC FSM 1224 or other logic. Figure 12 Other components of the display system 1200 can be referenced from [the relevant documentation / reference]. Figure 10 The description of the corresponding components of System 1000. Using NVM instead of OTP memory provides a more cost-effective solution with lower cost and lower operating power. Furthermore, NVM can be reprogrammed if needed. Moreover, the memory control logic is simplified because all memory modules can be controlled in the same way.

[0067] Although examples and features of the disclosed principles are described herein, variations, adaptations, and other implementations may be made without departing from the spirit and scope of the disclosed embodiments. Similarly, the terms “comprising,” “having,” “containing,” and “including,” and other similar forms, are equivalent in meaning and are open-ended, as one or more items following any of these terms do not represent an exhaustive list of those items or are limited to those listed. It must also be noted that, as used herein and in the claims, the singular forms “a,” “an,” and “the” include plural references unless the context clearly indicates otherwise.

[0068] The embodiments shown herein have been described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived from them, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. Therefore, the detailed description should not be understood in a limiting sense, and the scope of the various embodiments is defined only by the claims and the full scope of their equivalents.

Claims

1. A device having a non-volatile memory, characterized in that, include: A circuit structure for adjusting the brightness of a display device, wherein the circuit structure includes: A non-volatile memory array having multiple storage cells for storing brightness data of the display device, and A brightness adjustment circuit is configured to receive image data to be displayed on the display device and adjust the image data according to the brightness data of the display device; and A unified controller is provided to provide: (i) memory control signals to control the operation of the non-volatile memory array; and (ii) brightness control signals to control the operation of the brightness adjustment circuit. The unified controller includes a non-volatile memory and a single finite state machine, wherein the finite state machine is used to generate: (i) the memory control signal; and (ii) the brightness control signal.

2. The apparatus according to claim 1, characterized in that: The circuit structure for adjusting the brightness of a display device further includes: another non-volatile memory array having additional storage units, wherein the additional storage units are used to buffer the image data before the brightness adjustment circuit adjusts the image data; and The unified controller is also used to provide (iii) other memory control signals to control the operation of the other non-volatile memory array.

3. The apparatus according to claim 2, characterized in that, The finite state machine is used to generate (iii) the other memory control signals.

4. The apparatus according to claim 1, characterized in that, The non-volatile memory array includes one of resistive random access memory, phase-change random access memory, ferroelectric random access memory, or spin torque transfer magnetic random access memory.

5. The apparatus according to claim 1, characterized in that, The non-volatile memory array is a one-time programmable memory.

6. The apparatus according to claim 5, characterized in that, The non-volatile memory array includes a redundant memory portion for correcting errors in the luminance data after the one-time programmable memory has been programmed with the luminance data.

7. The apparatus according to claim 1, characterized in that, The non-volatile memory array includes multiple memory cells, wherein the brightness adjustment circuit is used to receive a set of data in parallel from the multiple memory cells and serially output pixel data corresponding to the set of data.

8. The apparatus according to claim 1, characterized in that, The unified controller is used to provide the memory control signal and the brightness control signal based on the data stored in the non-volatile memory.

9. A single integrated circuit, characterized in that, Includes the apparatus according to claim 1.

10. A device having non-volatile memory, characterized in that, include: A circuit structure for adjusting the brightness of a display device, wherein the circuit structure includes: A non-volatile memory array having multiple storage cells for storing brightness data of the display device, and A brightness adjustment circuit is used to receive image data to be displayed on the display device and to adjust the image data according to the brightness data of the display device. A brightness controller includes a first non-volatile memory, wherein the brightness controller is configured to provide a brightness control signal based on first data stored in the first non-volatile memory to control the operation of the brightness adjustment circuit; and A memory controller includes a second non-volatile memory, wherein the memory controller is configured to provide memory control signals based on second data stored in the second non-volatile memory to control the operation of the non-volatile memory array. The brightness controller includes a single finite state machine for generating the brightness control signal, and the memory controller includes a single finite state machine for generating the memory control signal.

11. The apparatus according to claim 10, characterized in that: The circuit structure for adjusting the brightness of the display device further includes another non-volatile memory array having additional storage units, wherein the additional storage units are used to buffer the image data before the brightness adjustment circuit adjusts the image data; and The memory controller is also used to provide other memory control signals to control the operation of the other non-volatile memory array.

12. The apparatus according to claim 11, characterized in that, The memory controller includes: A single finite state machine for generating the memory control signals and the other memory control signals.

13. The apparatus according to claim 10, characterized in that, The non-volatile memory array includes one of resistive random access memory, phase-change random access memory, ferroelectric random access memory, or spin torque transfer magnetic random access memory.

14. The apparatus according to claim 10, characterized in that, The non-volatile memory array is a one-time programmable memory.

15. The apparatus according to claim 14, characterized in that, The non-volatile memory array includes a redundant memory portion for correcting errors in the luminance data after the one-time programmable memory has been programmed with the luminance data.

16. The apparatus according to claim 10, characterized in that, The non-volatile memory array includes multiple memory cells, wherein the brightness adjustment circuit is used to receive a set of data in parallel from the multiple memory cells and serially output pixel data corresponding to the set of data.

17. A single integrated circuit, characterized in that, Includes the apparatus according to claim 10.

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