Control system, vehicle display device and dimming method

Abstract

A control system, display device, and dimming method are applied in the field of vehicle-mounted displays. The system includes a timing control subcircuit, a gamma register subcircuit, a source driver subcircuit, and a power management subcircuit. The timing control subcircuit is electrically connected to the gamma register subcircuit and the source driver subcircuit, the gamma register subcircuit and the source driver subcircuit are electrically connected, and the power management subcircuit is electrically connected to the timing control subcircuit, the gamma register subcircuit, and the source driver subcircuit.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a control system, an in-vehicle display device, and a dimming method. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess a range of advantages, including an all-solid-state structure, high brightness, wide viewing angle, fast response time, wide operating temperature range, and the ability to achieve flexible displays. OLED display panels represent a major development trend in the display technology field, and automotive displays using OLED panels have opened a new window for building an ecosystem for human-vehicle interaction.

[0003] An in-vehicle display is a display device placed in a vehicle to display images or play videos. In-vehicle displays have very high requirements for product lifespan and reliability, and automotive-grade products must have a service life of at least 10 years.

[0004] Public content

[0005] In a first aspect, some embodiments of this disclosure provide a control system, the control system comprising: a timing control subcircuit, a gamma register subcircuit, a source driver subcircuit, and a power management subcircuit. The timing control subcircuit is electrically connected to the gamma register subcircuit and the source driver subcircuit, the gamma register subcircuit and the source driver subcircuit are electrically connected, and the power management subcircuit is electrically connected to the timing control subcircuit, the gamma register subcircuit, and the source driver subcircuit.

[0006] The timing control subcircuit is configured to read pre-stored binding point data to generate voltage binding point signals and transmit them to the gamma register subcircuit, and to receive N gamma voltages provided by the source driver subcircuit and generate M register values, where M is greater than N. The timing control subcircuit is also configured to transmit the register values ​​to the source driver subcircuit in response to a signal received at the client assembly.

[0007] The gamma register subcircuit is configured to generate an analog gamma voltage signal and transmit it to the source driver subcircuit in response to a first voltage signal received at the power management subcircuit and a voltage binding signal received at the timing control subcircuit.

[0008] The source drive sub-circuit is configured to receive a plurality of the analog gamma voltage signals, generate a plurality of the gamma voltages between two adjacent analog gamma voltage signals, and generate a data signal and transmit it to the display panel in response to receiving the register value signal at the timing control sub-circuit.

[0009] The power management subcircuit is configured to generate a first voltage signal and transmit it to the gamma register subcircuit, and to generate an operating voltage and transmit it to the timing control subcircuit and the source driver subcircuit.

[0010] In some embodiments, the timing control subcircuit includes at least: a first memory, a timing control chip, and a second memory. The first memory is configured to pre-store binding point data. The timing control chip is electrically connected to the first memory and is configured to read the binding point data from the first memory, generate the voltage binding point signal, and receive N gamma voltages transmitted by the source driver subcircuit, generate and store M register values. The timing control chip is also configured to read the register values ​​and transmit them to the source driver subcircuit in response to a signal received at the client assembly. The second memory is electrically connected to the timing control chip and is configured to receive and store the M register values ​​transmitted by the timing control chip.

[0011] In some embodiments, the gamma register subcircuit includes at least a gamma chip, which is electrically connected to the timing control chip, the source driver subcircuit, and the power management subcircuit.

[0012] The gamma chip is configured to generate an analog gamma voltage signal and transmit it to the source driver subcircuit in response to the voltage binding signal received at the timing control chip and the first voltage signal received at the power management subcircuit.

[0013] In some embodiments, the source driver sub-circuit includes at least a source driver chip, which is electrically connected to the timing control chip and the gamma chip. The source driver chip is configured to receive an analog gamma voltage signal output by the gamma chip and generate a gamma voltage; and to receive a signal output by the timing control chip and transmit a data signal to the display panel.

[0014] In some embodiments, the power management subcircuit includes at least a power management chip, which is electrically connected to the timing control chip, the gamma chip, the source driver chip, the level shifting subcircuit, and the display panel. The power management chip is configured to provide an operating voltage to the timing control chip, a first voltage signal to the gamma chip and the source driver chip, a high / low level signal to the level shifting subcircuit, and a reset signal to the display panel.

[0015] In some embodiments, the control system further includes a level shifting sub-circuit, which is electrically connected to the timing control sub-circuit and the power management chip.

[0016] In some embodiments, the control system further includes a level shifting chip, which is electrically connected to the timing control chip and the power management chip, respectively. The level shifting chip is configured to generate a second signal and transmit it to the display panel in response to a signal received by the timing control chip.

[0017] Secondly, some embodiments of this disclosure also provide an in-vehicle display device, including: a display panel and a control system as described in any of the foregoing embodiments. The display panel is electrically connected to the control system.

[0018] Thirdly, some embodiments of this disclosure also provide a dimming method for an in-vehicle display device, applied to an in-vehicle display device as described in any of the above embodiments, wherein the control system of the in-vehicle display device transmits data signals to the display panel.

[0019] The dimming method of the in-vehicle display device includes: generating multiple gamma voltages arranged in descending or ascending order; generating multiple register values ​​based on the multiple gamma voltages using a dithering algorithm; modulating a gamma curve; and generating a corresponding segment of the gamma curve based on the multiple register values ​​and the brightness of the display panel.

[0020] In some embodiments, the power management subcircuit of the control system is configured to provide a first voltage signal to the gamma register subcircuit of the control system, and the timing control subcircuit of the control system is configured to provide a plurality of voltage binding point signals to the gamma register subcircuit.

[0021] The method for generating multiple gamma voltages arranged in descending or ascending order includes: generating multiple simulated gamma voltages based on the first voltage signal and the multiple voltage binding point signals, with each voltage binding point signal corresponding to one simulated gamma voltage. Two adjacent simulated gamma voltages are respectively set across multiple resistors connected in series, with the voltage between each resistor being one gamma voltage. The adjacent simulated gamma voltages generate multiple gamma voltages arranged in ascending order.

[0022] In some embodiments, the number of gamma voltages is 256.

[0023] In some embodiments, the method for generating multiple register values ​​based on multiple gamma voltages using a dithering algorithm includes: multiple adjacent pixels on the display panel forming a pixel group; the grayscale of each pixel within the pixel group corresponding to one of the multiple gamma voltages; and the grayscale value of the pixel group being the average of the grayscale values ​​of the multiple pixels. The gamma voltage of the multiple pixels corresponding to the grayscale of the pixel group is a register value corresponding to the grayscale of the pixel group.

[0024] In some embodiments, the number of adjacent pixels within the pixel group is at least two, and the grayscale values ​​of each pixel are the same and / or consecutive, and the number of register values ​​is at least 512.

[0025] In some embodiments, the method of generating multiple register values ​​based on multiple gamma voltages using a dithering algorithm includes: within a series of consecutive frames of images, the average grayscale value of a pixel on the display panel in each frame of the image is used as the display grayscale of any pixel. The gamma voltage corresponding to the grayscale of any pixel within the series of consecutive frames of images is used as a register value corresponding to the display grayscale.

[0026] In some embodiments, within at least two adjacent frames, the grayscale values ​​of any pixel are the same and / or consecutive, and the number of register values ​​is at least 512.

[0027] In some embodiments, the control system transmits data signals to the display panel.

[0028] The dimming method of the vehicle-mounted display device further includes: the vehicle-mounted display device modulating the data signal from a continuous signal into a pulse signal. Based on the duty cycle of the pulse signal and the brightness of the display panel, the maximum register value corresponding to the pixel of the display panel is determined, and the corresponding gamma curve is selected based on the maximum register value corresponding to the pixel.

[0029] In some embodiments, selecting the corresponding gamma curve based on the maximum register value corresponding to the pixel includes: the maximum value among the register values ​​corresponding to the gamma curve is consistent with the maximum register value corresponding to the pixel of the display panel.

[0030] In some embodiments, the brightness of the consecutive multi-frame images of the display panel decreases or increases. When the gamma curve is constant, the ratio of the brightness of the current frame image to the brightness of the next frame image in the consecutive multi-frame images is the same as the ratio of the duty cycle of the pulse signal forming the current frame image to the duty cycle of the pulse signal forming the next frame image.

[0031] In some embodiments, the number of pulses in the data signal that forms a frame of an image is 4.

[0032] In some embodiments, the duty cycle of the pulse signal is greater than or equal to 9%.

[0033] Fourthly, a computer-readable storage medium is provided, which stores computer instructions executable on a processor, wherein the computer instructions, when executed by the processor, implement one or more steps of the dimming method of the vehicle display device as described in any of the above embodiments.

[0034] Fifthly, a computer program product is provided that, when run on a computer, causes the computer to perform one or more steps of the dimming method for an in-vehicle display device as described in any of the above embodiments. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0036] Figure 1 A structural diagram of a display device provided for some embodiments of this disclosure;

[0037] Figure 2 A circuit diagram of a control system provided for some embodiments of this disclosure;

[0038] Figure 3 A circuit diagram of a timing control sub-circuit provided for some embodiments of this disclosure;

[0039] Figure 4 A circuit diagram of another control system provided for some embodiments of this disclosure;

[0040] Figure 5 Flowcharts of the operation of the control system provided for some embodiments of this disclosure;

[0041] Figure 6 A step diagram illustrating a dimming method for a display device provided in some embodiments of this disclosure;

[0042] Figure 7 Structural diagrams of a display panel provided for some embodiments of this disclosure;

[0043] Figure 8 A process diagram of a first jitter algorithm provided for some embodiments of this disclosure;

[0044] Figure 9 A process diagram of a second jitter algorithm provided for some embodiments of this disclosure;

[0045] Figure 10 A process diagram of a third jitter algorithm provided for some embodiments of this disclosure;

[0046] Figure 11 Structural diagrams of gamma curves of partial display panel brightness provided for some embodiments of this disclosure;

[0047] Figure 12 A structural diagram of multiple gamma segments of a register value-grayscale brightness value is provided for some embodiments of this disclosure;

[0048] Figure 13 A structural diagram of multiple gamma segments of another register value—grayscale brightness value—provided for some embodiments of this disclosure;

[0049] Figure 14 A step diagram illustrating a gamma voltage generation method provided for some embodiments of this disclosure;

[0050] Figure 15 A process diagram of a fourth jitter algorithm provided for some embodiments of this disclosure;

[0051] Figure 16 A process diagram of a fifth jitter algorithm provided for some embodiments of this disclosure;

[0052] Figure 17 A process diagram of a sixth jitter algorithm provided for some embodiments of this disclosure;

[0053] Figure 18 The diagram shows the structure of the enable signal of the display panel at different brightness levels, as provided in some embodiments of this disclosure. Detailed Implementation

[0054] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0055] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0056] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0057] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0058] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0059] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0060] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0061] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0062] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0063] As used herein, “about,” “approximately,” or “approximately” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] Some embodiments of this disclosure provide a display device, which may be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, in-vehicle computer, wearable display device, etc. Figure 1 As shown, the display device 1000 can be, for example, an in-vehicle display, and the display device 1000 includes a display panel 100. Embodiments of this disclosure are described using an in-vehicle display as an example.

[0066] In some embodiments, the display device 1000 includes a display panel 100 and a control system. The display panel 100 can be an OLED display panel, and the following description uses an OLED display panel as an example. The control system is used to drive the display panel 100 to operate. The control system may include a source driver sub-circuit, a timing controller, and a level shifter, etc. In consumer-specification products, control systems often use highly integrated chips to reduce product size and cost. For example, the source driver sub-circuit, timing controller, and level shifter of display devices such as mobile phones and televisions often use highly integrated chips. The high integration and high complexity of the chips may lead to a risk of reduced reliability and a significant decrease in service life. Overall, the reliability of the control system decreases, and correspondingly, the reliability of the display device 1000 decreases, resulting in a significant reduction in product lifespan.

[0067] In-vehicle displays have very high requirements for product lifespan and reliability, with a service life of at least 10 years. The aforementioned consumer-grade products cannot meet the performance requirements of in-vehicle displays.

[0068] Based on this, some embodiments of this disclosure provide a control system 200, such as... Figure 2 As shown, the control system 200 includes: a timing control subcircuit 210, a gamma register subcircuit 220, a source driver subcircuit 230, a power management subcircuit 240, and a level shifting subcircuit 250. The timing control subcircuit 210 is electrically connected to the gamma register subcircuit 220 and the source driver subcircuit 230; the gamma register subcircuit 220 and the source driver subcircuit 230 are electrically connected; the power management subcircuit 240 is electrically connected to the timing control subcircuit 210, the gamma register subcircuit 220, and the source driver subcircuit 230; and the level shifting subcircuit 250 is electrically connected to the timing control subcircuit 210 and the power management subcircuit 240.

[0069] The timing control sub-circuit 210 is configured to read pre-stored binding point data and generate a voltage binding point signal 211, transmit the voltage binding point signal 211 to the gamma register sub-circuit 220, and receive N gamma voltages provided by the source driver sub-circuit 230 and generate M register values, where M is greater than N. The timing control sub-circuit 210 is also configured to transmit the register values ​​to the source driver sub-circuit 230 in response to a signal received at the client assembly.

[0070] The gamma register subcircuit 220 is configured to generate an analog gamma voltage signal 221 and transmit it to the source driver subcircuit in response to a first operating voltage 241 received at the power management subcircuit 240 and a voltage binding signal 211 received at the timing control subcircuit 210.

[0071] The source drive sub-circuit 230 is configured to receive a plurality of analog gamma voltage signals 221 and generate a plurality of gamma voltages between two adjacent analog gamma voltage signals 221, and generate a data signal 231 and transmit it to the display panel 100 in response to receiving a register value signal 212 at the timing control sub-circuit 210.

[0072] The power management subcircuit 240 is configured to generate a first operating voltage 241 and transmit it to the gamma register subcircuit 220, and to generate an operating voltage and transmit it to the timing control subcircuit 210 and the source drive subcircuit 230.

[0073] The level shift sub-circuit 250 is configured to generate a second signal 251 and transmit it to the display panel 100 in response to the timing control signal 213 received at the timing control sub-circuit 210 and based on the high / low level signal 242 received at the power management sub-circuit 240.

[0074] In some examples, the timing control subcircuit 210 communicates with the gamma register subcircuit 220 via a serial communication bus. For instance, the timing control subcircuit 210 and the gamma register subcircuit 220 can communicate using an Inter-Integrated Circuit (IIC) bus. The timing control subcircuit 210 and the source driver subcircuit 230 are electrically connected via a Mini-LVDS interface to achieve the purpose of transmitting electrical signals from the timing control subcircuit 210 to the source driver subcircuit 230.

[0075] The power management subcircuit 240 generates various voltages and provides them to the corresponding modules. For example, the power management subcircuit 240 provides a second operating voltage 243 to the timing control subcircuit 210; for instance, the voltage of the second operating voltage 243 can be 1.8V and 1.1V. The power management subcircuit 240 provides a first operating voltage 241 to the source drive subcircuit 230, a third operating voltage 244 to the gamma register subcircuit 220, a high / low level signal 242 to the level shifting subcircuit, and a reset signal 245 to the display panel 100. The power management subcircuit 240 can supply power to other modules via connection traces fixed to the substrate or printed circuit board, or via a flexible circuit board.

[0076] In some examples, the gamma register subcircuit 220 generates an analog gamma voltage signal 221 and transmits it to the source driver subcircuit 230. The gamma register subcircuit 220 can transmit the analog gamma voltage signal to the source driver subcircuit 230 via connection traces fixed to the substrate or printed circuit board or a flexible circuit board. Similarly, the gamma register subcircuit 220 can transmit timing control signals 213 to the level shift subcircuit 250 via connection traces fixed to the substrate or printed circuit board or a flexible circuit board.

[0077] In some embodiments of this disclosure, the timing control subcircuit 210 serves as the central control unit, responsible for data computation and processing. It receives LVDS signals and Reset signals sent by the client assembly. The source drive subcircuit 230 receives the register value signal 212 transmitted by the timing control subcircuit 210. The source drive subcircuit performs digital-to-analog conversion on the register value signal 212 and transmits it to the display panel 100. The source drive subcircuit 230 and the timing control subcircuit 210 communicate via a Mini-LVDS interface. Each module is responsible for a single function, and each module has a low integration level, thus ensuring high reliability for each module. The cascaded low-integration, single-function modules form a complete system, which exhibits more stable performance compared to a highly integrated, multi-functional single module. In other words, a control system composed of low-integration, single-function modules has higher stability and reliability than a control system composed of highly integrated, multi-functional single modules, thereby significantly improving the stability of the vehicle-mounted display device.

[0078] In some embodiments, such as Figure 3 and Figure 4 As shown, the timing control sub-circuit 210 includes at least: a first memory 214, a timing control chip 215, and a second memory 216. The first memory 214 is configured to pre-store binding point data. The timing control chip 215 is electrically connected to the first memory 214 and includes at least a jitter calculation module 217 capable of performing jitter algorithms. The timing control chip 215 is configured to read the binding point data from the first memory 214, generate voltage binding point signals, and receive N gamma voltages transmitted from the source driver sub-circuit, generate and store M register values. The timing control chip 215 is also configured to read the register values ​​and transmit them to the source driver sub-circuit in response to signals received at the client assembly. The second memory 216 is electrically connected to the timing control chip 215 and is configured to receive and store the M register values ​​transmitted by the timing control chip 215.

[0079] In some examples, the first memory 214 can be an electrically erasable programmable read-only memory (EEPROM), which can be used to store pre-stored binding point data. The control system can read the pre-stored binding point data and generate register values ​​through data calculation. The second memory 216 can be an encoded flash memory (FLASH chip), which can be used to store register values. The control system can read the stored register values ​​and control the brightness of the display panel according to the data from the client assembly.

[0080] The first memory 214 stores data that is less prone to loss, but its read / write speed is relatively slow, and its memory size is small. The second memory 216, on the other hand, has a faster data read speed and a relatively larger memory size. The binding point data, as pre-stored data, is rarely read during normal operation of the vehicle display device, and its content is relatively small, requiring little storage space; therefore, the first memory 214 is suitable. The register values, however, contain relatively more data and require more storage space, and are frequently read during vehicle display device operation; therefore, the register values ​​are suitable for storage in the second memory 216. The first memory 214 and the second memory 216 do not interfere with each other, further improving the reliability of the control system, and both are suitable for storing their respective data.

[0081] In some embodiments, such as Figure 4 As shown, the gamma register sub-circuit 220 includes at least a gamma chip 222, which is electrically connected to the timing control chip 215, the source driver sub-circuit 230, and the power management sub-circuit 240. The gamma chip 222 is configured to generate an analog gamma voltage signal 221 and transmit it to the source driver sub-circuit 230 in response to a voltage binding point signal 211 received at the timing control chip 215 and a first voltage signal 241 received at the power management sub-circuit 240.

[0082] For example, the gamma register sub-circuit 220 includes a gamma chip 222 and a step-down converter. The step-down converter is electrically connected to the gamma chip 222. The gamma chip 222 reads the voltage binding point signal and generates a set of voltages arranged in ascending order through the step-down converter from the received first voltage signal 241. This set of voltages arranged in ascending order can be, for example, analog gamma voltage signals GM1, GM2, GM3, GM4, GM5, GM6, GM7, GM8, and GM9. The analog gamma voltage signals 221 (GM1 to GM9) are also transmitted by the gamma chip 222 to the source driver sub-circuit for calculation.

[0083] In some embodiments, such as Figure 4 As shown, the source driver sub-circuit 230 includes at least a source driver chip 232 and multiple resistors connected in series. The multiple resistors in series form a resistor string, and both ends of the resistor string can be electrically connected to the source driver chip 232. Each resistor in the resistor string can have a gamma voltage output terminal at both ends. The source driver chip 232 is electrically connected to the timing control chip 215 and the gamma chip 222. The source driver chip 232 is configured to receive the analog gamma voltage signal 221 output by the gamma chip 222 and generate a gamma voltage; and to receive the signal output by the timing control chip 215 and transmit a data signal to the display panel 100.

[0084] In some examples, the source driver chip 232 receives the analog gamma voltage signal 221 transmitted by the gamma chip 222. For example, the source driver chip 232 receives analog gamma voltage signal GM1 and analog gamma voltage signal GM2. The analog gamma voltage signal GM1 and analog gamma voltage signal GM2 are transmitted one-to-one to the two ends of the resistor string, and the voltage across each resistor in the resistor string is a gamma voltage.

[0085] In some embodiments, such as Figure 4 As shown, the power management sub-circuit 240 includes at least a power management chip 246, which is electrically connected to the timing control chip 215, the gamma chip 222, the source driver chip 232, the level shift sub-circuit 250, and the display panel 100.

[0086] The power management chip 246 is configured to provide an operating voltage to the timing control chip 215, a second voltage signal 241 to the gamma chip 222, a second operating voltage 244 to the source driver chip 232, a high / low level signal 242 to the level shift sub-circuit 250, and a reset signal 245 to the display panel 100.

[0087] In some examples, the power management chip 246 is used to generate the various voltages required by the control system and provide these voltages to the corresponding chips or modules to enable the control system to operate normally. For example, the power management chip 246 can provide operating voltages of 1.8V and 1.1V to the timing control chip 215. The power management chip 246 can also provide a second operating voltage 244 to the gamma chip 222 and the source driver chip 232. The first voltage signal 241 generates analog gamma voltage signals 221 (GM1 to GM9) under the control of the gamma chip 222, and the second operating voltage 244 is used as the operating voltage in the source driver chip 232.

[0088] In some embodiments, such as Figure 4As shown, the control system also includes a level shift chip 252, which is electrically connected to the timing control chip 215 and the power management sub-circuit 240 respectively. The level shift chip 252 is configured to generate a second signal 251 in response to the signal received by the timing control chip 215 and transmit it to the display panel.

[0089] In some examples, the level shifting chip 252 receives the signal transmitted by the timing control chip 215, generates a second signal 251, and transmits it to the gate on array (GOA) circuit on the display panel 100. The second signal 251 may be, for example, a clock signal, a start signal, etc.

[0090] The second signal 251 can control the operation of the GOA circuit on the display panel 100. The source driver chip 232 transmits data signal 231 to the display panel 100. The second signal 251 and the data signal 231 work together to control the operation of the display panel 100.

[0091] In this disclosure, the various modules of the control system operate in coordination with each other, such as... Figure 5 The operation flow of the control system is shown.

[0092] Specifically, the gamma chip 222 receives the first operating voltage 241, and the timing control chip 215 reads the pre-stored binding point data in the first memory 214 and generates a voltage binding point signal, which is then transmitted to the gamma chip 222. The gamma chip 222 generates nine analog gamma voltage signals 221 (GM1 to GM9). After passing through the source driver chip 232, two adjacent analog gamma voltage signals 221 are divided by multiple series voltages to generate 256 gamma voltages. The timing control chip 215 receives the 256 gamma voltages. A portion of the timing control chip 215 serves as a jitter calculation module 217, which converts the 256 gamma voltages into 1024 register values ​​through jitter calculation. The timing control chip 215 and the external fixture 260 perform gamma adjustment so that the display panel generates corresponding gamma curves based on the register values ​​under different brightness levels and stores them in the second memory 216. Among them, the external fixture 260 is a debugging device set in the production line to debug the monitor or display panel so that the display effect meets the standard after leaving the factory.

[0093] On the other hand, some embodiments of this disclosure also provide an in-vehicle display device, including a control system as described in any of the above embodiments and a display panel. The display panel is electrically connected to the control system.

[0094] In some embodiments, the control system is used to drive the display panel to operate. Under the premise of high reliability of the control system, the display device has high reliability and long life, which meets the high requirements of vehicle display for product life and reliability.

[0095] Of course, the vehicle-mounted display device provided in this disclosure can also be applied to other places besides vehicles, such as trains, ferries, and other places where the lifespan and reliability of the display are required to be high. Alternatively, the control system used in the vehicle-mounted display device provided in this disclosure can also be applied to other displays with high lifespan and reliability requirements.

[0096] In some embodiments, the low-integration source driver chip outputs a low number of gray levels, only 8 bits. For example, the source driver chip can only generate 256 voltage values, which are arranged in ascending order of their values ​​as voltage value V1, voltage value V2... voltage value V256, with each voltage value corresponding to one gray level.

[0097] Typically, OLED display panels have a brightness adjustment range, allowing the display brightness to vary within this range. To ensure clear color differentiation at different brightness levels, grayscale values ​​are matched with corresponding voltage values. Specifically, at higher brightness levels, the voltage value corresponding to the grayscale of the brightest pixel in the display panel is the highest among 256 voltage values. At this brightness, the voltage values ​​selectable for other pixels in the display panel should be lower than the voltage value corresponding to the grayscale of the brightest pixel. In other words, at higher brightness, the range of selectable voltage values ​​for grayscale is larger, while at lower brightness, the range is smaller. Especially at lower brightness, because the number of selectable voltage values ​​for grayscale is limited, the display panel cannot effectively differentiate colors. For example, when the display brightness is low, the voltage value corresponding to the grayscale of the brightest pixel of the display panel is low. The voltage value corresponding to the grayscale of the brightest pixel of the display panel can be a voltage value V100, a voltage value V80, or a voltage value V50. That is to say, when the display brightness is low, the voltage value corresponding to the grayscale of each pixel of the display panel can be selected from the range of voltage value V1 to voltage value V100, the range of voltage value V1 to voltage value V80, or the range of voltage value V1 to voltage value V50.

[0098] Taking the example that the voltage value corresponding to the grayscale of each pixel on the display panel can be selected within the range of voltage value V1 to voltage value V100, grayscale adjustment can be performed within this range of voltage value V1 to voltage value V100 at this display brightness. Each voltage value corresponds to one grayscale, with the grayscale value corresponding to voltage value V1 being the lowest (lowest brightness) and the grayscale value corresponding to voltage value V100 being the highest (highest brightness). In other words, at this display brightness, the brightness of each pixel on the display panel can be adjusted within a range of 100 grayscale levels.

[0099] It is understandable that the number of gray levels corresponding to each pixel of the display panel is relatively small. When the image is displayed, the gray levels and the actual colors of the image may not match well, which may cause the colors of the displayed image to be indistinguishable. Therefore, color shift may occur under different display brightness.

[0100] Based on this, in another aspect, some embodiments of this disclosure also provide a dimming method for an in-vehicle display device, such as... Figure 6 As shown, the dimming method of the vehicle display device, applied to any of the above embodiments, includes:

[0101] S1. Generate multiple gamma voltages arranged in descending or ascending order;

[0102] S2. Based on multiple gamma voltages, a jitter algorithm is used to generate multiple register values;

[0103] S3. Modulate the gamma curve: Generate a corresponding gamma curve based on multiple register values ​​and the brightness of the display panel.

[0104] In some examples, there are multiple gamma voltages, for example, there can be 256 gamma voltages, each gamma voltage corresponds to a gray level. That is to say, in step S1, any pixel of the display panel can be adjusted within a range of up to 256 gray levels.

[0105] In step S2, Figures 8 to 10 as well as Figures 15 to 17 The process shown illustrates the use of a dithering algorithm to expand the range of register values, where... Figures 8 to 10 This demonstrates a method for implementing a dithering algorithm. Figures 15 to 17 This demonstrates another method of jittering algorithm.

[0106] like Figure 7As shown, the display panel includes a display area AA and a peripheral area BB disposed at least on one side of the display area. Multiple pixels P are arrayed within the display area AA, and each pixel P includes multiple sub-pixels. During the display process, the multiple sub-pixels are scanned line by line. Each sub-pixel, under the control of different data signals, forms different light emission brightness, that is, each sub-pixel generates different gray levels. In this way, all sub-pixels generate an image on the display panel.

[0107] For an 8-bit automotive display device, there are 256 gray levels, while for a 10-bit automotive display device, there are 1024 gray levels. Therefore, the higher the bit depth of an automotive display device, the larger the gray level range, and the smoother the brightness variations in the image. For 8-bit automotive displays, a dithering algorithm can be used to increase the number of gray levels.

[0108] Dithering, or dithering, refers to controlling the grayscale of a pixel or adjacent pixels in adjacent frames through temporal or spatial means to create grayscale levels that would otherwise be impossible to produce on the entire screen, thus expanding the number of grayscale levels. In other words, dithering can divide the original 256 grayscale levels into a larger number of new grayscale levels, with each new grayscale level corresponding to a register value. Each new grayscale level can be understood as a superposition of multiple original grayscale levels; that is, one register value corresponds to one new grayscale level, and one new grayscale level is a superposition of multiple original grayscale levels corresponding to a set of gamma voltages. For ease of distinction, the grayscale level corresponding to the register value will be referred to as a virtual grayscale level below.

[0109] like Figures 8 to 10 As shown, taking the spatial control of grayscale of adjacent pixels as an example, two adjacent pixels can be selected as a group, namely the first pixel P1 and the second pixel P2. The grayscale of each pixel can be either one of two consecutive grayscale levels. Thus, the grayscale of the first pixel P1 can be grayscale Gx, and the grayscale of the second pixel P2 can also be grayscale Gx, meaning the virtual grayscale of the two adjacent pixels is Gx; or, the grayscale of the first pixel P1 can be grayscale Gy, and the grayscale of the second pixel P2 can also be grayscale Gy, meaning the virtual grayscale of the two adjacent pixels is Gy; or, the grayscale of the first pixel P1 can be grayscale Gx, and the grayscale of the second pixel P2 can also be grayscale Gy, meaning the virtual grayscale of the two adjacent pixels is a mixture of one Gx and one Gy. In this way, the number of virtual grayscale levels for two adjacent pixels is twice the number of original grayscale levels. That is, when the total number of grayscale levels is 256, the number of virtual grayscale levels is 512.

[0110] Alternatively, four adjacent pixels can be selected as a group, with the four adjacent pixels being, in sequence, pixel P1, pixel P2, pixel P3, and pixel P4. The grayscale of each pixel can be any one of two consecutive grayscale levels. For example, the grayscale of pixel P1 can be Gx, the grayscale of pixel P2 can be Gy, and the grayscale of both pixels P1 and P4 can be Gy. In this case, the virtual grayscale of the four adjacent pixels can be a mixture of one grayscale level Gx and three grayscale levels Gy. Alternatively, the grayscale of pixel P1 can be Gx, the grayscale of pixel P2 can be Gx, the grayscale of both pixels P3 and P4 can be Gy, and the virtual grayscale of the four adjacent pixels can be a mixture of two grayscale levels Gx and two grayscale levels Gy. Alternatively, the gray level of the first pixel P1 can be gray level Gx, the gray level of the second pixel P2 can be gray level Gx, the gray level of the third pixel P1 can be gray level Gx, and the gray level of the fourth pixel can be gray level Gy. Then the virtual gray levels of the four adjacent pixels can be a mixture of three gray levels Gx and one gray level Gy.

[0111] Thus, three additional virtual gray levels are added to gray levels Gx and Gy. The number of virtual gray levels is three times greater than the number of gray levels corresponding to the gamma voltage, meaning the number of virtual gray levels is four times the number of gray levels corresponding to the gamma voltage. Specifically, when the total number of gray levels is 256, the number of virtual gray levels is 1024. The register values ​​are arranged in ascending order of their corresponding brightness, as register value J0, register value J1... register value J1023. This expands the number of register values ​​from 8 bits to 10 bits, resulting in 1024 new register values.

[0112] In some embodiments, such as Figure 11 As shown, the adjustable brightness value (DBV) of the display panel controls the display brightness, and each DBV corresponds to a different gamma curve.

[0113] Because the human eye is much more sensitive to brightness in darker environments than to brightness in brighter environments, the relationship between human eye perception and brightness is not linear, but rather follows a certain pattern. Figure 11A gamma curve is shown, where the horizontal axis represents the brightness output by a pixel or the grayscale displayed externally (hereinafter referred to as grayscale), and the vertical axis represents the corresponding grayscale brightness value output by the pixel. In this disclosure, the grayscale brightness value refers to the perceived brightness of different grayscale levels under different brightness levels of the display panel. To make the display effect of the OLED display device conform to the visual perception of the human eye, the relationship between the input grayscale and the corresponding output grayscale brightness value needs to be set such that the grayscale brightness value is proportional to the grayscale level raised to the power of γ. This relationship between the grayscale brightness value and the grayscale is called the gamma curve of the automotive display device. For example, the value of γ is set to 2.2 ± 0.2 to make the displayed image close to what the human eye actually sees.

[0114] Each brightness value of the display panel corresponds to a different gamma curve. Accordingly, in the coordinate system of register value-grayscale brightness value, each brightness value corresponds to a gamma band, and each gamma band includes 256 gray levels. The gamma curves of different gamma bands correspond to different brightness of the display panel. For example, the gamma curve of one gamma band can correspond to the case where the brightness of the display panel is 5 nits, or the gamma curve of another gamma band can correspond to the case where the brightness of the display panel is 800 nits.

[0115] The grayscale brightness value corresponding to the gamma band gamma curve can be matched with the corresponding register value, such as... Figure 12 As shown, there are a total of 256 register values. Each gamma voltage corresponds to one register value, and each register value can represent a gray level (brightness). Therefore, the gray level on the horizontal axis can be replaced with the register value.

[0116] Similarly, such as Figure 13 As shown, there are a total of 1024 register values, each representing a virtual grayscale (brightness). The virtual grayscale on the horizontal axis can be replaced with register values.

[0117] like Figure 12 and Figure 13 As shown, the display panel is matched with the corresponding gamma band at different brightness levels. The register value of the gamma band corresponding to the display panel at high brightness is larger than the register value of the gamma band corresponding to the display panel at low brightness. Therefore, the grayscale of the display panel at low brightness cannot be fully matched with the register value, resulting in unclear color differentiation at low brightness and potentially causing color shift in the displayed image.

[0118] Figure 13 By expanding the range of register values, even at low brightness, the grayscale of the display panel matches sufficient register values, making color distinctions clear and the color fidelity of the displayed image high.

[0119] It should be noted that, Figure 12 and Figure 13When the values ​​of the registers in the system are the same, their corresponding gray levels and virtual gray levels (brightness) are not the same. Figure 12 The register value in the value has 256 brightness levels between the darkest and brightest. Figure 13 The register value has 1024 brightness levels between the darkest and brightest.

[0120] It is understandable that the register values ​​corresponding to the 256 gray levels in this gamma band are between register value J0 and the register value that matches the maximum brightness of the pixel corresponding to the gamma curve of the gamma band. The maximum register value in the gamma curve of the gamma band varies depending on the brightness of the display panel, therefore the range of register values ​​for searching the 256 gray levels of each gamma curve is different.

[0121] For example, the highest brightness of the gamma segment corresponding to a gamma curve with a brightness of 800 nits matches the register value J950, ​​and the 256 gray levels of the gamma curve with a brightness of 800 nits can be found within the range of register values ​​J0 to J950. ​​Alternatively, the highest brightness of the gamma segment corresponding to a gamma curve with a brightness of 300 nits matches the register value J400, and the 256 gray levels of the gamma curve with a brightness of 300 nits can be found within the range of register values ​​J0 to J400.

[0122] By employing a dithering algorithm, the range of register values ​​is expanded, such as... Figure 13 As shown, the display panel displays gamma curves corresponding to different brightness levels. Each gamma segment of the curve corresponds to 256 gray levels, and each gray level can be matched with a corresponding register value. This allows the entire control system to provide 10 bits of register value, enabling the display panel to display previously unavailable gray levels, even when the low-integration source driver chip can only provide 8 bits of gray levels. Overall, this expands the number of gray levels. Consequently, the display panel maintains a consistent color accuracy at different brightness levels, preventing color shifts and ensuring minimal color shifts, thus providing high-quality display images even with low-integration hardware.

[0123] In some embodiments, the power management subcircuit of the control system is configured to provide a first voltage signal to the gamma register subcircuit of the control system, and the timing control subcircuit of the control system is configured to provide a plurality of voltage binding point signals to the gamma register subcircuit.

[0124] like Figure 14 As shown, the gamma voltage generation method includes:

[0125] S11. Generate multiple simulated gamma voltages based on the first voltage signal and multiple voltage binding point signals, with each voltage binding point signal corresponding to a simulated gamma voltage.

[0126] S12. Two adjacent simulated gamma voltages are respectively set across the two ends of multiple resistors connected in series. The voltage between the two ends of each resistor is a gamma voltage. Two adjacent simulated gamma voltages generate multiple gamma voltages arranged in ascending order.

[0127] In some examples, the gamma register subcircuit receives voltage binding signals and generates multiple analog gamma voltages through a step-down converter based on the first voltage signal. Each voltage binding signal corresponds to one analog gamma voltage. For example, there can be nine voltage binding signals, and correspondingly, there are nine analog gamma voltages. The nine analog gamma voltages are arranged in ascending order of voltage value as follows: analog gamma voltage GM1, analog gamma voltage GM2, analog gamma voltage GM3... analog gamma voltage GM9.

[0128] The gamma register subcircuit transmits the analog gamma voltage to the source driver subcircuit. The source driver subcircuit obtains the gamma voltage using a resistor series voltage divider. Specifically, the source driver subcircuit includes a circuit with multiple resistors connected in series, for example, 32 resistors. Two adjacent analog gamma voltages are transmitted to the two ends of the circuit with multiple resistors connected in series, and the voltage across each resistor is one gamma voltage. For example, analog gamma voltage GM1 is transmitted to one end of the circuit with multiple resistors connected in series, and analog gamma voltage GM2 is transmitted to the other end of the circuit with multiple resistors connected in series. The circuit has 32 resistors, and the voltage across each resistor is one gamma voltage. Thus, 32 gamma voltages can be generated between analog gamma voltages GM1 and GM2. This can generate eight sets of gamma voltages, each set of gamma voltages being generated by voltage divider between two adjacent analog gamma voltages, with each set containing 32 gamma voltages, for a total of 256 gamma voltages.

[0129] It should be noted that the embodiments of this disclosure do not limit the number of analog gamma voltages generated by the gamma register subcircuit, nor do they limit the number of gamma voltages generated by each resistor string in the source driver subcircuit. It is understood that the total number of gamma voltages is the product of the number of analog gamma voltages and the number of resistors in a resistor string. The total number of gamma voltages should match the number of gray levels in the grayscale image; for example, the total number of gamma voltages can be 16, 32, or 256. In this disclosure, the number of gamma voltages can be extended to 256.

[0130] By controlling the voltage binding point signal, the voltage between two adjacent analog gamma voltages can be controlled, thereby controlling the gamma voltage accuracy (or the magnitude of the gamma voltage). This disclosure can use hardware with low integration to generate high-precision gamma voltages and can relatively control the magnitude of the gamma voltage.

[0131] In some embodiments, the dithering algorithm includes: a plurality of adjacent pixels on the display panel are a pixel group, the gray level of each pixel in the pixel group corresponds to one of a plurality of gamma voltages, and the gray level value of the pixel group is the average of the gray level values ​​of the plurality of pixels.

[0132] The gamma voltage of multiple pixels corresponding to the gray level of a pixel group is a register value corresponding to the gray level of the pixel group.

[0133] In some examples, the dithering algorithm can spatially control adjacent pixels, allowing the overall grayscale of adjacent pixels to exhibit multiple grayscale levels. This method has already been described above and will not be repeated here.

[0134] In other embodiments, such as Figures 15 to 17 As shown, the dithering algorithm includes: the average grayscale value of a pixel on the display panel in each frame of a series of consecutive images, which is the display grayscale of any pixel. The gamma voltage corresponding to the grayscale of any pixel in a series of consecutive images is a register value corresponding to the display grayscale.

[0135] In some embodiments, within at least two adjacent frames, the grayscale values ​​of any pixel are the same and / or consecutive, and the number of register values ​​is at least 512.

[0136] In some examples, the dithering algorithm can also use a time-based approach to control the grayscale of pixels when displaying adjacent frames of the image.

[0137] For example, if two adjacent frame images are selected, and any pixel in the display panel has a gray level of Gx in the first frame image and a gray level of Gy in the second frame image, then the virtual gray level of the pixel as a whole in the display of the two adjacent frames can be a mixed state of a gray level Gx and a gray level Gy.

[0138] Alternatively, if any pixel in the display panel has a grayscale of Gx in the first frame and a grayscale of Gx in the second frame, then the virtual grayscale of that pixel in the display of the two adjacent frames can be grayscale Gx.

[0139] Alternatively, if any pixel in the display panel has a grayscale of Gy in the first frame and a grayscale of Gy in the second frame, then the virtual grayscale of that pixel in the display of the two adjacent frames can be a grayscale of Gy.

[0140] Thus, the number of virtual gray levels is twice that of the number of gray levels corresponding to the gamma voltage; that is, when the number of gray levels is 256, the number of virtual gray levels is 512.

[0141] In other examples, four adjacent frame images are selected. Any pixel in the display panel has a gray level of Gx in the first frame image, Gy in the second frame image, Gy in the third frame image, and Gy in the fourth frame image. Then, the virtual gray level of the pixel in the display of the four adjacent frames can be a mixture of one gray level Gx and three gray levels Gy.

[0142] Alternatively, if any pixel in the display panel has a grayscale of Gx in the first frame, Gx in the second frame, Gy in the third frame, and Gy in the fourth frame, then the virtual grayscale of that pixel in the four adjacent frames can be a mixture of two grayscales Gx and two grayscales Gy.

[0143] Alternatively, if any pixel in the display panel has a grayscale of Gx in the first frame, Gx in the second frame, Gx in the third frame, and Gy in the fourth frame, then the virtual grayscale of that pixel in the four adjacent frames can be a mixture of three grayscale Gx and one grayscale Gy.

[0144] Thus, the number of virtual gray levels is three times greater than the number of gray levels corresponding to the gamma voltage. In other words, the number of virtual gray levels is four times the number of gray levels corresponding to the gamma voltage. That is, when the number of gray levels is 256, the number of virtual gray levels is 1024. The register values, representing brightness from smallest to largest, are register value J0, register value J1... register value J1023. The range of register values ​​is expanded from 8 bits to 10 bits, and the number of register values ​​is 1024.

[0145] Under different display brightness levels, the pixels of the display panel need to adjust their grayscale within a certain range of register values ​​to achieve a certain display brightness without causing color shift in the displayed image. Specifically, under different display brightness levels, the pixel with the largest grayscale value in the display panel should decrease as the display brightness decreases. Correspondingly, as the display brightness decreases, the range of selectable virtual grayscale values ​​for the pixels in the display panel decreases, that is, the range of selectable register values ​​for the pixels in the display panel decreases.

[0146] The embodiments of this disclosure extend the range of register values ​​to 10 bits. However, when the display panel is in low grayscale, the range of register values ​​that can be selected for the pixels in the display panel is small. In this state, the image formed by the display panel may have color shift.

[0147] Based on this, the dimming method for the vehicle display device provided in some embodiments of this disclosure further includes:

[0148] H1. The vehicle-mounted display device modulates the data signal from a continuous signal into a pulse signal;

[0149] H2. Based on the duty cycle of the pulse signal and the brightness of the display panel, the maximum register value corresponding to the pixel of the display panel is selected, and the corresponding gamma curve is selected based on the maximum register value corresponding to the pixel.

[0150] In some examples, the pixel brightness (grayscale) of the display panel can be controlled by modulating the power of the data signal. At low brightness, the range of selectable virtual grayscale values ​​for each pixel is small. For example, as shown in Table 1, the number of first register values ​​in Table 1 refers to the number of selectable register values ​​for each pixel of the display panel when the data signal output by the control system is a continuous signal at the corresponding display panel brightness. The number of second register values ​​in Table 1 refers to the number of selectable register values ​​for each pixel of the display panel when the data signal output by the control system is modulated into a pulse signal at the corresponding display panel brightness. The duty cycle mentioned in Table 1 refers to the duty cycle when the data signal output by the control system is modulated into a pulse signal.

[0151]

[0152] Table 1

[0153] For example, when the display panel is dimmed to 5 nits and the data signal output by the control system is a continuous signal, the pixels can be selected from six virtual gray levels. In other words, at this time, the displayed image may experience color shift due to the limited number of virtual gray levels.

[0154] While the overall brightness of a pixel decreases within a single image frame, the brightness of a pixel after receiving each pulse signal is higher than the overall brightness within that frame. In other words, when the brightness of the display panel decreases, the instantaneous brightness of the pixel increases. Therefore, using the display panel dimming method provided in this disclosure, the display panel should reference the gamma curve corresponding to the instantaneous brightness of the pixel at a given brightness level. Because the instantaneous brightness is higher than the brightness of the display panel, the range of selectable virtual grayscale levels for the pixel is expanded. This means that using the display panel dimming method provided in this disclosure, the range of register values ​​for the display panel will be significantly improved at low brightness levels.

[0155] For example, when the display panel is 5 nits and the display panel dimming method provided in this disclosure is not used, the pixels can select values ​​from six register values. After using the display panel dimming method provided in this disclosure, the duty cycle of the pulse signal is 9%, and the pixels can select values ​​from 69 register values.

[0156] For example, as shown in Table 1, the data signal is modulated from a continuous signal to a pulse signal. This reduces the overall brightness of the pixels within a single frame, achieving a reduction of 5 nits in the display panel brightness. The instantaneous brightness of each pixel during emission is higher than 5 nits, meaning the range of virtual grayscale options for the pixels can be wider. For instance, when the duty cycle of the pulse signal (data signal) is 9%, the display panel brightness is 5 nits, and the number of selectable virtual grayscale levels for the pixels is 69. In this case, the displayed image has greater color differentiation, and color shift is significantly improved.

[0157] The pixels have a wider range of register values. Using the display panel dimming method provided in this disclosure, the picture is clearer and the color shift phenomenon is significantly improved when the display panel is at low brightness.

[0158] In some embodiments, when the brightness of the display panel changes, the brightness of consecutive frames of images gradually decreases or increases. When the gamma curve corresponding to the display brightness is constant, the ratio of the brightness of the current frame to the brightness of the next frame in consecutive frames of images is the same as the ratio of the duty cycle of the data signal forming the current frame to the duty cycle of the data signal forming the next frame.

[0159] In some examples, during actual use of the in-vehicle display device, the user adjusts the display brightness of the in-vehicle display device (e.g., by dragging the brightness slider on the display screen of the in-vehicle display device to adjust the display brightness of the display screen), or the in-vehicle display device automatically adjusts its own display brightness in response to changes in ambient brightness.

[0160] To prevent abrupt brightness changes during the adjustment of brightness in vehicle-mounted display devices or display panels, multiple consecutive frames can be used to gradually decrease or increase brightness. By maintaining a constant gamma curve corresponding to the display panel's brightness and controlling the duty cycle, the brightness of multiple frames can be controlled; specifically, a larger duty cycle results in lower image brightness. Therefore, the change in the duty cycle of the data signal forming each frame should not be too large to avoid abrupt brightness changes.

[0161] In some embodiments, the way the vehicle display device modulates the data signal into a pulse signal can be by the source driver sub-circuit converting the data signal into a pulse signal, or by the level shift sub-circuit transmitting a control signal to the GOA circuit. The enable signal output by the GOA circuit can control the conduction and cutoff of the current path of the data signal transmission to the pixel driver circuit, thereby realizing the continuous data signal modulation into a pulse signal.

[0162] In some embodiments, the number of pulses in the data signal that forms a frame of an image is 4. For example, the data signal that forms each frame of an image in an automotive OLED display device includes 4 pulses.

[0163] For example, such as Figure 18 As shown, within one frame of an image, the number of pulses of the enable signal EM, which controls the transmission of data signals to the current path of the pixel driving circuit, is four. For example, combined with... Figure 18 As shown in Table 1, when the duty cycle of the enable signal EM is 97%, the corresponding brightness of the display panel can be 815 nits; when the duty cycle of the enable signal EM is 48%, the corresponding brightness of the display panel is between 390 nits and 500 nits; and when the duty cycle of the enable signal EM is 9%, the corresponding brightness of the display panel can be 5 nits. It can be understood that the duty cycle of the enable signal directly affects the duty cycle of the data signal; that is, the duty cycle of the enable signal is the same as the duty cycle of the data signal. Furthermore, when the duty cycle of the data signal is different, the power of the data signal decreases accordingly.

[0164] It should be noted that in some other types of OLED display devices, the data signal that forms a frame of an image may include 16 or 32 pulse signals, such as in a mobile phone that uses an OLED display panel.

[0165] In some embodiments, the duty cycle of the pulse signal is greater than or equal to 9%. For example, when the duty cycle of the pulse signal is 9%, the brightness of the display panel is 5 nits. A minimum brightness of 5 nits can meet the minimum brightness requirements of some display panels. However, if the duty cycle of the pulse signal is too low, it may cause the OLED display panel to emit light unstablely.

[0166] Some embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions executable on a processor, which, when executed by the processor, implement one or more steps in the dimming method for the vehicle-mounted display device described above.

[0167] It should be noted that the computer-readable storage medium provided in the embodiments of this disclosure may include, but is not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), and various other media capable of storing program code.

[0168] Some embodiments of this disclosure also provide a computer program product that, when run on a computer, causes the computer to perform one or more steps of the dimming method for the in-vehicle display device described above.

[0169] The computer storage medium or computer program product provided in this disclosure is used to execute the dimming method of the vehicle display device provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0170] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A control system, comprising: The circuit includes a timing control subcircuit, a gamma register subcircuit, a source driver subcircuit, and a power management subcircuit; wherein the timing control subcircuit is electrically connected to the gamma register subcircuit and the source driver subcircuit, the gamma register subcircuit and the source driver subcircuit are electrically connected, and the power management subcircuit is electrically connected to the timing control subcircuit, the gamma register subcircuit and the source driver subcircuit. The timing control subcircuit is configured to read pre-stored binding point data to generate a voltage binding point signal and transmit it to the gamma register subcircuit, and to receive N gamma voltages provided by the source driver subcircuit and generate M register values ​​using a jitter algorithm, wherein M is greater than N. The timing control subcircuit is also configured to transmit the register values ​​to the source driver subcircuit in response to a signal received at the client assembly. The gamma register subcircuit is configured to generate an analog gamma voltage signal and transmit it to the source driver subcircuit in response to a first voltage signal received at the power management subcircuit and a voltage binding point signal received at the timing control subcircuit. The source driving sub-circuit is configured to receive a plurality of the analog gamma voltage signals, generate a plurality of the gamma voltages between two adjacent analog gamma voltage signals, and generate a data signal and transmit it to the display panel in response to receiving a register value signal at the timing control sub-circuit; the display panel includes a plurality of pixels, the pixels include a plurality of sub-pixels, and the sub-pixels form different luminous brightness under the control of the data signal; The power management subcircuit is configured to generate a first voltage signal and transmit it to the gamma register subcircuit, and to generate an operating voltage and transmit it to the timing control subcircuit and the source driver subcircuit.

2. The control system according to claim 1, wherein, The timing control sub-circuit includes at least: The first memory is configured to pre-store binding point data; A timing control chip is electrically connected to the first memory. The timing control chip is configured to read the binding point data of the first memory, generate the voltage binding point signal, and receive N gamma voltages transmitted by the source driver sub-circuit, generate M register values ​​and store them. The timing control chip is also configured to read the register values ​​and transmit them to the source driver sub-circuit in response to a signal received at the client assembly. The second memory is electrically connected to the timing control chip and is configured to receive and store M register values ​​transmitted by the timing control chip.

3. The control system according to claim 1, wherein, The gamma register sub-circuit includes at least a gamma chip, and the gamma chip is electrically connected to the timing control chip, the source driver sub-circuit, and the power management sub-circuit. The gamma chip is configured to generate an analog gamma voltage signal and transmit it to the source driver subcircuit in response to the voltage binding signal received at the timing control chip and the first voltage signal received at the power management subcircuit.

4. The control system according to claim 1, wherein, The source driver sub-circuit includes at least a source driver chip, and the source driver chip is electrically connected to the timing control chip and the gamma chip. The source driver chip is configured to receive the analog gamma voltage signal output by the gamma chip and generate a gamma voltage; and to receive the signal output by the timing control chip and transmit a data signal to the display panel.

5. The control system according to claim 1, wherein, The power management sub-circuit includes at least a power management chip, which is electrically connected to the timing control chip, the gamma chip, the source driver chip, the level shifting sub-circuit, and the display panel. The power management chip is configured to provide an operating voltage to the timing control chip, provide a first voltage signal to the gamma chip and the source driver chip, provide a high / low level signal to the level shifting sub-circuit, and provide a reset signal to the display panel.

6. The control system according to any one of claims 1 to 5, wherein, The control system further includes a level shifting sub-circuit, which is electrically connected to the timing control sub-circuit and the power management chip.

7. The control system according to claim 6, wherein, The control system further includes a level shifting chip, which is electrically connected to the timing control chip and the power management chip respectively. The level shifting chip is configured to generate a second signal and transmit it to the display panel in response to a signal received by the timing control chip.

8. A vehicle-mounted display device, comprising: The control system as described in any one of claims 1 to 7; The display panel is electrically connected to the control system.

9. A dimming method for an in-vehicle display device, applied to the in-vehicle display device as described in claim 8, wherein the control system of the in-vehicle display device transmits data signals to the display panel; The dimming method of the vehicle-mounted display device includes: Generate multiple gamma voltages arranged in descending or ascending order; Based on the multiple gamma voltages, a jitter algorithm is used to generate multiple register values; Modulate the gamma curve by generating a corresponding segment of the gamma curve based on the multiple register values ​​and the brightness of the display panel.

10. The dimming method for an in-vehicle display device according to claim 9, wherein, The power management subcircuit of the control system is configured to provide a first voltage signal to the gamma register subcircuit of the control system, and the timing control subcircuit of the control system is configured to provide multiple voltage binding point signals to the gamma register subcircuit. The method for generating multiple gamma voltages arranged in descending or ascending order includes: Multiple simulated gamma voltages are generated based on the first voltage signal and the multiple voltage binding point signals, with each voltage binding point signal corresponding to a simulated gamma voltage. Two adjacent simulated gamma voltages are respectively set across multiple resistors connected in series. The voltage between the two ends of each resistor is a gamma voltage. The two adjacent simulated gamma voltages generate multiple gamma voltages arranged in ascending order.

11. The dimming method for an in-vehicle display device according to claim 9, wherein, The number of gamma voltages is 256.

12. The dimming method for an in-vehicle display device according to any one of claims 9 to 11, wherein, The method for generating multiple register values ​​based on multiple gamma voltages using a dithering algorithm includes: The multiple adjacent pixels on the display panel form a pixel group. The gray level of each pixel in the pixel group corresponds to one of the multiple gamma voltages. The gray level value of the pixel group is the average value of the gray level values ​​of the multiple pixels. The gamma voltage of the plurality of pixels corresponding to the gray level of the pixel group is a register value corresponding to the gray level of the pixel group.

13. The dimming method for an in-vehicle display device according to claim 12, wherein, The number of adjacent pixels in the pixel group is at least two, and the gray level values ​​of each pixel are the same and / or consecutive. The number of register values ​​is at least 512.

14. The dimming method for an in-vehicle display device according to any one of claims 9 to 11, wherein, The method for generating multiple register values ​​based on multiple gamma voltages using a dithering algorithm includes: Within a series of consecutive frames, the average grayscale value of the pixels on the display panel in each frame is the display grayscale of any pixel. The gamma voltage corresponding to the gray level of any pixel in the continuous multi-frame image is a register value corresponding to the display gray level.

15. The dimming method for an in-vehicle display device according to claim 14, wherein, Within at least two adjacent frames, the grayscale values ​​of any pixel are the same and / or continuous. The number of register values ​​is at least 512.

16. The dimming method for an in-vehicle display device according to claim 13 or 15, wherein, The control system transmits data signals to the display panel; The dimming method for the vehicle-mounted display device further includes: The vehicle-mounted display device modulates the data signal from a continuous signal into a pulse signal; Based on the duty cycle of the pulse signal and the brightness of the display panel, the maximum register value corresponding to the pixel of the display panel is determined, and the corresponding gamma curve is selected based on the maximum register value corresponding to the pixel.

17. The dimming method for an in-vehicle display device according to claim 16, wherein, The step of selecting the corresponding gamma curve based on the maximum register value corresponding to the pixel includes: The maximum value in the register corresponding to the gamma curve is consistent with the maximum register value corresponding to the pixel of the display panel.

18. The dimming method for an in-vehicle display device according to claim 16, wherein, When the brightness of multiple consecutive frames of images on the display panel decreases or increases, and the gamma curve is constant; The ratio of the brightness of the current frame to the brightness of the next frame in the continuous multi-frame images is the same as the ratio of the duty cycle of the pulse signal forming the current frame to the duty cycle of the pulse signal forming the next frame.

19. The dimming method for an in-vehicle display device according to claim 17 or 18, wherein, The number of pulses in the data signal that forms one frame of an image is 4.

20. The dimming method for an in-vehicle display device according to claim 17 or 18, wherein, The duty cycle of the pulse signal is greater than or equal to 9%.

21. A computer-readable storage medium storing computer instructions executable on a processor, wherein the computer instructions, when executed by the processor, implement one or more steps of the dimming method for an in-vehicle display device as claimed in any one of claims 9 to 20.

22. A computer program product, when run on a computer, causes the computer to perform one or more steps of the dimming method for an in-vehicle display device as claimed in any one of claims 9 to 20.

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