Silicon carbide semiconductor devices and power conversion devices using silicon carbide semiconductor devices

Abstract

The silicon carbide semiconductor device disclosed herein includes: a first conductivity type drift layer (20) on a first conductivity type semiconductor substrate (10); a second conductivity type well region (30) on the surface of the drift layer; a first conductivity type source region (40); a first conductivity type first departure region (21) formed in the well region with a constant width stripe shape and bent ends when viewed from above; a first conductivity type second departure region formed adjacent to the well region; a gate insulating film (50); a gate electrode (60); a Schottky electrode (71) on the first departure region; and a source electrode (80).

Description

Technical Field

[0001] This disclosure relates to silicon carbide semiconductor devices made of silicon carbide and power conversion devices using silicon carbide semiconductor devices. Background Technology

[0002] Regarding PN diodes constructed using silicon carbide (SiC), reliability issues are known, such as forward voltage shift due to stacking defects occurring in the crystal structure when a forward current (i.e., a bipolar current) continuously flows through it. This is believed to be caused by the recombination energy of minority and majority carriers injected through the PN diode, which propagates as surface defects (such as dislocations on the silicon carbide substrate). These stacking defects impede current flow, thus reducing the current due to their propagation, increasing the forward voltage, and consequently decreasing the reliability of the semiconductor device.

[0003] This increase in forward voltage also occurs in silicon carbide vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Vertical MOSFETs have a parasitic PN diode (body diode) between the source and drain. When forward current flows through this body diode, it causes the same reliability degradation as with PN diodes in vertical MOSFETs. When the body diode of a SiC-MOSFET is used as the freewheeling diode of the MOSFET, a degradation in the MOSFET's characteristics sometimes occurs.

[0004] As a method to solve the reliability problem caused by forward current flowing through the parasitic PN diode as described above, one approach is to incorporate a Schottky barrier diode (SBD), a unipolar diode, as a freewheeling diode within the active region of a semiconductor device such as a MOSFET. In this case, the SBD density is lower at the periphery of the active region compared to the interior of the active region, thus the body diode operates preferentially.

[0005] To suppress preferential body diode operation in the periphery of the active region, a technique has been disclosed in which a higher density of SBDs is configured in the terminal region surrounding the active region than in the active region (e.g., Patent Document 1).

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: WO2019 / 124378 International Publication Summary of the Invention

[0009] Furthermore, even when applying the techniques described in the prior art, the SBD density around the active region is sometimes lower than that inside the active region. When increasing the apparent width of the SBD profile to improve the SBD density around the active region, the electric field applied to the Schottky interface increases, leading to an increase in leakage current under reverse blocking conditions.

[0010] This disclosure was made to solve the problems described above, and its purpose is to provide a silicon carbide semiconductor device that can allow a higher density of unipolar current to flow without increasing the leakage current in the reverse blocking state and increasing the SBD density around the active region.

[0011] The silicon carbide semiconductor device and power conversion device disclosed herein include: a silicon carbide semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on the semiconductor substrate; a well region of the second conductivity type disposed on the surface of the drift layer; a source region of the first conductivity type formed on the surface of the well region, and inside the well region when viewed from above; a first exit region of the first conductivity type formed inside the well region when viewed from above, which is a stripe of constant width with bent ends; a Schottky electrode formed on the first exit region and connected to the first exit region by Schottky; a source electrode ohmically connected to the well region and the source region and formed on the Schottky electrode; a second exit region of the first conductivity type formed adjacent to the well region; and a gate electrode formed on the well region between the source region and the second exit region when viewed from above, separated by a gate insulating film.

[0012] According to the silicon carbide semiconductor device disclosed herein, a silicon carbide semiconductor device with high reliability can be obtained. Attached Figure Description

[0013] Figure 1 This is a top view of the silicon carbide semiconductor device according to Embodiment 1.

[0014] Figure 2 This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 1.

[0015] Figure 3 This is a reference top view of the silicon carbide semiconductor device according to Embodiment 1.

[0016] Figure 4 This is a reference top view of the silicon carbide semiconductor device according to Embodiment 1.

[0017] Figure 5 This is a top view of the silicon carbide semiconductor device according to Embodiment 2.

[0018] Figure 6This is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 2.

[0019] Figure 7 This is a top view of a modified example of the silicon carbide semiconductor device according to Embodiment 2.

[0020] Figure 8 This is a top view of a modified example of the silicon carbide semiconductor device according to Embodiment 2.

[0021] Figure 9 This is a top view of the silicon carbide semiconductor device according to Embodiment 3.

[0022] Figure 10 This is a top view of the silicon carbide semiconductor device according to Embodiment 4.

[0023] Figure 11 This is a top view of the silicon carbide semiconductor device according to Embodiment 5.

[0024] Figure 12 This is a schematic diagram showing the structure of the power conversion device according to Embodiment 6.

[0025] (Symbol Explanation)

[0026] 10: Semiconductor substrate; 20: Drift layer; 21: First departure region; 22: Second departure region; 30: Well region; 31: Terminal well region; 35: Contact region; 40: Source region; 50: Gate insulating film; 55: Interlayer insulating film; 60: Gate electrode; 71: Schottky electrode; 80: Source electrode; 81: Drain electrode; 90: Contact hole; 100: Power supply; 200: Power conversion device; 201: Main conversion circuit; 202: Drive circuit; 203: Control circuit; 300: Load. Detailed Implementation

[0027] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, the drawings are schematic illustrations, and the dimensions and relative positions of the images shown in different drawings may not be accurately depicted and may be appropriately varied. Additionally, in the following description, the same reference numerals are used to illustrate the same constituent elements, and their names and functions are also the same. Therefore, detailed descriptions of them are sometimes omitted.

[0028] In the following embodiments, the first conductivity type is defined as n-type and the second conductivity type as p-type, but the conductivity types can also be reversed.

[0029] Implementation method 1.

[0030] First, the silicon carbide semiconductor device of Embodiment 1 of this disclosure will be described.

[0031] Figure 1This is a top view near the surface of the silicon carbide layer at the end of the active region of the silicon carbide MOSFET (SiC-MOSFET with built-in SBD) that is a silicon carbide semiconductor device with a built-in Schottky barrier diode, as described in Embodiment 1. Additionally, Figure 2 This is a cross-sectional view of the SBD region at the active region end of the SiC-MOSFET with built-in SBD in this embodiment.

[0032] like Figure 1 As shown, in the active region of the SiC-MOSFET with built-in SBD in this embodiment, striped n-type first departure regions 21 corresponding to the striped SBD are periodically formed. The active region is surrounded by a termination region, in which a p-type termination well region 31 is formed in a manner that surrounds the active region.

[0033] At the end of the active region, that is, near the boundary between the active region and the terminal region, a striped first departure region 21 is formed by bending at a right angle relative to the direction extending from the center of the active region. Here, the striped first departure region 21 is formed with the same width, that is, a constant width, in the center and the periphery of the active region.

[0034] Around each first exit region 21, p-type well regions 30 are periodically formed in a manner that surrounds the first exit region 21 when viewed from above. That is, n-type first exit regions 21 are formed inside the well regions 30 when viewed from above. Inside each well region 30 when viewed from above, a low-resistance p-type contact region 35 is formed within a predetermined distance extending inward from the first exit region 21 side. In addition, a low-resistance n-type source region 40 is formed on the side of the contact region 35 opposite to the first exit region 21. The well regions 30 are formed outside the source regions 40.

[0035] On the outer side of each well region 30 where the contact region 35 and the source region 40 are formed, that is, on the side opposite to the side where the first departure region 21 is formed when viewed from above, an n-type second departure region 22 is formed adjacent to the well region 30. The second departure region 22 is part of the drift layer 20.

[0036] Furthermore, adjacent trap regions 30 are formed separately from each other. A second separation region 22 is also formed between the trap region 30 and the terminal trap region 31 of the terminal region.

[0037] Next, use Figure 2 This indicates the cross section Figure 1 A cross-sectional structure of a direction of the first departure region 21, that is, a direction orthogonal to the extension direction of the striped first departure region 21.

[0038] like Figure 2As shown, in the SiC-MOSFET with built-in SBD of this embodiment, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type and low-resistance silicon carbide. A pair of well regions 30 made of p-type silicon carbide, which are separated in cross-sectional view, are provided on the surface portion of the drift layer 20. The pair of well regions 30 forms a first n-type separation region 21, which is part of the drift layer 20.

[0039] On the opposite side of the well region 30, sandwiching the first departure region 21, i.e., on the outer side of the well region 30, a portion of the drift layer 20 is formed, becoming the n-type second departure region 22. At a predetermined interval extending inward from the end of the well region 30 from the second departure region 22 side toward the first departure region 21, a source region 40 made of n-type silicon carbide is formed. Furthermore, further inward of the source region 40, i.e., inside the surface portion of the well region 30 closer to the first departure region 21 than the source region 40, a low-resistance p-type contact region 35 made of p-type silicon carbide with a higher p-type impurity concentration than the well region 30 is formed. Here, regardless of the presence or absence of ion implantation, the region made of silicon carbide, i.e., the region initially formed as the drift layer 20, is referred to as the silicon carbide layer.

[0040] Here, the source region 40 and the contact region 35 are grounded.

[0041] A source electrode 80, ohmically connected to the well region 30 and the source region 40, is formed on the surfaces of the source region 40 and the contact region 35. A Schottky electrode 71 is formed from the surface of the first exit region 21 to the surface of the well region 30 adjacent to the first exit region 21, and the Schottky electrode 71 and the first exit region 21 are Schottky connected. The first exit region 21 and the Schottky electrode 71 constitute an SBD, and the interface between the first exit region 21 and the Schottky electrode 71 is called a Schottky interface.

[0042] A gate insulating film 50 made of silicon oxide is formed on the surface of the source region 40 within the well region 30, on the second exit region 22, and on the well region 30 between the source region 40 and the second exit region 22 when viewed from above. A gate electrode 60 made of low-resistance polycrystalline silicon is formed on the well region 30 between the source region 40 and the second exit region 22 when viewed from above, separated by the gate insulating film 50. Below the location where the gate electrode 60 is formed, the surface portion of the well region 30, which faces the gate electrode 60 separated by the gate insulating film 50, forms a channel region.

[0043] An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60 and the gate insulating film 50. Contact holes 90 are formed on the source region 40, the contact region 35, and the Schottky electrode 71, where the gate insulating film 50 and the interlayer insulating film 55 are removed. An active electrode 80 is formed within the contact holes 90 and on the interlayer insulating film 55. Figure 1 In the diagram, the position of the contact hole 90 when viewed from above is indicated by a dashed line.

[0044] An ohmic electrode (not shown) made of metal silicide is formed between the source electrode 80 and the contact region 35 to ohmically connect the contact region 35 and the source electrode 80.

[0045] A drain electrode 81 is formed on the side of the semiconductor substrate 10 opposite to the drift layer 20. An ohmic electrode (not shown) made of metal silicide is formed between the semiconductor substrate 10 and the drain electrode 81, and is ohmically connected to the semiconductor substrate 10 and the drain electrode 81.

[0046] Furthermore, the Schottky electrode 71 and the source electrode 80 can also be formed from the same material.

[0047] The following describes a method for manufacturing a SiC-MOSFET with a built-in SBD, which is a silicon carbide semiconductor device according to Embodiment 1 of this disclosure.

[0048] First, on the first main surface of a semiconductor substrate 10, which has a (0001) plane with an offset angle (4°, etc.) on the first main surface and is polymorphic with 4H, and is composed of n-type and low-resistivity silicon carbide, a 1×10⁻⁶ m² / m² substrate is epitaxially grown by chemical vapor deposition (CVD). 15 cm -3 Above and 1×10 17 cm -3 The drift layer 20 is made of silicon carbide and has the following impurity concentration, n-type, and a thickness of 5 μm or more but less than 100 μm. The thickness of the drift layer 20 can also be 100 μm or more depending on the breakdown voltage of the silicon carbide semiconductor device.

[0049] Next, an implantation mask is formed in a predetermined area on the surface of the drift layer 20 using a photoresist or the like, and Al (aluminum) ions, which are p-type impurities, are implanted. At this time, the depth of Al ion implantation is no more than 0.5 μm and no more than 3 μm, which is less than the thickness of the drift layer 20. Furthermore, the impurity concentration of the implanted Al is 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3The following range has an impurity concentration higher than that of drift layer 20. Afterwards, the implantation mask is removed. The region implanted with Al ions through this process becomes the trap region 30.

[0050] Next, an implantation mask is formed using a photoresist or the like to open a predetermined portion inside the well region 30 on the surface of the drift layer 20, and N (nitrogen) ions, which are n-type impurities, are implanted. The implantation depth of the N ions is set to be shallower than the thickness of the well region 30. Furthermore, the impurity concentration of the implanted N is 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The following range is defined as the p-type impurity concentration exceeding that of the well region 30. The n-type region implanted in the N-region during this process is designated as the source region 40. Afterwards, the implantation mask is removed.

[0051] Additionally, using the same method, Al ions are implanted into a predetermined region inside the trap region 30 at a higher impurity concentration than that in the trap region 30 to form a contact region 35. The impurity concentration of Al in the contact region 35 is 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 The following range is acceptable.

[0052] Next, the material is annealed for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) using a heat treatment apparatus at a temperature of 1300 to 1900°C. This annealing electrically activates the ion-implanted N and Al.

[0053] Next, the surfaces of the silicon carbide layers in the drift layer 20, well region 30, source region 40, and contact region 35 are thermally oxidized to form a silicon oxide film with a thickness of 10 nm or more and 300 nm or less, serving as a gate insulating film 50. Next, a conductive polycrystalline silicon film is formed on the gate insulating film 50 using a reduced-pressure CVD method, and patterned to form the gate electrode 60. Then, an interlayer insulating film 55 composed of silicon oxide is formed using a reduced-pressure CVD method.

[0054] Next, a contact hole (the first part of the contact hole) is formed by dry etching, which penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 35 and the source region 40 in the active region.

[0055] Next, a nickel (Ni)-based metal film is formed using sputtering or similar methods. Then, a heat treatment at 600 to 1100°C is performed, causing the Ni-based metal film to react with the silicon carbide layer within the contact hole (Part 1), forming a silicide between the silicon carbide layer and the metal film. In the case where the metal film is Ni, the silicide becomes nickel silicide. Next, wet etching is used to remove any remaining metal film other than the reacted silicide. The silicide formed here becomes an ohmic electrode (not shown).

[0056] Next, a resist mask is formed on the surface of the ohmic electrode and the interlayer insulating film 55 by photolithography.

[0057] Next, with the resist mask in place, the gate insulating film 50 and the interlayer insulating film 55 above the surface of the first departure region 21 are wet-etched using an etchant containing hydrofluoric acid. The area wet-etched here also becomes part of the contact hole (the second part of the contact hole). Afterward, the resist mask is removed.

[0058] Next, a Schottky electrode 71, of Ti, Mo, etc., is formed on the surface of the first departure region 21 and is Schottky-connected to the first departure region 21. Additionally, a source electrode 80, primarily composed of Al, is formed on the Schottky electrode 71 and on the ohmic electrode.

[0059] Next, by grounding the drain electrode 81 on the bottom side with the back ohmic electrode on the back side, it is possible to manufacture... Figure 2 The SiC-MOSFET with built-in SBD, which is shown in cross-sectional view, is a silicon carbide semiconductor device according to this embodiment.

[0060] Furthermore, the bending angle of the first departure region 21 does not need to be 90°, but can be close to 90°. In addition, as long as the bending angle is greater than 60°, the SBD density around the active region can be increased compared to the case without bending.

[0061] Furthermore, it is noted that the first departure region 21 is formed with the same width when viewed from above, but it is also possible that the first departure region 21 is not formed with a strictly uniform width. Regarding the width of the first departure region 21, there can be a difference of ±1 μm as long as the electric field applied to the Schottky interface does not increase.

[0062] In the freewheeling operation of the silicon carbide semiconductor device of this embodiment, the freewheeling current flows into the SBD, and no freewheeling current flows through the pn body diode between the well region 30 and the drift layer 20. As described in this embodiment, if the SBD is not formed with an end bend, the areal density of the SBD is smaller near the boundary between the active region and the terminal region than in the center of the active region, which sometimes makes it easier to apply a voltage to the body diode and for the body diode to conduct easily. In addition, increasing the width of the SBD sometimes increases the leakage current in the reverse blocking state.

[0063] However, in the silicon carbide semiconductor device of this embodiment, a first departure region 21 is formed by bending at the active region end, so that the areal density of the SBD can be made to the same level as the central part of the active region near the boundary between the active region and the terminal region. Therefore, it is possible to prevent the body diode from easily turning on at the end of the active region.

[0064] In the SiC-MOSFET with built-in SBD of the silicon carbide semiconductor device in this embodiment, the width of the striped first departure region 21 is constant, and the striped first departure region 21 is bent in the active region. Therefore, without increasing the leakage current of the reverse blocking state of the active region, the SBD density around the active region can be increased, allowing a higher density of unipolar current to flow.

[0065] Furthermore, to increase the SBD density around the active region, a method of setting isolated SBDs independently of the active region's SBD is considered. However, regarding the SBD region whose width is reduced in cross-sectional view, the area surrounding the trap region 30 formed by ion implantation is protected with resist to form the SBD region. At this time, as... Figure 3 as well as Figure 4 As shown in the reference top view, the SBD region is formed in isolation by narrowing its width. Specifically, when the first departure region 21 is formed separately within the trap region 30, the thin, straight resist sometimes collapses and becomes a pattern defect during ion implantation.

[0066] However, in the silicon carbide semiconductor device according to this embodiment, a first departure region 21 corresponding to the SBD region is continuously formed in a bent manner within a range surrounded by a well region 30. Therefore, the thin resist is difficult to collapse during ion implantation. Compared with the case of forming an isolated SBD region or a straight SBD region, the occurrence of pattern defects can be suppressed.

[0067] Implementation method 2.

[0068] Figure 5This is a top view near the surface of the silicon carbide layer at the end of the active region in the silicon carbide semiconductor device of Embodiment 2. The silicon carbide semiconductor device of this embodiment differs from that of Embodiment 1 in that the striped first departure region 21 is bent twice at the end of the active region. The portion after being bent twice is bent 180° relative to the portion extending from the center of the active region, and is formed parallel to the portion extending from the center of the active region. Other aspects are the same as in Embodiment 1, so detailed descriptions are omitted.

[0069] like Figure 5 As shown, in this embodiment, the SBD of the SiC-MOSFET with a built-in SBD, i.e., the first departure region 21, is bent 180° at the end of the active region. A well region 30 is formed between the bent first departure regions 21. The top of the bent first departure region 21 is not connected to the first departure region 21 itself.

[0070] Here, Figure 6 A schematic cross-sectional view is shown of the area where the first departure region 21 is bent, transversely intersecting the two striped surfaces of the first departure region 21 within a trap region 30. (See diagram below.) Figure 6 As shown in the cross-sectional schematic diagram, two striped first departure regions 21 are formed in the trap region 30, and a p-shaped trap region 30 is also formed in the area between the two first departure regions 21 that is sandwiched by the first departure regions 21.

[0071] exist Figure 6 In the middle, a Schottky electrode 71 is formed on the two first departure regions 21, the well region 30 sandwiched between them, and the well region 30 outside the first departure regions 21. The contact hole 90 is as follows... Figure 5 As shown by the dashed lines, the first departure region 21, the well region 30 sandwiched by the first departure region 21, the well region 30 between the first departure region 21 and the contact region 35, the contact region 35, and a portion of the source region 40 are formed with openings. A source electrode 80 is formed within the contact hole 90 and on the interlayer insulating film 55. An ohmic electrode (not shown) is also formed on the contact region 35.

[0072] The well region 30 and the Schottky electrode 71 can also be Schottky connected.

[0073] Furthermore, regarding the manufacturing method of the SiC-MOSFET with built-in SBD in this embodiment, if the area that combines the first departure region 21 and the well region 30 therebetween is manufactured as the second part of the contact hole, it can be manufactured using the same method as the SiC-MOSFET with built-in SBD in Embodiment 1.

[0074] In the SiC-MOSFET with a built-in SBD in the silicon carbide semiconductor device of this embodiment, a first departure region 21 is formed by bending 180° at the end of the active region. Therefore, in the region where the first departure region 21 is bent, compared to the case where the width of the first departure region 21 is increased, while preventing the leakage current from increasing in the reverse blocking state due to a decrease in the electric field applied to the Schottky interface, it is possible to form an SBD with an area more than twice that of the center of the active region per unit length relative to the extension direction of the first departure region 21.

[0075] Furthermore, when the trap region 30 surrounding the SBD region is formed by ion implantation, the ion implantation resist mask is bent 180° to form a narrow width, so the resist mask is less likely to collapse at the end, which can further suppress the occurrence of pattern defects.

[0076] Furthermore, the top of the bent portion of the first departure area 21, which is bent 180°, is as follows: Figure 5 As shown, it is not connected to the first exit region 21 itself. However, it can also be as shown in Figure 7 As shown in the top view, the top of the bent portion of the first departure region 21 is connected to the straight first departure region 21. Here, the area surrounded by the first departure region 21 in the top view forms a trap region 30.

[0077] exist Figure 7 In the structure shown, while preventing the leakage current from increasing in the reverse blocking state, an SBD with an area more than twice that of the central part of the active region can be formed at the end of the active region.

[0078] exist Figure 7 In the configuration shown, the leakage current is higher in the reverse blocking state than... Figure 5 The structure is slightly increased, but it is more difficult to cause the resist to collapse during manufacturing. Furthermore, at the end of the active region, an SBD with an area more than twice that of the central part of the active region can be formed.

[0079] Furthermore, the first departure area 21 of the bend can also be as follows: Figure 8 As shown in its top view, it bends in a curve. Figure 8 In the structure shown, the first exit region 21 is bent in a U-shape, and the outer periphery of the first exit region 21 is formed in a curved shape. With this structure, while preventing the leakage current from increasing in the reverse blocking state, an SBD with an area more than twice that of the central part of the active region can be formed at the end of the active region. As a whole, the unipolar current flowing into the end of the active region can be made to have the same density as that in the central part of the active region.

[0080] Implementation method 3.

[0081] Figure 9 This is a top view near the surface of the silicon carbide layer at the end of the active region in the silicon carbide semiconductor device of Embodiment 3. The silicon carbide semiconductor device of this embodiment differs from that of Embodiment 1 in that the striped first departure region 21 is bent more than three times at the end of the active region. Other aspects are the same as in Embodiment 1, so detailed descriptions are omitted.

[0082] As in Figure 9 As shown in the top view, the first departure region 21 of the SBD of the SiC-MOSFET with built-in SBD in the silicon carbide semiconductor device of this embodiment is formed in a zigzag shape at the end of the active region, that is, in a shape in which straight lines are alternately bent left and right. The number of bends is three or more.

[0083] In the silicon carbide semiconductor device of this embodiment, in the region where the first departure region 21 is bent, compared to the case where the width of the first departure region 21 is increased, while preventing the leakage current from increasing in the reverse blocking state due to a decrease in the electric field applied to the Schottky interface, it is possible to form an SBD with an area more than twice that of the central portion of the active region per unit length relative to the extension direction of the first departure region 21. Furthermore, when the trap region 30 surrounding the SBD region is formed by ion implantation, a narrow ion implantation resist mask is formed by zigzagging, so the resist mask is less likely to be squeezed at the ends, further suppressing the occurrence of pattern defects.

[0084] Implementation method 4.

[0085] Figure 10 This is a top view near the surface of the silicon carbide layer at the end of the active region in the silicon carbide semiconductor device of Embodiment 4. The silicon carbide semiconductor device of this embodiment differs from that of Embodiment 1 in that the source region 40 within the well region 30 is not formed in the region where the first departure region 21 at the end of the active region is bent. Other aspects are the same as in Embodiment 2, so detailed descriptions are omitted.

[0086] Figure 10 This is a top view near the surface of the silicon carbide layer of the SBD in the SiC-MOSFET with its built-in SBD, which is a silicon carbide semiconductor device in this embodiment. Figure 10 As shown, in the SiC-MOSFET with built-in SBD in this embodiment, a source region 40 is formed in a striped pattern in the center of the active region within the well region 30, sandwiching the first exit region 21. In contrast, the source region 40 is not formed in the region where the first exit region 21 is bent at the end of the active region.

[0087] Here, regarding the contact region 35 that surrounds the first exit region 21 within the trap region 30 in the same manner as the source region 40 in Embodiment 2, it is formed in a manner that surrounds the entire first exit region 21, just as in Embodiment 2.

[0088] According to the SiC-MOSFET with a built-in SBD in the silicon carbide semiconductor device of this embodiment, the source region 40 is not formed in the region where the first departure region 21 is formed in the folded-back area. Therefore, the width of the well region 30 in the folded-back portion in the direction orthogonal to the extending direction of the first departure region 21 can be further reduced. Therefore, even if there is a reduction in current due to the removal of the source region 40 from the folded-back portion and the absence of a MOSFET in that location, more well regions 30 can be configured per unit area because the width of one well region 30 can be reduced, and the well regions 30 can be configured at a high density overall. Therefore, the on-resistance can be further reduced.

[0089] In the silicon carbide semiconductor device of this embodiment, in addition to the effects obtained by the silicon carbide semiconductor device of embodiment 2, the on-resistance can be further reduced.

[0090] Furthermore, compared to the silicon carbide semiconductor device of Embodiment 2, the width of the second departure region 22 in the central part of the active region (the length in the direction orthogonal to the extending direction of the first departure region 21) can be reduced, thus further reducing the electric field applied to the gate insulating film 50 formed on the second departure region 22, thereby improving the reliability of the silicon carbide semiconductor device. Additionally, compared to the silicon carbide semiconductor device of Embodiment 2, the density of the first departure region 21 per unit area of ​​the active region as a whole, i.e., the SBD density, can be increased, thus enabling a higher density of unipolar current to flow.

[0091] Furthermore, in this embodiment, the structure in which the contact region 35 surrounds the first departure region 21 is described, but the contact region 35 does not necessarily need to surround the first departure region 21, and can also be removed in the fold-back section in the same way as the source region 40.

[0092] Implementation method 5.

[0093] Figure 11 This is a top view near the surface of the silicon carbide layer at the end of the active region in the silicon carbide semiconductor device of Embodiment 5. The silicon carbide semiconductor device of this embodiment differs from that of Embodiment 4 in that, in the region where the first departure region 21 is bent, the well region 30 is connected to the adjacent well region 30. Other aspects are the same as in Embodiment 4, so detailed descriptions are omitted.

[0094] Figure 11This is a top view near the surface of the silicon carbide layer of the SBD in the SiC-MOSFET with its built-in SBD, which is a silicon carbide semiconductor device in this embodiment. Figure 11 As shown, in the SiC-MOSFET with built-in SBD in this embodiment, the well regions 30 surrounding each first departure region 21, that is, the well regions 30 having the first departure region 20 inside, are interconnected. In embodiments 1 to 4, an n-type second departure region 22 is provided between the well region 30 of the fold-back portion of the first departure region 21 and the adjacent well region 30, but in this embodiment, the second departure region 22 is not provided in the fold-back portion.

[0095] Here, the contact area 35 is formed in the same manner as in embodiment 4, in a way that surrounds the entirety of each first departure area 21.

[0096] According to the SiC-MOSFET with built-in SBD in the silicon carbide semiconductor device of this embodiment, the source region 40 is not formed in the fold-back portion of the first departure region 21, and the adjacent well regions 30 are interconnected. Therefore, the width of the fold-back portion surrounding one of the well regions 30 in the direction orthogonal to the extension direction of the first departure region 21 can be further reduced. Therefore, more well regions 30 surrounding one of the first departure regions 21 can be arranged per unit area, and the on-resistance can be further reduced.

[0097] Furthermore, compared to the silicon carbide semiconductor device of Embodiment 4, the width of the second exit region 22 in the central part of the active region (the length in the direction orthogonal to the extending direction of the first exit region 21) can be reduced, thus further reducing the electric field applied to the gate insulating film 50 formed on the second exit region 22, thereby improving the reliability of the silicon carbide semiconductor device. Additionally, compared to the silicon carbide semiconductor device of Embodiment 4, the density of the first exit region 21 per unit area of ​​the active region as a whole, i.e., the SBD density, can be increased, thus enabling a higher density of unipolar current to flow.

[0098] In the silicon carbide semiconductor device of this embodiment, in addition to the effects obtained by the silicon carbide semiconductor device of embodiment 4, the on-resistance can be further reduced and the reliability can be further improved.

[0099] Furthermore, in the above embodiments, aluminum (Al) was used as the p-type impurity, but the p-type impurity could also be boron (B) or gallium (Ga). The n-type impurity could also be phosphorus (P) instead of nitrogen (N). In the MOSFETs described in embodiments 1 to 5, the gate insulating film does not necessarily have to be an oxide film such as SiO2; it can be an insulating film other than an oxide film or a combination of an insulating film other than an oxide film and an oxide film. In addition, in the above embodiments, specific examples of crystal structure, main surface orientation, offset angle, and various injection conditions were used for description, but the application scope is not limited to these numerical ranges.

[0100] Furthermore, in the above embodiment, an example of a silicon carbide semiconductor device with a so-called vertical MOSFET in which the drain electrode 81 is formed on the back side of the semiconductor substrate 10 has an integrated SBD has been described, but it can also be applied to an example of an SBD being integrated into a MOSFET with a superstructure.

[0101] Implementation method 6.

[0102] This embodiment is an example of applying the silicon carbide semiconductor device of Embodiments 1 to 5 described above to a power conversion device. This disclosure is not limited to a specific power conversion device, but hereinafter, as Embodiment 6, the case of applying this disclosure to a three-phase inverter will be described.

[0103] Figure 12 A block diagram showing the structure of the power conversion system of the power conversion device using this embodiment is provided.

[0104] Figure 12 The power conversion system shown includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source that supplies DC power to the power conversion device 200. The power source 100 can be constructed from various examples, such as a DC system, solar cells, a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, the power source 100 can also be constructed from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0105] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converting the DC power supplied from the power source 100 into AC power to supply AC power to the load 300. The power conversion device 200 is as follows... Figure 12 As shown, it includes: a main converter circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals to drive each switching element of the main converter circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0106] The drive circuit 202 controls the cut-off of each normally off switching element by making the voltage of the gate electrode and the voltage of the source electrode the same potential.

[0107] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. Furthermore, the load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning systems.

[0108] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power source 100 into AC power, which is then supplied to the load 300. Various examples exist for the specific circuit structure of the main conversion circuit 201, but in this embodiment, the main conversion circuit 201 is a two-level three-phase full-bridge circuit, which can be constructed from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. In each switching element of the main conversion circuit 201, a silicon carbide semiconductor device from any of the embodiments described in 1 to 5 is used. For each of the six switching elements, two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower branch, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0109] The drive circuit 202 generates drive signals to drive the switching elements of the main converter circuit 201 and supplies them to the control electrodes of the switching elements of the main converter circuit 201. Specifically, according to the control signal from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is kept in the on state, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is kept in the off state, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0110] The control circuit 203 controls the switching elements of the main converter circuit 201 to supply the desired power to the load 300. Specifically, based on the power to be supplied to the load 300, the control circuit 203 calculates the time (on-time) during which each switching element of the main converter circuit 201 should be in the on state. For example, the main converter circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Furthermore, the control circuit 203 outputs control commands (control signals) to the drive circuit 202 in a manner that outputs on signals to the switching elements that should be in the on state at each time point and outputs off signals to the switching elements that should be in the off state. The drive circuit 202 outputs on or off signals as drive signals to the control electrodes of each switching element according to the control signals.

[0111] In the power conversion device of this embodiment, the silicon carbide semiconductor device of embodiments 1 to 5 is used as the switching element of the main conversion circuit 201, so a power conversion device with low loss and improved high-speed switching reliability can be realized.

[0112] In this embodiment, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but it can also be a 3-level or multi-level power conversion device. When supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, the present disclosure can also be applied to DC / DC converters and AC / DC converters.

[0113] Furthermore, the power conversion device disclosed herein is not limited to the case where the load is an electric motor. For example, it can be used as a power supply device for electrical discharge machining, laser processing machines, induction heating cookers, non-contact power supply systems, and also as a power regulator for solar power generation systems, energy storage systems, etc.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: Silicon carbide semiconductor substrate of the first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; A trap region of the second conductivity type is disposed on the surface of the drift layer; The source region of the first conductivity type is formed inside the well region when viewed from above in the surface portion of the well region; The first departure region of the first conductivity type, inside the trap region when viewed from above, is formed as a stripe of constant width with its ends bent when viewed from above; A Schottky electrode is formed on the first departure region and is Schottky connected to the first departure region; A source electrode, ohmically connected to the well region and the source region, is formed on the Schottky electrode; The second departure region of the first conductivity type is formed adjacent to the well region; as well as A gate electrode is formed, when viewed from above, over the well region between the source region and the second departure region, with a gate insulating film in between.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The first departure area is bent 180° at the end.

3. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that, The first departure region is not connected to itself.

4. The silicon carbide semiconductor device according to claim 1 or 2, characterized in that, Regarding the first departure area, the outer periphery of the bent portion at the end is curved.

5. The silicon carbide semiconductor device according to claim 1, characterized in that, The first departure area bends more than three times when viewed from above.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that, The source region was not formed at the end.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, The trap regions are formed in multiple ways on the surface of the drift layer, away from each other.

8. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, When viewed from above, the trap regions, which contain the first departure region, are interconnected on the surface of the drift layer.

9. The silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that, The area within the trap region that is sandwiched by the first departure region is part of the trap region.

10. The silicon carbide semiconductor device according to claim 9, characterized in that, The source electrode is formed on a portion of the well region that is sandwiched by the first departure region within the well region.

11. The silicon carbide semiconductor device according to any one of claims 1 to 10, characterized in that, Furthermore, a contact region of a second conductivity type has a higher impurity concentration than the well region, in a manner that surrounds the first departure region within the well region.

12. A power conversion device, characterized in that, have: A main converter circuit having a silicon carbide semiconductor device as described in any one of claims 1 to 11, the main converter circuit converting input power into output power; The driving circuit cuts off the silicon carbide semiconductor device by making the voltage of the gate electrode the same as the voltage of the source electrode, and outputs a driving signal to the silicon carbide semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

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