Depth controlled deposition for plasma based deposition of surface modification

Abstract

A method for performing gap fill of a feature on a substrate includes: (a) moving the substrate into a processing chamber; (b) performing a plurality of cycles of an ALD process; (c) purging the processing chamber of process gases from the ALD process; (d) plasma treating the substrate by introducing a fluorine-containing gas into the processing chamber and applying RF power to the fluorine-containing gas to generate a fluorine plasma in the processing chamber; (e) purging the processing chamber of process gases from the plasma treating; (f) repeating operations (b) through (e) until a predetermined number of cycles is performed.

Description

[0001] This application is a divisional application of application No. 201980045632.0, filed on June 21, 2019, entitled "Deep-Controlled Deposition for Surface Modification of Plasma-Based Deposition". Background Technology

[0002] Deposition-etch-deposition (DED) has been proven effective for filling high aspect ratio vias, holes, and trenches. However, DED methods face gap-filling limitations when used to fill features with enlarged reentrancy beneath the top of a structure. Structures with large reentrancy features relative to the opening size, or any large reentrancy feature relative to a large opening, result in insufficient material growth within the line of sight of the ions used for etching before the feature is pinched off.

[0003] It was in this context that the embodiments of the present invention were developed. Summary of the Invention

[0004] In some embodiments, a method for gap filling of features on a substrate is provided, comprising: (a) moving the substrate into a processing chamber; (b) performing multiple cycles of an ALD process; (c) purging the processing chamber of process gases from the ALD process; (d) plasma treating the substrate by introducing a fluorine-containing gas into the processing chamber and applying RF power to the fluorine-containing gas to generate fluorine plasma in the processing chamber; (e) purging the processing chamber of process gases from the plasma treatment; and (f) repeating operations (b) to (e) until a predetermined number of cycles are performed.

[0005] In some embodiments, the fluorine plasma passivates a portion of the feature on the substrate, thereby suppressing deposition of the passivated portion of the feature by the ALD process.

[0006] In some implementations, the passivated portion of the feature extends downward from the top of the feature to a predetermined target level within the feature.

[0007] In some implementations, the predetermined target level is controlled by one or more parameters of the plasma treatment.

[0008] In some embodiments, the parameters of the plasma treatment include one or more of the following: the duration of the plasma treatment, the temperature of the plasma treatment, the pressure of the fluorine-containing gas, and the level of the RF power.

[0009] In some embodiments, the feature includes a recess, and the predetermined target level is defined approximately at the level of the recess to substantially suppress deposition by the ALD process above the level of the recess by the plasma treatment.

[0010] In some embodiments, the fluorine plasma passivates the portion of the feature by forming a fluorine-terminated material along the surface of the portion of the feature.

[0011] In some implementations, the method further includes: (g) performing one or more cycles of the ALD process.

[0012] In some implementations, the predetermined number of cycles of operation (e) is configured to affect gap filling to remove the recesses in the feature.

[0013] In some implementations, one or more cycles of the ALD process in operation (g) are configured to complete the gap filling of the feature.

[0014] In some embodiments, the ALD process is configured to deposit oxide in the features of the substrate.

[0015] In some embodiments, the fluorine-containing gas is CH3F, CHF3, CF4, C2H4F2, C2H2F4, C3H2F6, C4H2F8, C4F8, NF3, or SF6.

[0016] In some embodiments, a method for performing gap filling of a feature on a substrate is provided, comprising: (a) moving the substrate into a processing chamber; (b) performing multiple cycles of an ALD process configured to deposit oxide in the feature on the substrate; (c) purging process gases from the ALD process from the processing chamber; (d) plasma treating the substrate by introducing a fluorine-containing gas into the processing chamber and applying RF power to the fluorine-containing gas to generate fluorine plasma in the processing chamber; (e) purging process gases from the plasma treatment from the processing chamber; (f) repeating operations (b) to (e) until a predetermined number of cycles are performed; and (g) performing multiple cycles of the ALD process.

[0017] In some embodiments, the fluorine plasma passivates a portion of the feature on the substrate, thereby suppressing deposition of the passivated portion of the feature by the ALD process.

[0018] In some implementations, the passivated portion of the feature extends downward from the top of the feature to a predetermined target level within the feature.

[0019] In some implementations, the predetermined target level is controlled by one or more parameters of the plasma treatment.

[0020] In some embodiments, the parameters of the plasma treatment include one or more of the following: the duration of the plasma treatment, the temperature of the plasma treatment, the pressure of the fluorine-containing gas, and the level of the RF power.

[0021] In some embodiments, a method for gap filling of features on a substrate is provided, comprising: (a) moving the substrate into a processing chamber; (b) performing multiple cycles of an ALD process; (c) purging the processing chamber of process gases from the ALD process; (d) plasma treating the substrate by introducing a fluorine-containing gas into the processing chamber and applying RF power to the fluorine-containing gas to generate fluorine plasma in the processing chamber, the RF power being applied at a frequency in the range of about 200 to 600 kHz; (e) purging the processing chamber of process gases from the plasma treatment; and (f) repeating operations (b) to (e) until a predetermined number of cycles are performed.

[0022] In some implementations, the pressure of the plasma treatment is in the range of about 0.5 to 8 Torr.

[0023] In some implementations, the duration of the plasma treatment is in the range of about 0.1 to 3 seconds.

[0024] Other aspects and advantages of this disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of this disclosure by way of example. Attached Figure Description

[0025] Figure 1A , 1B Figure 1C conceptually illustrates a cross-sectional view of a recessed portion according to an embodiment of the invention.

[0026] Figure 2A and 2B The application of gap filling on a multilayer stack according to an embodiment of the present invention is shown.

[0027] Figure 3A , 3B 3C and 3D illustrate suppression-based techniques for gap filling to achieve concave features.

[0028] Figure 4 A method for performing a gap-filling process using fluorine plasma suppression according to an embodiment of the present invention is shown.

[0029] Figure 5A This is a diagram illustrating the effect of the suppression treatment according to an embodiment of the present invention on subsequent deposition cycles.

[0030] Figure 5B This diagram illustrates the relationship between suppression depth and suppression processing time according to an embodiment of the present invention.

[0031] Figure 6A , 6B Figure 6C conceptually illustrates a cross-sectional view of features on a substrate and shows a gap-filling process according to an embodiment of the invention.

[0032] Figures 7A to 7F A cross-sectional view showing a feature with multiple recesses is provided, illustrating a process for gap filling according to an embodiment of the invention.

[0033] Figure 8 A gas supply system according to an embodiment of the invention is shown for supplying processing gas to a processing chamber for ALD process.

[0034] Figure 9A and 9B The difference between an existing system and a system with separate manifolds for conveying suppression / passivation gases and cleaning / etching gases according to an embodiment of the invention is shown.

[0035] Figure 10A , 10B 10C demonstrates how the gap-filling performance can be improved by utilizing the technique according to an embodiment of the invention.

[0036] Figure 11 A cluster tool system 1100 for processing a substrate is shown according to an embodiment of the present invention.

[0037] Figure 12 This is a simplified schematic diagram of a computer system used to implement the embodiments of this disclosure. Detailed Implementation

[0038] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the exemplary embodiments may be practiced without some of these specific details. In other instances, process operations and implementation details are not described in detail where they are already well known.

[0039] As used herein, the terms “about” and “approximately” mean that a particular parameter may vary within reasonable tolerances, such as ±10% in some embodiments, ±15% in some embodiments, or ±20% in some embodiments.

[0040] In a broader sense, embodiments of the present invention provide methods, systems, and apparatus for dielectric gap filling on high aspect ratio features with large recessed structures within holes or trenches. In some embodiments, the disclosed technique utilizes surfaces modified with fluorine using low-frequency (LF: e.g., 200 to 600 Hz) and high-frequency (HF: e.g., 13 to 14 MHz) plasmas. Surface modification allows for control of the deposition depth within the feature during the growth process. Fluorine surface treatment can be applied to gap filling of vias, holes, shallow trench isolation (STI) structures, and trenches on multilayer stacks (not just features fabricated in a single material), including but not limited to a variety of materials, including silicon / polysilicon, silicon dioxide, germanium, nitrides, oxides, or multilayer stack materials. This modification allows for multiple plasma cycles before the need for re-application of surface modification.

[0041] Generally, a concave feature is a feature with a sidewall profile where some portions of the sidewalls are etched / removed laterally to a greater extent than another portion directly above it at a shallower depth. Therefore, the first portion can be said to be "masked" by the second portion at a shallower depth. Concave features are often caused by undercutting or masking due to the etching process deviating from a straight line, and the area where this occurs is the concave portion. This can happen anywhere within the feature. Concave features can have many origins. For example, during the etching process, there may be sidewall passivation; if the passivation changes or becomes inconsistent, some areas may bend due to inconsistent etching along the sidewalls. In some cases, layers of different materials may be etched at different rates, resulting in a raised sidewall etch profile due to the different etching rates of the materials.

[0042] Figure 1A , Figure 1B and Figure 1C A cross-sectional view conceptually illustrating a feature with a recess according to an embodiment of the invention is shown. For example, as Figure 1A As shown, some recesses are characterized by feature 100, which is smaller at the top and wider at the bottom. They are sometimes described as sidewalls 102 with a negative slope or tapering. For example, in some processes, there is a two-layer etching that can create a recess at the top and a recess somewhere in the middle of the feature.

[0043] like Figure 1B As shown, in some cases, recesses occur due to bends in the linear feature 104. For example, these bends may be caused by improper etching or stress in the film. This bend causes one side of the feature to be recessed relative to the opposite side. It should be understood that in the illustrated embodiment, the back-and-forth bend of feature 104 creates a recess 106 along one side in the upper region of feature 104, and another recess 108 along the opposite side in the lower region of feature 104.

[0044] like Figure 1C As shown, another example of a recess is caused by the sidewall morphology of feature 110. This can occur, for example, but not limited to, in NAND devices, FinFET devices, ONON (oxide / nitride) stacks, OPOP (oxide / polysilicon) stacks, etc. For example, the sidewalls may have fins 112 or other features that create the recess within the feature.

[0045] The ability of an etching process to remove unwanted recesses and sidewall contours for gap filling may depend on the structure being etched. Structures with "necking" features or internal recesses may be pinched off before the etched portion of the DED can remove the deposited material that would cause the pinch-off.

[0046] Figure 2A and 2B The illustration shows a gap-filling application on a multilayer stack according to an embodiment of the invention. For example, but not limited to, the multilayer stack can be an ONON or OPOP material stack. In the illustrated embodiment, a first material 202 layer and a second material 204 layer alternate to form the multilayer stack. When etching such a multilayer stack, recesses are often included, resulting in partial undercuts. For example, the first material 202 may be etched at a slower rate than the second material 204, thus the second material 204 layer becomes recessed along the sidewalls of feature 200 compared to the first material 202 layer.

[0047] Figure 2B Interstitial filling 206 deposited in feature 200 is shown. When deposition is performed in these areas, recesses may become voids using common interstitial filling processes (e.g., atomic layer deposition (ALD) or other methods).

[0048] Figure 3A , 3B 3C and 3D demonstrate suppression-based techniques for filling gaps in concave features. For example... Figure 3A As shown, feature 300 may have a recess 302. In the example shown, the recess 302 is present at the top of feature 300, but in various features, the recess can occur anywhere from the top to the bottom of the feature. Where such recesses exist, they may become voids once the gap is filled.

[0049] Using existing technology, inhibitors, such as nitrogen (N2) plasma inhibitors, can be used to apply inhibitor-filling processes. The purpose of this process is to inhibit growth and fill at different rates, causing the deposition at the bottom of the feature to grow faster than at the top, allowing growth within the recess to proceed more rapidly before pinch-off. That is, an inhibitor is applied in each ALD cycle, causing the deposition rate near the top of the feature to decrease.

[0050] In some cases, the inhibitor filling process performs multiple cycles until a certain thickness is reached, resulting in, for example... Figure 3A The partial inhibitor-filled layer 304 is shown. Optionally, an etching step can then be performed to remove the material, such as... Figure 3C As shown. Subsequently, a standard ALD (inhibitor-free) filling process is used to complete the filling of the feature gaps, such as... Figure 3D As shown.

[0051] However, the problem with the inhibitor-filled process described above is that the inhibitor must be applied in every ALD cycle of the flow. Applying the inhibitor every time material is deposited in a cycle is a lengthy additional step, thus becoming a very slow process. For example, but not limited to, for inhibitor-filled processes using inhibitors such as nitrogen (N2) plasma, the ALD cycle itself can be about 1.5 seconds; however, each cycle may require an additional 20 seconds to perform N2 plasma suppression. Therefore, the deposition cycle time can increase from 1.5 seconds to 21.5 seconds. The growth rate is typically about 0.8 angstroms per second, and the required thickness is typically close to 200 angstroms, so the number of cycles is usually on the order of about 200-300 cycles. Therefore, the increased cycle time is amplified, and the reduction in throughput due to the suppression process can be very significant. The purpose of the etching step is to attempt and make the process faster by allowing the filling process to switch back to general ALD without the risk of pinch-off. Therefore, existing procedures may require an inhibitor-filling process (e.g., a 20-25 second cycle, which is a very slow fill) until the recess is filled to the point where there is no more masking, followed by a long etching (e.g., close to 30 seconds), and then switching to general ALD deposition to complete the fill. However, although etching back and switching to general ALD fill can help improve throughput, the entire process is still significantly hampered by the inhibitor-filling process.

[0052] However, according to embodiments of the invention, the use of an inhibitor allows the suppression effect to persist through multiple iterations of the ALD plasma cycle. This enables the continuous execution of multiple ALD cycles without the need for reapplication of the inhibitor. Previously applied inhibitors cannot persist through multiple ALD cycles. However, embodiments of the invention provide an inhibitor capable of achieving a suppression effect that lasts for multiple ALD cycles.

[0053] In some implementations, fluorinated gases are used to treat the substrate surface and provide a suppressive effect. More broadly, the process flow may require performing multiple ALD cycles, followed by purging the ALD gas, and then applying a fluorinated gas to treat the surface; this process is repeated multiple times. Fluorinated gases provide a suppressive effect that lasts for multiple ALD cycles, therefore it is not necessary to reapply them in each ALD cycle.

[0054] Note that fluorinated gases are generally not used in deposition processes, but rather tend to be used in etching processes. The use of fluorinated agents in chamber cleaning processes is known. However, in this case, the purpose of fluorine is to perform cleaning and be removed. According to embodiments of the invention, fluorine is used to selectively retain certain areas of the substrate, thus providing a suppressive effect during gap-filling deposition.

[0055] Figure 4 A method for performing a gap-filling process using fluorine plasma suppression is illustrated according to an embodiment of the invention. In method operation 400, a wafer (substrate) is introduced into a processing chamber. In method operation 402, optionally, wafer heating or cooling with a thermal soak step may be performed to bring the wafer to a desired temperature. In method operation 404, a gas pre-flow for ALD is introduced. This may include, for example, introducing an inert gas into the processing chamber and balancing the gas flows into and out of the processing chamber.

[0056] In method operation 406, one or more ALD cycles are performed. Each ALD cycle typically consists of a first reactant injection, a first purge, a second reactant injection, and a second purge. In some embodiments, the first or second reactant injection may also be a plasma process. After the ALD cycle is completed, in method operation 408, all process gases from the ALD are purgeed from the processing chamber (e.g., using an inert gas). It should be understood that the specific number of ALD cycles performed in method operation 406 may vary depending on the application, the size of the feature to be filled, and any recesses therein. In some embodiments, the number of ALD cycles is in the range of approximately 5 to 25 cycles; in some embodiments, it is in the range of approximately 10 to 20 cycles; and in some embodiments, it is in the range of approximately 10 to 15 cycles.

[0057] In method operation 410, a fluorine-containing gas is introduced into the processing chamber. In method operation 412, RF power is applied to the processing chamber to generate plasma from the fluorine-containing gas, thus performing fluorine plasma treatment. After plasma treatment, the processing chamber is then cleaned in method operation 414. In method operation 416, if the predetermined number of cycles has not been reached, the method then returns to method operation 406. Therefore, the cycle of ALD deposition and fluorine plasma treatment is repeated until the predetermined number of cycles is reached.

[0058] After completing the predetermined number of cycles, the wafer is then removed from the processing tool in method operation 420.

[0059] Optionally, in some embodiments, after method operation 416 has completed a predetermined number of cycles, an additional predetermined number of ALD cycles are performed (without the suppression treatment of method operations 410, 412, and 414). This is useful when the ALD+ suppression treatment cycles of method operations 406 to 416 are sufficient to achieve deposition to the level of the recess, thereby removing (or sufficiently reducing) the recess, allowing general ALD gap filling to fill the remainder of the feature.

[0060] The process parameters for fluorine plasma treatment can be varied according to various embodiments of the invention. In some embodiments, dual-frequency RF power is applied, which combines a relatively low frequency (LF; e.g., generated by an LF generator) with a relatively high frequency (HF; e.g., generated by an HF generator). In some embodiments, the low frequency is in the range of approximately 400 to 430 kHz. In some embodiments, the frequency is in the range of approximately 200 to 600 kHz. In some embodiments, the high frequency is in the range of approximately 13 to 14 MHz. In some embodiments, the high frequency range can extend from approximately 10 MHz to 120 MHz. In some embodiments, the high frequency is 13.56 MHz.

[0061] In some embodiments, the power used for fluorine plasma treatment is in the range of about 500 to 2500 watts. In some embodiments, the power is in the range of about 50 watts to 5 kilowatts. Generally, increasing the power is associated with an increase in the suppression effect, which extends deeper into the feature.

[0062] In some embodiments, the temperature used for fluorine plasma treatment is in the range of approximately 75 to 550 degrees Celsius. In some embodiments, the temperature is in the range of approximately 20 to 800 degrees Celsius. It should be understood that the optimal temperature may depend on the specific application, such as what circuitry is located in the appropriate position on a given substrate / wafer. For example, a higher temperature may be used at a lower level, while a lower temperature may be used at a higher level to protect existing structures.

[0063] In some implementations, the pressure of the fluorine plasma treatment is in the range of approximately 0.5 to 8 Torr. More broadly, increasing the pressure is associated with a greater suppression effect that extends deeper into the features.

[0064] In some implementations, the fluorine plasma treatment time ranges from about 0.1 to 3 seconds. Generally, increasing the time is associated with an increase in the inhibition effect, which extends deeper into the feature.

[0065] In addition, increasing the flow rate of fluorine-containing gas will improve the suppression effect.

[0066] In view of the above, it should be understood that the parameters of the ALD+ plasma suppression treatment cycle defined by method operations 406 to 416 may vary from one cycle to the next or from one set of cycles to the next set of cycles to optimize the amount and level of suppression effect according to the structure of the feature (including depth and severity of any recesses) and the changes in the feature’s profile or structure as the filling process proceeds.

[0067] For example, in some implementations, using a first set of parameters, method operations 406 to 416 are performed for a first number of cycles with the goal of filling the feature to the level of a first recess. Subsequently, using a second set of parameters, method operations 406 to 416 are performed for a second number of cycles with the goal of filling the feature to the level of a second recess. It should be understood that this concept can be extended to aim for filling to the level of an additional recess, and optionally followed by ALD filling without suppression as described above.

[0068] In some implementations, the parameters of the fluorine plasma suppression treatment can be gradually changed during multiple ALD+ suppression treatment cycles. In other implementations, the fluorine plasma suppression treatment can be gradually stopped during these cycles, resulting in a gradual decrease in the effectiveness and depth of suppression.

[0069] Figure 5A This is a graph illustrating the effect of the suppression treatment according to an embodiment of the invention on subsequent deposition cycles. The graph shows the relationship between deposition thickness and the number of ALD cycles. Curve 500 shows the case without suppression treatment, which confirms that the deposition thickness increases approximately linearly with the increase of the number of ALD deposition cycles. Curve 502 shows the deposition thickness after fluorine plasma suppression treatment according to an embodiment of the invention. As shown by curve 502, the deposition thickness does not increase after a certain number of cycles following the suppression treatment, therefore ALD deposition is suppressed during these cycles. Subsequently, as the number of ALD cycles further increases, the final deposition thickness increases, indicating that the suppression effect of the suppression treatment gradually weakens.

[0070] For example, but not limited to, curve 502 could correspond to 1 second of inhibitor application, and near-no growth could occur until approximately 15 cycles after inhibitor application. Therefore, this shows that inhibition (e.g., at the top of the feature) reaches an amplified number of cycles.

[0071] Figure 5B To illustrate the relationship between suppression depth and suppression treatment time according to an embodiment of the invention. As curve 510 shows, the depth to which the suppression effect extends within the feature increases with the duration of the fluorine plasma suppression treatment. The graph shown represents a straight-walled feature, and as illustrated, for this feature, the effect is nearly linear, such that the suppression depth increases approximately linearly with the fluorine plasma treatment time. It should be understood that for other types of feature profiles, the effect may not be linear.

[0072] As shown in the figure, by adjusting certain parameters, such as the duration of the fluorine plasma suppression treatment, the amount and depth of suppression can be adjusted, thus targeting the location within the feature where deposition growth can occur. Therefore, time (or another adjustable parameter) can be used to target the recess, suppressing growth to the level of the recess, but allowing normal ALD growth to occur below the recess level. For recesses located at shallower depths, a shorter suppression treatment time can be used. For recesses located at deeper depths, a longer time can be used to target the recess and prevent ALD growth from reaching the level of the recess. Therefore, depending on the depth of the recess, the recess can be targeted by using a shorter time for the upper recess or a longer time for the lower recess.

[0073] It should be noted that, unlike prior art suppression techniques, the suppression effect provided by the fluorine plasma treatment according to the embodiments of the present invention lasts for multiple ALD cycles. Unbound by theory, it is assumed that the plasma initially contains fluorine-containing gas, and that bonds homogenize to generate fluorine-localized radicals. Since radicals are highly reactive, fluorine radicals exhibit enhanced reactivity towards the substrate. Therefore, theoretically, there may be not only physical adsorption but also chemisorption of terminal fluorine substances. This produces a very inert surface structure that can withstand multiple ALD cycles.

[0074] Furthermore, note that some etching may be caused by fluorine plasma suppression treatment. Therefore, theoretically, plasma treatment can also achieve selective deposition by selectively etching to a certain depth within the feature.

[0075] It should be understood that the techniques disclosed herein can be applied to gap-filling applications in trenches (STI), vias, and the like. For example, but not limited to, the deposited materials may include nitrides, oxides, polysilicon, silicon, etc. For example, but not limited to, the techniques disclosed herein may be useful in processes used to create NAND devices, DRAM, logic, STI, horizontal gap filling, vertical gap filling, etc.

[0076] The technology according to embodiments of the invention provides a significant improvement in throughput and achieves complete gap filling of concave structures without pinch-offs or void formation. To process the concave portion at the top of a feature, previous deposition techniques required very lengthy inhibitor filling (e.g., 20-25 second cycles with inhibitor treatment in each ALD cycle); then, when the gap filling reached a point where there was no more masking in the feature, a long etching process (e.g., 30 seconds) was performed, followed by general ALD deposition to complete the filling. However, contrary to the prior methods, for example, but not limited to, embodiments of the invention, a fully filled structure can be obtained by performing approximately ten ALD filling cycles, followed by 0.1-0.3 second inhibition, and then repeating the process approximately 60 to 100 times.

[0077] As described herein, plasma suppression can be used to control deposition depth in pores and trenches. Plasma suppression continues for multiple ALD cycles without requiring surface reprocessing. Regarding the fluorine plasma described, it should be understood that any fluorine-containing precursor suitable for generating the fluorine plasma can be used, including but not limited to the following examples: CH3F, CHF3, CF4, C2H4F2, C2H2F4, C3H2F6, C4H2F8, C4F8, NF3, SF6, etc. Furthermore, although fluorine plasma has been specifically described, it should be understood that other inhibitors can be used, including the following: NH3, ethylenediamine, methylamine, dimethylamine, trimethylamine, tert-butylamine, ethylamine, diethylamine, trimethylamine, methanol, ethanol, propanol, isopropanol, ethylene glycol, alkanolamine, ethanolamine, etc.

[0078] Figure 6A , 6B Figure 6C conceptually illustrates a cross-sectional view of features on a substrate and shows a gap-filling process according to an embodiment of the invention. Figure 6A As shown, feature 600 is defined in a substrate. Feature 600 includes a recess 602. To fill feature 600, it is desirable to minimize or reduce growth above the recess 602, and to allow growth to reach and include the recess 602. Therefore, generally speaking, as shown, the level at the beginning of the recess 602 defines a target suppression level when moving down along feature 600, such that growth above the target suppression level is suppressed, while growth below the target suppression level is permitted.

[0079] Therefore, the gap-filling procedure according to an embodiment of the present invention can be used to fill the feature 600, including the gap filling of the recess 602, while avoiding pinching or void formation caused by the recess 602. That is, as Figure 6B As shown, the adjustable ALD+ suppression treatment cycle suppresses ALD growth above the recess 602, while allowing faster growth below and up to the recess 602. It should be understood that each cycle comprises multiple ALD cycles with a single suppression treatment. In some embodiments, the gap-filling process fills more slowly above the recess, thus filling the recess before the area above it is filled. This process allows for complete gap-filling of feature 600 without voids, such as... Figure 6C As shown.

[0080] Figures 7A to 7F A cross-sectional view showing a feature with multiple recesses is illustrated, demonstrating a process for gap filling according to an embodiment of the invention. Figure 7A As shown, feature 700 includes a first recess 702 located deep within feature 700 and a second recess 704 located toward the center of feature 700. The first recess 702 defines a first inhibition target level, and inhibition is targeted thereto such that growth can reach and encompass the first recess 702, while inhibiting growth above that level.

[0081] Therefore, as Figure 7B As shown, the first cycle of ALD+ suppression processing is performed with the first suppression target level as the target. Therefore, feature 700 is filled to reach and include the first recess 702, and no gaps are formed, as... Figure 7C As shown.

[0082] Similar to the description of the first recess 702, the second recess 704 also defines a second inhibition target level, and inhibition is targeted thereto, so that growth can reach and include the second recess 704, while inhibiting growth above that level.

[0083] Therefore, as Figure 7D As shown, a second ALD+ suppression processing cycle is performed with the second suppression target level as the objective. Therefore, feature 700 is filled to reach and include the second recess 704, and no voids are formed, as... Figure 7E As shown.

[0084] After the first and second recesses are filled, in some embodiments, general ALD (non-inhibition process) is then performed to complete the gap filling of feature 700, such as... Figure 7F As shown.

[0085] Deposition processes based on deposition-etch-deposition (DED) (e.g., ALD oxide → etching → repetition) and suppression (e.g., fluorine suppression as described above) have been shown to fill high aspect ratio vias, holes, and trenches, as mentioned above. However, compared to standard ALD-based growth techniques, the DED / suppression method suffers from throughput limitations due to existing hardware configurations.

[0086] Therefore, according to embodiments of the invention, hardware enhancement is combined with DED / suppression technology to fill high aspect ratio structures with concave features, thereby providing throughput comparable to or better than standard ALD filling processes. The overall throughput of ALD films grown under standard ALD process conditions is also improved. To achieve higher throughput, new growth technologies are combined with new hardware. More specifically, in terms of hardware, a new set of manifolds is employed to allow for rapid circulation times of the etch / suppression / passivation gases. The etch / suppression / passivation gases are used to reshape / treat the surface to achieve gapless growth.

[0087] Figure 8 A gas supply system according to an embodiment of the invention is shown for supplying process gas to a processing chamber for ALD (Alternating Current Discharge) process. A central gas supply unit 800 is configured to deliver the process gas of the system to nozzles 856. The central gas supply unit 800 is defined by several sections and manifolds capable of supplying various gases to nozzles 856 and thus to the processing chamber.

[0088] As shown in the figure, the central gas supply device 800 includes a feed line 806 through which inert gas 802 is supplied to the central gas supply device 800. The flow of inert gas 802 into the central gas supply device 800 can be controlled by a valve 804.

[0089] The central gas supply unit 800 also includes a manifold 808 configured to allow oxidant 812 to be delivered into the central gas supply unit 800. Oxidant 812 is delivered via a feed line 810 connected to manifold 808. Furthermore, the flow of oxidant into manifold 808 can be controlled by valve 814. Additionally, in some embodiments, the oxidant can be diverted via valve 816 as shown.

[0090] Section 818 connects manifold 808 and manifold 820. Manifold 820 is configured to allow suppression or passivation gas 824 to be delivered to the central gas supply unit 800. Suppression / passivation gas 824 is delivered via feed line 822 connected to manifold 820. The delivery of suppression / passivation gas 824 is controlled by valve 826. In the illustrated embodiment, actuator 828 is configured to control the opening / closing of valve 826.

[0091] Section 830 connects between manifold 820 and manifold 832. Manifold 832 is configured to allow cleaning or etching gas 836 to be delivered to the central gas supply unit 800. Cleaning / etching gas 836 is delivered via feed line 834 connected to manifold 832. The delivery of cleaning / etching gas 836 is controlled by valve 838. In the illustrated embodiment, actuator 840 is configured to control the opening / closing of valve 838.

[0092] Section 842 connects manifold 832 and manifold 844. Manifold 844 is configured to allow ALD precursor gas 848 to be delivered to the central gas supply unit 800. ALD precursor gas 848 is delivered via feed line 846 connected to manifold 844. The delivery of ALD precursor gas 848 is controlled by valve 850. In the illustrated embodiment, inert gas 802 may also be delivered via feed line 846, as controlled by valve 852. This inert gas can be used after the ALD precursor is injected to purge any residual precursor in feed line 846.

[0093] Section 854 is connected to manifold 844 and directs gas to nozzle 856, which is configured to deliver the treatment gas to the treatment chamber.

[0094] As shown in the figure, the suppression / passivation gas and the cleaning / etching gas are supplied through separate manifolds, which are completely independent of the delivery of ALD precursor gas 848 and oxidant 812.

[0095] Figure 9A and 9B The difference between the existing system and a system with separate manifolds for delivering suppression / passivation gases and cleaning / etching gases is shown.

[0096] Figure 9A The configuration of an existing system is shown. As illustrated, gases are delivered to the processing chamber via two manifolds. An oxidant (e.g., for the second injection step in the ALD process) is delivered through one manifold. However, the deposition (ALD precursor) and etching / cleaning (e.g., fluorine-containing) gases are delivered through the other manifold. Because the deposition and cleaning / etching gases share a manifold, processing delays occur when switching between deposition and etching-cleaning processes due to the need to purge the precursor / cleaning-etching manifold. For example, switching between the ALD precursor and fluorine-containing gas could require lengthy purging times, taking approximately 100 to 300 seconds in total.

[0097] Figure 9BA system configuration with independent manifolds for multiple process gases according to an embodiment of the invention is shown. To overcome purging requirements, throughput is increased by using separate suppression, cleaning-etching, oxidant, and precursor manifolds. Long purging times (e.g., minutes) can be reduced to seconds to achieve deposition-etching-suppression / passivation cycle times similar to ALD.

[0098] For example, in the case of fluorinated suppressant gases as previously described, the fluorinated gas can be supplied via a cleaning-etching manifold independent of the ALD precursor manifold, thus eliminating the previously required lengthy purging. Additionally, the system can accommodate the use of other suppressant gases, which are also configured with independent suppressant / passivation manifolds for delivery.

[0099] Both the cleaning-etching and suppression / passivation manifolds are independent of the ALD precursor manifold, thus the entire ALD process is independent of the suppression or fluorine treatment gas in terms of gas delivery. This accelerates the changeover time of multiple processes, enabling rapid and continuous execution of combinations of ALD, etching, and suppression / passivation processes with minimal changeover time, thereby increasing system throughput.

[0100] Figure 10A , 10B 10C demonstrates that gap-filling performance can be improved by utilizing techniques according to embodiments of the present invention. Figure 10A A cross-sectional view of feature 1000 after a gap-filling process using the standard ALD process according to the most well-known method is conceptually shown. The resulting gap fill 1002 may include voids 1004. Generally speaking, it is desirable to minimize these voids, making them as deep as possible, but also to make the gap-filling deposition as fast as possible. Figure 10B The diagram illustrates gap filling using a high-throughput ALD process, specifically feature 1000, which, for example, reduces processing time to 0.3 times that of the standard ALD process. However, as shown, gap filling 1006 exhibits poor results, with gaps 1008 extending higher and wider than those in the standard ALD process. Despite improved throughput, gap filling performance is compromised.

[0101] However, Figure 10C This illustrates gap filling characterized by a DED process followed by a high-throughput ALD process (e.g., DED to overcome concavity, followed by high-throughput ALD to complete the filling) utilizing the technology and hardware according to embodiments of the invention. In the resulting gap fill 1010, minimal voids 1012 or no voids were observed, and the throughput was improved to 0.5 times the process time of a standard ALD.

[0102] Figure 11A cluster tooling system 1100 for processing substrates according to an embodiment of the invention is shown. Cluster tooling systems are typically installed in manufacturing facilities. Substrates (e.g., wafers) are transported into or out of the cluster tooling system using a transport container 1102 (e.g., a front-opening wafer transfer cassette (FOUP)). An equipment front-end module (EFEM) 1104 includes a robot 1106 configured to transfer wafers between the transport module 1102 and a loading lock 1108. A transfer module 1110 includes a robot 1112 configured to transfer wafers between the loading lock 1108 and one of a plurality of processing tools 1114. In the illustrated embodiment, each processing tool 1114 is a multi-station processing tool with a plurality of processing stations 1116 to be able to process multiple wafers simultaneously. For example, in the illustrated embodiment, each multi-station processing tool 1114 has four processing stations 1116, which are capable of processing four wafers simultaneously (e.g., performing an ALD process as described in an embodiment of the invention).

[0103] In some embodiments, a controller is part of a system configured to perform operations or methods according to the disclosed embodiments. Such systems may include semiconductor processing apparatuses comprising one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronics may be referred to as a “controller” and may control various components or sub-components of one or more systems. Depending on the processing requirements and / or system type, the controller may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer tools and other transfer tools, and / or loading locks connected to or interfaced with a specific system.

[0104] In general, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. Integrated circuits can include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions can be instructions sent to the controller in the form of various individual settings (or program files), which define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silica, surfaces, circuits, and / or the die of the wafer.

[0105] In some implementations, the controller may be part of or coupled to a computer integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or be all or part of a fab host system, allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria of multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool, to which the controller is configured to interface with or control the tool. Therefore, as described above, a controller can be distributed, for example, by comprising one or more discrete controllers networked together and operating toward a common purpose (such as the process and control described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a room that communicate with one or more integrated circuits remotely (e.g., at the platform level or as part of a remote computer), which together control the process on the room.

[0106] Example systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, rotary rinsing chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfering edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0107] As described above, depending on one or more processing steps to be performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a host computer, another controller, or tools used in the transport of materials to and from the tool location and / or loading port in the semiconductor manufacturing plant.

[0108] Figure 12 This is a simplified schematic diagram of a computer system used to implement embodiments of this disclosure. It should be understood that the methods described herein can be executed with a digital processing system, such as a conventional general-purpose computer system. A dedicated computer designed or programmed to perform only one function may be used as an alternative. Computer system 1800 includes a central processing unit (CPU) 1804 coupled via bus 1810 to random access memory (RAM) 1828, read-only memory (ROM) 1812, and mass storage device 1814. System controller program 1808 resides in random access memory (RAM) 1828, but may also reside in mass storage device 1814.

[0109] Mass storage device 1814 represents a persistent data storage device, such as a floppy disk drive or a fixed disk drive, which can be local or remote. Network interface 1830 provides connectivity via network 1832, allowing communication with other devices. However, it should be understood that CPU 1804 can be embodied within a general-purpose processor, a dedicated processor, or a dedicated programming logic device. Input / output (I / O) interface 1820 provides communication with various peripheral devices and is connected to CPU 1804, RAM 1828, ROM 1812, and mass storage device 1814 via bus 1810. Examples of peripheral devices include a display 1818, a keyboard 1822, a cursor control 1824, a removable media device 1834, and so on.

[0110] Display 1818 is configured to display the user interface described herein. Keyboard 1822, cursor control (mouse) 1824, removable media device 1834, and other peripheral devices are coupled to I / O interface 1820 to transmit information to CPU 1804 during command selection. It should be understood that data entering and leaving external devices can be transmitted via I / O interface 1820. The implementation can also be carried out in a distributed computing environment where tasks are performed by remote processing devices connected via wired or wireless networks.

[0111] The implementation schemes can be run with various computer system configurations, including handheld devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. These implementation schemes can also be implemented in a distributed computing environment where tasks are performed by remote processing devices connected via a network.

[0112] In light of the above embodiments, it should be understood that the embodiments can employ various computer-implemented operations involving data stored in a computer system. These operations are those that require physical manipulation of physical quantities. Any operation described herein that forms part of the embodiments is a useful machine operation. The embodiments also relate to devices or apparatuses for performing these operations. The apparatus can be specifically configured for the desired purpose, such as a dedicated computer. When defined as a dedicated computer, the computer can also perform other processing, program execution, or routines that are not part of the dedicated purpose, while still being able to operate for the dedicated purpose. Alternatively, the operations can be performed by a general-purpose computer selectively started or configured by one or more computer programs stored in computer memory, cache, or obtained via a network. When data is obtained via a network, the data can also be processed by other computers on the network, such as cloud computing resources.

[0113] One or more embodiments may also be configured as computer-readable code on a computer-readable medium. This computer-readable medium is any data storage device capable of storing data that can subsequently be read by a computer system. Examples of computer-readable media include hard disk drives, network attached storage (NAS), read-only memory, random access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. Computer-readable media may include computer-readable tangible media distributed across network-coupled computer systems, thereby distributively storing and executing computer-readable code.

[0114] Although the operations of this method are described in a specific order, it should be understood that other housekeeping operations may be performed between operations, or operations may be adjusted so that they can occur at slightly different times, or they may be distributed in the system to allow processing operations to occur at different intervals associated with processing, as long as the processing of overlapping operations is performed in the desired manner.

[0115] Therefore, the disclosure of exemplary embodiments is intended to be illustrative and not to limit the scope of this disclosure, which is set forth in the appended claims and their equivalents. Although exemplary embodiments of this disclosure have been described in detail for clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. Unless expressly stated in the claims or implied by the disclosure, elements and / or steps do not imply any particular order of operations in the appended claims.

Claims

1. A method for performing gap filling of features on a substrate, comprising: Perform the following operations in sequence: (a) Performing a first plurality of cycles of an atomic layer deposition process on the substrate continuously in a processing chamber; (b) Purge the first processing gas from the first plurality of cycles of the atomic layer deposition process from the processing chamber; (c) The substrate is subjected to a first plasma treatment by introducing a fluorine-containing gas into the processing chamber and applying a first RF power to the fluorine-containing gas to generate a first fluorine plasma in the processing chamber; (d) Purge the second processing gas from the first plasma treatment from the processing chamber; (e) Repeat operations (a) through (d) in sequence until multiple loops of the predetermined operations (a) through (d) are performed; (f) Performing a second plurality of cycles of the atomic layer deposition process on the substrate continuously in the processing chamber; (g) Purge the third processing gas from the second plurality of cycles of the atomic layer deposition process from the processing chamber; (h) The substrate is subjected to a second plasma treatment by introducing a fluorine-containing gas into the processing chamber and applying a second RF power to the fluorine-containing gas to generate a second fluorine plasma in the processing chamber; (i) Purge the fourth processing gas from the second plasma process from the processing chamber; (j) Repeat operations (f) to (i) in sequence until multiple loops of predetermined operations (f) to (i) are executed.

2. The method according to claim 1, in, The first plasma treatment passivation extends downward from the top of the feature to a first portion of the feature at a first predetermined target level, thereby suppressing deposition by the atomic layer deposition process on the passivated first portion of the feature; The second plasma treatment passivation extends downward from the top of the feature to a second portion of the feature at a second predetermined target level, thereby suppressing deposition by the atomic layer deposition process on the passivated second portion of the feature.

3. The method according to claim 2, wherein, The first predetermined target level defines a first depth in the feature, and the second predetermined target level defines a second depth in the feature, wherein the first depth is greater than the second depth.

4. The method of claim 3, wherein the first predetermined target level or the second predetermined target level is controlled by one or more parameters of the first plasma treatment or the second plasma treatment.

5. The method according to claim 4, The parameters of the first plasma treatment include one or more of the following: the duration of the first plasma treatment, the temperature of the first plasma treatment, the first pressure of the fluorine-containing gas, and the level of the first RF power; and The parameters of the second plasma treatment include one or more of the following: the duration of the second plasma treatment, the temperature of the second plasma treatment, the second pressure of the fluorine-containing gas, and the level of the second RF power.

6. The method according to claim 2, The feature includes a first recess, and the first predetermined target level is defined at the level of the first recess to substantially suppress deposition by the atomic layer deposition process above the level of the first recess by the first plasma treatment. The feature includes a second recess, and the second predetermined target level is defined at the level of the second recess to substantially suppress deposition by the atomic layer deposition process above the level of the second recess by the second plasma treatment.

7. The method of claim 6, wherein a predetermined number of cycles of operation (e) is configured to affect gap filling to remove a first recess in the feature, and wherein a predetermined number of cycles of operation (j) is configured to affect gap filling to remove a second recess in the feature.

8. The method of claim 2, wherein the first fluorine plasma or the second fluorine plasma passivates the first portion or the second portion of the feature by forming a fluorine terminal material along the surface of the first portion or the second portion of the feature.

9. The method of claim 1, further comprising: (k) Perform one or more cycles of the atomic layer deposition process.

10. The method of claim 9, wherein the one or more cycles of the atomic layer deposition process of operation (k) are configured to complete the gap filling of the feature.

11. The method of claim 1, wherein the atomic layer deposition process is configured to deposit an oxide in the feature of the substrate.

12. The method according to claim 1, wherein the fluorine-containing gas is CH3F, CHF3, CF4, C2H4F2, C2H2F4, C3H2F6, C4H2F8, C4F8, NF3 or SF6.

13. The method of claim 1, wherein the first RF power or the second RF power is applied at a frequency in the range of 200 to 600 kHz.

14. The method of claim 1, wherein the pressure of the first plasma treatment or the second plasma treatment is in the range of 0.5 to 8 Torr.

15. The method of claim 1, wherein the duration of the first plasma treatment or the second plasma treatment is in the range of 0.1 to 3 seconds.

16. The method according to claim 9, in, The first plasma treatment passivation extends downward from the top of the feature to a first portion of the feature at a first predetermined target level, thereby inhibiting deposition by the atomic layer deposition process on the passivated first portion of the feature; The second plasma treatment passivation extends downward from the top of the feature to a second portion of the feature at a second predetermined target level, thereby suppressing deposition by the atomic layer deposition process on the passivated second portion of the feature.

17. The method according to claim 16, wherein, The first predetermined target level defines a first depth in the feature, and the second predetermined target level defines a second depth in the feature, wherein the first depth is greater than the second depth.

18. The method of claim 17, wherein the first predetermined target level or the second predetermined target level is controlled by one or more parameters of the first plasma treatment or the second plasma treatment.

19. The method according to claim 18, The parameters of the first plasma treatment include one or more of the following: the duration of the first plasma treatment, the temperature of the first plasma treatment, the first pressure of the fluorine-containing gas, and the level of the first RF power; and The parameters of the second plasma treatment include one or more of the following: the duration of the second plasma treatment, the temperature of the second plasma treatment, the second pressure of the fluorine-containing gas, and the level of the second RF power.

Images