Source switch charge pump and phase-locked loop for low temperature applications

Abstract

The application discloses a low-temperature source switch charge pump and a phase-locked loop. The low-temperature source switch charge pump comprises a bias unit and a core unit. The bias unit is used for providing a first reference current irrelevant to the voltage of a power supply; the core unit is connected with the bias unit, and the core unit comprises a charging module, a discharging module and two feedback transistors. The charging module is used for charging an output node by the first reference current through a charging control signal; the discharging module is used for discharging the output node by the first reference current through a discharging control signal; and the two feedback transistors are connected with the charging module and the discharging module respectively, and are used for feeding back the output node voltage to the charging module and the discharging module, so as to compensate the charging and discharging currents in the case that a first tail current source of the charging module or a second tail current source of the discharging module is in a linear region, and make the charging current and the discharging current match.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a source-switched charge pump and phase-locked loop for use at low temperatures. Background Technology

[0002] Phase-locked loops (PLLs) can generate low-jitter clock signals with stable frequency and phase, and can be used as clock generators. With the continuous development of technologies such as deep space exploration and quantum computing, there is a need for low-jitter clock generators to operate normally at extremely low temperatures (e.g., 4K). Charge pump PLLs can be applied to low-temperature clock circuit designs due to their good robustness. However, at extremely low temperatures, the channel length modulation effect of MOSFETs becomes more significant, leading to increased charge-discharge mismatch of the charge pump. Moreover, the threshold voltage of the transistor becomes higher, further reducing the output voltage range for charge-discharge current matching. This severely deteriorates the reference spurious and phase noise performance of the clock generator. These problems make it very difficult for low-temperature clock generators to achieve the same performance as room-temperature clock generators. Summary of the Invention

[0003] To address at least one of the technical problems mentioned above and others in the prior art, this disclosure provides a source-switched charge pump for low-temperature applications, which can eliminate charge sharing and clock feedthrough effects, improve the matching degree of charging and discharging currents, and enhance the dynamic performance of the clock generation circuit under harsh process or environmental conditions.

[0004] One aspect of this disclosure provides a source-switched charge pump for cryogenic applications, comprising:

[0005] A biasing unit, which provides a first reference current independent of the supply voltage; and

[0006] The core unit, connected to the aforementioned bias unit, includes:

[0007] The charging module is used to charge the output node using the charging control signal and the aforementioned first reference current;

[0008] The discharge module is used to discharge the output node using the first reference current via a discharge control signal; and

[0009] Two feedback transistors are connected to the charging module and the discharging module respectively, and are used to feed back the output node voltage to the charging module and the discharging module to compensate for the charging and discharging current when the first tail current source of the charging module or the second tail current source of the discharging module is in the linear region, so that the charging current and the discharging current are matched.

[0010] According to an embodiment of this disclosure, the adjustment unit is connected between the bias unit and the core unit and is adapted to output the first reference current from the bias unit as a compensation current in proportion to the binary code value through the binary code from the outside, and to superimpose the compensation current and the first reference current as a second reference current to resist the change of at least one of the loop parameters of the external frequency division ratio and the filter capacitor.

[0011] The core unit receives a second reference current from the regulating unit for charging and discharging.

[0012] According to embodiments of this disclosure, the adjustment unit includes:

[0013] The first current mirror module is adapted to mirror the first reference current from the above-mentioned bias unit to generate a second current.

[0014] Multiple sequentially connected adjustment modules are each connected to the first current mirror module, used to receive multiple bits of the aforementioned binary code and output the aforementioned second current proportionally according to the binary code value as a compensation current; and

[0015] The second current mirror module is connected to the output terminals of the first current mirror module and the aforementioned adjustment unit. The second current and the compensation current are superimposed at the input terminal of the second current mirror module to form a third current. The second current mirror module is adapted to mirror the third current to generate the second reference current.

[0016] According to embodiments of this disclosure, each of the above-described adjustment modules includes:

[0017] An adjusting transistor, the source of which is connected to the low-level terminal of the power supply, and the gate of which is connected to the output terminal of the first current mirror module; and a receiving transistor, the source of which is connected to the drain of the adjusting transistor, the gate of which is used to receive one bit of the binary code, and the source of which is connected between the first current mirror module and the second current mirror module to output the compensation current to the input terminal of the second current mirror module.

[0018] According to embodiments of this disclosure, the width-to-length ratio of a plurality of the above-described regulating transistors is increased or decreased in binary multiples to match the input binary code.

[0019] According to embodiments of this disclosure, the charging module includes:

[0020] The third current mirror assembly, connected to the aforementioned bias unit, is adapted to generate a first mirror current and a second mirror current based on the aforementioned first reference current mirror; and

[0021] The fourth current mirror assembly includes the first tail current source mentioned above. The fourth current mirror assembly is used to receive the first mirror current to generate a third mirror current, and under the action of the charging control signal, outputs the third mirror current as a charging current to the output node through the first tail current source.

[0022] The above-mentioned discharge module includes:

[0023] The fifth current mirror assembly, connected to the third current mirror assembly, is adapted to generate a fourth mirror current based on the second mirror current; and

[0024] The sixth current mirror assembly includes the second tail current source mentioned above. The sixth current mirror assembly is used to receive the fourth mirror current and generate the fifth mirror current. Under the action of the discharge control signal, the fifth mirror current is output as a discharge current to the output node through the second tail current source.

[0025] The first feedback transistor is connected in parallel with the third current mirror assembly. When the voltage at the output node causes the first tail current source to operate in the linear region, and the charging current is less than the discharging current, the first feedback transistor is turned on, drawing additional current from the low-level end of the power supply voltage and injecting it into the first tail current source to compensate for the charging current. The second feedback transistor is connected in parallel with the fifth current mirror assembly. When the voltage at the output node causes the second tail current source to operate in the linear region, and the charging current is greater than the discharging current, the second feedback transistor is turned on, drawing additional current from the high-level end of the power supply voltage and injecting it into the second tail current source to compensate for the discharging current.

[0026] According to embodiments of this disclosure, at least one of the third, fourth, fifth, and sixth current mirror assemblies is a Wilson current mirror structure.

[0027] According to embodiments of this disclosure, the bias unit includes: a current mirror bias module and a linear load.

[0028] The aforementioned current mirror bias module includes multiple first transistors operating in the saturation region. These multiple first transistors form a Wilson current mirror structure and are connected in series with the aforementioned linear load, so that the aforementioned first reference current is related to the resistance value of the aforementioned linear resistor but is independent of the aforementioned source voltage.

[0029] According to embodiments of this disclosure, the linear load is a second transistor operating in the linear region to improve layout matching.

[0030] Another aspect of the embodiments of this disclosure also provides a phase-locked loop, comprising:

[0031] A frequency and phase detector is suitable for converting the phase difference between a reference signal and a feedback signal into at least one of a charging control signal and a discharging control signal.

[0032] The aforementioned source-switched charge pump is suitable for charging and discharging a loop filter according to at least one of the aforementioned charging control signal and the aforementioned discharging control signal.

[0033] The above-mentioned loop filter is suitable for generating control voltage by charging and discharging resistors and capacitors;

[0034] A voltage-controlled oscillator, suitable for changing the output clock frequency according to the aforementioned control voltage; and

[0035] The frequency divider is suitable for using the clock frequency as the feedback signal to negatively feed back to the frequency and phase detector, so that the control voltage tends to be stable and the phases of the reference signal and the feedback signal are kept consistent.

[0036] According to embodiments of the present disclosure, a source-switched charge pump applied to low temperatures, by setting a feedback transistor, feeds back the voltage of the output node to the charging module and the discharging module, compensating for the charging and discharging currents of the first tail current source of the charging module or the second tail current source of the discharging module in the linear region. This achieves compensation for the matching degree of the charging and discharging currents. The source negative feedback improves the output impedance of the current mirror and enhances the current replication accuracy. It can improve the dynamic performance of the clock generation circuit under harsh process or environmental conditions, thereby at least partially overcoming the problem that the channel length modulation effect of the MOSFET becomes more significant at extremely low temperatures, leading to an increase in the charging and discharging mismatch of the charge pump. This achieves the suppression of the channel length modulation effect of the MOSFET at extremely low temperatures, increases the matching range of the output voltage, and increases the matching degree of charging and discharging. Attached Figure Description

[0037] Figure 1 The schematic diagram illustrates a circuit diagram of a source-switched charge pump applied at low temperatures according to an embodiment of the present disclosure;

[0038] Figure 2 The diagram schematically illustrates the charge-discharge matching curves of a source-switched charge pump according to an embodiment of the present disclosure.

[0039] Figure 3 The schematic diagram illustrates the charge-discharge matching curve of the source-switched charge pump with a 55µA output according to an embodiment of the present disclosure;

[0040] Figure 4 The schematic diagram illustrates the charge-discharge matching curve of a source-switched charge pump without a feedback transistor at a 55µA output according to an embodiment of the present disclosure.

[0041] Figure 5The diagram schematically illustrates the dynamic charge-discharge matching curve of the source-switched charge pump under a 2ns pulse input according to an embodiment of the present disclosure.

[0042] Figure 6 The diagram schematically illustrates the charging and discharging results of the charge pump during a single-cycle pulse input according to an embodiment of the present disclosure; and

[0043] Figure 7 A block diagram of a phase-locked loop according to an embodiment of the present disclosure is shown schematically.

[0044] Explanation of reference numerals in the attached figures:

[0045] 1-Bias unit;

[0046] 11- Current mirror bias module;

[0047] 2-Core Unit;

[0048] 21-Third current mirror assembly;

[0049] 22-Fourth current mirror assembly;

[0050] 23-Fifth current mirror assembly;

[0051] 24-Sixth Current Mirror Assembly;

[0052] 3-Adjustment unit;

[0053] 31-First Current Mirror Module;

[0054] 32-Adjustment module;

[0055] 33-Second Current Mirror Module. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. However, this disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout.

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0058] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprising", "including", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0059] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0060] For the convenience of those skilled in the art to understand the technical solutions of the present disclosure, the following technical terms will be explained.

[0061] In cases where expressions similar to "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). In cases where expressions similar to "at least one of A, B, or C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0062] In the prior art, quantum chips operate in an extremely low-temperature environment (for example, at a temperature of 4K), and a series of integrated circuits配套 with the quantum chips will also operate in an extremely low-temperature environment. The digital modules of these integrated circuits require a low-temperature clock to generate a low-jitter clock signal. Among them, the low-temperature clock generally adopts a charge pump phase-locked loop structure. Limited by the refrigeration power and volume of the low-temperature cavity, the low-temperature clock must have low power consumption and a small area.

[0063] To address the aforementioned issues, this disclosure provides a programmable source-switched charge pump capable of operating at extremely low temperatures. Based on Nexchip's 110nm CMOS process, it is a circuit optimized for extremely low temperature environments. The circuit has no operational amplifiers and adopts an output feedback structure, thus exhibiting better dynamic and static matching characteristics, smaller area, and lower power consumption.

[0064] Figure 1 The schematic diagram illustrates a circuit diagram of a source-switched charge pump applied at low temperatures according to an embodiment of the present disclosure.

[0065] This disclosure provides a source-switched charge pump for use at low temperatures, such as... Figure 1 As shown, it includes a bias unit 1 and a core unit 2. The bias unit 1 is used to provide a first reference current independent of the power supply voltage. The core unit 2 is connected to the bias unit 1 and includes a charging module, a discharging module, and two feedback transistors (MP2 and NP2). The charging module is used to charge the output node OUT using the charging control signal UP through the first reference current. The discharging module is used to discharge the output node OUT using the discharging control signal DN through the first reference current. The two feedback transistors are connected to the charging module and the discharging module respectively and are used to feed back the voltage of the output node OUT to the charging module and the discharging module to compensate for the charging and discharging currents when the first tail current source PM1 of the charging module or the second tail current source NM1 of the discharging module is in the linear region, so that the charging current and the discharging current are matched.

[0066] According to embodiments of the present disclosure, a source-switched charge pump applied to low temperatures, by setting a feedback transistor, feeds back the voltage of the output node to the charging module and the discharging module, compensating for the charging and discharging currents of the first tail current source of the charging module or the second tail current source of the discharging module in the linear region. This achieves compensation for the matching degree of the charging and discharging currents. The source negative feedback improves the output impedance of the current mirror and enhances the current replication accuracy. It can improve the dynamic performance of the clock generation circuit under harsh process or environmental conditions, thereby at least partially overcoming the problem that the channel length modulation effect of the MOSFET becomes more significant at extremely low temperatures, leading to an increase in the charging and discharging mismatch of the charge pump. This achieves the suppression of the channel length modulation effect of the MOSFET at extremely low temperatures, increases the matching range of the output voltage, and increases the matching degree of charging and discharging.

[0067] According to some embodiments of this disclosure, the source switching charge pump provided by this disclosure is applicable to low temperature environments, which may include any of the following temperature environments: 4K (Kelvin), 10K, 16K and 50K.

[0068] According to some embodiments of this disclosure, bias unit 1 is a Wilson current mirror bias circuit. A current mirror circuit is used to copy one current to another to achieve functions such as a current source or current amplifier. Figure 1 As shown, bias unit 1 can be composed of three NPN transistors and two PNP transistors. The three NPN transistors include NM3, NM5 and NM6 transistors; the two PNP transistors include PM3 and PM4 transistors.

[0069] In the source-switched charge pump for cryogenic applications provided in this disclosure, the transistor can be at least one of a MOS transistor or a CMOS transistor.

[0070] According to some embodiments of this disclosure, the first feedback transistor of the charging module is a P-type transistor PM2, and the second feedback transistor of the discharging module is an N-type transistor NM2. The output voltage from the output node OUT is connected to the gate of the second feedback transistor PM2 and the gate of the first feedback transistor NM2, respectively.

[0071] According to some embodiments of this disclosure, such as Figure 1 As shown, the source-switched charge pump also includes an adjustment unit 3, which is connected between the bias unit 1 and the core unit 2. It is adapted to output the first reference current from the bias unit 1 as a compensation current according to the binary code value through the binary code from the outside, and to make the compensation current superimposed with the first reference current as a second reference current, so as to resist the change of at least one of the loop parameters such as the external frequency division ratio and the filter capacitor. The core unit 2 receives the second reference current from the adjustment unit 3 for charging and discharging.

[0072] According to some embodiments of this disclosure, the compensation current refers to the current output by the first reference current in proportion to the binary code value, and the compensation current plus the first reference current is the second reference current.

[0073] According to some embodiments of this disclosure, since the loop filter of the clock generation circuit is designed off-chip, its bandwidth is not fixed and needs to be adjusted according to the phase noise of each module being tested. Therefore, the loop bandwidth may vary. Furthermore, to make the output frequency adjustable, the clock generator employs a 2 / 3-mode multi-mode divider; different division ratios will also lead to changes in loop parameters. By setting an adjustment unit, the first reference current can be compensated for different division ratios according to the actual circuit.

[0074] According to some embodiments of this disclosure, the adjustment unit 3 includes a first current mirror module 31, a plurality of adjustment modules 32 connected in sequence, and a second current mirror module 33. The first current mirror module 31 is adapted to mirror a first reference current from the bias unit 1 to generate a second current; the plurality of adjustment modules 32 connected in sequence are respectively connected to the first current mirror module 31, and are used to receive multiple bits of binary code and output the second current as a compensation current proportional to the binary code value; the second current mirror module 33 is connected to the output terminals of the first current mirror module 31 and the adjustment unit 3, and the second current and the compensation current are superimposed at the input terminal of the second current mirror module 33 to form a third current, and the second current mirror module 33 is adapted to mirror the third current to generate the second reference current.

[0075] According to some embodiments of this disclosure, the number of adjustment modules 32 may include any one of 1, 2, 3, 4, 5, etc.

[0076] According to some embodiments of this disclosure, such as Figure 1 As shown, each adjustment module 32 includes an adjustment transistor and a receiving transistor. The source of the adjustment transistor is connected to the low-level terminal of the power supply, and the gate of the adjustment transistor is connected to the output terminal of the first current mirror module 31. The source of the receiving transistor is connected to the drain of the adjustment transistor, the gate of the receiving transistor is used to receive one bit of the binary code, and the source of the receiving transistor is connected between the first current mirror module 31 and the second current mirror module 33 to output the compensation current to the input terminal of the second current mirror module 33.

[0077] According to embodiments of this disclosure, both the regulating transistor and the receiving transistor can be N-type transistors.

[0078] In one illustrative embodiment, the adjustment module 32 employs a current-mode digital-to-analog converter (DAC), such as... Figure 1 As shown, the adjustment unit includes three adjustment modules 32 connected in sequence. The first adjustment module includes N-type transistors MN11 and MN12, the second adjustment module includes N-type transistors MN13 and MN14, and the third adjustment module includes N-type transistors MN15 and MN16. MN11, MN13, and MN15 are adjustment transistors, as are MN12, MN14, and MN16. Three binary codes, S0, S1, and S2, are connected sequentially to the gates of the adjustment transistors MN12, MN14, and MN16 to receive binary codes from the outside. These binary codes are used to control the switching on and off of the three adjustment transistors MN11, MN13, and MN15, respectively, to output a compensation current matching the binary code value.

[0079] When the binary code value received by the adjustment module is 001 (that is, S0=0, S1=0, S2=1), the compensation current output by the adjustment unit is 1 / 8 times the second current, and the magnitude of the third current is 9 / 8 times the second current; when the binary code value received by the adjustment module is 101 (that is, S0=1, S1=0, S2=1), the compensation current output by the adjustment unit is 5 / 8 times the second current.

[0080] According to some embodiments of this disclosure, the width-to-length ratio of a plurality of regulating transistors is increased or decreased by a binary multiple to match the input binary code.

[0081] In one illustrative embodiment, such as Figure 1 As shown, the adjustment unit includes three adjustment modules 32 connected in sequence. The width-to-length ratio of the adjustment transistors (NM11, NM13 and NM15) of each adjustment module 32 is increased or decreased by a binary multiple to adjust the magnitude of the compensation current so that the compensation current matches the binary code value received by the three adjustment units.

[0082] According to some embodiments of this disclosure, such as Figure 1 As shown, the charging module includes a third current mirror assembly 21 and a fourth current mirror assembly 22. The third current mirror assembly 21 is connected to the bias unit 1 and is used to generate a first mirror current and a second mirror current based on the first reference current. The fourth current mirror assembly 22 includes a first tail current source PM1. The fourth current mirror assembly 22 is used to receive the first mirror current to generate a third mirror current, and under the action of the charging control signal UP, it outputs the third mirror current as the charging current to the output node OUT through the first tail current source PM1.

[0083] According to some embodiments of this disclosure, such as Figure 1 As shown, the discharge module includes a fifth current mirror assembly 23 and a sixth current mirror assembly 24. The fifth current mirror assembly 23 is connected to the third current mirror assembly 21 and is used to generate a fourth mirror current based on the second mirror current. The sixth current mirror assembly 24 includes a second tail current source NM1. The sixth current mirror assembly 24 is used to receive the fourth mirror current and generate the fifth mirror current. Under the action of the discharge control signal DN, the fifth mirror current is output as the discharge current to the output node OUT through the second tail current source NM1.

[0084] According to some embodiments of this disclosure, such as Figure 1As shown, the first feedback transistor NM2 is connected in parallel with the third current mirror assembly 21. When the voltage at the output node OUT causes the first tail current source PM1 to operate in the linear region, the charging current is less than the discharging current. The first feedback transistor NM2 turns on, drawing additional current from the low-level terminal GND of the power supply voltage and injecting it into the first tail current source PM1 to compensate for the charging current. The second feedback transistor PM2 is connected in parallel with the fifth current mirror assembly 23. When the voltage at the output node OUT causes the second tail current source NM1 to operate in the linear region, the charging current is greater than the discharging current. The second feedback transistor PM2 turns on, drawing additional current from the high-level terminal of the power supply voltage and injecting it into the second tail current source NM1 to compensate for the discharging current. By appropriately adjusting the width-to-length ratio of the feedback transistors, the feedback strength is adjusted, thereby widening the matching range of the output voltage and reducing the charging and discharging current mismatch.

[0085] According to some embodiments of this disclosure, such as Figure 1 As shown, at least one of the third current mirror assembly 21, the fourth current mirror assembly 22, the fifth current mirror assembly 23 and the sixth current mirror assembly 24 is a Wilson current mirror structure.

[0086] In one illustrative embodiment, the third current mirror assembly 21, the fourth current mirror assembly 22, the fifth current mirror assembly 23, and the sixth current mirror assembly 24 can all be Wilson current mirror structures.

[0087] In one illustrative embodiment, such as Figure 1 As shown, the third current mirror assembly 21 is a Wilson current mirror structure, including six N-type transistors: NM9, NM10, NM21, NM22, NM23, and NM24. NM9 is a diode-connected transistor, meaning its gate and drain are shorted. The gates of NM10, NM22, and NM24 are connected to the high-level power supply terminal VDD, and their sources are connected to the low-level power supply terminal GND. The gates of NM9, NM21, and NM23 are interconnected. The source of NM9 is connected to the drain of NM10, the source of NM21 is connected to the drain of NM22, the source of NM23 is connected to the drain of NM24, and the drain of NM21 is connected to the fifth current mirror unit 23. The source of the first feedback transistor NM2 is connected to the low-level terminal GND, the drain of the first feedback transistor NM2 is connected to the source of NM23, and the gate of the first feedback transistor NM2 is used to receive the voltage from the output node OUT.

[0088] In one illustrative embodiment, such as Figure 1As shown, the fourth current mirror assembly 22 is a Wilson current mirror structure, including four P-type transistors: PM25, PM26, and PM27, including the first tail current source PM1. PM25 is a diode, with its gate and drain connected, and its source connected to the drain of PM26. The gate of PM26 is connected to the low-level terminal GND, and the source of PM26 is connected to the high-level terminal VDD along with the source of PM27. The gate of PM27 receives the charging control signal UP, and the drain of PM27 is connected to the source of the first tail current source PM1. The gate of the first tail current source PM1 is connected to the gate of PM25, and the drain of the first tail current source PM1 is connected to the output node OUT.

[0089] In one illustrative embodiment, such as Figure 1 As shown, the fifth current mirror assembly 23 is a Wilson current mirror structure, including four P-type transistors: PM28, PM29, PM210, and PM211. PM28 is a diode-connected transistor, meaning its gate and drain are shorted. The gates of PM29 and PM210 are connected to the low-level terminal GND of the power supply, and their sources are connected to the high-level terminal VDD. The gates of PM28 and PM29 are interconnected. The source of PM28 is connected to the drain of PM29, the source of PM211 is connected to the drain of PM210, the drain of PM28 is connected to the drain of NM21, and the drain of PM211 is connected to the sixth current mirror unit 24. The source of the second feedback transistor PM2 is connected to the high-level terminal VDD, and the drain of the second feedback transistor PM2 is connected to the source of PM211. The gate of the second feedback transistor PM2 is used to receive the voltage from the output node OUT.

[0090] In one illustrative embodiment, such as Figure 1 As shown, the sixth current mirror assembly 24 is a Wilson current mirror structure, including four N-type transistors: NM 212, NM 213, and NM 214, including the second tail current source NM1. NM212 is a diode-connected transistor, with its gate and drain connected, and its source connected to the drain of NM213. The gate of NM213 is connected to the high-level terminal VDD, and the source of NM213 is connected to the low-level terminal GND. The gate of NM214 is used to receive the discharge control signal DN. The drain of NM214 is connected to the source of the second tail current source NM1, and the gate of the second tail current source NM1 is connected to the gate of NM212. The drain of the second tail current source NM1 is connected to the output node OUT.

[0091] According to some embodiments of this disclosure, such as Figure 1As shown, the bias unit 1 includes a current mirror bias module 11 and a linear load. The current mirror bias module 11 includes multiple first transistors operating in the saturation region. The multiple first transistors form a Wilson current mirror structure and are connected in series with the linear load, so that the first reference current is related to the resistance value of the linear resistor and is independent of the source voltage.

[0092] According to some embodiments of this disclosure, the number of the plurality of first transistors can be any number of 4, 8, 10, etc.

[0093] According to some embodiments of this disclosure, a linear load may include at least one second transistor or resistor operating in the linear region.

[0094] In one illustrative embodiment, such as Figure 1 As shown, the linear load is the second transistor NM3 operating in the linear region to improve layout matching. The source of NM3 is connected to the low-level terminal GND.

[0095] According to embodiments of this disclosure, the linear load of bias unit 1 can be set to one or more as needed.

[0096] In one illustrative embodiment, a bias unit with a reference current of approximately 6µA is provided. For example... Figure 1 As shown, the first transistor operating in the saturation region consists of five transistors: three P-type transistors (PM3, PM4, and PM5) and two N-type transistors (NM5 and NM6). The condition for operation in the saturation region is that the gate-source voltage V0 must be within a certain range. GS and threshold voltage V th The difference is less than the drain-source voltage V. dS V GS -V th <V dS Since PM3 and NM6 both use diode connections, PM4, PM5, and NM5 can be kept in the saturation region.

[0097] The width-to-length ratio of the PNP (P-type) transistors PM3 and PM4 in bias unit 1, i.e., the width-to-length ratio, can be expressed by formula (1):

[0098]

[0099] Among them, L PM3 L represents the length of PM3. PM4 W represents the length of PM4, and W represents the width of PM3 and PM4.

[0100] The relationship between the width-to-length ratio of NM5 and NM6 can be expressed by formula (2):

[0101]

[0102] Among them, L NM5 L represents the length of NM5. NM6 This indicates the length of NM6.

[0103] The drain current I of the saturation region transistor D The formula can be expressed as formula (3):

[0104]

[0105] Among them, I D μ represents the drain current of a transistor in the saturation region. n c represents the electron migration rate. ox V represents the dielectric constant. GS V represents the gate-source voltage. th The threshold voltage is represented by W, the width of the MOS transistor is represented by W, and the length of the MOS transistor is represented by L.

[0106] The condition that must be met for operation in the linear region is the gate-source voltage V. GS and threshold voltage V th The difference is greater than the drain-source current V. dS That is: V GS -V th >V dS Let the on-resistance of the N-type transistor NM3 be r. n3 Then the gate-source voltages of NM5 and NM6 are related to the on-resistance r of NM3. n3 The relationship can be expressed as formula (4):

[0107] V GSn6 -V GSn5 =I Dn5 r n3 (4).

[0108] Among them, V GSn6 V represents the gate-source voltage of NM6. GSn5 I represents the gate-source voltage of NM5. Dn5 This represents the current r when NM5 is operating in the saturation region. n3 This represents the on-resistance of NM3.

[0109] First reference current I D5 The first reference current I can be obtained by combining formulas (3) and (4). D5 As shown in formula (5):

[0110]

[0111] Among them, I D5 For the first reference current, μ n c represents the electron migration rate.ox R represents the dielectric constant. n3 L is the on-resistance of the NM3 transistor. p3 W represents the length of the P-type MOSFET PM3, and W represents the width of the P-type MOSFET PM3.

[0112] Therefore, a first reference current independent of the power supply voltage can be obtained through the biasing unit. The magnitude of the first reference current is determined by the on-resistance r of NM3. n3 Decide. Figure 2 A charge-discharge matching curve of a source-switched charge pump according to an embodiment of the present disclosure is shown.

[0113] like Figure 2 As shown, the horizontal axis represents the voltage value V at the output node. dc (V), the vertical axis represents the current I (μA), the charging current I of the source-switched charge pump. charge Curve and discharge current I discharge Curve graph. It receives binary code (000-111) from an external source through three sequentially configured adjustment modules, which... Figure 2 It can be seen that the charging current and discharging current increase from 31μA to 55μA in 3μA increments, with a mismatch of less than 1.5% throughout the entire range, which can effectively cope with changes in loop parameters such as frequency division ratio and filter bandwidth.

[0114] Figure 3 A charge-discharge matching curve of the source-switched charge pump with a 55µA output according to an embodiment of the present disclosure is shown.

[0115] Figure 3 The horizontal axis represents the voltage value V at the output node. dc (V), where the vertical axis represents the current I (μA). For example... Figure 3 As shown, the source-switched charge pump provided in this disclosure has a charging current I within an output voltage range of 0.3 to 1.2V. charge and discharge current I discharge The maximum charge-discharge mismatch is only 1.5%, achieving good matching characteristics.

[0116] Figure 4 A charge-discharge matching curve of a source-switched charge pump without a feedback transistor at a 55µA output according to an embodiment of the present disclosure is shown.

[0117] Figure 4 The horizontal axis represents the voltage value V at the output node. dc (V), where the vertical axis represents the current I (μA). For example... Figure 4 As shown, within the output voltage range of 0.3 to 1.2V, the charging current I... charge and discharge current I dischargeThe maximum charge-discharge mismatch reached 10%.

[0118] Figure 3 and Figure 4 The effects of having or not having a feedback transistor on the charging and discharging current matching of the charge pump circuit were compared: Within the output voltage range of 0.3–1.2V, with a feedback transistor (the source-switching charge pump structure provided in this disclosure), the charging current I… charge and discharge current I discharge The maximum charge / discharge DC mismatch is only 1.5%; without a feedback transistor, the charging current I... charge and discharge current I discharge The maximum charge / discharge DC mismatch reached 10%. This indicates that the source-switched charge pump provided in this disclosure has good structural matching characteristics and improved static matching.

[0119] This disclosure provides a programmable source charge pump for use in cryogenic clock generators, which can generate a charge and discharge current with a mismatch of less than 1.5% in the output voltage range of 0.3-1.2V, with a current magnitude of 31-55uA and an on-time of about 1ns.

[0120] Figure 5 A dynamic charge-discharge matching curve of a source-switched charge pump with a 2ns pulse input according to an embodiment of the present disclosure is shown.

[0121] Figure 5 The horizontal axis represents time (ns), and the vertical axis represents current (μA). For example... Figure 5 As shown, this disclosure describes the dynamic matching characteristics of the source-switching charge pump when a 2ns pulse switching signal is input to the charging control signal UP and the discharging control signal DN. Figure 5 As shown, the charging current I charge and discharge current I discharge The matching degree is good, and the glitches are very small when the switch is turned off. Therefore, the source switch charge pump provided in this disclosure effectively suppresses the clock feedthrough effect and the charge sharing effect.

[0122] Figure 6 A graph showing the results of the charge and discharge quantities of the charge pump when a single-cycle pulse is input according to an embodiment of the present disclosure is displayed.

[0123] like Figure 6 As shown, 123.4E-15 represents the discharge charge and -126.2E-15 represents the charging charge. The difference between the charging and discharging charges is only 2.2%, which is a small mismatch and can effectively reduce the reference spurious signals of the clock generator.

[0124] Figure 7 A block diagram of a phase-locked loop according to an embodiment of the present disclosure is shown schematically.

[0125] As another aspect of the embodiments of this disclosure, such as Figure 7 As shown, a phase-locked loop (PLL) is provided, comprising a frequency and phase detector, any one of the aforementioned source-switched charge pumps, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The frequency and phase detector is suitable for converting the phase difference between a reference signal and a feedback signal into at least one of a charging control signal and a discharging control signal. The source-switched charge pump is suitable for charging and discharging the loop filter according to at least one of the charging control signal and the discharging control signal. The loop filter is suitable for generating a control voltage using a resistor-capacitor charging and discharging mechanism. The VCO is suitable for changing the output clock frequency according to the control voltage. The frequency divider is suitable for negatively feeding the clock frequency as a feedback signal to the frequency and phase detector, thereby stabilizing the control voltage and ensuring that the phases of the reference signal and the feedback signal remain consistent.

[0126] According to embodiments of this disclosure, such as Figure 7 As shown, As a phase reference signal, This is the phase signal output by the phase-locked loop. The reference signal is then processed by a frequency and phase detector. The phase difference between the two signals is compared with the signal output from the frequency divider and converted into a charging control signal UP and a discharging control signal DN. After receiving at least one of the charging control signal UP and the discharging control signal DN, the source-switched charge pump outputs a corresponding current to charge and discharge the low-pass filter. The low-pass filter uses resistors and capacitors to charge and discharge to generate the control voltage of the voltage-controlled oscillator and simultaneously eliminates the high-frequency components of the control voltage. The control voltage causes the output clock frequency of the voltage-controlled oscillator to change, and is fed back to the frequency and phase detector through the clock signal of the frequency divider. Through dynamic feedback adjustment, the control voltage tends to stabilize, and the reference signal and the frequency output by the frequency divider are kept in phase, and the phase-locked loop is locked.

[0127] According to some embodiments of this disclosure, when the charging control signal UP is high and the discharging control signal DN is low, the source switch charge pump charges the filter, and the output voltage of the source switch charge pump rises; when the charging control signal UP is low and the discharging control signal DN is high, the source switch charge pump draws current from the filter, and the output voltage of the source switch charge pump decreases; when the charging control signal UP and the discharging control signal DN are both high or low, the output of the source switch charge pump remains unchanged.

[0128] According to some embodiments of this disclosure, compared with traditional drain-switched charge pumps, the source-switched charge pump provided by this disclosure has a simpler structure, occupies less area and consumes less power than drain-switched charge pumps. Moreover, when the output voltage is low / high, causing the NMOS / PMOS to enter the linear operating region, an output feedback transistor is used to detect the output voltage and inject additional current into the charging and discharging path to improve the current matching degree. In addition, a current-type DAC structure adjustment unit is added at the current mirror, which controls the charging and discharging current of the source-switched charge pump through externally input binary code, and can resist changes in loop parameters such as frequency division ratio and filter capacitor.

[0129] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure, and the shapes and dimensions of the components in the drawings do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0130] Unless otherwise stated, the numerical parameters in this specification and the appended claims are approximate values ​​and can be varied according to desired characteristics derived from the content of this disclosure. Specifically, all figures used in the specification and claims to indicate composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Generally, this means that a specific amount varies by ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0131] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0132] Furthermore, unless specifically described or required to occur in a specific order, the order of the above steps is not limited to those listed above and can be varied or rearranged according to the desired design. Moreover, the above embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations; that is, technical features from different embodiments can be freely combined to form more embodiments.

[0133] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A source-switched charge pump for cryogenic applications, characterized in that, include: The bias unit is used to provide a first reference current that is independent of the voltage of the power supply. as well as A core unit, connected to the bias unit, the core unit comprising: The charging module is used to charge the output node using the first reference current via a charging control signal; A discharge module is configured to discharge the output node using a discharge control signal and the first reference current; and Two feedback transistors are connected to the charging module and the discharging module respectively, and are used to feed back the output node voltage to the charging module and the discharging module to compensate for the charging and discharging current when the first tail current source of the charging module or the second tail current source of the discharging module is in the linear region, so that the charging current and the discharging current are matched. An adjustment unit, connected between the bias unit and the core unit, is adapted to output the first reference current from the bias unit as a compensation current proportional to the binary code value, and to superimpose the compensation current with the first reference current as a second reference current, to resist changes in at least one of the loop parameters of the external frequency division ratio and filter capacitor; wherein, the core unit receives the second reference current from the adjustment unit for charging and discharging, and the adjustment unit includes: The first current mirror module is adapted to mirror the first reference current from the bias unit to generate a second current. Multiple sequentially connected adjustment modules are each connected to a first current mirror module, used to receive multiple bits of the binary code and output the second current proportionally to the binary code value as a compensation current; and The second current mirror module is connected to the output terminals of the first current mirror module and the adjustment unit. The second current and the compensation current are superimposed at the input terminal of the second current mirror module to form a third current. The second current mirror module is adapted to mirror the third current to generate the second reference current.

2. The source-switched charge pump according to claim 1, characterized in that, Each of the adjustment modules includes: An adjusting transistor, wherein the source of the adjusting transistor is connected to the low-level terminal of the power supply, and the gate of the adjusting transistor is connected to the output terminal of the first current mirror module; and A receiving transistor is provided, the source of which is connected to the drain of the regulating transistor, the gate of which is used to receive one bit of the binary code, and the source of which is connected between the first current mirror module and the second current mirror module to output the compensation current to the input terminal of the second current mirror module.

3. The source-switched charge pump according to claim 2, characterized in that, The aspect ratio of the plurality of said regulating transistors is increased or decreased in binary multiples to match the input binary code.

4. The source-switched charge pump according to claim 1, characterized in that, The charging module includes: A third current mirror assembly, connected to the bias unit, is adapted to generate a first mirror current and a second mirror current based on the mirror image of the first reference current; and The fourth current mirror assembly includes the first tail current source. The fourth current mirror assembly is used to receive the first mirror current to generate a third mirror current, and under the action of the charging control signal, outputs the third mirror current as a charging current to the output node through the first tail current source. The discharge module includes: A fifth current mirror assembly, connected to the third current mirror assembly, is adapted to generate a fourth mirror current based on the second mirror current; and The sixth current mirror assembly includes the second tail current source. The sixth current mirror assembly is used to receive the fourth mirror current and generate the fifth mirror current. Under the action of the discharge control signal, the fifth mirror current is output as a discharge current to the output node through the second tail current source. The first feedback transistor is connected in parallel with the third current mirror assembly. When the voltage at the output node causes the first tail current source to operate in the linear region, and the charging current is less than the discharging current, the first feedback transistor is turned on, drawing additional current from the low-level terminal of the power supply and injecting it into the first tail current source to compensate for the charging current. The second feedback transistor is connected in parallel with the fifth current mirror assembly. When the voltage at the output node causes the second tail current source to operate in the linear region, and the charging current is greater than the discharging current, the second feedback transistor is turned on, drawing additional current from the high-level terminal of the power supply and injecting it into the second tail current source to compensate for the discharging current.

5. The source-switched charge pump according to claim 4, characterized in that, At least one of the third current mirror assembly, the fourth current mirror assembly, the fifth current mirror assembly, and the sixth current mirror assembly is a Wilson current mirror structure.

6. The source-switched charge pump according to any one of claims 1-5, characterized in that, The bias unit includes: a current mirror bias module and a linear load. The current mirror bias module includes multiple first transistors operating in the saturation region. The multiple first transistors form a Wilson current mirror structure and are connected in series with the linear load, so that the first reference current is related to the resistance of the linear load and is independent of the voltage of the power supply.

7. The source-switched charge pump according to claim 6, characterized in that, The linear load is a second transistor operating in the linear region to improve layout matching.

8. A phase-locked loop, characterized in that, include: A frequency and phase detector is suitable for converting the phase difference between a reference signal and a feedback signal into at least one of a charging control signal and a discharging control signal. The source-switched charge pump according to any one of claims 1-7 is suitable for charging and discharging a loop filter according to at least one of the charging control signal and the discharging control signal; The loop filter is suitable for generating control voltage by charging and discharging resistors and capacitors. A voltage-controlled oscillator suitable for changing the output clock frequency according to the control voltage; as well as The frequency divider is suitable for using the clock frequency as the feedback signal to negatively feed back to the frequency and phase detector, so that the control voltage tends to be stable and the phases of the reference signal and the feedback signal are kept consistent.

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