Chip boot mode establishment method and chip

Abstract

The application discloses a method for establishing a chip boot mode, which comprises the following steps: firstly, resetting the chip; after the pin reset is removed, intercepting the level of the SWDIO pin to make a judgment; if the level is low, inputting a boot mode code through the SWDIO pin; after judging that the input boot mode code is correct, entering the boot mode to complete the establishment of the boot mode. The establishment of the boot mode is realized by using the existing SWD debugging pin, and no extra pin resource is occupied, so that the utilization rate of the debugger resource can be effectively improved, the number of chip pins can be reduced, and the size of the chip can be reduced.

Description

Technical Field

[0001] This invention relates to the field of microcontroller technology, and in particular to a method for establishing a chip boot mode and a chip. Background Technology

[0002] A Microcontroller Unit (MCU) is a single chip that integrates a Central Processing Unit (CPU) with appropriately reduced frequency and specifications, along with peripheral interfaces such as memory, timer, USB, A / D converter, UART, PLC, DMA, and even LCD driver circuitry. It can be considered a chip-level computer. MCUs are widely used in many application fields, providing different combinations of control for various applications. Motor-specific MCUs integrate a microprocessor, power supply circuitry, and control circuitry onto a single chip to control various types of electric motors. These motor-specific MCUs can implement motion control functions such as acceleration, deceleration, constant speed, and reverse rotation according to specific requirements, thus achieving motor control.

[0003] MCUs typically have in-circuit upgrade capabilities. When an MCU program needs to be upgraded, the MCU must first be reset, then switched to boot mode, and the update program injected. In existing MCU designs, one or more dedicated mode pins are usually used to enter boot mode during chip reset by using a fixed voltage level or inputting a specific code. However, due to considerations such as reducing product size, some MCU chips have fewer pins. If additional dedicated mode pins are configured to establish boot mode, it will reduce pin resource utilization and may affect the performance of the chip's actual application functions. Summary of the Invention

[0004] To address some or all of the problems in the existing technology, the first aspect of this invention provides a method for establishing a chip boot mode. This method establishes the boot mode by utilizing the debugger's SWD pins, thereby maximizing the utilization of debugger resources, freeing up mode pins, and ensuring that all chip pin resources can be used for actual chip application functions. The establishment method includes:

[0005] Reset chip;

[0006] After the pin reset is released, the voltage level of the SWDIO pin is captured;

[0007] If the intercepted level is low when the reset is released, then the boot mode code is input through the SWDIO pin; and

[0008] Determine if the input boot mode code is correct. If correct, enter boot mode and complete the boot mode setup.

[0009] Furthermore, the establishment method also includes:

[0010] If the SWDIO pin is high when the pin reset is released, the chip will be reset again.

[0011] Furthermore, the establishment method also includes:

[0012] If the entered boot mode code is incorrect, reset the chip and repeat the above steps.

[0013] Furthermore, the establishment method also includes:

[0014] Using SWCLK as the sampling clock signal, the time taken from self-reset release to code input completion, and the time taken from self-reset release to boot mode establishment completion are recorded by the LRC counter.

[0015] Furthermore, the establishment method also includes:

[0016] If the count value of the LRC counter is greater than the specified value, the boot mode establishment fails, the chip is reset, and the aforementioned steps are repeated.

[0017] Furthermore, the chip is reset via the reset pin NRST.

[0018] Furthermore, capturing the voltage levels of the SWDIO pins includes:

[0019] The latch is triggered by the edge of the reset signal changing from active to inactive to latch the level of SWDIO.

[0020] Furthermore, the boot mode code has the same instruction format as SWD, including an 8-bit value, which is 01110001 from high to low.

[0021] Based on the aforementioned establishment method, a second aspect of the present invention provides an MCU chip including an SWD pin, wherein the MCU chip uses the SWD pin to establish a boot mode based on the aforementioned method.

[0022] A third aspect of the present invention provides a motor control module, which includes the MCU chip as described above.

[0023] This invention provides a method for establishing a chip boot mode that uses readily available SWD debug pins to achieve the chip entering boot mode without consuming additional resources, thereby effectively improving the utilization rate of debugger resources. Furthermore, since no additional mode pins are required, the number of chip pins can be effectively reduced, thus shrinking the chip size and meeting product miniaturization requirements. Attached Figure Description

[0024] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0025] Figure 1 A flowchart illustrating a method for establishing a chip boot mode according to an embodiment of the present invention is shown; and

[0026] Figure 2 This diagram illustrates the timing of a chip boot mode establishment method according to an embodiment of the present invention. Detailed Implementation

[0027] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0028] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0029] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0030] To reduce the number of pins in an MCU chip and ensure that all pin resources are used for the chip's actual functions, this invention provides a method for establishing a chip boot mode. This method establishes the boot mode through pin multiplexing, eliminating the need for additional dedicated mode pins. Therefore, it is suitable for MCU chips with fewer pins, such as motor-related MCU chips. Specifically, in this embodiment, the debugger's SWD pin is used to establish the boot mode, reducing the number of pins while maximizing the utilization of debugger resources. The SWD pin is an interface for debugging and programming, mainly including the SWDIO and SWCLK pins. The SWDIO pin is a data line used for data transmission, and the SWCLK pin is a clock line used for synchronous data transmission. In practical applications, the SWD pin is not always enabled, especially when the chip has just completed a reset, it is usually in an idle state. Since the boot mode is established upon reset, using the SWD pin to establish the boot mode upon chip reset does not affect the chip's functionality.

[0031] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0032] Figure 1 This diagram illustrates a flowchart of a method for establishing a chip boot mode according to an embodiment of the present invention. Figure 1 As shown, a method for establishing a chip boot mode includes:

[0033] First, in step 101, the chip is reset. In one embodiment of the invention, the chip is reset via a reset pin.

[0034] Next, in step 102, the level of the SWDIO pin is captured. To avoid conflicts with the SWD pin's own tasks, the state of the SWDIO pin needs to be confirmed before establishing the boot mode. If it is high, it means the SWD pin is in use, and the boot mode cannot be established at this time. Therefore, after the pin reset is released, the level of the SWDIO pin needs to be captured to determine the SWD pin state. In one embodiment of the present invention, the level of the SWDIO pin is latched by triggering a latch on the edge of the reset signal changing from valid to invalid.

[0035] Next, in step 103, the level of the SWDIO pin is determined. As mentioned earlier, the boot mode can only be established through the SWD pin when the level of the SWDIO pin is low, i.e., when the SWD pin is in an idle state. Therefore, after capturing the level, it needs to be judged. If the level is high, the user mode is automatically entered. At this time, if the boot mode still needs to be established, it is necessary to return to step 101 and reset the chip again. When the reset is released, the level of the SWDIO pin is low, and then proceed to step 104.

[0036] In step 104, the boot mode code is entered. In one embodiment of the present invention, the boot mode code is entered through the SWDIO pin. The SWD instruction format is shown in Table 1, and it typically contains 8 bits of value, detailed below:

[0037] Start: The start bit, which is always 1;

[0038] APnDP: Used to select the register to be accessed, wherein the registers include the DP register and the AP register;

[0039] Rnw: Used to select whether to perform a read or write operation;

[0040] A[2] and A[3]: These are the addresses of the DP or AP registers. In the SWD instruction, the least significant byte comes first. For example, if the address of the DP register is 0x08, then the value of A is 0b1000, and A[2] is 0 and A[3] is 1.

[0041] Praity: Check bits, which are the four check bits APnDP, RnW, A[2] and A[3];

[0042] Stop: The stop bit, which is always 0 in the SWD instruction; and

[0043] Park: Always equal to 1 in SWD commands.

[0044] name Start APnDP RnW A[2] A[3] Parity Stop Park Possible values 1 0 / 1 0 / 1 0 / 1 0 / 1 0 / 1 0 1 Bootstrapping mode code 1 0 0 0 1 1 1 0

[0045] To prevent the SWD instruction from causing the chip to mistakenly enter boot mode, in one embodiment of the present invention, although the structure of the boot mode code is the same as that of the SWD instruction, the values ​​of each bit are different. Specifically, in one embodiment of the present invention, the values ​​of each bit of the boot mode code are fixed, wherein the values ​​of the Stop bit and the Park bit are exactly the opposite of those of the SWD instruction, that is, in the boot mode code, the Stop bit is 1 and the Park bit is 0. In addition, the values ​​of the remaining bits, from Bit1 to Bit6, are 100011.

[0046] Next, in step 105, the code is checked for correctness. The input boot mode code is checked for correctness. If correct, proceed to step 106. If incorrect, automatically enter user mode. If boot mode still needs to be established, return to step 101 and reset the chip again.

[0047] In one embodiment of the present invention, to avoid affecting the normal use of the chip, a time limit is imposed on the establishment of the boot mode. This time limit mainly includes two aspects: completing the input of the boot mode code within a limited time, and completing the establishment of the boot mode within a limited time. The limited duration is determined based on the chip performance; specifically, for example, it can be slightly increased based on the time required for inputting SWD IO port instructions. Based on this, in one embodiment of the present invention, as... Figure 2 As shown, SWCLK is used as the sampling clock signal to control the time spent from reset release to code input completion and the time spent from reset release to boot mode establishment completion. In one embodiment of the invention, an LRC counter is used to record the duration. Specifically, the LRC counter starts counting when the reset is released, i.e., the LRC counter is triggered by the edge of the reset signal changing from valid to invalid. The LRC counter counts based on SWCLK and records the time spent from reset release to code input completion and the time spent from reset release to boot mode establishment completion. In one embodiment of the invention, if the time spent from reset release to code input completion or the time spent from reset release to boot mode establishment completion exceeds a preset value, the boot mode establishment is considered to have failed. At this time, the user mode is automatically entered. If the boot mode still needs to be established, it is necessary to return to step 101 and reset the chip again. In one embodiment of the invention, a code sampling counter is used to record the input of the SWD IO port to determine whether the code input is complete; and

[0048] Finally, in step 106, enter boot mode. Entering boot mode completes the boot mode setup.

[0049] Based on the aforementioned establishment method, this invention also provides an MCU chip that includes SWD pins but excludes mode pins. The MCU chip uses the SWD pins to establish a boot mode based on the aforementioned method. Comparatively, the MCU chip has fewer pins, resulting in a smaller size, making it suitable for applications with strict size requirements, such as motor control.

[0050] Based on this, the present invention also provides a motor control module, which includes the MCU chip as described above. Since the MCU chip does not require additional mode pins, the wiring of the control module is simpler, the overall structure is more compact, and the debugger resource utilization is higher.

[0051] This invention provides a method for establishing a chip boot mode that uses readily available SWD debug pins to achieve the chip entering boot mode without consuming additional resources, thereby effectively improving the utilization rate of debugger resources. Furthermore, since no additional mode pins are required, the number of chip pins can be effectively reduced, thus shrinking the chip size and meeting product miniaturization requirements.

[0052] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for establishing a chip boot mode, characterized in that, Including the following steps: Reset chip; After the pin reset is released, the voltage level of the SWD IO pin is captured; Determine the level of the intercepted SWD IO pin. If the level is low, input the boot mode code through the SWD IO pin. as well as Determine if the input boot mode code is correct. If correct, enter boot mode and complete the boot mode setup.

2. The method for establishing as described in claim 1, characterized in that, It also includes the following steps: If the SWD IO pin is high when the pin reset is released, the chip will be reset again.

3. The method for establishing as described in claim 1, characterized in that, It also includes the following steps: If the entered boot mode code is incorrect, the chip will be reset.

4. The method for establishing as described in claim 1, characterized in that, It also includes the following steps: Using SWCLK as the sampling clock signal, the time taken from self-reset release to code input completion, and the time taken from self-reset release to boot mode establishment completion are recorded by the LRC counter.

5. The method for establishing as described in claim 4, characterized in that, It also includes the following steps: If the count value of the LRC counter is greater than the specified value, the boot mode establishment fails and the chip is reset.

6. The method for establishing as described in claim 1, characterized in that, The chip is reset by using the reset pin.

7. The method for establishing as described in claim 1, characterized in that, The steps to capture the voltage level of the SWDIO pin are as follows: The latch is triggered by the edge of the reset signal changing from active to inactive to latch the level of the SWD IO at the current moment.

8. The method for establishing as described in claim 1, characterized in that, The boot mode code has the same instruction format as SWD, including an 8-bit value, which is 01110001 from high to low.

9. An MCU chip, characterized in that, It includes an SWD pin, and the MCU chip uses the SWD pin to establish the boot mode according to the establishment method described in any one of claims 1 to 8.

10. A motor control module, characterized in that, Including the MCU chip as described in claim 9.

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