An improved SRAM controller with error correction code check function

Abstract

The application relates to an improved SRAM controller with error correction code check function. The controller comprises: a high-performance bus configured to connect communication among a processor, a memory and a high-speed peripheral; a controller module with a data buffer configured to perform timing conversion of a high-performance bus interface and an SRAM interface, and perform SRAM read and write control with the data buffer; an error correction code check module configured to perform error correction code check; and an SRAM module configured to contain a plurality of SRAM units. The improved SRAM controller with error correction code check function provided by the application adds a data buffer in the controller module, and can greatly improve read and write efficiency compared with an existing circuit structure.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to an improved SRAM controller with error correction code verification function. Background Technology

[0002] Static Random-Access Memory (SRAM) is a type of random access memory. As long as power is supplied, the data stored in this type of memory remains constant. SRAM is primarily used in high-performance computing devices and scenarios requiring fast data access, such as processor caches, high-speed caches, and graphics processing units (GPUs).

[0003] Figure 1 This is a schematic diagram of the overall framework of an existing SRAM controller. Figure 1 As shown, existing SRAM controllers with error correction code verification functionality include an Advanced High-performance Bus (AHB), a controller module without a data buffer, an error correction code (ECC) verification module, and an SRAM module. Existing SRAM controllers generate excessive waiting time in the SRAM read-then-write operation logic, resulting in low read / write efficiency. Summary of the Invention

[0004] To address some or all of the problems in the prior art, this invention provides an improved SRAM controller with error correction code verification function, the controller comprising:

[0005] The advanced high-performance bus is configured to connect communication between the processor, memory, and high-speed peripherals;

[0006] The controller module with a data buffer is configured to perform timing conversion between the high-performance bus interface and the SRAM interface, as well as to perform SRAM read and write control with the data buffer.

[0007] The error correction code verification module is configured to perform error correction code verification;

[0008] The SRAM module is configured to contain multiple SRAM cells.

[0009] Furthermore, the advanced high-performance bus receives commands and data information sent from the processor, and simultaneously returns the status information fed back by the SRAM controller during operation to the processor.

[0010] Furthermore, the controller module with data buffer is connected to the high-performance bus, the error correction code verification module, and the SRAM module.

[0011] Furthermore, the data buffer is preferably a register composed of D flip-flops.

[0012] Furthermore, the SRAM controller supports byte / half-word / word read and write operations.

[0013] Furthermore, when the SRAM controller performs a byte / half-word write operation, it automatically completes the following steps:

[0014] Read the 32 bits of data corresponding to the byte / half-word;

[0015] The data is concatenated with the written byte / half-word data to obtain a new 32-bit data;

[0016] Perform a write operation on the new 32-bit data.

[0017] Furthermore, when no read / write operation occurs after the timing conversion from the advanced high-performance bus to the SRAM module interface, the operation includes:

[0018] The data buffer contains no data, so no read or write operations are performed.

[0019] If there is data in the data buffer, the existing data in the data buffer is written into the SRAM module.

[0020] Furthermore, performing a write operation on the SRAM module includes:

[0021] When there is no data in the data buffer, external data is written to the SRAM module.

[0022] If there is data in the data cache, the existing data in the data cache is written into the SRAM module, and external data is stored in the data cache.

[0023] Furthermore, performing a read operation on the SRAM module includes:

[0024] When there is no data in the data buffer, data is read from the SRAM module.

[0025] If the data buffer contains data, and the read address matches, the data is read from the data buffer; or, if the read addresses do not match, the data is read from the SRAM module.

[0026] Furthermore, performing both read and write operations on the SRAM module simultaneously includes:

[0027] If there is no data in the data buffer, external data is stored in the data buffer; if the read and write addresses are the same, data is read from the data buffer; or, if the read and write addresses are different, data is read from the SRAM module.

[0028] If there is data in the data buffer, the existing data in the data buffer is written into the SRAM module, external data is stored in the data buffer, and READYOUT is pulled low for one clock cycle. In the next clock cycle, if the read address matches the address corresponding to the data in the data buffer, the data is read from the data buffer; or, if the read address does not match the address corresponding to the data in the data buffer, the data is read from the SRAM module.

[0029] Compared with the prior art, the beneficial effects of the present invention are: it realizes an improved SRAM controller structure with error correction code verification function, which can significantly improve read and write efficiency compared with the existing circuit structure. Attached Figure Description

[0030] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0031] Figure 1 A schematic diagram of the overall framework of an existing SRAM controller;

[0032] Figure 2 This is a schematic diagram of the overall framework of an SRAM controller according to an embodiment of the present invention;

[0033] Figure 3 This is a timing diagram of the advanced high-performance bus interface and SRAM interface according to an embodiment of the present invention. Detailed Implementation

[0034] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0035] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0036] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0037] In this invention, the modules of the system according to the invention can be implemented using software, hardware, firmware, or a combination thereof. When a module is implemented using software, its function can be implemented through computer program flow. For example, the module can be implemented using code segments (such as code segments in languages ​​like C and C++) stored in a storage device (such as a hard disk, memory, etc.), wherein the corresponding function of the module can be implemented when the code segment is executed by a processor. When a module is implemented using hardware, its function can be implemented by setting a corresponding hardware structure. For example, the module's function can be implemented by hardware programming a programmable device such as a field-programmable gate array (FPGA), or by designing an application-specific integrated circuit (ASIC) that includes multiple transistors, resistors, capacitors, and other electronic devices. When a module is implemented using firmware, the module's function can be written into a read-only memory such as an EPROM or EEPROM in the form of program code, and the corresponding function of the module can be implemented when the program code is executed by a processor. In addition, some functions of the module may need to be implemented by separate hardware or by working in cooperation with the hardware. For example, the detection function is implemented by the corresponding sensor (such as a proximity sensor, accelerometer, gyroscope, etc.), the signal transmission function is implemented by the corresponding communication device (such as a Bluetooth device, infrared communication device, baseband communication device, Wi-Fi communication device, etc.), the output function is implemented by the corresponding output device (such as a display, speaker, etc.), and so on.

[0038] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0039] Figure 2 This is a schematic diagram of the overall framework of an SRAM controller according to an embodiment of the present invention. Figure 2As shown, the controller includes: an Advanced High-performance Bus (AHB), a controller with a data buffer module, an error correction code verification module (ECC verification module), and an SRAM module.

[0040] Advanced High Performance Bus (AHS) is a high-performance, high-bandwidth bus protocol configured to connect the processor, memory, and high-speed peripherals for communication. AHS receives commands and data from the processor and simultaneously returns status information from the SRAM controller to the processor.

[0041] The controller module with a data buffer is configured to perform timing conversion between the high-performance bus interface and the SRAM interface, as well as to perform SRAM read and write control with the data buffer. The data buffer is preferably a register composed of D flip-flops.

[0042] The error correction code verification module is configured to perform error correction code verification.

[0043] The SRAM module is configured to contain multiple SRAM cells.

[0044] like Figure 2 As shown, the connection relationship of the various parts of the SRAM controller is as follows: the controller module with data buffer is connected to the high-performance bus, the error correction code verification module, and the SRAM module.

[0045] The read and write operations of the SRAM controller in non-error-correcting code mode and error-correcting code mode are described in detail below.

[0046] Figure 3 This is a timing diagram of the advanced high-performance bus interface and SRAM interface according to an embodiment of the present invention. Figure 3 As shown, taking three 16-bit write operations with different addresses and data on an advanced high-performance bus as an example, Figure 3 The upper part is the high-performance bus timing diagram, and the lower part is the SRAM module interface timing diagram. W (Write) indicates writing, R (Read) indicates reading, A (Address) indicates address, and D (Data) indicates data; the number 16 indicates 16 bits (half-word), and the number 32 indicates 32 bits (word); the superscript 1 indicates the first read / write, 2 indicates the second read / write, and so on. Figure 3 All addresses and data are different, i.e., A1≠A2≠A3, WD1≠WD2≠WD3, RD1≠RD2≠RD3.

[0047] Table 1 shows... Figure 3 The SRAM module in the system performs read and write operations. The SRAM controller supports byte / half-word / word read and write operations. When the SRAM controller performs a byte / half-word write operation, it automatically completes the following steps: First, it reads the 32-bit data corresponding to the byte / half-word; next, it concatenates the byte / half-word data with the data to be written to obtain new 32-bit data; finally, it performs a write operation on the new 32-bit data.

[0048] Table 1 Figure 3 SRAM module read and write operations

[0049] T1 <![CDATA[SRAM→RD1]]> T2 <![CDATA[RD1+WD1→BUF,SRAM→RD2]]> T3 <![CDATA[RD2+WD2→BUF,BUF→RAM]]> T4 <![CDATA[SRAM→RD3]]> T5 <![CDATA[RD3+WD3→BUF,BUF→SRAM]]> T6 BUF→SRAM

[0050] As shown in Table 1, the read and write operations of the SRAM module are as follows: At time T1, data RD1 is read from the SRAM module (A1); at time T2, the 16 bits WD1 to be written are concatenated with the corresponding 16 bits and WD1 in the read 32 bits RD1 to form a new 32 bits, which are stored in the data buffer, and data RD2 is read from the SRAM module (A2); at time T3, the 16 bits WD2 to be written are concatenated with the corresponding 16 bits and WD2 in the read 32 bits RD2 to form a new 32 bits, which are stored in the buffer, and the data RD1+WD1 in the buffer from the previous time is written to the SRAM module (A1); at time T3, no read operation can be performed on the SRAM module (A3), and the HREADY signal is low; at time T4, data RD3 is read from the SRAM module (A3), and the HREADY signal is high; at time T5, the 16 bits WD3 to be written are concatenated with the corresponding 16 bits and WD2 in the read 32 bits RD2 to form a new 32 bits, which are stored in the buffer, and the data RD1+WD1 in the buffer from the previous time is written to the SRAM module (A1); at this time T3, no read operation can be performed on the SRAM module (A3), and the HREADY signal is low; at this time T4, data RD3 is read from the SRAM module (A3), and the HREADY signal is high; at this time T5, the 16 bits WD3 to be written are concatenated with the corresponding 16 bits and WD2 in the read 32 bits RD2 to form a new 32 bits, which are stored in the buffer, and the data RD1+WD1 in the buffer from the previous time is written to the SRAM module (A1); The corresponding 16 bits in RD3 and WD3 are concatenated to form a new 32 bits, which are stored in the buffer. The data RD2+WD2 in the buffer from the previous time step is written into the SRAM module (A2). At time T6, the data RD3+WD3 in the buffer is written into the SRAM module (A3).

[0051] Table 2 summarizes all read and write operations of the SRAM module interface of an SRAM controller according to an embodiment of the present invention. In Table 2, NA indicates that no read or write operation occurred after the timing conversion from the high-performance bus to the SRAM module interface; invalid indicates that there is no data in the data buffer; valid indicates that there is data in the buffer; W indicates that a write operation was performed on the SRAM module; R indicates that a read operation was performed on the SRAM module; R_req indicates that there is a read request for the SRAM module, but HREADY is low. Table 2 describes the states of the read and write process and does not consider the SRAM module read and write timing.

[0052] Table 2 summarizes all read / write operations of the SRAM module interface of the SRAM controller according to an embodiment of the present invention.

[0053]

[0054] When no read / write operation occurs after the timing conversion from the high-performance bus to the SRAM module interface, the operation includes two states: NA+invalid and NA+valid. In the NA+invalid state, no read or write operations are performed, and the buffer is empty. In the NA+valid state, the existing data in the buffer is written to the SRAM module, and the buffer is empty after the write operation is completed.

[0055] The write operation to the SRAM module includes two states: W+valid and W+invalid. In the W+valid state, the existing data in the buffer is written to the SRAM module, and external data is stored in the buffer. In the W+invalid state, external data is written to the SRAM module, and the buffer is empty after the read / write operation is completed.

[0056] Simultaneous read and write operations on the SRAM module include two states: W+R+invalid and W+R_rea+valid. In the W+R+invalid state, external data is stored in a buffer; if the read and write addresses match, data is read from the buffer; or, if the read and write addresses do not match, data is read from the SRAM module. In both the W+R_rea+valid states, the existing data in the buffer is written to the SRAM module, external data is stored in the buffer, and READYOUT is pulled low for one clock cycle; in the next clock cycle, if the read address matches the address corresponding to the data in the buffer, data is read from the buffer; or, if the read address does not match the address corresponding to the data in the buffer, data is read from the SRAM module.

[0057] Performing a read operation on the SRAM module includes two states: R+valid and R+invalid. In the R+invalid state, data is read from the SRAM module, and the buffer is empty after the read / write operation is completed. In the R+valid state, if the read address is consistent, data is read from the data buffer; or, if the read address is inconsistent, data is read from the SRAM module.

[0058] In existing technologies, readyout is 0 in both the W+R+invalid and W+R_req+valid states. This invention adds an internal data buffer, ensuring that readyout is 0 only in the W+R_req+valid state. When readyout is 0, there is an extra clock cycle in the read / write sequence. Compared to existing technologies, this invention significantly improves read / write efficiency.

[0059] The present invention provides an improved SRAM controller with error correction code verification function, which adds a data buffer to the controller module, and can significantly improve read and write efficiency compared with the existing circuit structure.

[0060] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. An improved SRAM controller with error correction code verification function, characterized in that, include: The advanced high-performance bus is configured to connect communication between the processor, memory, and high-speed peripherals; The controller module with a data buffer is configured to perform timing conversion between the high-performance bus interface and the SRAM interface, as well as to perform SRAM read and write control with the data buffer. The error correction code verification module is configured to perform error correction code verification; as well as The SRAM module is configured to contain multiple SRAM cells; The controller module with data buffer is connected to the high-performance bus, the error correction code verification module, and the SRAM module. When the SRAM controller performs a byte / half-word write operation, it automatically completes the following steps: Read the 32 bits of data corresponding to the byte / half-word; The data is concatenated with the written byte / half-word data to obtain a new 32-bit data; and Perform a write operation on the new 32-bit data; The simultaneous reading and writing operations performed on the SRAM module include: If the data buffer is empty, external data is stored in the data buffer; if the read and write addresses match, data is read from the data buffer; or, if the read and write addresses do not match, data is read from the SRAM module. If there is data in the data buffer, the existing data in the data buffer is written into the SRAM module, external data is stored in the data buffer, and READYOUT is pulled low for one clock cycle. In the next clock cycle, if the read address matches the address corresponding to the data in the data buffer, the data is read from the data buffer; or, if the read address does not match the address corresponding to the data in the data buffer, the data is read from the SRAM module.

2. The SRAM controller according to claim 1, characterized in that, The advanced high-performance bus receives commands and data from the processor, and simultaneously returns the status information fed back by the SRAM controller during operation to the processor.

3. The SRAM controller according to claim 1, characterized in that, The data buffer is a register composed of D flip-flops.

4. The SRAM controller according to claim 1, characterized in that, The SRAM controller supports byte / half-word / word read and write operations.

5. The SRAM controller according to claim 1, characterized in that, When no read / write operation occurs after the timing conversion from the high-performance bus to the SRAM module interface, the following operations are performed: The data buffer contains no data, so no read or write operations are performed. If there is data in the data buffer, the existing data in the data buffer is written into the SRAM module.

6. The SRAM controller according to claim 1, characterized in that, Performing a write operation on the SRAM module includes: When there is no data in the data buffer, external data is written to the SRAM module. If there is data in the data cache, the existing data in the data cache is written into the SRAM module, and external data is stored in the data cache.

7. The SRAM controller according to claim 1, characterized in that, Performing a read operation on the SRAM module includes: When there is no data in the data buffer, data is read from the SRAM module. If the data buffer contains data, and the read address matches, the data is read from the data buffer; or, if the read addresses do not match, the data is read from the SRAM module.

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