Multi-path server control method, device, system, electronic device and storage medium

Abstract

The application provides a multi-path server control method, device, system, electronic equipment and storage medium. The method comprises: performing central processor working state judgment on a multi-path server to obtain a central processor working state judgment result, wherein the multi-path server comprises a first central processor and a second central processor, and the first central processor and the second central processor can both load a basic input and output system of the multi-path server; when the central processor working state judgment result is that the first central processor and the second central processor are both working, a central processor switching signal is acquired; and according to the central processor switching signal, the control source of the multi-path server is switched from the first central processor to the second central processor to obtain a first multi-path server control result. Since the application can switch multiple server control sources according to the CPU switching signal issued by the user, the control flexibility and risk resistance of the multi-path server are improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a multi-channel server control method, apparatus, system, electronic device, and storage medium. Background Technology

[0002] With the development of server technology and the expansion of data processing needs, the requirements for server structural flexibility and performance are also increasing. Traditional server architectures are singular and cannot simultaneously meet the different needs of various industries and business functions, as well as user requirements such as cost optimization, and are gradually being replaced by multi-processor servers.

[0003] Specifically, existing technologies often employ a method of selecting one CPU from a multi-processor server as the master CPU to manage and control the SPI bus outputs. However, since the other CPUs in the multi-processor server lack master CPU control authority, a failure in the selected CPU has a large blast radius, severely impacting the normal operation of the server's functions. Summary of the Invention

[0004] This application provides a multi-channel server control method, apparatus, electronic device, and readable storage medium. By designing both the first CPU and the second CPU as CPUs capable of SPI bus management output, when both the first CPU and the second CPU are in working state, the control source of the multi-channel server can be switched from the first CPU to the second CPU according to the CPU switching signal issued by the user. This solves the problem in existing multi-channel servers where the normal operation of the corresponding functions of the server is severely affected when the selected CPU fails.

[0005] Firstly, this application provides a multi-channel server control method, the method comprising:

[0006] The CPLD logic control chip is used to determine the working status of the central processing unit of the multi-channel server and obtain the working status determination result of the central processing unit. Both the first central processing unit and the second central processing unit are able to load the basic input / output system of the multi-channel server.

[0007] When the CPU working status determination result is that both the first CPU and the second CPU are working, a CPU switching signal is obtained;

[0008] When the central processing unit switching signal indicates that a central processing unit switch is required, the control source of the multi-channel server is switched from the first central processing unit to the second central processing unit through the SWITCH chip, thereby obtaining the first multi-channel server control result.

[0009] Optionally, the multi-server control method provided in this application also includes:

[0010] When the CPU working status determination result is that the second CPU is working and the first CPU is not working, the control source of the multi-channel server is switched from the first CPU to the second CPU to obtain the second multi-channel server control result.

[0011] Optionally, the multi-server control method provided in this application also includes:

[0012] Obtain error information from the central processing unit;

[0013] When the error message from the central processing unit indicates a failure of the second central processing unit, the control source of the multi-processor is switched from the second central processing unit to the first central processing unit to obtain the control result of the third multi-processor.

[0014] Optionally, the multi-server control method provided in this application also includes:

[0015] According to the central processing unit switching signal, the serial peripheral device interface source of the multi-channel server is switched from the first central processing unit to the second central processing unit to obtain the control result of the first multi-channel server.

[0016] Optionally, the multi-server control method provided in this application also includes:

[0017] By using a pre-set time-sharing control principle, the pins of the single-pole double-throw switch are assigned values ​​according to the chip select signals of the first central processing unit and the second central processing unit.

[0018] The chip select signal of the first FLASH module is obtained according to the pin of the single-pole double-throw switch;

[0019] The chip select signal of the second FLASH module is obtained according to the pin of the single-pole double-throw switch;

[0020] Obtain the chip select control signal;

[0021] Based on the chip select control signal and the preset chip select strategy, a chip select change judgment is performed to obtain the chip select change judgment result;

[0022] When the chip select change judgment result is that the chip select control signal and the chip select strategy are inconsistent, the chip select signal from the first FLASH module to the second FLASH module is switched according to the chip select control signal to obtain the fourth multi-channel server control result.

[0023] Optionally, the multi-server control method provided in this application also includes:

[0024] The working status of the FLASH module is determined for the multi-channel server, and the working status determination result of the FLASH module is obtained.

[0025] When the FLASH module working status determination result is that the first FLASH module is working and the second FLASH module is not working, the chip select signal of the multi-channel server is switched from the second FLASH module to the first FLASH module to obtain the fifth multi-channel server control result.

[0026] Secondly, this application also provides a multi-channel server control device, comprising:

[0027] The central processing unit (CPU) status determination module is used to determine the CPU working status of the multi-channel server through the CPLD logic control chip and obtain the CPU working status determination result. The first CPU and the second CPU are both capable of loading the basic input / output system of the multi-channel server.

[0028] The switching signal acquisition module is used to acquire a central processing unit switching signal when the central processing unit's working status determination result is that both the first central processing unit and the second central processing unit are working;

[0029] The first server control module is used to switch the control source of the multi-channel server from the first central processor to the second central processor through the SWITCH chip when the central processor switching signal indicates that a central processor switching is required, so as to obtain the first multi-channel server control result.

[0030] Thirdly, this application also provides a multi-channel server control system, comprising:

[0031] The computing node module includes a first central processing unit and a second central processing unit. Both the first central processing unit and the second central processing unit are capable of loading the basic input / output system of the multi-channel server, so that the CPLD control module can switch the control source of the multi-channel server from the first central processing unit to the second central processing unit according to the central processing unit switching signal.

[0032] The CPLD control module is used to determine the working status of the central processing unit (CPU) of the multi-channel server and obtain the CPU working status determination result. When the CPU working status determination result is that both the first CPU and the second CPU are working, the module obtains a CPU switching signal and switches the control source of the multi-channel server from the first CPU to the second CPU according to the CPU switching signal.

[0033] Optionally, the multi-channel server control system provided in this application also includes:

[0034] The CPLD control module is also used to acquire chip select control signals, and switch the chip select signals of the first FLASH module and the second FLASH module according to the chip select control signals to obtain the fourth multi-channel server control result.

[0035] The first FLASH module is fixedly connected to the board of the multi-channel server, and the second FLASH module is movably connected to the board. It is used for the CPLD control module to switch the chip select signals of the first FLASH module and the second FLASH module to obtain the control result of the fourth multi-channel server.

[0036] Fourthly, this application also provides an electronic device including a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the multi-channel server control method as described in the first aspect.

[0037] Fifthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the multi-channel server control method as described in the first aspect.

[0038] In the technical solution provided in this application, by designing both the first CPU and the second CPU as CPUs capable of SPI bus management output, when both the first CPU and the second CPU are in working state, the control source of the multi-processor server can be switched from the first central processing unit to the second central processing unit according to the central processing unit switching signal issued by the user. This ensures that the first CPU and the second CPU in the multi-processor server can switch at any time, avoiding the problem that the multi-processor server is too dependent on a single CPU and that the CPU failure will have too great an impact on the entire multi-processor server. This realizes the function of flexible switching between multiple different CPUs in the multi-processor server, and improves the control flexibility and risk resistance of the multi-processor server.

[0039] The above description is merely an overview of the technical solution provided in this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are described below. Attached Figure Description

[0040] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0041] Figure 1 This is an example of an existing multi-channel server control system;

[0042] Figure 2 This is one of the schematic diagrams of the multi-channel server control method provided in the embodiments of this application;

[0043] Figure 3 This is a second schematic diagram of the multi-channel server control method provided in the embodiments of this application;

[0044] Figure 4 This is the third schematic diagram of the multi-channel server control method provided in the embodiments of this application;

[0045] Figure 5 This is the fourth schematic diagram of the multi-channel server control method provided in the embodiments of this application;

[0046] Figure 6 This is the fifth schematic diagram of the multi-channel server control method provided in the embodiments of this application;

[0047] Figure 7 This is the sixth schematic diagram of the multi-channel server control method provided in the embodiments of this application;

[0048] Figure 8 This is one example of a multi-channel server control system provided in this application;

[0049] Figure 9 This is the second example of a multi-channel server control system provided in this application;

[0050] Figure 10 This is an example diagram of the card module connector provided in this application;

[0051] Figure 11 This is a schematic diagram of a multi-channel server control device provided in an embodiment of this application;

[0052] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0053] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0054] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0055] With the development of server technology and the expansion of data processing needs, the requirements for server structural flexibility and performance are also increasing. Traditional server architectures are singular and cannot simultaneously meet the different needs of various industries and business functions, as well as user requirements such as cost optimization, and are gradually being replaced by multi-processor servers.

[0056] like Figure 1 As shown, taking a dual-socket server in a multi-socket server configuration as an example, it includes compute node modules, a Baseboard Management Controller (BMC) module, a Complex Programmable Logic Device (CPLD) interface module, and a chassis. One or more compute nodes can be installed within the chassis. The main central processing unit (CPU), for example... Figure 1 The CPU0 in the system outputs a Serial Peripheral Interface (SPI) signal as a channel for the Basic Input Output System (BIOS) FLASH, responsible for loading various firmware configurations and printing information required by the server system. For example, CPU0 directly controls BIOS FLASH0 and BIOS FLASH1. At this time, although the other CPUs in the multi-processor server, such as CPU1, can also provide SPI signals, they cannot obtain control of BIOS FLASH0 and BIOS FLASH1.

[0057] This multi-processor server architecture selects one CPU from multiple servers as the primary CPU for SPI bus management. When this selected CPU fails, for example, CPU0, the other CPUs lack control (e.g., CPU1 lacks independent control of the server system). This results in a large blast radius for the server failure, which is difficult to mitigate and severely impacts the normal operation of the server's functions. Furthermore, in this multi-processor server, multiple flash memory modules (e.g., primary and backup flash) are designed on separate boards, requiring manual intervention via the backup flash. Figure 1 The red FLASH1 related materials determine whether it supports backup function, which wastes board layout space and increases the difficulty of SPI bus layout.

[0058] To reduce the blast radius of multi-socket servers and minimize the impact of motherboard failures, existing technologies often employ multi-node servers as an alternative. Multi-node servers divide the system into multiple modules, each designed independently, and then integrated, assembled, and debugged. Since single or multiple nodes can be selected based on user needs, this approach ensures design flexibility and reduces board complexity, meeting diverse user requirements while also lowering board production and maintenance costs. However, this multi-node server approach suffers from difficulties in unified scheduling of the CPU, SPI, and FLASH. Furthermore, to address FLASH backup requirements, this multi-node design necessitates repetitive design in areas such as the motherboard to accommodate multiple FLASH backups, posing challenges to motherboard structure and layout design, hindering board reuse and decoupled component development. Moreover, the extremely high layout and routing requirements of the SPI bus on the motherboard introduce significant difficulties during the board design phase when implementing backup BIOS FLASH, extending the board design and development cycle. Furthermore, the functional requirements of the board during the product stage are optional based on the actual needs of the user. Boards that have BIOS FLASH backup wiring but do not have backup requirements will not only waste board layout space, but also lose some of the circuit designs that the original board could support. As a result, the overall performance of boards based on multi-node independent design and integrated assembly is not as good as that of traditionally designed boards.

[0059] The server control method provided in this application addresses the problem in existing technologies where multi-processor servers rely on a selected master CPU for SPI bus management output, while other CPUs lack control authority, leading to a large failure radius of the server when the master CPU fails. In this multi-processor server, multiple CPUs are designed as processors capable of independently loading BIOS, and the function of switching from the first CPU to the second CPU is realized by switching the node SPI interface. This avoids the problem of multi-processor servers being overly dependent on a single CPU, and the problem of excessive impact on the entire multi-processor server when a CPU fails, thus achieving the effect of flexible switching between multiple different CPUs in a multi-processor server.

[0060] Furthermore, in existing technologies where both the main FLASH and backup FLASH are designed on the board, the support for backup functionality can only be controlled by whether the material is installed, resulting in significant waste of board layout space and high difficulty in SPI wiring. This application fixes the main FLASH as the default onboard FLASH on the board as a fixed configuration of the board, and designs the backup FLASH as a modular plug-in card. Based on user needs, the modular design of components can be achieved through wiring components and control lines, saving board layout wiring space while improving the flexibility of board design.

[0061] The multi-channel server control method, apparatus, electronic device, and non-volatile readable storage medium provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0062] The first embodiment of this application relates to a multi-channel server control method, applied to a multi-channel server control system. The multi-channel server control system includes a switch chip and a CPLD logic control chip. The switch chip is connected to a first central processing unit (CPU) and a second CPU of the multi-channel server, respectively. Figure 2 As shown, it includes:

[0063] Step 101: The CPLD logic control chip is used to determine the working status of the central processing unit of the multi-channel server, and the result of the central processing unit working status determination is obtained. The first central processing unit and the second central processing unit are both able to load the basic input / output system of the multi-channel server.

[0064] Step 102: When the result of the central processing unit's working status determination is that both the first central processing unit and the second central processing unit are working, obtain the central processing unit switching signal;

[0065] Step 103: When the central processing unit switching signal indicates that a central processing unit switch is required, the control source of the multi-channel server is switched from the first central processing unit to the second central processing unit through the SWITCH chip to obtain the first multi-channel server control result.

[0066] Specifically, in the multi-processor server control method provided in this application, the working status of multiple CPUs in the multi-processor server is first determined to obtain the working status determination result of the central processing unit. When the working status determination result of the central processing unit indicates that both the first CPU and the second CPU are working, a central processing unit switching instruction issued by the BMC is received through the CPLD. For example, if the user issues a switching instruction to switch the first CPU to the second CPU, the CPU_SPI_SEL control signal is switched according to the central processing unit switching instruction, and the control source of the multi-processor server is switched from the first CPU to the second CPU, thus obtaining the first multi-processor server control result.

[0067] For example, the multi-server control method provided in this application is applied to a multi-server control system, which includes a SWITCH chip, a BMC substrate control chip, and a CPLD logic control chip. The SWITCH chip is located in a multiplexer (MUX) module and is connected to a first CPU, a second CPU, and a FLASH chip, respectively. It splits the SPI signals transmitted by the first CPU and the second CPU through the SPI link from 2 to 1 and outputs them to the FLASH chip.

[0068] The CPLD logic control chip aggregates the CS0 / CS1 signals output from the SWITCH switch on the motherboard and monitors the presence status of the first and second CPUs, obtaining their operating states. The CPLD logic control chip can also transmit signals via the CS0 signal to the onboard FLASH chip, i.e., the default primary FLASH chip or the first FLASH chip soldered onto the board. Furthermore, it can transmit commands from the BMC's serial port or network port via the I2C signal from the OMC to the CPLD, allowing switching between the primary and backup FLASH chips or switching between the first and second FLASH chips.

[0069] To achieve the above functions, the SWITCH chip can be a 2:1 high-speed bus MUX / DEMUX switch chip, such as the 74CBTLV3257PW. Since the 74CBTLV3257PW chip is a 4-channel MUX, and the SPI signal of a single CPU includes 10 signals such as CS0 / CS1 / MOSI / MISO / IO[3:0] / CLK / RESET, five 74CBTLV3257PW chips are needed to simultaneously switch the SPI signals of two CPUs for use by one or more FLASH chips. When there are more than two CPUs in a multi-channel server, and the number of MUX channels on the SWITCH chip is different, the SWITCH chip should be adjusted according to actual needs to ensure that the effect of switching the SPI signals of multiple CPUs for use by one or more FLASH chips can be achieved. This application does not limit the brand or number of SWITCH chips.

[0070] In the technical solution provided in this application, by designing both the first CPU and the second CPU as CPUs capable of SPI bus management output, when both the first CPU and the second CPU are in working state, the control source of the multi-processor server can be switched from the first central processing unit to the second central processing unit according to the central processing unit switching signal issued by the user. This ensures that the first CPU and the second CPU in the multi-processor server can switch at any time, avoiding the problem that the multi-processor server is too dependent on a single CPU and that the CPU failure will have too great an impact on the entire multi-processor server. This achieves the effect of flexible switching between multiple different CPUs in the multi-processor server, improving the control flexibility and risk resistance of the multi-processor server.

[0071] Based on the above implementation methods, such as Figure 3 As shown, in the multi-server control method provided in this application, after step 101, it further includes:

[0072] Step 104: When the working status judgment result of the central processing unit is that the second central processing unit is working and the first central processing unit is not working, the control source of the multi-channel server is switched from the first central processing unit to the second central processing unit to obtain the second multi-channel server control result.

[0073] Specifically, in the multi-channel server control method provided in this application, multiple CPUs in the multi-channel server perform working status judgment. After obtaining the working status judgment result of the central processing unit, when the working status judgment result of the central processing unit is that the first CPU is not working and the second CPU is working, for example, the CPLD determines that the first CPU is not working and the second CPU is working by recognizing the presence signal of the first CPU and the presence chip of the second CPU. Then, it switches the control source of the multi-channel server from the first CPU to the second CPU by issuing the CPU_SPI_SEL control signal, so that the second CPU can complete the control effect of the FLASH chip.

[0074] Based on the above embodiments, the multi-server control method provided in this application can switch the control source of the multi-server from the CPU that is not in operation to the CPU that is in operation when it is detected that some of the CPUs are in operation. This further improves the flexibility of multi-server control and expands the application scope of this application.

[0075] Based on the above implementation methods, such as Figure 4 As shown, in the multi-channel server control method provided in this application, after step 103, it further includes:

[0076] Step 105: Obtain the CPU error message;

[0077] Step 106: When the error message from the central processing unit indicates a fault in the second central processing unit, the control source of the multi-channel server is switched from the second central processing unit to the first central processing unit to obtain the control result of the third multi-channel server.

[0078] Specifically, the multi-server control method provided in this application can also monitor the first CPU and the second CPU in real time, generate corresponding central processing unit error information when the first CPU or the second CPU reports an error, and switch the CPU according to the central processing unit error information.

[0079] For example, when the control source of the multi-channel server is switched from the first CPU to the second CPU, the first CPU and the second CPU are monitored in real time. When the CPU corresponding to the second CPU reports an error, the CPU master control is switched according to the error information. By switching the source of the SPI, the control source of the CPU is switched from the second CPU back to the first CPU, and the control result of the third multi-channel server is obtained.

[0080] Based on the above embodiments, the multi-server control method provided in this application can also switch the CPU master control when the CPU corresponding to the control source of the multi-server alarms an error, switching the control source of the multi-server from the CPU in the error state to the CPU in the working state and in normal working state, which further improves the flexibility of multi-server control and expands the application scope of this application.

[0081] Based on the above implementation methods, such as Figure 5 As shown, the control source includes a serial peripheral device interface source. In the multi-channel server control method provided in this application, step 103 includes:

[0082] Step 131: According to the central processing unit switching signal, switch the serial peripheral device interface source of the multi-channel server from the first central processing unit to the second central processing unit to obtain the control result of the first multi-channel server.

[0083] Specifically, in the multi-server control method provided in this application, the control source of the multi-server can be an SPI source. Both the first CPU and the second CPU provide SPI interfaces and are connected to the MUX. The switching effect from the first CPU to the second CPU can be achieved simply by switching the SPI signal source.

[0084] Based on the above implementation methods, such as Figure 6 As shown, the multi-channel server includes a first FLASH module and a second FLASH module. In the multi-channel server control method provided in this application, after step 103, it further includes:

[0085] Step 171: Based on the pre-set time-sharing control principle, assign values ​​to the pins of the single-pole double-throw switch according to the chip select signal of the first central processing unit and the chip select signal of the second central processing unit.

[0086] Step 172: Obtain the chip select signal of the first FLASH module according to the pin of the single-pole double-throw switch;

[0087] Step 173: Obtain the chip select signal of the second FLASH module according to the pin of the single-pole double-throw switch;

[0088] Step 174: Obtain the chip select control signal;

[0089] Step 175: Based on the chip select control signal and the preset chip select strategy, perform chip select change judgment to obtain the chip select change judgment result;

[0090] Step 176: When the chip select change judgment result is that the chip select control signal and the chip select strategy are inconsistent, the chip select signal of the first FLASH module and the chip select signal of the second FLASH module are switched according to the chip select control signal to obtain the fourth multi-channel server control result.

[0091] Specifically, in the multi-channel server control method provided in this application, the CPLD logic control chip can switch between the first FLASH module or main FLASH and the second FLASH module or secondary FLASH by controlling the single-pole double-throw switch of the FLASH module. For example, the CPLD logic control chip can switch the single-pole double-throw switch through the chip select (CS) control signal to switch the chip select signals of the first FLASH module and the second FLASH module. Furthermore, the CPLD logic control chip can also assign the CPU's CS0 / CS1 signals to CS according to the time-division control principle, and then provide them to the 1A pin of the single-pole double-throw switch on the FLASH module, serving as the CS source for the first FLASH module and the CS source for the second FLASH module.

[0092] The first FLASH module is fixedly connected to the board, for example, soldered onto it, while the second FLASH module is designed to be pluggable, meaning it can be fixed to the board or removed according to user needs. The single-channel double-throw switch controlling the first and second FLASH modules defaults to the first FLASH module's CS (switching) state. For example, by defaulting to a low S position on the single-channel double-throw switch, A = B0, ensuring the board defaults to the first FLASH module's CS state.

[0093] Based on the above implementation methods, such as Figure 7 As shown, in the multi-channel server control method provided in this application, after step 176, it further includes:

[0094] Step 177: Determine the working status of the FLASH module on the multi-channel server and obtain the FLASH module working status determination result;

[0095] Step 178: When the FLASH module working status judgment result is that the first FLASH module is working and the second FLASH module is not working, switch the chip select signal of the multi-channel server from the two FLASH modules to the first FLASH module to obtain the fifth multi-channel server control result.

[0096] Specifically, in the multi-channel server control method provided in this application, when there is a switching between the first FLASH module and the second FLASH module on the board of the multi-channel server, the CPLD logic control chip can also monitor the first FLASH module and the second FLASH module, and switch the chip select signal according to the presence signal of the first FLASH module and the presence signal of the second FLASH module.

[0097] For example, when the multi-channel server switches to the second FLASH module according to the chip select control signal, if the CPLD logic control chip detects that the second FLASH module is not in place and the current multi-channel server does not have the hardware configuration of the backup FLASH chip corresponding to the second FLASH module, the chip select signal of the multi-channel server is adjusted back to the first FLASH module through the alkaline adjustment of the single-channel dual-branch switch, and the control result of the fifth multi-channel server is obtained.

[0098] Furthermore, the multi-server control method provided in this application allows for flexible switching of the CPU, which can be applied to the flexible switching of multiple FLASH chips in the BMC, thus realizing the decoupling design of the BMC from the perspective of hardware modules.

[0099] Based on the above embodiments, the multi-channel server control method provided in this application can switch and adjust not only according to the working state of the CPU, but also according to the working state of the FLASH module, thus expanding the flexibility of multi-channel server control and improving the versatility of this application.

[0100] Based on the above implementation methods, such as Figures 8-10 As shown, this application also provides an example of multi-channel server control:

[0101] like Figure 8As shown, the multi-server control system provided in this application includes CPU0, CPU1, MUX, BIOS FLASH1 module, BIOS FLASH0 module, CPLD module, and BMC module. The BMC module is connected to the CPLD module via an I2C link, providing control interfaces for various external systems such as UART serial port and RJ45 network port, and also providing an interface for users to control the server system. The CPLD module is connected to the MUX via a CPU_SPI_EL link, capable of monitoring various GPIO and I2C bus signals of CPU0 and CPU1, such as SPI signals, and flexibly switching the CPU and FLASH modules operating in the multi-server control system as needed. Both CPU0 and CPU1 are connected to the MUX via SPI links, such as the SPI_CPU0 link and the SPI_CPU1 link, allowing the CPLD to switch the control source of the multi-server system according to the control strategy. In addition, the BIOS FLASH0 module is soldered onto the board and connected to the MUX as the default onboard FLASH, while the BIOS FLASH1 module, such as "BIOSFLASH1MODULAR", is designed as a modular plug-in card that can be detachably installed on the board. The "SPI_CPU" link connects the MUX to the BIOS FLASH1 module and BIOS FLASH0 respectively, and the modular components are designed through specific connector layout wiring and control lines.

[0102] like Figure 9 As shown, in the FLASH1 module, a single-pole double-throw (SPDT) switch is used to switch between the BIOS FLASH1 module and the BIOS FLASH0 module. For example, the SPDT switch includes pins 1A, S, 1B0, and 1B1. For instance, the SPDT switch with part number SN 74LVC1G3157 is designed so that when the S pin is pulled low (B-low), A = B0, and when the S pin is pulled high (B-high), A = B1. Before switching, the S pin of the SPDT switch is pulled low by default, and A = B0, to ensure that the board defaults to CS to the first FLASH module.

[0103] Among them, the spare FLASH card module provided in this application is as follows: Figure 10As shown, since board-to-board connectors require latching and securing functions, the hardware anti-reverse insertion device for the card provided in this application includes a male connector, a female connector, a FLASH card PCB, plastic studs, and a motherboard PCB. Through the PCB structure and the design of the plastic studs on the motherboard, the latch of the male connector interferes with the plastic studs when inserted in reverse, preventing insertion. Due to the daisy-chain routing requirements commonly used in SPI buses, this application designs the module connector around the main FLASH, allowing for the expansion of upper-layer space through the card, reducing the layout footprint of the spare FLASH on the baseboard. The module SPI traces follow equal-length parallel routing, reducing the routing difficulty in the dense space of the baseboard. In summary, when a product configuration requires backup FLASH, this module can be added to the overall list and reused in different projects, thereby avoiding redundant SPI design in different projects, reducing SPI routing needs, and lowering the difficulty of board layout and routing. It should be emphasized that... Figure 10 The spare FLASH card module connector shown is merely an example of how this application enables the FLASH1 to be detachably mounted on the motherboard, and this application does not impose any limitations.

[0104] The second embodiment of this application relates to a multi-channel server control device, applied to a multi-channel server control system. The multi-channel server control system includes a switch chip and a CPLD logic control chip. The switch chip is connected to a first central processing unit (CPU) and a second CPU of the multi-channel server, respectively. Figure 11 As shown, it includes:

[0105] The central processing unit status judgment module 201 is used to judge the central processing unit working status of the multi-channel server through the CPLD logic control chip and obtain the central processing unit working status judgment result. The first central processing unit and the second central processing unit are both able to load the basic input / output system of the multi-channel server.

[0106] The switching signal acquisition module 202 is used to acquire a central processing unit switching signal when the central processing unit working status determination result is that both the first central processing unit and the second central processing unit are working.

[0107] The first server control module 203 is used to switch the control source of the multi-channel server from the first central processor to the second central processor through the SWITCH chip when the central processor switching signal indicates that a central processor switching is required, so as to obtain the first multi-channel server control result.

[0108] Based on the above embodiments, the multi-channel server control device provided in this application further includes:

[0109] A single central processing unit control module is used to switch the control source of the multi-processor from the first central processing unit to the second central processing unit when the central processing unit's working status determination result is that the second central processing unit is working and the first central processing unit is not working, so as to obtain the second multi-processor control result.

[0110] Based on the above embodiments, the multi-channel server control device provided in this application further includes:

[0111] The processor error acquisition module is used to acquire error information from the central processing unit.

[0112] The fault switching module is used to switch the control source of the multi-channel server from the second central processor to the first central processor when the error message of the central processor indicates that the second central processor is faulty, so as to obtain the control result of the third multi-channel server.

[0113] Based on the above implementation method, multiple account information is created. In the multi-channel server control device provided in this application, the first server control module 203 includes:

[0114] The serial peripheral device interface source switching unit is used to switch the serial peripheral device interface source of the multi-channel server from the first central processing unit to the second central processing unit according to the switching signal of the central processing unit, so as to obtain the control result of the first multi-channel server.

[0115] Based on the above embodiments, the multi-channel server control device provided in this application further includes:

[0116] The chip select assignment module is used to assign values ​​to the pins of the single-pole double-throw switch according to the chip select signal of the first central processing unit and the chip select signal of the second central processing unit, based on a pre-set time-division control principle.

[0117] The first chip select signal determination module is used to obtain the chip select signal of the first FLASH module according to the pin of the single-pole double-throw switch;

[0118] The second chip select signal determination module is used to obtain the chip select signal of the second FLASH module according to the pin of the single-pole double-throw switch;

[0119] Chip select control signal acquisition module, used to acquire chip select control signals;

[0120] The chip select strategy change judgment module is used to judge chip select changes based on the chip select control signal and the preset chip select strategy, and obtain the chip select change judgment result.

[0121] The first chip select signal switching module is used to switch the chip select signal of the first FLASH module and the chip select signal of the second FLASH module according to the chip select control signal when the chip select change judgment result is that the chip select control signal and the chip select strategy are inconsistent, so as to obtain the fourth multi-channel server control result.

[0122] Based on the above embodiments, the multi-channel server control device provided in this application further includes:

[0123] The module working status judgment module is used to judge the working status of the FLASH module of the multi-channel server and obtain the FLASH module working status judgment result.

[0124] The second chip select signal switching module is used to switch the chip select signal of the multi-channel server from the two FLASH modules to the first FLASH module when the FLASH module working status determination result is that the first FLASH module is working and the second FLASH module is not working, thereby obtaining the fifth multi-channel server control result.

[0125] The third embodiment of this application relates to a multi-channel server control system, comprising:

[0126] The computing node module includes a first central processing unit and a second central processing unit. Both the first central processing unit and the second central processing unit are capable of loading the basic input / output system of the multi-channel server, so that the CPLD control module can switch the control source of the multi-channel server from the first central processing unit to the second central processing unit according to the central processing unit switching signal.

[0127] The CPLD control module is used to determine the working status of the central processing unit (CPU) of the multi-channel server and obtain the CPU working status determination result. When the CPU working status determination result is that both the first CPU and the second CPU are working, the module obtains a CPU switching signal and switches the control source of the multi-channel server from the first CPU to the second CPU according to the CPU switching signal.

[0128] Based on the above embodiments, the multi-channel server control system provided in this application further includes:

[0129] The CPLD control module is also used to acquire chip select control signals, and switch the chip select signals of the first FLASH module and the second FLASH module according to the chip select control signals to obtain the fourth multi-channel server control result.

[0130] The first FLASH module is fixedly connected to the board of the multi-channel server, and the second FLASH module is movably connected to the board. It is used for the CPLD control module to switch the chip select signals of the first FLASH module and the second FLASH module to obtain the control result of the fourth multi-channel server.

[0131] The fourth embodiment of this application relates to an electronic device, such as... Figure 12 As shown, it includes:

[0132] At least one processor 301; and,

[0133] The memory 302 is communicatively connected to the at least one processor 301; wherein,

[0134] The memory 302 stores instructions that can be executed by the at least one processor, which are executed by the at least one processor 301 to enable the at least one processor 301 to implement the multi-channel server control method described in the first embodiment of this application.

[0135] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0136] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0137] The fifth embodiment of this application relates to a non-volatile computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the multi-channel server control method described in the first embodiment of this application.

[0138] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0139] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0140] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A multiplex server control method characterized by comprising: This invention is applied to a multi-channel server control system, which includes a SWITCH chip, a CPLD logic control chip, and a control source. The control source includes a serial peripheral device interface source. The SWITCH chip is located in a multiplexing module and is connected to the first central processing unit (CPU) of the multi-channel server, the second CPU of the multi-channel server, and a FLASH chip, respectively. It selects one of the SPI signals transmitted by the first CPU and the second CPU through the serial peripheral device interface link and outputs it to the FLASH chip. The FLASH chip includes a first FLASH module and a second FLASH module. The first FLASH module is fixedly connected to the board of the multi-channel server as the main FLASH, and the second FLASH module is movably connected to the board in the form of a modular plug-in card as a backup FLASH. Both the first central processing unit and the second central processing unit are configured to perform SPI bus management output; The method includes: The CPLD logic control chip is used to determine the working status of the central processing unit of the multi-channel server and obtain the working status determination result of the central processing unit. Both the first central processing unit and the second central processing unit are able to load the basic input / output system of the multi-channel server. When the CPU working status determination result is that both the first CPU and the second CPU are working, a CPU switching signal is obtained; When the central processing unit switching signal indicates that a central processing unit switch is required, the control source of the multi-channel server is switched from the first central processing unit to the second central processing unit through the SWITCH chip, thereby obtaining the first multi-channel server control result.

2. The method according to claim 1, characterized in that, After determining the CPU operating status of the multi-processor server and obtaining the CPU operating status determination result, the process further includes: When the CPU working status determination result is that the second CPU is working and the first CPU is not working, the control source of the multi-channel server is switched from the first CPU to the second CPU to obtain the second multi-channel server control result.

3. The method according to claim 1, characterized in that, After switching the control source of the multi-channel server from the first central processing unit to the second central processing unit according to the central processing unit switching signal, and obtaining the first multi-channel server control result, the method further includes: Obtain error information from the central processing unit; When the error message from the central processing unit indicates a failure of the second central processing unit, the control source of the multi-processor is switched from the second central processing unit to the first central processing unit to obtain the control result of the third multi-processor.

4. The method according to claim 1, characterized in that, When the central processing unit switching signal indicates that a central processing unit switch is required, the control source of the multi-channel server is switched from the first central processing unit to the second central processing unit via the SWITCH chip to obtain the first multi-channel server control result, including: According to the central processing unit switching signal, the serial peripheral device interface source of the multi-channel server is switched from the first central processing unit to the second central processing unit to obtain the control result of the first multi-channel server.

5. The method according to claim 4, characterized in that, After switching the control source of the multi-channel server from the first central processing unit to the second central processing unit according to the central processing unit switching signal, and obtaining the first multi-channel server control result, the method further includes: By using a pre-set time-sharing control principle, the pins of the single-pole double-throw switch are assigned values ​​according to the chip select signals of the first central processing unit and the second central processing unit. The chip select signal of the first FLASH module is obtained according to the pin of the single-pole double-throw switch; The chip select signal of the second FLASH module is obtained according to the pin of the single-pole double-throw switch; Obtain the chip select control signal; Based on the chip select control signal and the preset chip select strategy, a chip select change judgment is performed to obtain the chip select change judgment result; When the chip select change judgment result is that the chip select control signal and the chip select strategy are inconsistent, the chip select signal from the first FLASH module to the second FLASH module is switched according to the chip select control signal to obtain the fourth multi-channel server control result.

6. The method according to claim 5, characterized in that, When the chip select change judgment result indicates that the chip select control signal and the chip select strategy are inconsistent, the chip select signal of the first FLASH module and the chip select signal of the second FLASH module are switched according to the chip select control signal to obtain the fourth multi-channel server control result. This further includes: The working status of the FLASH module is determined for the multi-channel server, and the working status determination result of the FLASH module is obtained. When the FLASH module working status determination result is that the first FLASH module is working and the second FLASH module is not working, the chip select signal of the multi-channel server is switched from the second FLASH module to the first FLASH module to obtain the fifth multi-channel server control result.

7. A multi-channel server control device, characterized in that, This invention is applied to a multi-channel server control system, which includes a SWITCH chip, a CPLD logic control chip, and a control source. The control source includes a serial peripheral device interface source. The SWITCH chip is located in a multiplexing module and is connected to the first central processing unit (CPU) of the multi-channel server, the second CPU of the multi-channel server, and a FLASH chip, respectively. It selects one of the SPI signals transmitted by the first CPU and the second CPU through the serial peripheral device interface link and outputs it to the FLASH chip. The FLASH chip includes a first FLASH module and a second FLASH module. The first FLASH module is fixedly connected to the board of the multi-channel server as the main FLASH, and the second FLASH module is movably connected to the board in the form of a modular plug-in card as a backup FLASH. Both the first central processing unit and the second central processing unit are configured to perform SPI bus management output; include: The central processing unit (CPU) status determination module is used to determine the CPU working status of the multi-channel server through the CPLD logic control chip and obtain the CPU working status determination result. The first CPU and the second CPU are both capable of loading the basic input / output system of the multi-channel server. The switching signal acquisition module is used to acquire a central processing unit switching signal when the central processing unit's working status determination result is that both the first central processing unit and the second central processing unit are working; The first server control module is used to switch the control source of the multi-channel server from the first central processor to the second central processor through the SWITCH chip when the central processor switching signal indicates that a central processor switching is required, so as to obtain the first multi-channel server control result.

8. A multi-channel server control system, characterized in that, include: The computing node module includes a first central processing unit and a second central processing unit. Both the first central processing unit and the second central processing unit are capable of loading the basic input / output system of the multi-way server, so that the CPLD control module can switch the control source of the multi-way server from the first central processing unit to the second central processing unit through the SWITCH chip according to the central processing unit switching signal. The SWITCH chip is located in the multiplexing module and is connected to the first central processing unit of the multiplexing server, the second central processing unit of the multiplexing server, and the FLASH chip respectively. It selects one of the SPI signals transmitted by the first central processing unit and the second central processing unit through the serial peripheral interface link and outputs it to the FLASH chip. The CPLD control module is used to determine the working status of the central processing unit of the multi-channel server and obtain the working status determination result. When the working status determination result is that both the first central processing unit and the second central processing unit are working, the module obtains the central processing unit switching signal and switches the control source of the multi-channel server from the first central processing unit to the second central processing unit through the SWITCH chip according to the central processing unit switching signal. The CPLD control module is also used to acquire chip select control signals, and control a single-pole double-throw switch to switch the chip select signals of the first FLASH module and the second FLASH module according to the chip select control signals, so as to obtain the fourth multi-channel server control result; the single-pole double-throw switch is connected to the first FLASH module and the second FLASH module; The FLASH chip includes a first FLASH module and a second FLASH module. The first FLASH module is fixedly connected to the board of the multi-channel server as the main FLASH, and the second FLASH module is movably connected to the board as a backup FLASH in the form of a modular plug-in card. It is used for the CPLD control module to switch the chip select signals of the first FLASH module and the second FLASH module to obtain the fourth multi-channel server control result.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the multi-channel server control method as described in any one of claims 1-6.

10. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the multi-channel server control method as described in any one of claims 1-6.

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