Data processing method and device based on multi-digital filter fusion

Abstract

The application provides a data processing method and device based on multi-digital filter fusion, wherein the method comprises the following steps: acquiring an original data stream; synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to a setting parameter and an output rate; transmitting the original data stream to the target digital filter to trigger the target digital filter to perform preset calculation within a corresponding valid timing to obtain a target data stream after filtering processing; and outputting the target data stream after filtering processing in accordance with a set output rate; wherein the plurality of digital filters time-multiplex the same group of multiplier-accumulators within an ADC conversion period. By time-multiplexing the same group of operation units, the actual called operation units are less, the power consumption of the digital processing circuit is reduced, and the area of the digital processing circuit is minimized.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and in particular to a data processing method and apparatus based on the fusion of multiple digital filters. Background Technology

[0002] With the development of VLSI technology, digital filters, as an important branch of digital signal processing, are widely used components in speech, image signal processing, and digital communication. Because digital filters involve a large amount of computation, achieving high performance while fully utilizing hardware resources and reducing area is a current research topic that is attracting considerable attention.

[0003] Figure 1 It is a data processing flowchart provided in commonly used technologies. For example... Figure 1 As shown, in the data processing solutions provided by common technologies, the implementation paths of multiple digital filters are separate. Each digital filter includes an adder and a multiplier. Each digital filter needs to call its own adder and multiplier and other operation units when performing filtering processing. This results in the large size and high operating voltage of the mixed-signal circuit chip with digital processing circuit. Area and power consumption are often important technical indicators for the design of mixed-signal circuit chips.

[0004] Furthermore, since the noise suppression and bandwidth of digital signals vary depending on the sampling frequency, different data output rates are required. Similarly, for different sampling and data output frequencies, the subsequent digital processing circuits also need to select different types of digital filters according to different application scenarios.

[0005] Therefore, in order to solve the above-mentioned technical problems, there is an urgent need to provide a data processing method and device based on the fusion of multiple digital filters. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a data processing method and apparatus based on multi-digital filter fusion, so as to solve the technical problems existing in the present technology.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] According to one aspect of the present invention, a data processing method based on the fusion of multiple digital filters is provided, wherein the method includes: acquiring an original data stream; synchronizing the original data stream to the system clock domain and configuring a corresponding target digital filter according to setting parameters and output rate; transmitting the original data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within a corresponding effective time sequence to obtain a filtered target data stream; and outputting the filtered target data stream according to a set output rate; wherein the multiple digital filters time-division multiplex the same group of multipliers and accumulators within one ADC conversion cycle.

[0009] Furthermore, the method also includes: determining a matching system clock frequency based on the conversion frequency of the ADC.

[0010] Furthermore, the method for determining the matching system clock frequency based on the conversion frequency of the ADC includes:

[0011] Based on the ADC conversion time and the system clock frequency, determine the number of available system clock cycles within each ADC conversion cycle to determine the matching system clock frequency; and / or

[0012] Based on the computing resources required for each of the digital filters to subsequently perform the preset calculation, a number of system clock cycles corresponding to the computing resources are allocated, and a matching system clock frequency is determined based on the number of system clock cycles; wherein, one calculation step is allocated within each system clock cycle.

[0013] Furthermore, the step of transmitting the original data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding effective timing includes: in each effective timing of the target digital filter, applying the values ​​and coefficients of the original data stream to the input of combinational logic in the same set of multiply-accumulators in succession.

[0014] Furthermore, the method also includes: employing gated clock control to enable the high-frequency clock only within the operation window corresponding to each of the target digital filters.

[0015] Optionally, the method further includes: receiving data and configuring the corresponding different target output rates and selected digital filters in a register table.

[0016] Furthermore, the method for outputting the target data stream within the corresponding data output cycle includes:

[0017] Configure the current data output rate;

[0018] The target data stream is output within the corresponding data output cycle according to the current data output rate.

[0019] Furthermore, the method for outputting the target data stream within the corresponding data output cycle further includes:

[0020] Determine if the current calculation cycle is the output cycle of the set data output rate;

[0021] If so, perform subsequent calibration calculations on the current filtered target data stream and output the final converted data;

[0022] Conversely, the currently filtered target data stream is stored and transferred to the next ADC conversion cycle for processing.

[0023] Furthermore, the method further includes: performing calibration processing on the output target data stream.

[0024] According to another aspect of the present invention, a data processing apparatus based on multi-digital filter fusion is also provided, the apparatus comprising:

[0025] The data acquisition unit is used to acquire the raw data stream;

[0026] A synchronization and matching unit is used to synchronize the raw data stream to the system clock domain and configure the corresponding target digital filter according to the setting parameters and output rate.

[0027] A data processing unit is configured to receive the raw data stream and trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence to obtain the filtered target data stream; and

[0028] The data output unit is used to output the filtered target data stream at a set output rate.

[0029] In this configuration, the multiple digital filters share the same set of multiply-accumulators within a single ADC conversion cycle.

[0030] Compared to commonly used technologies, the data processing method and apparatus based on multi-digital filter fusion provided in this invention reduces the number of actual computing units called by time-division multiplexing the same group of computing units. In mixed-signal chips, even with large feature sizes and high operating voltages, the power consumption of the digital processing circuit can be reduced and the area of ​​the digital processing circuit can be minimized.

[0031] Furthermore, the high-frequency system clock was gated, which enabled the digital processing circuit to achieve a good balance between processing speed, area, and power consumption. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 It is a data processing flowchart provided in commonly used technologies.

[0034] Figure 2 This is a flowchart illustrating a data processing method based on multi-digital filter fusion provided in an embodiment of the present invention.

[0035] Figure 3 This is a data processing flowchart provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram illustrating the calculation steps for the system clock cycle corresponding to the ADC conversion cycle provided in an embodiment of the present invention.

[0037] Figure 5 This is a timing diagram of the CIC filter in a non-decimation period provided in an embodiment of the present invention.

[0038] Figure 6 This is a timing diagram of the CIC filter during the decimation period provided in an embodiment of the present invention.

[0039] Figure 7 This is a timing diagram of the window function filter provided in an embodiment of the present invention during a non-output period.

[0040] Figure 8 This is a timing diagram of the window function filter at the output cycle provided in an embodiment of the present invention.

[0041] Figure 9 This is a structural block diagram of a data processing device based on multi-digital filter fusion provided in an embodiment of the present invention. Detailed Implementation

[0042] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0043] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] Figure 2 This is a flowchart illustrating a data processing method based on multi-digital filter fusion provided in an embodiment of the present invention. Figure 3 This is a data processing flowchart provided in an embodiment of the present invention.

[0045] refer to Figure 2 As shown, an embodiment of the present invention provides a data processing method based on multi-digital filter fusion, which includes the following steps:

[0046] Step S10: Obtain the raw data stream;

[0047] Step S20: Synchronize the raw data stream to the system clock domain and configure the corresponding digital filter according to the setting parameters and output rate;

[0048] Step S30: The original data stream is transmitted to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence to obtain the filtered target data stream;

[0049] Step S40: Output the filtered target data stream according to the set output rate;

[0050] In this configuration, the multiple digital filters share the same set of multiply-accumulators within a single ADC conversion cycle.

[0051] The following will combine Figure 3 The specific steps S10 to S40 are described.

[0052] In step S10, the ADC receives multiple analog signals and outputs corresponding digital signals, such as a bit stream. In this embodiment of the invention, the data stream converted by the ADC is used as the original data stream.

[0053] In step S20, the raw data stream is synchronized to the system clock domain, and a target digital filter matching the raw data stream is selected from multiple digital filters based on the target output rate of the raw data stream. This is because the raw data stream and the system clock belong to two different systems and have different clocks. If synchronization is not performed, clock violations will occur. Therefore, before inputting the raw data stream output from the ADC conversion to the digital signal processing circuit for processing, the raw data stream needs to be synchronized to the system clock domain.

[0054] For example, depending on the application scenario, the target output rate of the raw data stream can be configured differently. Therefore, it is generally possible to use the SPI general interface to write to the register table and use different filters according to the target output rate configuration of the raw data stream and different filtering requirements (spectral response). For example, in this embodiment of the invention, for different cutoff frequencies and the suppression effect on the power frequency of 50 Hz and 60 Hz, a comb filter (CIC) or a window function filter or a combination of both can be configured. In addition, other types of filters can also be configured and used according to different application requirements, and this embodiment of the invention does not impose any limitations.

[0055] In step S30, the original data stream is transmitted to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence, so as to obtain the filtered target data stream;

[0056] Specifically, since the ADC in this example is an "oversampling ADC," it typically requires continuous decimation in the subsequent digital processing circuit after the ADC output. For example, a data stream (data signal) is decimated at regular intervals to achieve a moving average effect. Different frequencies require different decimation methods, thereby configuring different filters. For example, the comb filter (CIC), as one type of decimation filter, has a simple structure with only an adder unit, can achieve multiple rate down-decimation, and can filter out high-frequency components. Moreover, it does not require multipliers or coefficient storage during implementation, making it a simple and effective sampling rate conversion method. A comb filter (CIC) is usually composed of a cascaded integral comb filter and a decimation filter. The integral comb filter part is also called the integral part, and the decimation filter part is also called the differential part.

[0057] For example, in this embodiment of the invention, the ADC may be a Sigma Delta ADC or a similar type of circuit, and the ADC has an oversampling rate (OSR) of N, where N is a positive integer greater than 1. For example, a 1-bit ADC may have an OSR of N = 3600, and the OSR of the ADC may be set by control logic.

[0058] The target digital filter is triggered to perform corresponding digital filtering operations under the corresponding effective timing, executing preset calculations. For example, a comb filter (CIC) performs three integration operations, then decimates, and then performs three difference operations before outputting. Generally, the above effective timing corresponds to the period during which the pulse waveform of the system clock cycle rises from a low level to a high level.

[0059] In step S40, since the noise suppression and bandwidth of digital signals at different frequencies vary when sampling, different data output rates are required for output. In this embodiment of the invention, different data output rates can be configured at the output end of the target digital filter. Based on the different output rates, the decimation factor and multiplication / addition coefficients of the digital filter are adjusted to output the filtered target data stream at the set data output rate.

[0060] In this configuration, the multiple digital filters share the same set of multiply-accumulators within a single ADC conversion cycle.

[0061] For example, the method of outputting the filtered target data stream at a set output rate includes: configuring the current data output rate; and outputting the target data stream at the current data output rate within the corresponding data output cycle.

[0062] For example, the method of outputting the filtered target data stream at a set output rate further includes: determining whether the current operation cycle is the output cycle of the set data output rate;

[0063] If so, perform subsequent calibration calculations on the current filtered target data stream and output the final converted data;

[0064] Conversely, the currently filtered target data stream is stored and transferred to the next ADC conversion cycle for processing.

[0065] The technical solution provided by this invention uses time-division multiplexing of the same group of multiply-accumulators to fuse multiple digital filters, thereby reducing the digital circuit area and static power consumption. By reducing the digital circuit area, the performance of the mixed-signal chip is improved while the cost is well controlled.

[0066] Furthermore, the method also includes: determining a matching system clock frequency based on the conversion frequency of the ADC.

[0067] Specifically, in one embodiment, before circuit design, the number of system clock cycles available in each ADC conversion cycle is determined based on the ADC conversion time and the system clock frequency, in order to determine the matching system clock frequency.

[0068] In another embodiment, based on the computing resources required for each of the digital filters to subsequently perform the preset calculation, a number of system clock cycles corresponding to the computing resources are allocated, and a matching system clock frequency is determined based on the number of system clock cycles; wherein, one calculation step is allocated within each system clock cycle.

[0069] In another embodiment, the two embodiments described above can be considered in combination.

[0070] Figure 4 This is a schematic diagram illustrating the calculation steps for the system clock cycle corresponding to the ADC conversion cycle provided in an embodiment of the present invention.

[0071] like Figure 4 As shown, the computational steps required for the multiple digital filters are arranged within each system clock cycle, wherein each computational step will time-multiplex the same set of multiply-accumulators 1. It should be understood that the multiple digital filters share the same digital signal processing link and are time-triggered to perform preset computations within the effective timing sequence.

[0072] For example, the ADC conversion frequency is 256kHz (generally determined by analog circuitry). The computational resources required for each of the multiple digital filters in the subsequent digital signal processing chain to perform the preset calculations are considered. If the CIC filter requires 6 calculation steps and the window function filter requires 3, plus the subsequent calibration calculations, then the relationship between the corresponding system clock frequency and the ADC conversion frequency (16 times) can be estimated. In this case, the system clock frequency is 4096kHz, which meets the aforementioned calculation cycle requirement.

[0073] Furthermore, the step of transmitting the original data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding effective timing sequence includes: in each effective timing sequence of the target digital filter, successively applying the values ​​and coefficients of the original data stream to the input of combinational logic in the same set of multiply-accumulators. Combinational logic is used to pass the input down level by level, and then the required data is retrieved through timing control logic.

[0074] Optionally, the coefficients mentioned above can be stored within each target digital filter itself, or they can be written into a register table or generated as required by control. This embodiment of the invention does not impose any limitations.

[0075] Optionally, the method further includes: receiving data and configuring the corresponding different target output rates and selected digital filters in a register table.

[0076] Furthermore, the method also includes: calibrating the output target data.

[0077] Figure 5 This is a timing diagram of the CIC filter in a non-decimation period provided in an embodiment of the present invention.

[0078] like Figure 5 As shown, when the CIC filter is in a non-decimation period, the CIC integral part is the operation window, while the CIC differential part is the non-operation window. Therefore, within each ADC conversion cycle, the system's high-frequency clock only needs to be connected to the operation unit during the corresponding CIC integral part (operation window) time window. During other non-operation window time windows, clock gating ensures the system's high-frequency clock is low and does not flip. That is, only multiplier-accumulator 1 connects the system's high-frequency clock to the register storing the operation result during the corresponding CIC integral part (operation window) time window to retrieve the operation data. Specifically, by using a gated clock module to control the system clock to be released only during the target digital filter's operation window period, and turned off during other non-operation window periods, the high-frequency system clock does not need to be constantly on, thereby reducing the dynamic power consumption caused by high-frequency clock flipping.

[0079] Figure 6 This is a timing diagram of the CIC filter during the decimation period provided in an embodiment of the present invention.

[0080] like Figure 6 As shown, during the decimation period of the CIC filter, which is the data output period, the high-frequency clock of the system is enabled in the operation window of the CIC integral part, the operation window of the CIC differential part, and the operation window of the subsequent calculation steps. In other words, the high-frequency clock of the system is connected to the storage register of the calculation result in the operation window of the CIC integral part, the operation window of the CIC differential part, and the operation window of the subsequent calculation steps.

[0081] It should be noted that since it may not be possible to complete all data processing within the current ADC conversion cycle, another set of multiply-accumulators 2 can be turned on simultaneously in the next ADC conversion cycle to perform calibration calculations while performing digital filtering processing.

[0082] Figure 7This is a timing diagram of the window function filter provided in an embodiment of the present invention during a non-output period. Figure 8 This is a timing diagram of the window function filter at the output cycle provided in an embodiment of the present invention.

[0083] like Figure 7 and Figure 8 As illustrated, for example, if the ADC oversampling uses a 64x decimation, decimation needs to be performed within the corresponding 64 ADC conversion cycles. From the 1st to the 63rd ADC conversion cycle, the window function filter is in a non-output cycle, performing only multiplication operations (multiplying by the corresponding coefficients). In the 64th ADC conversion cycle, the window function filter is in the output cycle. Similarly, when the window function filter is in a non-output cycle, the system clock is only released during its operation window, and turned off during other non-operation windows. This eliminates the need for the high-frequency system clock to be constantly on, thereby reducing the dynamic power consumption caused by high-frequency clock flipping. When the window function filter is in the output cycle, the high-frequency system clock is on during the window function filter's operation window and in the operation windows of subsequent calculation steps.

[0084] Compared to commonly used technologies, the data processing method and apparatus based on multi-digital filter fusion provided in this invention reduces the number of actual computing units called by time-division multiplexing the same group of computing units. In mixed-signal chips, even with large feature sizes and high operating voltages, the power consumption of the digital processing circuit can be reduced and the area of ​​the digital processing circuit can be minimized.

[0085] Furthermore, the high-frequency system clock was gated, which enabled the digital processing circuit to achieve a good balance between processing speed, area, and power consumption.

[0086] Furthermore, when the computation cycle is insufficient, another set of computation units (such as multiply-accumulator 2) can be activated in parallel, which balances the computational speed and area / power consumption of the digital processing circuit. By reducing the area of ​​the digital processing circuit, the performance of the mixed-signal chip can be improved while the cost can be well controlled.

[0087] Figure 9 This is a structural block diagram of a data processing device based on multi-digital filter fusion provided in an embodiment of the present invention.

[0088] like Figure 9 As shown, according to another aspect of the present invention, an embodiment of the present invention also provides a data processing apparatus 300 based on multi-digital filter fusion, the apparatus 300 comprising:

[0089] Data acquisition unit 310 is used to acquire raw data stream;

[0090] Synchronization and matching unit 320 is used to synchronize the raw data stream to the system clock domain and configure the corresponding digital filter according to the setting parameters and output rate.

[0091] The data processing unit 330 is used to receive the original data stream and trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence to obtain the filtered target data stream.

[0092] Data output unit 340 is used to output the filtered target data stream at a set output rate;

[0093] In this configuration, the multiple digital filters share the same set of multiply-accumulators within a single ADC conversion cycle.

[0094] For example, in the data acquisition unit 310, the ADC receives a plurality of corresponding analog signals and outputs corresponding digital signals, such as a bit stream of digital signals. In this embodiment of the invention, the data stream converted by the ADC is acquired as the original data stream.

[0095] The synchronization and matching unit 320 includes a selector, which is used to select a matching target digital filter based on different application scenarios.

[0096] After synchronizing the raw data stream to the system clock domain, a target digital filter that matches the raw data stream is selected from a plurality of digital filters based on the target output rate of the raw data stream.

[0097] For example, depending on the application scenario, the target output rate of the raw data stream can be configured differently. Therefore, it is generally possible to use the SPI general interface to write to the register table and use different filters according to the target output rate configuration of the raw data stream and different filtering requirements (spectral response). For example, in this embodiment of the invention, for different cutoff frequencies and the suppression effect on the power frequency of 50 Hz and 60 Hz, a comb filter (CIC) or a window function filter or a combination of both can be configured. In addition, other types of filters can also be configured and used according to different application requirements, and this embodiment of the invention does not impose any limitations.

[0098] The data output unit 340 includes a discriminator, which is used to determine whether the current operation cycle is the output cycle of the set data output rate based on the currently configured data output rate.

[0099] By employing the technical solution provided in the embodiments of the present invention, the same group of computing units is time-division multiplexed, resulting in fewer computing units actually called. In mixed-signal chips, even with large feature sizes and high operating voltages, the power consumption of digital processing circuits can be reduced, and the area of ​​digital processing circuits can be minimized.

[0100] It should be understood that the execution principle, other aspects and effects of each unit (module) in the data processing device based on multi-digital filter fusion can be found in the content of the foregoing embodiments, and will not be repeated here.

[0101] The data processing method and apparatus based on multi-digital filter fusion provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method based on multi-digital filter fusion, characterized in that, The method includes: Obtain the raw data stream; The raw data stream is synchronized to the system clock domain and the corresponding target digital filter is configured according to the set parameters and output rate. The original data stream is transmitted to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence, so as to obtain the filtered target data stream; The filtered target data stream is output at the set output rate. Among them, the multiple digital filters share the same group of multiply-accumulators in a time-division multiplexing manner within one ADC conversion cycle; The step of outputting the filtered target data stream at a set output rate includes: configuring the current data output rate; and outputting the target data stream at the current data output rate within the corresponding data output cycle.

2. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The method further includes: Based on the conversion frequency of the ADC, a matching system clock frequency is determined.

3. The data processing method based on multi-digital filter fusion as described in claim 2, characterized in that, The method for determining the matching system clock frequency based on the conversion frequency of the ADC includes: Based on the ADC conversion time and the system clock frequency, determine the number of available system clock cycles within each ADC conversion cycle to determine the matching system clock frequency; and / or Based on the computing resources required for each of the digital filters to subsequently perform the preset calculation, a number of system clock cycles corresponding to the computing resources are allocated, and a matching system clock frequency is determined based on the number of system clock cycles; wherein, one calculation step is allocated within each system clock cycle.

4. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The step of transmitting the raw data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within the corresponding valid time sequence includes: In the effective timing of each of the target digital filters, the values ​​and coefficients of the original data stream are successively applied to the input of the combinational logic in the same set of multiply-accumulators.

5. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The method further includes: A gated clock control is used to enable the high-frequency clock only in the operation window corresponding to each of the target digital filters.

6. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The method further includes: It receives data and configures the corresponding target output rate and selected digital filter in the register table.

7. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The method for outputting the filtered target data stream at a set output rate further includes: Determine if the current calculation cycle is the output cycle of the set data output rate; If so, perform subsequent calibration calculations on the current filtered target data stream and output the final converted data; Conversely, the currently filtered target data stream is stored and transferred to the next ADC conversion cycle for processing.

8. The data processing method based on multi-digital filter fusion as described in claim 1, characterized in that, The method further includes: The output target data stream is then calibrated.

9. A data processing device based on multi-digital filter fusion, characterized in that, The device includes: The data acquisition unit is used to acquire the raw data stream; A synchronization and matching unit is used to synchronize the raw data stream to the system clock domain and configure the corresponding target digital filter according to the setting parameters and output rate. A data processing unit is configured to receive the raw data stream and trigger the target digital filter to perform a preset calculation within the corresponding effective time sequence to obtain the filtered target data stream; and The data output unit is used to output the filtered target data stream at a set output rate. Among them, the multiple digital filters share the same set of multiply-accumulators in a time-division multiplexing manner within one ADC conversion cycle; The data processing unit is further configured to configure the current data output rate and output the target data stream within the corresponding data output cycle according to the current data output rate.

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