Simulation acceleration method, device, equipment and storage medium

Abstract

This application relates to a simulation acceleration method, apparatus, device, and storage medium, applied in the field of chip design technology. The method includes: acquiring a Device Under Test (DUT) module; constructing a dual-top-level verification environment according to a preset method, wherein the dual-top-level verification environment includes a synthesis BFM module, a chip verification file, and test data, and the synthesis BFM module includes state machine transition flags; combining the test data and the state machine transition flags to generate a data set; calling the simulation acceleration software to transmit the synthesis BFM module, the DUT module, and the data set to the hardware execution unit; calling the simulation acceleration software to compile and run the chip verification file; and receiving the test results generated by the hardware execution unit running the data set. The technical effect of this application is: improving chip simulation speed and increasing chip simulation efficiency.

Description

Technical Field

[0001] This application relates to the field of chip design verification technology, and in particular to a simulation acceleration method, apparatus, device and storage medium. Background Technology

[0002] Since Moore's Law was proposed in the 1870s, chip design has reached the scale of hundreds of millions of gates, and the size continues to shrink. High-performance, high-frequency, low-power, low-cost, and multifunctional chips have become the design goals of chip manufacturers, and integrated circuits are gradually shifting towards a system-level architecture. With the increasing complexity of chip functions and structures, tape-out failures can lead to huge economic losses for companies, and in the worst case, the entire batch of chips can be scrapped. Therefore, the industry is placing increasing emphasis on chip verification. Currently, chip verification accounts for about 70% of the chip development process, and as chip size continues to increase, the proportion of time spent on verification is also constantly growing.

[0003] Currently, the most widely used chip simulation and verification technology in the industry is simulation, or software simulation technology. This involves running the DUT (Design Under Test) and Testbench (verification platform) on a computer, using simulation software to simulate the hardware circuitry to achieve functional verification of the chip. In the verification process of small-scale integrated circuits, software simulation technology can leverage its high visibility and ease of debugging to complete various verification tasks. However, the high design complexity of software simulators and their sequential execution characteristics lead to slow simulation speeds. Currently, SoC chips reach the scale of hundreds of millions of transistors, and completing a single SoC chip verification process using software simulation technology can take several months. This results in low chip debugging efficiency, making it unaffordable for most companies due to the significant time cost. Summary of the Invention

[0004] To help solve the problem of slow simulation speed in software simulators, this application provides a simulation acceleration method, apparatus, device, and storage medium.

[0005] In a first aspect, this application provides a simulation acceleration method, employing the following technical solution: the method is applied to a simulation acceleration system, the simulation acceleration system comprising a hardware execution unit and simulation acceleration software, and the method includes:

[0006] Obtain the DUT module;

[0007] A dual-top-level verification environment is built according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files, and test data. The comprehensive BFM module includes a state machine transition flag.

[0008] The test data and the state machine transition flags are combined to generate a data set;

[0009] The simulation acceleration software is invoked to transmit the integrated BFM module, the DUT module, and the data set to the hardware execution unit.

[0010] The simulation acceleration software is invoked to compile and run the chip verification file;

[0011] Receive the test results generated by the hardware execution unit running the data set.

[0012] Through the above technical solution, a new dual-top-level verification environment is established, employing a collaborative simulation approach combining software and hardware. The hardware execution unit operates on the hardware side, with test data running simultaneously on both the software and hardware sides. A BFM module is configured on the software side, and both the BFM and DUT modules are transmitted to the hardware side for execution. This effectively reduces the runtime of the DUT module, which typically accounts for a large proportion of the computer-side runtime. The parallel operation of the software and hardware sides significantly improves the processing speed of the DUT module. Furthermore, the generated dataset elevates the simulation interaction from the signal-level to the transaction-level. The dual-top-level verification environment prepares the dataset and sends it to the BFM module via simulation acceleration software. The BFM module then interacts with the DUT module, reducing the software and hardware synchronization time and thus the overall simulation time.

[0013] In a specific feasible implementation, the step of building a dual-top-level verification environment according to a preset method includes:

[0014] A single top-level verification environment is built according to a preset method, wherein the single top-level verification environment includes the original BFM module;

[0015] The original BFM module is removed from the single top-level verification environment, and the integrated BFM module is generated according to the preset communication protocol;

[0016] The integrated BFM module and the DUT module are instantiated into a newly created top-level file to generate the dual top-level verification environment.

[0017] Through the above technical solution, a new dual-top-level verification environment can be generated by redeveloping the BFM module in the traditional single-top-level verification environment. The dual-top-level verification environment re-divides the structural content of the single-top-level verification environment, allowing the software and hardware sides to run test data simultaneously; it changes the serial operation on the software side to the parallel operation on the hardware side, thereby improving the chip verification simulation speed.

[0018] In one specific implementation, the simulation acceleration software includes a first simulation acceleration software and a second simulation acceleration software, and the step of calling the simulation acceleration software to compile and run the chip verification file includes:

[0019] The first simulation acceleration software is invoked to generate database and EDIF files;

[0020] The second simulation acceleration software is invoked, and the EDIF file and the dual top-level verification environment are imported into the second simulation acceleration software according to the database file;

[0021] The chip verification file is compiled and run by calling the first simulation acceleration software and the second simulation acceleration software.

[0022] The above technical solution calls the simulation acceleration software to run the chip verification file, thereby realizing the simulation verification of the chip. The database file generated by the first simulation acceleration software can mainly be the configuration file, description file and other files needed during the test simulation process, so as to facilitate the subsequent use of the first simulation acceleration software and the second simulation acceleration software to run the chip verification file.

[0023] In one specific implementation, the step of calling the first simulation acceleration software to generate the database file and EDIF file includes:

[0024] The first simulation acceleration software is invoked to set the integrated BFM module and the DUT module as top-level modules;

[0025] The first simulation acceleration software is invoked to synthesize the integrated BFM module and the DUT module to generate an EDIF file;

[0026] The preset debug signal is added to the first simulation acceleration software, and the database file is generated after the first simulation acceleration software is called to lay out and route.

[0027] In one specific implementation scheme, the step of calling the second simulation acceleration software and importing the EDIF file and the dual top-level verification environment into the second simulation acceleration software according to the database file includes:

[0028] The second simulation acceleration software is invoked to generate intermediate files;

[0029] The second simulation acceleration software is invoked to download the database file;

[0030] The second simulation acceleration software is invoked, and the EDIF file and the dual top-level verification environment are imported into the second simulation acceleration software according to the database file.

[0031] In one specific implementation, after the second simulation acceleration software is invoked to download the database file, the method further includes:

[0032] The second simulation acceleration software is invoked to compile the dual-top-level verification environment and generate an executable file;

[0033] The second simulation acceleration software is invoked to run the executable file to achieve simulation.

[0034] In one specific implementation scheme, after the second simulation acceleration software is invoked to run the executable file to perform the simulation, the method further includes:

[0035] The second simulation acceleration software is invoked to generate waveform files.

[0036] Through the above technical solutions, the simulation acceleration system can perform emulation-level simulation verification and can set probes in the system to capture waveforms. Compared with traditional FPGA prototype verification methods, it has more debugging means and improves work efficiency.

[0037] Secondly, this application provides a simulation acceleration device, which adopts the following technical solution: the device is applied to a simulation acceleration system, the simulation acceleration system includes a hardware operating unit and simulation acceleration software, and the device includes:

[0038] The information acquisition module is used to acquire information from the DUT module.

[0039] The environment setup module is used to build a dual-top-level verification environment according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files, and test data. The comprehensive BFM module includes a state machine transition flag.

[0040] The data generation module is used to combine the test data and the state machine transition flags to generate a data set;

[0041] The data transmission module is used to call the simulation acceleration software to transmit the integrated BFM module, the DUT module and the data set to the hardware execution unit;

[0042] The compilation and execution module is used to call the simulation acceleration software to compile and run the chip verification file;

[0043] The result receiving module is used to receive the test results generated by the hardware running unit running the data set.

[0044] Thirdly, this application provides a computer device that adopts the following technical solution: it includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as any of the above-described simulation acceleration methods.

[0045] Fourthly, this application provides a computer-readable storage medium that stores a computer program capable of being loaded by a processor and executing any of the above-mentioned simulation acceleration methods.

[0046] In summary, this application has the following beneficial technical effects:

[0047] A new dual-top-level verification environment was established, employing a hardware-software co-simulation approach. The hardware execution unit operates on the hardware side, with test data running simultaneously on both the software and hardware sides. A BFM module is configured on the software side, and both the BFM and DUT modules are transmitted to the hardware side for execution. This effectively reduces the runtime of the DUT module, which typically accounts for a large proportion of computer-side runtime. Parallel operation on both the software and hardware sides significantly improves the processing speed of the DUT module. Furthermore, the generated dataset elevates the simulation interaction from signal-level to transaction-level. The dual-top-level verification environment prepares the dataset and sends it to the BFM module via simulation acceleration software. The BFM module then interacts with the DUT module, reducing the hardware-software synchronization time and the overall simulation time. Ultimately, the hardware-software co-simulation acceleration is consistently more than 100 times faster than pure software simulation. Attached Figure Description

[0048] Figure 1 This is a flowchart of the simulation acceleration method in the embodiments of this application;

[0049] Figure 2 This is a schematic diagram of the simulation acceleration device in the embodiments of this application;

[0050] Figure 3 This is a schematic diagram used to illustrate a computer device in the embodiments of this application.

[0051] Attached reference numerals: 201, Information acquisition module; 202, Environment setup module; 203, Data generation module; 204, Data transmission module; 205, Compilation and execution module; 206, Result receiving module. Detailed Implementation

[0052] The following is in conjunction with the appendix Figure 1-3 This application will be described in further detail.

[0053] This application discloses a simulation acceleration method for chip verification simulation testing. This method, employing a hardware-software combined approach, improves debugging efficiency and reduces the overall simulation time for chip verification. Users create a new dual-top-level verification environment, running the DUT module and BFM module on the hardware side. Furthermore, the traditional data combination method in the verification environment is changed to transaction-level data. Simulation acceleration software transmits transaction-level data from the software side to the BFM module on the hardware side, and then the BFM module transmits the data to the DUT module for execution, significantly increasing the speed of verification simulation, typically achieving speedups of hundreds to thousands of times. The need for faster chip verification simulation stems from the high design complexity and sequential execution characteristics of traditional simulation software for hardware circuits, leading to slow simulation speeds. For example, SoC chips have reached the scale of hundreds of millions of transistors; completing a single SoC chip verification process using software simulation technology could take months, resulting in low chip debugging efficiency and significant time costs.

[0054] Reference Figure 1 The method includes the following steps:

[0055] S10, Obtain the DUT module.

[0056] Specifically, the computer acquires the DUT module; the DUT module refers to the chip's design under test module, and the purpose of chip verification is to find design defects in the DUT module and modify those defects.

[0057] S20, builds a dual-top-level verification environment according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files and test data. The comprehensive BFM module includes state machine transition flags.

[0058] Specifically, the computer software builds a dual-top-level verification environment according to a preset method. The preset method can be UVM, or Universal Verification Methodology, which is a verification platform development framework that users can use to build functional verification environments. The built dual-top-level verification environment includes a synthesis BFM module, chip verification files, and test data. The synthesis BFM module is the BFM module in the dual-top-level verification environment. The BFM module, or Bus Function Model, can directly interact with the DUT module through a communication interface according to different communication protocols and the interaction methods specified by the protocols. The test data is generated by the dual-top-level verification environment, and the chip verification files are verification files developed by the user according to the functions that need to be verified by the chip. The synthesis BFM module also contains information such as state machine transition flags required to generate the data set.

[0059] S30 combines the test data and the state machine jump flags to generate a data set.

[0060] Specifically, test data is generated using a dual-top-level verification environment built with UVM. Users then combine the test data and the state machine transition flags in the integrated BFM module into a data set via a computer according to a specific communication protocol. To achieve transaction-level interaction between the hardware and software and reduce the synchronization time, the transaction width of the data set should be as large as possible. For example, a 256-bit transaction width can be formed based on the SDIO 3.0 protocol.

[0061] S40 calls the simulation acceleration software to transmit the integrated BFM module, DUT module, and data set to the hardware execution unit.

[0062] Specifically, the simulation acceleration software is called on the computer to transmit the synthesis BFM module, DUT module and data set to the hardware execution unit, so that the synthesis BFM module and DUT module can run on the hardware side. The parallel operation of the computer side and the hardware side can improve the processing speed of the DUT.

[0063] S50 calls simulation acceleration software to compile and run chip verification files.

[0064] Specifically, on the computer side, simulation acceleration software is called to compile and run chip verification files. The chip verification files can be developed and written by the user according to the functions that the chip needs to verify. After running through the simulation acceleration software, simulation tests for chip verification can be performed. On the computer side, the chip verification files are first compiled and run, and then the hardware side runs the test data to generate test results.

[0065] S60 receives the test results generated by the hardware operation unit's operation data set.

[0066] Specifically, the hardware execution unit receives the integrated BFM module, DUT module, and data set. The hardware execution unit runs the verification chip function and returns the final test results to the computer. The computer receives the test results of the chip verification simulation test from the hardware execution unit.

[0067] In this application, a new dual-top-level verification environment is established, employing a hardware-software co-simulation approach. The hardware execution unit is on the hardware side, with test data running simultaneously on both the software and hardware sides. A BFM module is configured on the software side, and both the BFM and DUT modules are transmitted to the hardware side for execution. This effectively reduces the runtime of the DUT module, which typically accounts for a large proportion of the computer's runtime. The parallel operation of the software and hardware sides significantly improves the processing speed of the DUT module. Furthermore, the generated dataset elevates the simulation interaction from the signal-level to the transaction-level. The dual-top-level verification environment prepares the dataset and sends it to the BFM module via simulation acceleration software. The BFM module then interacts with the DUT module, reducing the hardware-software synchronization time and thus the overall simulation time.

[0068] In one embodiment, building a dual-top-level verification environment according to a preset method can be specifically performed as follows:

[0069] First, a single-top-level verification environment is built using a preset method, which can be the UVM method. UVM stands for Universal Verification Methodology. The environment built using UVM includes a driver, monitor, agent, and sequencer. The built single-top-level verification environment contains the original BFM module, which is the BFM module in the single-top-level verification environment and exists in the driver and monitor. Next, the single-top-level verification environment is improved by deleting the original BFM module. When deleting the original BFM module, all timing components in the single-top-level verification environment should be removed, so that the driver and monitor do not contain any timing components. Then, a new synthesized BFM module is developed using Verilog language according to a preset communication protocol. The preset protocol can be SDIO 3.0, but users can also choose an applicable communication protocol according to their actual needs. Finally, a new top-level file is created, and the newly generated synthesized BFM module and DUT module are instantiated in the new top-level file, thus generating a dual-top-level verification environment. In a dual-top-level verification environment, HVL and HDL domains are included. On the computer side, transaction-level data transmitted from the HVL domain to the HDL domain can be converted into signal-level data, and signal-level data from the HDL domain can be converted into transaction-level data, according to a specific communication protocol, so as to realize mutual transmission. The specific communication protocol can be the SDIO3.0 protocol.

[0070] It should be noted that a dual top-level verification environment can be built in two ways. One is to use the preset method, namely UVM, to directly build and generate the dual top-level verification environment; the other is to use the preset method, namely, UVM first builds a single top-level verification environment, and then redevelops the BFM module part in the single top-level verification environment and instantiates it into the newly created top-level file to generate a dual top-level verification environment. Users can choose the appropriate environment building method according to their actual needs, and there are no restrictions here.

[0071] In this application, a new dual-top-level verification environment can be generated by redeveloping the BFM module in the traditional single-top-level verification environment. The dual-top-level verification environment re-divides the structural content of the single-top-level verification environment, allowing the software and hardware sides to run test data simultaneously. This changes the serial operation on the software side to the parallel operation on the hardware side, thereby improving the chip verification simulation speed.

[0072] In one embodiment, the simulation acceleration software includes a first simulation acceleration software and a second simulation acceleration software. Calling the simulation acceleration software to compile and run the chip verification file can be specifically executed as follows:

[0073] First, the first simulation acceleration software is invoked to generate a database file and an EDIF file. Then, the second simulation acceleration software is invoked, importing the EDIF file and the dual-top-level verification environment into the second simulation acceleration software based on the database file. The database file can be a collection of files, such as configuration files, description files, and configuration information. Next, on the computer, based on the information and configuration in the database file, the EDIF file and the dual-top-level verification environment are imported into the second simulation acceleration software. Finally, the first and second simulation acceleration software are invoked to compile and run the chip verification file, with the first and second simulation acceleration software operating using a Makefile.

[0074] In this application, simulation acceleration software is called to run the chip verification file to realize the simulation verification of the chip. The database file generated by the first simulation acceleration software can mainly be the configuration file, description file and other files needed during the test simulation, so as to facilitate the subsequent use of the first simulation acceleration software and the second simulation acceleration software to run the chip verification file.

[0075] In one embodiment, calling the first simulation acceleration software to generate the database file and EDIF file can be specifically performed as follows:

[0076] First, a new project is created using the first simulation acceleration software, with the BFM module and DUT module set as top-level modules. Then, the first simulation acceleration software is used to perform synthesis operations on the BFM module and DUT module to generate an EDIF file. Next, preset debug signals, clock signals, and other signals are added to the first simulation acceleration software. After placement and routing using the first simulation acceleration software, a database file is generated. The database file can be a collection of files, including configuration files, description files, and configuration information.

[0077] In one embodiment, invoking the second simulation acceleration software and importing the EDIF file and the dual top-level verification environment into the second simulation acceleration software based on the database file can be specifically executed as follows:

[0078] First, the second simulation acceleration software is invoked to generate intermediate files, which mainly include usercapi files, SVTB templates, and other files. The SVTB template is a template developed based on the SV language, which users can use to connect signals. Next, the second simulation acceleration software is invoked to download the database file. Then, the second simulation acceleration software is invoked again to import the EDIF file and the dual top-level verification environment into the second simulation acceleration software based on the database file. The second simulation acceleration software includes multiple modes for users to choose from, and users can import the EDIF file and the dual top-level verification environment into the second simulation acceleration software in the selected mode.

[0079] In one embodiment, after downloading the database file using the second simulation acceleration software, the following steps can also be performed:

[0080] First, the second simulation acceleration software is called to compile the dual-top-level verification environment and generate an executable file; then, the second simulation acceleration software is called to run the executable file to perform the simulation.

[0081] In one embodiment, considering the inconvenience for users to observe the simulated signal when the signal waveform cannot be visually seen, the following steps can be performed after calling the second simulation acceleration software to run the executable file to achieve simulation:

[0082] Calling the second simulation acceleration software to generate waveform files on the computer software side can visualize the waveform of the signal, making it easier for users to observe. It also increases debugging methods and can improve the efficiency of chip simulation.

[0083] In this application, the simulation acceleration system can perform emulation-level simulation verification and can set probes in the system to capture waveforms. Compared with traditional FPGA prototype verification methods, it has additional debugging means and improves work efficiency.

[0084] Figure 1 This is a flowchart illustrating a simulation acceleration method in one embodiment. It should be understood that, although... Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; unless explicitly stated otherwise, there is no strict order requirement for the execution of these steps, and they can be executed in other orders; and Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0085] Based on the above method, this application also discloses a simulation acceleration device.

[0086] Reference Figure 2 The device includes the following modules:

[0087] Information acquisition module 201 is used to acquire information from the DUT module;

[0088] The environment setup module 202 is used to build a dual-top-level verification environment according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files and test data. The comprehensive BFM module includes state machine transition flags.

[0089] Data generation module 203 is used to combine test data and state machine transition flags to generate a data set;

[0090] Data transmission module 204 is used to call simulation acceleration software to transmit the integrated BFM module, DUT module and data set to the hardware execution unit;

[0091] Compile and run module 205 is used to call the simulation acceleration software to compile and run chip verification files;

[0092] The result receiving module 206 is used to receive the test run results generated by the hardware running unit running data set.

[0093] In one embodiment, the environment setup module 202 is specifically used to set up a single top-level verification environment according to a preset method. The single top-level verification environment includes the original BFM module; delete the original BFM module from the single top-level verification environment and generate a comprehensive BFM module according to a preset communication protocol; instantiate the comprehensive BFM module and the DUT module under the newly created top-level file to generate a dual top-level verification environment.

[0094] In one embodiment, the simulation acceleration software includes a first simulation acceleration software and a second simulation acceleration software. The compilation and execution module 206 is specifically used to call the first simulation acceleration software to generate a database file and an EDIF file; call the second simulation acceleration software to import the EDIF file and the dual top-level verification environment into the second simulation acceleration software according to the database file; and call the first simulation acceleration software and the second simulation acceleration software to compile and run the chip verification file.

[0095] In one embodiment, the compilation and execution module 206 is further configured to call the first simulation acceleration software to set the synthesized BFM module and DUT module as top-level modules; call the first simulation acceleration software to synthesize the synthesized BFM module and DUT module to generate an EDIF file; add preset debug signals to the first simulation acceleration software; and call the first simulation acceleration software to place and route the data to generate a database file.

[0096] In one embodiment, the compilation and execution module 206 is further configured to call the second simulation acceleration software to generate intermediate files; call the second simulation acceleration software to download database files; and call the second simulation acceleration software to import the EDIF file and the dual top-level verification environment into the second simulation acceleration software based on the database file.

[0097] In one embodiment, the compilation and execution module 206 is further used to call the second simulation acceleration software to compile the dual top-level verification environment and generate an executable file; and to call the second simulation acceleration software to run the executable file to perform simulation.

[0098] In one embodiment, the compilation and execution module 206 is also used to call the second simulation acceleration software to generate waveform files.

[0099] The simulation acceleration device provided in this application embodiment can be applied to the simulation acceleration method provided in the above embodiment. For relevant details, please refer to the above method embodiment. The implementation principle and technical effect are similar, and will not be repeated here.

[0100] It should be noted that the simulation acceleration device provided in this embodiment is only illustrated by the above-described division of functional modules / units. In practical applications, the functions described above can be assigned to different functional modules / units as needed, that is, the internal structure of the simulation acceleration device can be divided into different functional modules / units to complete all or part of the functions described above. Furthermore, the implementation methods of the simulation acceleration method provided in the above embodiments and the implementation methods of the simulation acceleration device provided in this embodiment belong to the same concept. For details of the specific implementation process of the simulation acceleration device provided in this embodiment, please refer to the above method embodiments, which will not be repeated here.

[0101] This application also discloses a computer device.

[0102] Specifically, such as Figure 3 As shown, the computer device can be a desktop computer, laptop computer, handheld computer, or cloud server, etc. The computer device may include, but is not limited to, a processor and memory. The processor and memory can be connected via a bus or other means. The processor can be a Central Processing Unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, graphics processing units (GPUs), embedded neural network processing units (NPUs) or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0103] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the above embodiments of this application. The processor executes various functional applications and data processing by running the non-transitory software programs, instructions, and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0104] This application also discloses a computer-readable storage medium.

[0105] Specifically, the computer-readable storage medium is used to store a computer program, which, when executed by a processor, implements the methods described in the above-described method embodiments. Those skilled in the art will understand that implementing all or part of the processes in the methods described in the above-described embodiments of this application can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0106] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A simulation acceleration method, characterized in that: The method is applied to a simulation acceleration system, which includes a hardware execution unit and simulation acceleration software. The method includes: Obtain the DUT module; A dual-top-level verification environment is built according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files, and test data. The comprehensive BFM module includes a state machine transition flag. The test data and the state machine transition flags are combined to generate a data set; The simulation acceleration software is invoked to transmit the integrated BFM module, the DUT module, and the data set to the hardware execution unit. The simulation acceleration software is invoked to compile and run the chip verification file; Receive the test results generated by the hardware execution unit running the data set; The step of building a dual-top-level verification environment according to a preset method includes: A single top-level verification environment is built according to a preset method, wherein the single top-level verification environment includes the original BFM module; The original BFM module is removed from the single top-level verification environment, and the integrated BFM module is generated according to the preset communication protocol. Instantiate the integrated BFM module and the DUT module into the newly created top-level file to generate the dual top-level verification environment; The simulation acceleration software includes a first simulation acceleration software and a second simulation acceleration software. The step of calling the simulation acceleration software to compile and run the chip verification file includes: The first simulation acceleration software is invoked to generate database and EDIF files; The second simulation acceleration software is invoked, and the EDIF file and the dual top-level verification environment are imported into the second simulation acceleration software according to the database file; The first and second simulation acceleration software are invoked to compile and run the chip verification file; The step of calling the first simulation acceleration software to generate the database file and EDIF file includes: The first simulation acceleration software is invoked to set the integrated BFM module and the DUT module as top-level modules; The first simulation acceleration software is invoked to synthesize the integrated BFM module and the DUT module to generate an EDIF file; Add the preset debug signal to the first simulation acceleration software, and generate a database file after calling the first simulation acceleration software for layout and routing. The step of calling the second simulation acceleration software and importing the EDIF file and the dual top-level verification environment into the second simulation acceleration software according to the database file includes: The second simulation acceleration software is invoked to generate intermediate files; The second simulation acceleration software is invoked to download the database file; The second simulation acceleration software is invoked, and the EDIF file and the dual top-level verification environment are imported into the second simulation acceleration software according to the database file.

2. The method according to claim 1, characterized in that: After the second simulation acceleration software is invoked to download the database file, the process further includes: The second simulation acceleration software is invoked to compile the dual-top-level verification environment and generate an executable file; The second simulation acceleration software is invoked to run the executable file to achieve simulation.

3. The method according to claim 2, characterized in that: After the second simulation acceleration software is invoked to run the executable file to perform the simulation, the method further includes: The second simulation acceleration software is called to generate waveform files.

4. A simulation acceleration device, characterized in that: The device is used in a simulation acceleration system, which includes a hardware execution unit and simulation acceleration software. The device includes: Information acquisition module (201) is used to acquire information from the DUT module; The environment setup module (202) is used to build a dual-top-level verification environment according to a preset method. The dual-top-level verification environment includes a comprehensive BFM module, chip verification files and test data. The comprehensive BFM module includes a state machine transition flag. The data generation module (203) is used to combine the test data and the state machine jump flag to generate a data set; The data transmission module (204) is used to call the simulation acceleration software to transmit the integrated BFM module, the DUT module and the data set to the hardware execution unit; The compilation and execution module (205) is used to call the simulation acceleration software to compile and run the chip verification file; The result receiving module (206) is used to receive the test run results generated by the hardware running unit running the data set; Environment setup module 202 is specifically used to build a single top-level verification environment according to a preset method. The single top-level verification environment includes the original BFM module; delete the original BFM module from the single top-level verification environment and generate a comprehensive BFM module according to a preset communication protocol; instantiate the comprehensive BFM module and the DUT module into the newly created top-level file to generate a double top-level verification environment. The simulation acceleration software includes a first simulation acceleration software and a second simulation acceleration software. The compilation and execution module 206 is specifically used to call the first simulation acceleration software to generate a database file and an EDIF file; call the second simulation acceleration software to import the EDIF file and the dual top-level verification environment into the second simulation acceleration software based on the database file; and call the first and second simulation acceleration software to compile and run the chip verification file. The compilation and execution module 206 is also used to call the first simulation acceleration software to set the synthesis BFM module and DUT module as the top-level modules; call the first simulation acceleration software to synthesize the synthesis BFM module and DUT module to generate an EDIF file; add the preset debug signals to the first simulation acceleration software; and call the first simulation acceleration software to generate a database file after placement and routing. The compilation and execution module 206 is also used to call the second simulation acceleration software to generate intermediate files; call the second simulation acceleration software to download the database file; and call the second simulation acceleration software to import the EDIF file and the dual top-level verification environment into the second simulation acceleration software based on the database file.

5. A computer device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed according to any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed according to any one of claims 1 to 3.

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