A semiconductor package structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor package structure and a preparation method thereof. The semiconductor package structure comprises a first substrate, a first semiconductor chip connected with the first substrate, a second semiconductor chip stack structure comprising at least one first chip stack structure and at least one second chip stack structure, the first chip stack structure and the second chip stack structure being arranged side by side on the first semiconductor chip along a first direction, the first chip stack structure and the second chip stack structure being respectively provided with a plurality of second conductive bumps on a side away from each other along the first direction, the first direction being a direction parallel to a plane of the first substrate, and a plurality of second substrates, signal lines in the second substrates being connected with the second conductive bumps, the second substrates being connected with the first substrate along a direction perpendicular to the plane of the first substrate.

Description

Technical Field

[0001] This disclosure relates to the field of three-dimensional fabrication technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] HBM (High Bandwidth Memory) is a high-performance DRAM memory based on 3D stacking technology. Compared with traditional memory technologies, HBM memory has higher bandwidth, more I / O, lower power consumption, and smaller size, and can be applied to high-performance computing, supercomputers, large data centers, artificial intelligence / deep learning, cloud computing and other fields.

[0003] HBM memory technology primarily evolved to meet the demands of processor computing scale. In the early days, the requirements for computer data processing were not high, the processor architecture had fewer layers, the computing scale was smaller, and the computing power was also lower. Later, with the development of technologies such as AI, the requirements for processors became increasingly higher. The deepening of models increased the demand for computing power, leading to bandwidth bottlenecks, i.e., I / O problems. At this time, this was solved by increasing on-chip cache and optimizing scheduling models to increase data reuse. However, with the popularization of AI and other technologies and the increase in the number of users, cloud AI processing requires multi-user, high-throughput, low-latency, and high-density deployment. The surge in computing units made the I / O bottleneck even more severe. At this point, the emergence of on-chip HBM memory made it possible to put AI / deep learning entirely on-chip. While improving integration, it also freed bandwidth from being limited by the number of interconnects of chip pins, thus solving the bandwidth and computing power bottlenecks to a certain extent.

[0004] However, as the integration requirements of HBM memory increase, the number of chip stacking layers increases, and the technical challenges also increase. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor packaging structure and a method for preparing the same.

[0006] According to a first aspect of the present disclosure, a semiconductor packaging structure is provided, comprising:

[0007] First substrate;

[0008] A first semiconductor chip is connected to the first substrate;

[0009] The second semiconductor chip stack structure includes at least one first chip stack structure and at least one second chip stack structure, wherein the first chip stack structure and the second chip stack structure are arranged side by side on the first semiconductor chip along a first direction; the first chip stack structure and the second chip stack structure include a plurality of second semiconductor chips stacked sequentially along the first direction; the first chip stack structure and the second chip stack structure each have a plurality of second conductive bumps formed on the side away from each other along the first direction; wherein, the first direction is a direction parallel to the plane of the first substrate;

[0010] Multiple second substrates, signal lines within the second substrates are connected to the second conductive bumps; the second substrates are connected to the first substrate along a direction perpendicular to the plane of the first substrate.

[0011] In some embodiments, the first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

[0012] In some embodiments, it also includes:

[0013] An adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, and between the first chip stack structure and the second chip stack structure.

[0014] In some embodiments, the adhesive film includes a first adhesive film and a second adhesive film located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0015] In some embodiments, the first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

[0016] In some embodiments, a groove is formed in the first substrate, the first semiconductor chip is located in the groove, the first semiconductor chip is connected to the first substrate through a first conductive bump, and the second substrate is connected to the first substrate through a third conductive bump.

[0017] In some embodiments, the first semiconductor chip is located on the first substrate, the first semiconductor chip is connected to the first substrate via a first conductive bump, and the second substrate is connected to the first substrate via a third conductive bump.

[0018] In some embodiments, it also includes:

[0019] Multiple through-silicon vias, wherein the through-silicon vias penetrate the second semiconductor chip along a first direction;

[0020] Multiple fourth conductive bumps are located between two adjacent second semiconductor chips and are connected to the corresponding through-silicon vias;

[0021] The second conductive bump is connected to the through silicon via and the fourth conductive bump.

[0022] In some embodiments, the signal line includes a ground line and a power line, and the second conductive bump includes a first sub-conductive bump and a second sub-conductive bump;

[0023] The grounding wire is electrically connected to the first sub-conductive bump, and the power supply wire is electrically connected to the second sub-conductive bump.

[0024] In some embodiments, at least one first sub-conductive bump is spaced between two adjacent second sub-conductive bumps, and the first sub-conductive bump surrounds the second sub-conductive bump.

[0025] In some embodiments, it also includes:

[0026] A filling layer is located between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

[0027] In some embodiments, it also includes:

[0028] An encapsulation compound structure is located on the first substrate; the encapsulation compound structure at least encapsulates the second semiconductor chip stack structure and the second substrate.

[0029] The Young's modulus of the filling layer is greater than that of the Young's modulus of the encapsulated compound structure.

[0030] According to a second aspect of the present disclosure, a method for fabricating a semiconductor packaging structure as described in any of the above embodiments is provided, comprising:

[0031] A second semiconductor chip stack structure is formed, the second semiconductor chip stack structure including at least one first chip stack structure and at least one second chip stack structure, the first chip stack structure and the second chip stack structure including a plurality of second semiconductor chips stacked sequentially; a plurality of second conductive bumps are formed on one side of the first chip stack structure and the second chip stack structure along the stacking direction;

[0032] Forming the first semiconductor chip;

[0033] The surfaces of the first chip stack structure and the second chip stack structure that are away from the second conductive bump along the stacking direction are arranged opposite to each other, and the surfaces of the first chip stack structure and the second chip stack structure that are perpendicular to the stacking direction are connected to the surface of the first semiconductor chip.

[0034] A plurality of second substrates are provided; the second substrates are located along the stacking direction on the side of the first chip stack structure and the second chip stack structure where the second conductive bumps are formed, and the signal lines in the second substrates are connected to the second conductive bumps;

[0035] A first substrate is provided; the first semiconductor chip is connected to the first substrate; and the second substrate is connected to the first substrate.

[0036] In some embodiments, forming the second semiconductor chip stack structure includes:

[0037] Along the stacking direction, a through-silicon via is formed, penetrating the second semiconductor chip;

[0038] A fourth conductive bump is formed between two adjacent second semiconductor chips, and the fourth conductive bump is connected to the through silicon via accordingly;

[0039] Multiple second semiconductor chips are bonded together through the through-silicon vias and the fourth conductive bumps to form a stack of second semiconductor chips.

[0040] The second semiconductor chip stack is formed into a plurality of second semiconductor chip stack structures.

[0041] In some embodiments, providing the second substrate includes:

[0042] The second substrate is cut to form a third conductive bump, such that the surface of the second substrate with the third conductive bump is flush with the surface of the second semiconductor chip stack structure near the first semiconductor chip.

[0043] In some embodiments, a groove is formed within the first substrate;

[0044] The first semiconductor chip is placed in the groove.

[0045] In some embodiments, it also includes:

[0046] An adhesion film is formed to connect the second semiconductor chip stack structure and the first semiconductor chip, and to connect the first chip stack structure and the second chip stack structure.

[0047] In some embodiments, the first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

[0048] In some embodiments, it also includes:

[0049] A filling layer is formed between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

[0050] In this embodiment, the first chip stack structure and the second chip stack structure are respectively connected to a second substrate and connected to the first substrate through the second substrate. In this way, the first substrate can supply power to the first chip stack structure and the second chip stack structure respectively. By supplying power to the second semiconductor chip stack structure through a two-stage substrate, the power supply link can be effectively shortened and the voltage drop on the link can be reduced. At the same time, the first substrate can supply power to the first semiconductor chip through a wired connection and exchange signals with the first semiconductor chip, which has high reliability. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure;

[0053] Figure 2 This is a schematic diagram of a semiconductor packaging structure provided in another embodiment of the present disclosure;

[0054] Figure 3 A side view of the second conductive bump along a first direction provided in an embodiment of this disclosure;

[0055] Figure 4 A schematic flowchart illustrating the method for fabricating a semiconductor packaging structure according to an embodiment of this disclosure;

[0056] Figures 5a to 5g This is a schematic diagram of the device structure during the fabrication process of the semiconductor packaging structure provided in the embodiments of this disclosure.

[0057] Explanation of reference numerals in the attached figures:

[0058] 10-First substrate; 11-Lead wire; 12-Substrate connection bump; 101-Groove;

[0059] 20 - First semiconductor chip; 21 - First conductive bump;

[0060] 301 - First chip stack structure; 302 - Second chip stack structure; 300 - Second semiconductor chip stack; 31 - Second semiconductor chip; 311 - Through-silicon via; 312 - Fourth conductive bump; 32 - Second conductive bump; 321 - First sub-conductive bump; 322 - Second sub-conductive bump;

[0061] 40 - Second substrate; 41 - Signal line; 411 - Ground line; 412 - Power line; 42 - Third conductive bump; 40' - Remaining second substrate;

[0062] 50 - Adhesive film;

[0063] 60 - Dielectric layer;

[0064] 70 - Filler layer;

[0065] 80-Encapsulated compound structure. Detailed Implementation

[0066] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0067] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0068] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0069] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0070] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0071] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0072] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0073] HBM technology is a major representative of the evolution of DRAM from traditional 2D to stereoscopic 3D, paving the way for DRAM 3D. It primarily utilizes Through Silicon Via (TSV) technology for chip stacking to increase throughput and overcome the bandwidth limitations within a single package. Several DRAM dies are vertically stacked, with the dies connected using TVS technology. From a technical perspective, HBM makes full use of space and reduces area, perfectly aligning with the semiconductor industry's trend towards miniaturization and integration. Furthermore, it breaks through the bottlenecks of memory capacity and bandwidth, and is considered a next-generation DRAM solution.

[0074] In 3D IC product packaging, DRAM chips are generally stacked on logic dies using a parallel stacking (P-Stack) method. As integration requirements increase, the number of DRAM chip stacking layers increases, leading to more and more technical challenges. For example, the communication distance between the DRAM chips stacked on higher layers and the logic dies stacked on lower layers becomes longer, and the communication delay between different layers of DRAM chips and logic dies will vary due to the different distances; the number of TSV vias used for communication increases proportionally, sacrificing wafer area; and when using single-sided power supply, stability is poor.

[0075] Based on this, the present disclosure provides a semiconductor packaging structure. Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present disclosure.

[0076] See Figure 1 The semiconductor packaging structure includes:

[0077] First substrate 10;

[0078] The first semiconductor chip 20 is connected to the first substrate 10;

[0079] The second semiconductor chip stack structure includes at least one first chip stack structure 301 and at least one second chip stack structure 302, wherein the first chip stack structure 301 and the second chip stack structure 302 are arranged side by side on the first semiconductor chip 20 along a first direction; the first chip stack structure 301 and the second chip stack structure 302 include a plurality of second semiconductor chips 31 stacked sequentially along the first direction; the first chip stack structure 301 and the second chip stack structure 302 respectively form a plurality of second conductive bumps 32 on the side away from each other along the first direction; wherein, the first direction is a direction parallel to the plane of the first substrate 10;

[0080] Multiple second substrates 40, signal lines 41 within the second substrates 40 are connected to the second conductive bumps 32; the second substrates 40 are connected to the first substrate 10 along a direction perpendicular to the plane of the first substrate 10.

[0081] In this embodiment, the first chip stack structure and the second chip stack structure are respectively connected to a second substrate and connected to the first substrate through the second substrate. In this way, the first substrate can supply power to the first chip stack structure and the second chip stack structure respectively. By supplying power to the second semiconductor chip stack structure through a two-stage substrate, the power supply link can be effectively shortened and the voltage drop on the link can be reduced. At the same time, the first substrate can supply power to the first semiconductor chip through a wired connection and exchange signals with the first semiconductor chip, which has high reliability.

[0082] In one embodiment, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0083] The first substrate 10 may include a first substrate (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) located on the upper and lower surfaces of the first substrate, respectively.

[0084] The first substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0085] The first upper insulating dielectric layer and the first lower insulating dielectric layer can be solder resist layers, for example, the materials of the first upper insulating dielectric layer and the first lower insulating dielectric layer can be green paint.

[0086] A substrate connection bump 12 is formed on the lower surface of the first substrate 10. The substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, and can receive at least one of control signals, power signals and ground signals for operating the first semiconductor chip and the second semiconductor chip from the external device, or can receive data signals to be stored in the first semiconductor chip and the second semiconductor chip from the external device, and can also provide the data in the first semiconductor chip and the second semiconductor chip to the external device.

[0087] The substrate connection bump 12 comprises a conductive material. In this embodiment, the substrate connection bump 12 is a solder ball. It is understood that the shape of the substrate connection bump provided in this embodiment is only one lower-level, feasible specific implementation and does not constitute a limitation on this disclosure. The substrate connection bump can also be other shapes and structures. The number, spacing, and position of the substrate connection bumps are not limited to any specific arrangement and can be modified in various ways.

[0088] In one embodiment, a first conductive bump 21 is formed on one side of the first semiconductor chip 20.

[0089] The material of the first conductive bump 21 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.

[0090] The first semiconductor chip 20 is electrically connected to the first substrate 10 through the first conductive bump 21. The first substrate 10 supplies power to the first semiconductor chip 20 via a wired connection and performs signal exchange.

[0091] The first conductive bump 21 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first semiconductor chip 20 can interact with external devices through the substrate connection bump 12.

[0092] In one embodiment, such as Figure 1 As shown, a groove 101 is formed in the first substrate 10, the first semiconductor chip 20 is located in the groove 101, the first semiconductor chip 20 is connected to the first substrate 10 through a first conductive bump 21, and the second substrate 40 is connected to the first substrate 10 through a third conductive bump 42.

[0093] In this embodiment, placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor package structure.

[0094] In another embodiment, such as Figure 2 As shown, the first semiconductor chip 20 is located on the first substrate 10, and the first semiconductor chip 20 is connected to the first substrate 10 through the first conductive bump 21. The second substrate 40 is connected to the first substrate 10 through the third conductive bump 42.

[0095] In this embodiment, the first semiconductor chip is located above the first substrate. As a result, the first substrate does not need to be provided with a groove, thus simplifying the process. Furthermore, there is a gap between the first semiconductor chip and the first substrate, which can increase the heat dissipation effect of the first semiconductor chip.

[0096] The number of stacked second semiconductor chips 31 in the first chip stacking structure 301 and the second chip stacking structure 302 can be multiple. In this embodiment of the disclosure, as... Figure 1 and Figure 2 As shown, the number of stacked second semiconductor chips 31 in the first chip stacking structure 301 and the second chip stacking structure 302 is five.

[0097] In one embodiment, such as Figure 1 and Figure 2 As shown, the number of stacked second semiconductor chips 31 in the first chip stack structure 301 and the second chip stack structure 302 can be the same. In some other embodiments, the number of stacked second semiconductor chips in the first chip stack structure 301 and the second chip stack structure 302 can also be different.

[0098] In this embodiment of the disclosure, multiple second semiconductor chips in the first chip stacking structure and the second chip stacking structure are stacked vertically in parallel (V-Stack) on the first semiconductor chip. In this way, the first semiconductor chip and the second semiconductor chip can communicate wirelessly. This can effectively solve the communication difficulties caused by the increasing number of stacking layers of the second semiconductor chips when multiple second semiconductor chips are stacked in parallel (P-Stack) on the first semiconductor chip.

[0099] In one embodiment, the first semiconductor chip 20 includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

[0100] In one embodiment, the semiconductor packaging structure further includes: an adhesion film 50 located between the first semiconductor chip 20 and the second semiconductor chip stack structure, and located between the first chip stack structure 301 and the second chip stack structure 302.

[0101] The adhesive film can bond the first semiconductor chip and the second semiconductor chip stack, as well as the first chip stack and the second chip stack, together, enhancing their adhesion and thus improving the robustness of the semiconductor packaging structure. Simultaneously, the adhesive film can adjust the distance between the second semiconductor chip stack and the first semiconductor chip, preventing an angle between the second substrate and the second conductive block, which could cause additional stress and damage to the second conductive block on the second semiconductor chip stack.

[0102] In one embodiment, the adhesion film comprises a die bond film.

[0103] When the adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0104] In this embodiment, the first adhesive film is connected to the first semiconductor chip and mainly serves to bond the chips together. The second adhesive film is connected to the second semiconductor chip stack structure and mainly serves to prevent chip warping. Since the second adhesive film has a high elastic modulus, warping will not occur during the packaging process. The first adhesive film has a low elastic modulus and will not affect the bonding force between the first semiconductor chip and the second semiconductor chip stack structure in subsequent processes.

[0105] In one embodiment, the first semiconductor chip 20 and the second semiconductor chip stack structure communicate wirelessly.

[0106] Specifically, for example, a first wireless coil (not shown) is provided in each second semiconductor chip of the second semiconductor chip stack structure, and a second wireless coil (not shown) is provided in the first semiconductor chip at a position corresponding to the first wireless coil. The first semiconductor chip and the second semiconductor chip stack structure communicate through the first wireless coil and the second wireless coil.

[0107] The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip, while reducing the number of TSVs and reducing the process difficulty.

[0108] In one embodiment, such as Figure 1As shown, the semiconductor packaging structure further includes: a plurality of through-silicon vias 311, the through-silicon vias 311 penetrating the second semiconductor chip 31 along a first direction; a plurality of fourth conductive bumps 312, located between two adjacent second semiconductor chips 31, and correspondingly connected to the through-silicon vias 311; and the second conductive bumps 32 correspondingly connected to the through-silicon vias 311 and the fourth conductive bumps 312.

[0109] In this embodiment, subsequent power signals and ground signals can be led to the second conductive bump via the through-silicon via and the fourth conductive bump.

[0110] In the second semiconductor chip stack structure, two adjacent second semiconductor chips are electrically connected through through-silicon vias and a fourth conductive block.

[0111] The second semiconductor chip stack structure is obtained by a hybrid bonding method, which results in lower resistance, better performance, and the stacked chip structure can be used as a whole, thereby improving the mechanical strength of the stack structure when placed vertically, while reducing the pressure on the chip.

[0112] The semiconductor package structure further includes a dielectric layer 60 located between two adjacent second semiconductor chips 31. By providing the dielectric layer, the two adjacent second semiconductor chips can be insulated and isolated, and the fourth conductive bumps are located within the dielectric layer, which reduces the possibility of coupling between adjacent fourth conductive bumps.

[0113] The dielectric layer 60 is made of an oxide, and in one specific embodiment, the dielectric layer 60 is made of SiO2.

[0114] In addition, in order to increase the thickness of the second semiconductor chip stack structure and thus enhance its mechanical strength, the outermost chip does not need to be thinned during the through-silicon via (TSV) fabrication process.

[0115] The material and structure of the second substrate 40 can be the same as those of the first substrate 10, so they will not be described in detail here.

[0116] The first chip stack structure 301 and the second chip stack structure 302 are respectively connected to a second substrate 40 and connected to the first substrate 10 through the second substrate 40.

[0117] In this embodiment, the first and second chip stack structures, with the second conductive bumps formed on one side, are powered by a second substrate. Compared to powering multiple second semiconductor chip stack structures from only one side, this better solves the voltage drop problem caused by a large number of stacked layers, thereby improving the performance of the second semiconductor chip stack structure. Furthermore, it ensures that the power supplies for the first and second chip stack structures are consistent, reducing the impact of power supply voltage drop on the chips.

[0118] In one embodiment, the signal line 41 includes a ground line 411 and a power line 412, and the second conductive bump 32 includes a first sub-conductive bump 321 and a second sub-conductive bump 322; the ground line 411 is electrically connected to the first sub-conductive bump 321, and the power line 412 is electrically connected to the second sub-conductive bump 322.

[0119] In this embodiment, the ground signals of the first chip stack structure 301 and the second chip stack structure 302 are led out to the ground line 411 by the first sub-conductive bump 321, and the power signals of the first chip stack structure 301 and the second chip stack structure 302 are led out to the power line 412 by the second sub-conductive bump 322. Then, the ground line 411 and the power line 412 are electrically connected to the first substrate 10 through the third conductive bump 42. Thus, the first substrate 10 supplies power to the first chip stack structure 301 and the second chip stack structure 302 through the third conductive bump 42, the ground line 411, and the power line 412.

[0120] The third conductive bump 42 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first chip stack structure 301 and the second chip stack structure 302 can interact with external devices through the substrate connection bump 12.

[0121] Figure 3 A side view of the second conductive bump along a first direction, provided in an embodiment of this disclosure.

[0122] like Figure 3 As shown, at least one first sub-conductive bump 321 is spaced between two adjacent second sub-conductive bumps 322, and the first sub-conductive bump 321 surrounds the second sub-conductive bump 322.

[0123] Figure 3 In this context, P (Power) is the second sub-conductive bump 322, and G (Ground) is the first sub-conductive bump 321.

[0124] The first sub-conductive bump 321 completely surrounds the second sub-conductive bump 322. Since the first sub-conductive bump 321 is connected to the ground signal and the second sub-conductive bump 322 is connected to the power signal, crosstalk between different power signals can be reduced and the power shielding can be enhanced.

[0125] In one embodiment, the semiconductor packaging structure further includes: an encapsulation compound structure 80 located on the first substrate 10; the encapsulation compound structure 80 at least encapsulates the first chip stack structure 301, the second chip stack structure 302, and the second substrate 40.

[0126] exist Figure 2 In the embodiment shown, the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20.

[0127] The encapsulation compound structure 80 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0128] By forming an encapsulation compound structure 80, and the material of the encapsulation compound structure 80 including a silicon-containing compound, the warpage problem of the second semiconductor chip stack structure can be reduced.

[0129] The semiconductor packaging structure further includes: a filling layer 70 located between the second semiconductor chip stack structure and the second substrate 40, and / or between the first semiconductor chip 20 and the first substrate 10.

[0130] In one embodiment, the filling layer 70 may also be located between the first substrate 10 and the second substrate 40.

[0131] For example, in one embodiment, such as Figure 1 As shown, when the first semiconductor chip 20 is located in the groove of the first substrate 10, the filling layer 70 may be located between the first chip stack structure 301 and the second chip stack structure 302 and the second substrate 40, and / or between the second substrate 40 and the first substrate 10.

[0132] In another embodiment, such as Figure 2 As shown, when the first semiconductor chip 20 is located above the first substrate 10, the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10, and / or between the second substrate 40 and the first substrate 10, and / or between the first chip stack structure 301 and the second chip stack structure 302 and the second substrate 40.

[0133] For a three-dimensional stacked second semiconductor chip structure, because its thickness along the first direction is relatively thin, the warpage of the second semiconductor chip stack structure is relatively high. When erected on the first semiconductor chip, the high warpage makes it difficult to solder the second semiconductor chip stack structure to the second substrate. Therefore, providing a filler layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip, can effectively reduce the impact caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or external forces, thereby increasing the reliability of the semiconductor packaging structure.

[0134] In one embodiment, the filler layer 70 is made of epoxy resin.

[0135] Epoxy resin can be applied to the edge of the chip using the capillary action principle, allowing it to penetrate to the bottom of the chip or substrate, and then cured by heating. Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can extend the lifespan of the chip.

[0136] In one embodiment, the Young's modulus of the filler layer 70 is greater than that of the encapsulated compound structure 80.

[0137] Young's modulus is a physical quantity that describes the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the resistance to deformation. However, if the Young's modulus is too low, it will be difficult to maintain the rigidity of the encapsulation structure, and problems such as deformation, warping, or breakage will easily occur. Therefore, in the embodiments of this disclosure, by forming a filler layer, and the Young's modulus of the filler layer is greater than that of the Young's modulus of the encapsulation compound structure, the filler layer can have sufficient strength to support the entire encapsulation structure, making the encapsulation structure less prone to deformation, warping, or breakage.

[0138] This disclosure also provides a method for fabricating a semiconductor packaging structure as described in any of the foregoing embodiments. Please refer to the appendix for details. Figure 4 As shown in the figure, the method includes the following steps:

[0139] Step 401: Form a second semiconductor chip stack structure, the second semiconductor chip stack structure including at least one first chip stack structure and at least one second chip stack structure, the first chip stack structure and the second chip stack structure including a plurality of second semiconductor chips stacked sequentially; form a plurality of second conductive bumps on one side of the first chip stack structure and the second chip stack structure along the stacking direction;

[0140] Step 402: Form the first semiconductor chip;

[0141] Step 403: The surfaces of the first chip stack structure and the second chip stack structure that are away from the second conductive bump along the stacking direction are arranged opposite each other, and the surfaces of the first chip stack structure and the second chip stack structure that are perpendicular to the stacking direction are connected to the surface of the first semiconductor chip.

[0142] Step 404: Provide a plurality of second substrates; the second substrates are located along the stacking direction on the side of the first chip stack structure and the second chip stack structure where the second conductive bumps are formed, and the signal lines in the second substrates are connected to the second conductive bumps;

[0143] Step 405: Provide a first substrate; connect the first semiconductor chip to the first substrate, and connect the second substrate to the first substrate.

[0144] The method for fabricating the semiconductor packaging structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0145] Figures 5a to 5g This is a schematic diagram of the device structure during the fabrication process of the semiconductor packaging structure provided in the embodiments of this disclosure.

[0146] First, see Figure 5a and Figure 5b Step 401 is executed to form a second semiconductor chip stack structure. The second semiconductor chip stack structure includes at least one first chip stack structure and at least one second chip stack structure. The first chip stack structure and the second chip stack structure include a plurality of second semiconductor chips 31 stacked sequentially. A plurality of second conductive bumps 32 are formed on one side of the first chip stack structure and the second chip stack structure along the stacking direction.

[0147] See Figure 5a The formation of the second semiconductor chip stack structure includes: forming a through-silicon via 311 through the second semiconductor chip 31 along the stacking direction;

[0148] A fourth conductive bump 312 is formed between two adjacent second semiconductor chips 31, and the fourth conductive bump 312 is correspondingly connected to the through silicon via 311;

[0149] Multiple second semiconductor chips 31 are connected by hybrid bonding to form a second semiconductor chip stack 300;

[0150] The second semiconductor chip stack 300 is formed into a plurality of second semiconductor chip stack structures.

[0151] In one embodiment, the second semiconductor chip stack structure includes DRAM chips.

[0152] In practice, the second semiconductor chip stack can be cut to form multiple second semiconductor chip stack structures.

[0153] The number of stacked second semiconductor chips 31 in the second semiconductor chip stacking structure can be multiple. In this embodiment of the disclosure, as... Figure 5b As shown, the number of stacked second semiconductor chips 31 in the second semiconductor chip stacking structure is five.

[0154] In one embodiment, such as Figure 5aAs shown, the second conductive bump 32 can be located on the bottommost second semiconductor chip 31 of the second semiconductor chip stack 300. In other embodiments, the second conductive bump 32 can also be located on the topmost second semiconductor chip 31 of the second semiconductor chip stack 300.

[0155] See Figure 5b The figure only shows a second semiconductor chip stack structure, but it can be understood that the first chip stack structure and the second chip stack structure have the same structural composition.

[0156] See also Figure 5b The method for fabricating the semiconductor package structure further includes forming a dielectric layer 60 between two adjacent second semiconductor chips 31. By providing the dielectric layer, the two adjacent second semiconductor chips can be insulated and isolated, and since the fourth conductive bump is located within the dielectric layer, the possibility of coupling between adjacent fourth conductive bumps can be reduced.

[0157] The dielectric layer 60 is made of an oxide, and in one specific embodiment, the dielectric layer 60 is made of SiO2.

[0158] In addition, in order to increase the thickness of the second semiconductor chip stack structure and thus enhance its mechanical strength, the outermost chip does not need to be thinned during the through-silicon via (TSV) fabrication process.

[0159] Next, see Figure 5c Steps 402 and 403 are executed to form the first semiconductor chip 20;

[0160] The surfaces of the first chip stack structure 301 and the second chip stack structure 302 that are away from the second conductive bump 32 along the stacking direction are arranged opposite each other, and the surfaces of the first chip stack structure 301 and the second chip stack structure 302 that are perpendicular to the stacking direction are connected to the surface of the first semiconductor chip 20.

[0161] In some embodiments, if the stacking direction is perpendicular to the plane of the first semiconductor chip, the first chip stacking structure 301 and the second chip stacking structure 302 are rotated 90 degrees and then connected to the first semiconductor chip.

[0162] In some other embodiments, if the stacking direction is parallel to the plane of the first semiconductor chip, then it is not necessary to rotate the first chip stacking structure 301 and the second chip stacking structure 302.

[0163] In one embodiment, the first semiconductor chip 20 includes a logic chip.

[0164] In one embodiment, the method further includes: forming a first conductive bump 21 on one side surface of the first semiconductor chip 20; the first chip stack structure 301 and the second chip stack structure 302 are connected to the surface of the first semiconductor chip 20 away from the first conductive bump 21.

[0165] In one embodiment, the method further includes: forming an adhesion film 50, connecting the second semiconductor chip stack structure 30 and the first semiconductor chip 20 through the adhesion film 50, and connecting the first chip stack structure 301 and the second chip stack structure 302.

[0166] The adhesive film can bond the first semiconductor chip and the second semiconductor chip stack, as well as the first chip stack and the second chip stack, together, enhancing their adhesion and thus improving the robustness of the semiconductor packaging structure. Simultaneously, the adhesive film can adjust the distance between the second semiconductor chip stack and the first semiconductor chip, preventing an angle between the second substrate and the second conductive block, which could cause additional stress and damage to the second conductive block on the second semiconductor chip stack.

[0167] In one embodiment, the adhesion film comprises a die bond film.

[0168] When the adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0169] In this embodiment, the first adhesive film is connected to the first semiconductor chip and mainly serves to bond the chips together. The second adhesive film is connected to the second semiconductor chip stack structure and mainly serves to prevent chip warping. Since the second adhesive film has a high elastic modulus, warping will not occur during the packaging process. The first adhesive film has a low elastic modulus and will not affect the bonding force between the first semiconductor chip and the second semiconductor chip stack structure in subsequent processes.

[0170] In one embodiment, the first semiconductor chip 20 and the second semiconductor chip stack structure communicate wirelessly.

[0171] Specifically, for example, a first wireless coil (not shown) is provided in each second semiconductor chip of the second semiconductor chip stack structure, and a second wireless coil (not shown) is provided in the first semiconductor chip at a position corresponding to the first wireless coil. The first semiconductor chip and the second semiconductor chip stack structure communicate through the first wireless coil and the second wireless coil.

[0172] The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip, while reducing the number of TSVs and reducing the process difficulty.

[0173] Next, see Figure 5d and Figure 5e Step 404 is executed, providing a plurality of second substrates 40; the second substrates 40 are located along the stacking direction on the side where the first chip stacking structure 301 and the second chip stacking structure 302 have formed second conductive bumps 32, and the signal lines 41 in the second substrates 40 are connected to the second conductive bumps 32.

[0174] See Figure 5d and Figure 5e The provision of the second substrate 40 includes:

[0175] The second substrate 40 is cut to form a third conductive bump 42 on the second substrate 40, so that the surface of the second substrate 40 on which the third conductive bump 42 is formed is flush with the surface of the second semiconductor chip stack structure near the first semiconductor chip 20.

[0176] Specifically, the second conductive bumps 32 of the first chip stack structure 301 and the second chip stack structure 302 are first soldered to a second substrate 40, and then the second substrate 40 is cut to a suitable size, for example, cut to be flush with the surface of the first chip stack structure 301 and the second chip stack structure 302 near the first semiconductor chip 20, and the signal line 41 is exposed. Then the remaining second substrate 40' is removed.

[0177] In this embodiment, the first and second chip stack structures, with the second conductive bumps formed on one side, are powered by a second substrate. Compared to powering multiple second semiconductor chip stack structures from only one side, this better solves the voltage drop problem caused by a large number of stacked layers, thereby improving the performance of the second semiconductor chip stack structure. Furthermore, it ensures that the power supplies for the first and second chip stack structures are consistent, reducing the impact of power supply voltage drop on the chips.

[0178] It should be noted that, in Figure 5d In the illustrated embodiment, the surface of the second substrate 40 where the third conductive bump 42 is formed is flush with the surfaces of the first chip stack structure 301 and the second chip stack structure 302 near the first semiconductor chip 20, forming a surface where... Figure 2In the embodiment of the semiconductor packaging structure shown, the surface of the second substrate 40 where the third conductive bump 42 is formed is flush with the surface of the first semiconductor chip 20 where the first conductive bump 21 is formed.

[0179] Next, see Figure 5e A third conductive bump 42 is formed on the surface of the second substrate 40 after cutting, which exposes the signal line 41, and the third conductive bump 42 is connected to the signal line 41.

[0180] In one embodiment, the signal line 41 includes a ground line 411 and a power line 412, and the second conductive bump 32 includes a first sub-conductive bump 321 and a second sub-conductive bump 322; the ground line 411 is electrically connected to the first sub-conductive bump 321, and the power line 412 is electrically connected to the second sub-conductive bump 322.

[0181] In this embodiment, the ground signals of the first chip stack structure 301 and the second chip stack structure 302 are led out to the ground line 411 by the first sub-conductive bump 321, and the power signals of the first chip stack structure 301 and the second chip stack structure 302 are led out to the power line 412 by the second sub-conductive bump 322. Then, the ground line 411 and the power line 412 are electrically connected to the first substrate 10 through the third conductive bump 42. Thus, the first substrate 10 supplies power to the first chip stack structure 301 and the second chip stack structure 302 through the third conductive bump 42, the ground line 411, and the power line 412.

[0182] The third conductive bump 42 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first chip stack structure 301 and the second chip stack structure 302 can interact with external devices through the substrate connection bump 12.

[0183] Figure 3 A side view of the second conductive bump along a first direction, provided in an embodiment of this disclosure.

[0184] like Figure 3 As shown, at least one first sub-conductive bump 321 is spaced between two adjacent second sub-conductive bumps 322, and the first sub-conductive bump 321 surrounds the second sub-conductive bump 322.

[0185] Figure 3 In this context, P (Power) is the second sub-conductive bump 322, and G (Ground) is the first sub-conductive bump 321.

[0186] The first sub-conductive bump 321 completely surrounds the second sub-conductive bump 322. Since the first sub-conductive bump 321 is connected to the ground signal and the second sub-conductive bump 322 is connected to the power signal, crosstalk between different power signals can be reduced and the power shielding can be enhanced.

[0187] Next, see Figure 5f Step 405 is executed, providing a first substrate 10; connecting the first semiconductor chip 20 to the first substrate 10; and connecting the second substrate 40 to the first substrate 10.

[0188] In one embodiment, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0189] The first substrate 10 may include a first substrate (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) respectively located on the upper and lower surfaces of the first substrate.

[0190] The first substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0191] The first upper insulating dielectric layer and the first lower insulating dielectric layer can be solder resist layers, for example, the materials of the first upper insulating dielectric layer and the first lower insulating dielectric layer can be green paint.

[0192] A substrate connection bump 12 is formed on the lower surface of the first substrate 10. The substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, receive at least one of control signals, power signals and ground signals for operating the first semiconductor chip and the second semiconductor chip from the external device, or receive data signals to be stored in the first semiconductor chip and the second semiconductor chip from the external device, and can also provide data in the first semiconductor chip and the second semiconductor chip to the external device.

[0193] The substrate connection bump 12 comprises a conductive material. In this embodiment, the substrate connection bump 12 is a solder ball. It is understood that the shape of the substrate connection bump provided in this embodiment is only one lower-level, feasible specific implementation and does not constitute a limitation on this disclosure. The substrate connection bump can also be other shapes and structures. The number, spacing, and position of the substrate connection bumps are not limited to any specific arrangement and can be modified in various ways.

[0194] In one embodiment, specifically, the first semiconductor chip 20 is connected to the first substrate 10 via a first conductive bump 21, and the second substrate 40 is connected to the first substrate 10 via a third conductive bump 42.

[0195] In one embodiment, such as Figure 5f As shown, a groove 101 is formed in the first substrate 10; the first semiconductor chip 20 is placed in the groove 101.

[0196] In this embodiment, placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor package structure.

[0197] In some other embodiments, such as Figure 2 As shown, the first semiconductor chip 20 is located on the first substrate 10, and the first conductive bump 21 is located between the first semiconductor chip 20 and the first substrate 10.

[0198] In this embodiment, the first semiconductor chip is located above the first substrate. As a result, the first substrate does not need to be provided with a groove, thus simplifying the process. Furthermore, there is a gap between the first semiconductor chip and the first substrate, which can increase the heat dissipation effect of the first semiconductor chip.

[0199] The first semiconductor chip 20 is electrically connected to the first substrate 10 through the first conductive bump 21. The first substrate 10 supplies power to the first semiconductor chip and exchanges signals via a wired connection.

[0200] The first conductive bump 21 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first semiconductor chip 20 can interact with external devices through the substrate connection bump 12.

[0201] The third conductive bump 42 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the second semiconductor chip stack structure can interact with external devices through the substrate connection bump 12.

[0202] Next, see Figure 5gThe method further includes: forming an encapsulation compound structure 80 on the first substrate 10, the encapsulation compound structure 80 at least encapsulating the first chip stack structure 301, the second chip stack structure 302 and the second substrate 40.

[0203] exist Figure 2 In the embodiment shown, the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20.

[0204] The encapsulation compound structure 80 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0205] By forming an encapsulation compound structure 80, and the material of the encapsulation compound structure 80 including a silicon-containing compound, the warpage problem of the second semiconductor chip stack structure can be reduced.

[0206] Next, the method further includes: forming a filling layer 70, the filling layer 70 being located between the second semiconductor chip stack structure and the second substrate 40, and / or between the first semiconductor chip 20 and the first substrate 10.

[0207] In one embodiment, the filling layer 70 may also be located between the first substrate 10 and the second substrate 40.

[0208] For example, in one embodiment, such as Figure 5g As shown, when the first semiconductor chip 20 is located in the groove of the first substrate 10, the filling layer 70 may be located between the first chip stack structure 301 and the second chip stack structure 302 and the second substrate 40, and / or between the second substrate 40 and the first substrate 10.

[0209] In another embodiment, such as Figure 2 As shown, when the first semiconductor chip 20 is located above the first substrate 10, the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10, and / or between the second substrate 40 and the first substrate 10, and / or between the first chip stack structure 301 and the second chip stack structure 302 and the second substrate 40.

[0210] For a three-dimensional stacked second semiconductor chip structure, because its thickness along the first direction is relatively thin, the warpage of the second semiconductor chip stack structure is relatively high. When erected on the first semiconductor chip, the high warpage makes it difficult to solder the second semiconductor chip stack structure to the second substrate. Therefore, providing a filler layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip, can effectively reduce the impact caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or external forces, thereby increasing the reliability of the semiconductor packaging structure.

[0211] In one embodiment, the filler layer 70 is made of epoxy resin.

[0212] Epoxy resin can be applied to the edge of the chip using the capillary action principle, allowing it to penetrate to the bottom of the chip or substrate, and then cured by heating. Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can extend the lifespan of the chip.

[0213] In one embodiment, the Young's modulus of the filler layer 70 is greater than that of the encapsulated compound structure 80.

[0214] Young's modulus is a physical quantity that describes the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the resistance to deformation. However, if the Young's modulus is too low, it will be difficult to maintain the rigidity of the encapsulation structure, and problems such as deformation, warping, or breakage will easily occur. Therefore, in the embodiments of this disclosure, by forming a filler layer, and the Young's modulus of the filler layer is greater than that of the Young's modulus of the encapsulation compound structure, the filler layer can have sufficient strength to support the entire encapsulation structure, making the encapsulation structure less prone to deformation, warping, or breakage.

[0215] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: First substrate; A first semiconductor chip is connected to the first substrate; The second semiconductor chip stacking structure includes at least one first chip stacking structure and at least one second chip stacking structure, wherein the first chip stacking structure and the second chip stacking structure are arranged side by side on the first semiconductor chip along a first direction. The first chip stack structure and the second chip stack structure include a plurality of second semiconductor chips stacked sequentially along a first direction; the first chip stack structure and the second chip stack structure each have a plurality of second conductive bumps formed on the side away from each other along the first direction; wherein, the first direction is a direction parallel to the plane of the first substrate; Multiple second substrates, signal lines within the second substrates are connected to the second conductive bumps; the second substrates are connected to the first substrate along a direction perpendicular to the plane of the first substrate; The first semiconductor chip is located on the first substrate, and the first semiconductor chip is connected to the first substrate through a first conductive bump. The second substrate is connected to the first substrate through a third conductive bump.

2. The semiconductor packaging structure according to claim 1, characterized in that: The first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

3. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: An adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, and between the first chip stack structure and the second chip stack structure.

4. The semiconductor packaging structure according to claim 3, characterized in that, The adhesive film includes a first adhesive film and a second adhesive film located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

5. The semiconductor packaging structure according to claim 1, characterized in that, The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

6. The semiconductor packaging structure according to claim 1, characterized in that, A groove is formed in the first substrate, the first semiconductor chip is located in the groove, the first semiconductor chip is connected to the first substrate through a first conductive bump, and the second substrate is connected to the first substrate through a third conductive bump.

7. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: Multiple through-silicon vias, wherein the through-silicon vias penetrate the second semiconductor chip along a first direction; Multiple fourth conductive bumps are located between two adjacent second semiconductor chips and are connected to the corresponding through-silicon vias; The second conductive bump is connected to the through silicon via and the fourth conductive bump.

8. The semiconductor packaging structure according to claim 1, characterized in that, The signal line includes a ground line and a power line, and the second conductive bump includes a first sub-conductive bump and a second sub-conductive bump; The grounding wire is electrically connected to the first sub-conductive bump, and the power supply wire is electrically connected to the second sub-conductive bump.

9. The semiconductor packaging structure according to claim 8, characterized in that, There is at least one first sub-conductive bump between two adjacent second sub-conductive bumps, and the first sub-conductive bump surrounds the second sub-conductive bump.

10. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A filling layer is located between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

11. The semiconductor packaging structure according to claim 10, characterized in that, Also includes: An encapsulated compound structure is located on the first substrate; The encapsulation compound structure at least encapsulates the second semiconductor chip stack structure and the second substrate; The Young's modulus of the filling layer is greater than that of the Young's modulus of the encapsulated compound structure.

12. A method for fabricating a semiconductor packaging structure as described in any one of claims 1-11, characterized in that, include: A second semiconductor chip stack structure is formed, the second semiconductor chip stack structure includes at least one first chip stack structure and at least one second chip stack structure, the first chip stack structure and the second chip stack structure include a plurality of second semiconductor chips stacked sequentially; Multiple second conductive bumps are formed on one side of the first chip stack structure and the second chip stack structure along the stacking direction; Forming the first semiconductor chip; The surfaces of the first chip stack structure and the second chip stack structure that are away from the second conductive bump along the stacking direction are arranged opposite to each other, and the surfaces of the first chip stack structure and the second chip stack structure that are perpendicular to the stacking direction are connected to the surface of the first semiconductor chip. Provide multiple second substrates; The second substrate is located on the side of the first chip stack structure and the second chip stack structure where the second conductive bump is formed along the stacking direction, and the signal line in the second substrate is connected to the second conductive bump; Provide a first substrate; The first semiconductor chip is connected to the first substrate, and the second substrate is connected to the first substrate.

13. The method according to claim 12, characterized in that, The formation of the second semiconductor chip stack structure includes: Along the stacking direction, a through-silicon via is formed, penetrating the second semiconductor chip; A fourth conductive bump is formed between two adjacent second semiconductor chips, and the fourth conductive bump is connected to the through silicon via accordingly; Multiple second semiconductor chips are connected by hybrid bonding to form a second semiconductor chip stack; The second semiconductor chip stack is formed into a plurality of second semiconductor chip stack structures.

14. The method according to claim 12, characterized in that, The provision of the second substrate includes: The second substrate is cut to form a third conductive bump, such that the surface of the second substrate with the third conductive bump is flush with the surface of the second semiconductor chip stack structure near the first semiconductor chip.

15. The method according to claim 12, characterized in that, A groove is formed within the first substrate; The first semiconductor chip is placed in the groove.

16. The method according to claim 12, characterized in that, Also includes: An adhesion film is formed to connect the second semiconductor chip stack structure and the first semiconductor chip, and to connect the first chip stack structure and the second chip stack structure.

17. The method according to claim 12, characterized in that, The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

18. The method according to claim 12, characterized in that, Also includes: A filling layer is formed between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

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