A semiconductor package structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor packaging structure and a preparation method thereof. The semiconductor packaging structure comprises a first substrate, a first semiconductor chip connected with the first substrate, a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure comprising a plurality of second semiconductor chips stacked in a first direction, a first lead wire formed on an outermost second semiconductor chip of the second semiconductor chip stack structure in the first direction, wherein the first direction is parallel to the plane of the first substrate, and a second substrate, a signal line in the second substrate connected with the first lead wire, and the second substrate connected with the first substrate in a direction perpendicular to the plane of the first substrate.

Description

Technical Field

[0001] This disclosure relates to the field of three-dimensional fabrication technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] HBM (High Bandwidth Memory) is a high-performance DRAM memory based on 3D stacking technology. Compared with traditional memory technologies, HBM memory has higher bandwidth, more I / O, lower power consumption, and smaller size, and can be applied to high-performance computing, supercomputers, large data centers, artificial intelligence / deep learning, cloud computing and other fields.

[0003] HBM memory technology primarily evolved to meet the demands of processor computing scale. In the early days, the requirements for computer data processing were not high, processor architectures had fewer layers, smaller computing scales, and lower computing power. Later, with the development of technologies such as AI, the requirements for processors became increasingly demanding. As models became deeper, the computing power requirements increased accordingly, leading to bandwidth bottlenecks, i.e., I / O problems. This was addressed by increasing on-chip cache and optimizing scheduling models to increase data reuse. However, with the popularization of AI and other technologies and the increase in the number of users, cloud AI processing requires multi-user, high-throughput, low-latency, and high-density deployment. The surge in computing units exacerbated the I / O bottleneck. At this point, on-chip HBM memory made it possible to completely integrate AI / deep learning onto the chip. While increasing integration, it also freed bandwidth from being limited by the number of interconnects on the chip pins, thus solving the bandwidth and computing power bottlenecks to some extent.

[0004] However, as the integration requirements of HBM memory increase, the number of chip stacking layers increases, and the technical challenges also increase. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor packaging structure and a method for preparing the same.

[0006] According to a first aspect of the present disclosure, a semiconductor packaging structure is provided, comprising:

[0007] First substrate;

[0008] A first semiconductor chip is connected to the first substrate;

[0009] A second semiconductor chip stack structure is located on the first semiconductor chip. The second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked sequentially along a first direction. A first lead is formed on the outermost second semiconductor chip along the first direction. The first direction is a direction parallel to the plane of the first substrate.

[0010] The second substrate has signal lines connected to the first lead; the second substrate is connected to the first substrate along a direction perpendicular to the plane of the first substrate.

[0011] In some embodiments, the first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

[0012] In some embodiments, the second semiconductor chip stack structure includes at least one first chip stack structure and at least one second chip stack structure, wherein the first chip stack structure and the second chip stack structure are arranged side by side on the first semiconductor chip along a first direction, and the surfaces of the first chip stack structure that are away from the first lead along the first direction are disposed opposite to each other.

[0013] The first chip stack structure and the second chip stack structure are respectively connected to a second substrate.

[0014] In some embodiments, it also includes:

[0015] An adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, and / or between the first chip stack structure and the second chip stack structure.

[0016] In some embodiments, the adhesive film includes a first adhesive film and a second adhesive film located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0017] In some embodiments, the first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

[0018] In some embodiments, a groove is formed in the first substrate, the first semiconductor chip is located in the groove, the first semiconductor chip is connected to the first substrate through a first conductive bump, and the second substrate is connected to the first substrate through a second conductive bump.

[0019] In some embodiments, the first semiconductor chip is located on the first substrate, the first semiconductor chip is connected to the first substrate via a first conductive bump, and the second substrate is connected to the first substrate via a second conductive bump.

[0020] In some embodiments, it also includes:

[0021] Multiple through-silicon vias, wherein the through-silicon vias penetrate the second semiconductor chip along a first direction;

[0022] Multiple third conductive bumps are located between two adjacent second semiconductor chips and are connected to the vias.

[0023] The second semiconductor chip stack structure is connected by hybrid bonding.

[0024] In some embodiments, it also includes:

[0025] A connector, located on the outermost surface of the second semiconductor chip along the first direction of the second semiconductor chip stack structure, connects a plurality of through-silicon vias of the second semiconductor chip stack structure to a first lead.

[0026] In some embodiments, the signal line includes a ground line and a power line, and the first lead includes a first sub-lead and a second sub-lead;

[0027] The grounding wire is electrically connected to the first sub-lead, and the power supply wire is electrically connected to the second sub-lead.

[0028] In some embodiments, a first sub-lead is spaced apart between two adjacent second sub-leads.

[0029] In some embodiments, it also includes:

[0030] A filling layer is located between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

[0031] In some embodiments, it also includes:

[0032] An encapsulation compound structure is located on the first substrate; the encapsulation compound structure at least encapsulates the second semiconductor chip stack structure and the second substrate.

[0033] The Young's modulus of the filling layer is greater than that of the Young's modulus of the encapsulated compound structure.

[0034] According to a second aspect of the present disclosure, a method for fabricating a semiconductor packaging structure as described in any of the above embodiments is provided, comprising:

[0035] A second semiconductor chip stack structure is formed, the second semiconductor chip stack structure comprising a plurality of second semiconductor chips stacked sequentially;

[0036] Forming the first semiconductor chip;

[0037] The surface of the second semiconductor chip stack structure perpendicular to the stacking direction is connected to the surface of the first semiconductor chip.

[0038] A second substrate is provided; the second substrate is located along the stacking direction on the side of the second semiconductor chip stack structure on which the first lead is formed, and the signal line in the second substrate is connected to the first lead;

[0039] A first substrate is provided; the first semiconductor chip is connected to the first substrate; and the second substrate is connected to the first substrate.

[0040] In some embodiments, forming the second semiconductor chip stack structure includes:

[0041] Form at least one first chip stack structure and at least one second chip stack structure;

[0042] The method further includes:

[0043] After the first semiconductor chip is formed, the first chip stack structure and the second chip stack structure are arranged side by side on the first semiconductor chip along the stacking direction, and the surfaces away from the first lead along the stacking direction are arranged opposite each other.

[0044] After providing the second substrate, the first chip stack structure and the second chip stack structure are respectively connected to a second substrate.

[0045] In some embodiments, a groove is formed within the first substrate;

[0046] The first semiconductor chip is placed in the groove.

[0047] In some embodiments, it also includes:

[0048] An adhesion film is formed to connect the second semiconductor chip stack structure and the first semiconductor chip through the adhesion film, and / or to connect the first chip stack structure and the second chip stack structure.

[0049] In some embodiments, the first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

[0050] In some embodiments, it also includes:

[0051] A filling layer is formed between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

[0052] In this embodiment, multiple second semiconductor chips in the second semiconductor chip stack structure are vertically stacked (V-Stack) side-by-side on a first semiconductor chip. This allows for wireless communication between the first and second semiconductor chips, effectively solving the communication difficulties that arise when multiple second semiconductor chips are sequentially stacked (P-Stack) on a first semiconductor chip as the number of stacked layers increases. Simultaneously, the second semiconductor chip stack structure is connected to a second substrate via a first lead, and then to a first substrate. The first semiconductor chip is connected to the first substrate via a first conductive bump. Thus, the first substrate provides power to both the first and second semiconductor chip stack structures via a wired connection and simultaneously exchanges signals with the first semiconductor chip, resulting in high reliability. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure;

[0055] Figure 2 This is a schematic diagram of a semiconductor packaging structure provided in another embodiment of the present disclosure;

[0056] Figure 3 This is a schematic diagram of a semiconductor packaging structure provided in yet another embodiment of the present disclosure;

[0057] Figure 4 A top view of a semiconductor packaging structure provided in an embodiment of this disclosure;

[0058] Figure 5 A schematic flowchart illustrating the method for fabricating a semiconductor packaging structure according to an embodiment of this disclosure;

[0059] Figures 6a to 6g This is a schematic diagram of the device structure during the fabrication process of the semiconductor packaging structure provided in the embodiments of this disclosure.

[0060] Explanation of reference numerals in the attached figures:

[0061] 10-First substrate; 11-Lead wire; 12-Substrate connection bump; 101-Groove;

[0062] 20 - First semiconductor chip; 21 - First conductive bump;

[0063] 30-Second semiconductor chip stack structure; 301-First chip stack structure; 302-Second chip stack structure; 300-Second semiconductor chip stack body; 31-Second semiconductor chip; 311-Through silicon via; 312-Third conductive bump; 32-First lead; 321-First sub-lead; 322-Second sub-lead; 33-Connector; 34-First pad; 341-First sub-pad; 342-Second sub-pad;

[0064] 40-Second substrate; 41-Signal line; 411-Ground line; 412-Power line; 42-Second conductive bump; 43-Second pad; 431-Third sub-pad; 432-Fourth sub-pad; 40'-Remaining second substrate;

[0065] 50 - Adhesive film;

[0066] 60 - Dielectric layer;

[0067] 70 - Filler layer;

[0068] 80-Encapsulated compound structure. Detailed Implementation

[0069] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0070] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0071] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0072] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0073] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0076] HBM technology is a major representative of the evolution of DRAM from traditional 2D to stereoscopic 3D, paving the way for DRAM 3D. It primarily utilizes Through Silicon Via (TSV) technology for chip stacking to increase throughput and overcome the bandwidth limitations within a single package. Several DRAM dies are vertically stacked, with the dies connected using TVS technology. From a technical perspective, HBM makes full use of space and reduces area, perfectly aligning with the semiconductor industry's trend towards miniaturization and integration. Furthermore, it breaks through the bottlenecks of memory capacity and bandwidth, and is considered a next-generation DRAM solution.

[0077] In 3D IC product packaging, DRAM chips are generally stacked on logic dies using a parallel stacking (P-Stack) method. As integration requirements increase, the number of DRAM chip stacking layers increases, and the technical challenges also increase. For example, the communication distance between the DRAM chips stacked on the upper layers and the logic dies stacked on the lower layers becomes longer and longer, and the communication delay between different layers of DRAM chips and logic dies will vary due to the different distances; the number of TSV vias used for communication will increase proportionally, sacrificing wafer area.

[0078] Based on this, the present disclosure provides a semiconductor packaging structure. Figure 1 This is a schematic diagram of a semiconductor packaging structure provided in an embodiment of the present disclosure.

[0079] See Figure 1 The semiconductor packaging structure includes:

[0080] First substrate 10;

[0081] The first semiconductor chip 20 is connected to the first substrate 10;

[0082] A second semiconductor chip stack structure 30 is located on the first semiconductor chip 20. The second semiconductor chip stack structure 30 includes a plurality of second semiconductor chips 31 stacked sequentially along a first direction. A first lead 32 is formed on the outermost second semiconductor chip 20 along the first direction. The first direction is a direction parallel to the plane of the first substrate 10.

[0083] The second substrate 40 has a signal line 41 connected to the first lead 32; the second substrate 40 is connected to the first substrate 10 along a direction perpendicular to the plane of the first substrate 10.

[0084] In this embodiment, multiple second semiconductor chips in the second semiconductor chip stack structure are vertically stacked (V-Stack) side-by-side on a first semiconductor chip. This allows for wireless communication between the first and second semiconductor chips, effectively solving the communication difficulties that arise when multiple second semiconductor chips are sequentially stacked (P-Stack) on a first semiconductor chip as the number of stacked layers increases. Simultaneously, the second semiconductor chip stack structure is connected to a second substrate via a first lead, and then to a first substrate. The first semiconductor chip is connected to the first substrate via a first conductive bump. Thus, the first substrate provides power to both the first and second semiconductor chip stack structures via a wired connection and simultaneously exchanges signals with the first semiconductor chip, resulting in high reliability.

[0085] In one embodiment, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0086] The first substrate 10 may include a first substrate (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) located on the upper and lower surfaces of the first substrate, respectively.

[0087] The first substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0088] The first upper insulating dielectric layer and the first lower insulating dielectric layer can be solder resist layers, for example, the materials of the first upper insulating dielectric layer and the first lower insulating dielectric layer can be green paint.

[0089] A substrate connection bump 12 is formed on the lower surface of the first substrate 10. The substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, and can receive at least one of control signals, power signals and ground signals for operating the first semiconductor chip and the second semiconductor chip from the external device, or can receive data signals to be stored in the first semiconductor chip and the second semiconductor chip from the external device, and can also provide the data in the first semiconductor chip and the second semiconductor chip to the external device.

[0090] The substrate connection bump 12 comprises a conductive material. In this embodiment, the substrate connection bump 12 is a solder ball. It is understood that the shape of the substrate connection bump provided in this embodiment is only one lower-level, feasible specific implementation and does not constitute a limitation on this disclosure. The substrate connection bump can also be other shapes and structures. The number, spacing, and position of the substrate connection bumps are not limited to any specific arrangement and can be modified in various ways.

[0091] In one embodiment, a first conductive bump 21 is formed on one side of the first semiconductor chip 20.

[0092] The material of the first conductive bump 21 may include at least one of aluminum, copper, nickel, tungsten, platinum and gold.

[0093] The first semiconductor chip 20 is electrically connected to the first substrate 10 through the first conductive bump 21. The first substrate 10 supplies power to the first semiconductor chip and exchanges signals via a wired connection.

[0094] The first conductive bump 21 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first semiconductor chip 20 can interact with external devices through the substrate connection bump 12.

[0095] In one embodiment, such as Figure 1 As shown, a groove 101 is formed in the first substrate 10, the first semiconductor chip 20 is located in the groove 101, the first semiconductor chip 20 is connected to the first substrate 10 through a first conductive bump 21, and the second substrate 40 is connected to the first substrate 10 through a second conductive bump 42.

[0096] In this embodiment, placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor package structure.

[0097] In another embodiment, such as Figure 2As shown, the first semiconductor chip 20 is located on the first substrate 10, and the first semiconductor chip 20 is connected to the first substrate 10 through the first conductive bump 21. The second substrate 40 is connected to the first substrate 10 through the second conductive bump 42.

[0098] In this embodiment, the first semiconductor chip is located above the first substrate. As a result, the first substrate does not need to be provided with a groove, thus simplifying the process. Furthermore, the gap between the first semiconductor chip and the first substrate can increase the heat dissipation effect of the first semiconductor chip.

[0099] The number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 can be multiple. In this embodiment of the disclosure, as... Figure 1 As shown, the number of stacked second semiconductor chips 31 in the second semiconductor chip stacking structure 30 is five.

[0100] In one embodiment, the first semiconductor chip 20 includes a logic chip, and the second semiconductor chip stack structure 30 includes a DRAM chip.

[0101] In one embodiment, such as Figure 3 As shown, the second semiconductor chip stack structure includes at least one first chip stack structure 301 and at least one second chip stack structure 302. The first chip stack structure 301 and the second chip stack structure 302 are arranged side by side on the first semiconductor chip 20 along a first direction, and are disposed opposite to each other on the surfaces away from the first lead 32 along the first direction.

[0102] The first chip stack structure 301 and the second chip stack structure 302 are respectively connected to a second substrate 40.

[0103] In this embodiment, the first chip stack structure and the second chip stack structure, with the first leads formed on one side, are respectively powered by a second substrate. Compared to powering multiple second semiconductor chip stack structures from only one side, this better solves the voltage drop problem caused by a large number of stacked layers, thereby improving the performance of the second semiconductor chip stack structure. Furthermore, it ensures that the power supplies for the first and second chip stack structures are consistent, reducing the impact of power supply voltage drop on the chips.

[0104] In one embodiment, the semiconductor packaging structure further includes: an adhesion film 50 located between the first semiconductor chip 20 and the second semiconductor chip stack structure 30, and / or located between the first chip stack structure 301 and the second chip stack structure 302.

[0105] The adhesive film can bond the first semiconductor chip and the second semiconductor chip stack structure, as well as the first chip stack structure and the second chip stack structure, to enhance their adhesion and thus improve the robustness of the semiconductor packaging structure.

[0106] In one embodiment, the adhesion film 50 includes a die bond film.

[0107] In one embodiment, when the adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0108] In this embodiment, the first adhesive film is connected to the first semiconductor chip and mainly serves to bond the chips together. The second adhesive film is connected to the second semiconductor chip stack structure and mainly serves to prevent chip warping. Since the second adhesive film has a high elastic modulus, warping will not occur during the packaging process. The first adhesive film has a low elastic modulus and will not affect the bonding force between the first semiconductor chip and the second semiconductor chip stack structure in subsequent processes.

[0109] In one embodiment, the first semiconductor chip 20 and the second semiconductor chip stack structure 30 communicate wirelessly. For example, a wireless coil (not shown) is provided in each DRAM in the second semiconductor chip stack structure 30, and correspondingly, a corresponding wireless coil is provided at the corresponding position of the aforementioned coil on the first semiconductor chip 20.

[0110] The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip, while reducing the number of TSVs and reducing the process difficulty.

[0111] In one embodiment, the semiconductor packaging structure further includes: a plurality of through-silicon vias 311, the through-silicon vias 311 penetrating the second semiconductor chip 31 along a first direction; a plurality of third conductive bumps 312 located between two adjacent second semiconductor chips 31 and correspondingly connected to the through-silicon vias 311; and the second semiconductor chip stack structure 30 connected by hybrid bonding.

[0112] The second semiconductor chip stack structure is obtained by a hybrid bonding method. In this way, the stacked chip structure can be used as a whole, thereby improving the mechanical strength of the stack structure when placed vertically, while reducing the pressure on the chip.

[0113] The semiconductor package structure further includes a dielectric layer 60 located between two adjacent second semiconductor chips 31. By providing the dielectric layer, the two adjacent second semiconductor chips can be insulated and isolated, and the third conductive bumps are located within the dielectric layer, which can reduce the possibility of coupling between adjacent third conductive bumps.

[0114] The dielectric layer 60 is made of an oxide, and in one specific embodiment, the dielectric layer 60 is made of SiO2.

[0115] In addition, in order to increase the thickness of the second semiconductor chip stack structure and thus enhance its mechanical strength, the outermost chip does not need to be thinned during the through-silicon via (TSV) fabrication process.

[0116] In one embodiment, the semiconductor packaging structure further includes a connector 33 located on the surface of the outermost second semiconductor chip 31 along a first direction of the second semiconductor chip stack structure 30, connecting a plurality of through-silicon vias 311 of the second semiconductor chip stack structure 30 to a first lead 32.

[0117] The material and structure of the second substrate 40 can be the same as those of the first substrate 10, so they will not be described in detail here.

[0118] Figure 4 This is a top view of a semiconductor package structure provided in an embodiment of this disclosure.

[0119] In one embodiment, such as Figure 1 and Figure 4 As shown, the signal line 41 includes a ground line 411 and a power line 412, and the first lead 32 includes a first sub-lead 321 and a second sub-lead 322.

[0120] The grounding wire 411 is electrically connected to the first sub-lead 321, and the power supply wire 412 is electrically connected to the second sub-lead 322.

[0121] In this embodiment, the ground signal of the second semiconductor chip stack structure 30 is led out to the ground line 411 through the first sub-lead 321, and the power signal of the second semiconductor chip stack structure 30 is led out to the power line 412 through the second sub-lead 322. Then, the ground line 411 and the power line 412 are electrically connected to the first substrate 10 through the second conductive bump 42. Thus, the first substrate 10 supplies power to the second semiconductor chip stack structure 30 through the second conductive bump 42, the ground line 411, and the power line 412.

[0122] like Figure 4As shown, a first sub-lead 321 is spaced between two adjacent second sub-leads 322. Because the first sub-lead 321 is connected to the ground signal and the second sub-lead 322 is connected to the power signal, crosstalk between different power signals can be reduced and the power shielding can be enhanced.

[0123] Specifically, a first pad 34 is formed on the second semiconductor chip stack structure 30. The first pad includes a first sub-pad 341 and a second sub-pad 342. A second pad 43 is formed on the second substrate 40. The second pad 43 includes a third sub-pad 431 and a fourth sub-pad 432. The first sub-pad 341 is connected to the third sub-pad 431 through a first sub-lead 321, and the second sub-pad 342 is connected to the fourth sub-pad 432 through a second sub-lead 322.

[0124] In one embodiment, the second conductive bump 42 is also connected to the substrate connection bump 12 via a lead 11 in the first substrate 10, so that the second semiconductor chip stack structure 30 can interact with external devices through the substrate connection bump 12.

[0125] In one embodiment, the semiconductor packaging structure further includes: an encapsulation compound structure 80 located on the first substrate 10; the encapsulation compound structure 80 at least encapsulates the second semiconductor chip stack structure 30 and the second substrate 40.

[0126] exist Figure 2 In the embodiment shown, the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20.

[0127] The encapsulation compound structure 80 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0128] By forming an encapsulation compound structure 80, and the material of the encapsulation compound structure 80 including a silicon-containing compound, the warpage problem of the second semiconductor chip stack structure 30 can be reduced.

[0129] The semiconductor packaging structure further includes: a filling layer 70 located between the second semiconductor chip stack structure 30 and the second substrate 40, and / or between the first semiconductor chip 20 and the first substrate 10.

[0130] In some embodiments, the filling layer 70 may also be located between the second substrate 40 and the first substrate 10.

[0131] For example, in one embodiment, such as Figure 1As shown, when the first semiconductor chip 20 is located in the groove of the first substrate 10, the filling layer 70 may be located between the second semiconductor chip stack structure 30 and the second substrate 40, and / or between the second substrate 40 and the first substrate 10.

[0132] In another embodiment, such as Figure 2 As shown, when the first semiconductor chip 20 is located above the first substrate 10, the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10, and / or between the second substrate 40 and the first substrate 10, and / or between the second semiconductor chip stack structure 30 and the second substrate 40.

[0133] For a three-dimensional stacked second semiconductor chip structure, because its thickness along the first direction is relatively thin, the warpage of the second semiconductor chip stack structure is relatively high. When erected on the first semiconductor chip, the high warpage makes it difficult to solder the second semiconductor chip stack structure to the second substrate. Therefore, providing a filler layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip, can effectively reduce the impact caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or external forces, thereby increasing the reliability of the semiconductor packaging structure.

[0134] In one embodiment, the filler layer 70 is made of epoxy resin.

[0135] Epoxy resin can be applied to the edge of the chip using the capillary action principle, allowing it to penetrate to the bottom of the chip or substrate, and then cured by heating. Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can extend the lifespan of the chip.

[0136] In one embodiment, the Young's modulus of the filler layer 70 is greater than that of the encapsulated compound structure 80.

[0137] Young's modulus is a physical quantity that describes the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the resistance to deformation. However, if the Young's modulus is too low, it will be difficult to maintain the rigidity of the encapsulation structure, and problems such as deformation, warping, or breakage will easily occur. Therefore, in the embodiments of this disclosure, by forming a filler layer, and the Young's modulus of the filler layer is greater than that of the Young's modulus of the encapsulation compound structure, the filler layer can have sufficient strength to support the entire encapsulation structure, making the encapsulation structure less prone to deformation, warping, or breakage.

[0138] This disclosure also provides a method for fabricating a semiconductor packaging structure as described in any of the foregoing embodiments. Please refer to the appendix for details. Figure 5As shown in the figure, the method includes the following steps:

[0139] Step 501: Form a second semiconductor chip stack structure, the second semiconductor chip stack structure comprising a plurality of second semiconductor chips stacked sequentially;

[0140] Step 502: Form the first semiconductor chip;

[0141] Step 503: Connect the surface of the second semiconductor chip stack structure perpendicular to the stacking direction to the surface of the first semiconductor chip;

[0142] Step 504: Provide a second substrate; the second substrate is located along the stacking direction on the side of the second semiconductor chip stack structure where the first lead is formed, and the signal line in the second substrate is connected to the first lead;

[0143] Step 505: Provide a first substrate; connect the first semiconductor chip to the first substrate, and connect the second substrate to the first substrate.

[0144] The method for fabricating the semiconductor packaging structure provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0145] Figures 6a to 6g This is a schematic diagram of the device structure during the fabrication process of the semiconductor packaging structure provided in the embodiments of this disclosure.

[0146] First, see Figure 6a and Figure 6b Step 501 is executed to form a second semiconductor chip stack structure 30, which includes a plurality of second semiconductor chips 31 stacked sequentially.

[0147] See Figure 6a The formation of the second semiconductor chip stack structure 30 includes: connecting a plurality of second semiconductor chips 31 by hybrid bonding to form a second semiconductor chip stack body 300;

[0148] The second semiconductor chip stack 300 is cut to form multiple second semiconductor chip stack structures 30.

[0149] In one embodiment, the second semiconductor chip stack structure 30 includes a DRAM chip.

[0150] The number of stacked second semiconductor chips 31 in the second semiconductor chip stack structure 30 can be multiple. In this embodiment of the disclosure, as... Figure 6b As shown, the number of stacked second semiconductor chips 31 in the second semiconductor chip stacking structure 30 is five.

[0151] See Figure 6b The method for fabricating the semiconductor packaging structure further includes: forming a plurality of through-silicon vias 311, wherein the through-silicon vias 311 penetrate the second semiconductor chip 31 along the stacking direction;

[0152] A plurality of third conductive bumps 312 are formed between two adjacent second semiconductor chips 31, and the third conductive bumps 312 are correspondingly connected to the through silicon vias 311.

[0153] In the second semiconductor chip stack structure, two adjacent second semiconductor chips are connected by a hybrid bonding connection through silicon vias and a third conductive block.

[0154] The method for fabricating the semiconductor package structure further includes forming a dielectric layer 60 between two adjacent second semiconductor chips 31. By providing the dielectric layer, the two adjacent second semiconductor chips can be insulated and isolated, and since the third conductive bumps are located within the dielectric layer, the possibility of coupling between adjacent third conductive bumps can be reduced.

[0155] The dielectric layer 60 is made of an oxide, and in one specific embodiment, the dielectric layer 60 is made of SiO2.

[0156] In addition, in order to increase the thickness of the second semiconductor chip stack structure and thus enhance its mechanical strength, the outermost chip does not need to be thinned during the through-silicon via (TSV) fabrication process.

[0157] In one embodiment, the method further includes forming a connector 33 on the outermost surface of the second semiconductor chip 31 along the stacking direction of the second semiconductor chip stack structure 30, the connector 33 connecting a plurality of through-silicon vias 311 of the second semiconductor chip stack structure 30 to a first lead 32.

[0158] In some embodiments, such as Figure 6b As shown, the connector 33 can be located on the bottommost second semiconductor chip 31 of the second semiconductor chip stack structure 30. In other embodiments, the connector 33 can also be located on the topmost second semiconductor chip 31 of the second semiconductor chip stack structure 30.

[0159] Next, see Figure 6c Steps 502 and 503 are executed to form the first semiconductor chip 20;

[0160] The surface of the second semiconductor chip stack structure 30 perpendicular to the stacking direction is connected to the surface of the first semiconductor chip 20.

[0161] In some embodiments, if the stacking direction is perpendicular to the plane of the first semiconductor chip, the second semiconductor chip stacking structure 30 is rotated 90 degrees and then connected to the first semiconductor chip.

[0162] In some other embodiments, if the stacking direction is parallel to the plane of the first semiconductor chip, then it is not necessary to rotate the second semiconductor chip stacking structure 30.

[0163] In one embodiment, the first semiconductor chip 20 includes a logic chip.

[0164] In one embodiment, the method further includes: forming a first conductive bump 21 on one side surface of the first semiconductor chip 20; and connecting the second semiconductor chip stack structure 30 to the surface of the first semiconductor chip 20 away from the first conductive bump 21.

[0165] In one embodiment, the method further includes: forming an adhesion film 50 to connect the second semiconductor chip stack structure 30 and the first semiconductor chip 20 through the adhesion film 50.

[0166] The adhesive film 50 can bond the first semiconductor chip 20 and the second semiconductor chip stack structure 30 together, enhancing their adhesion and thus improving the robustness of the semiconductor packaging structure.

[0167] In one embodiment, the adhesion film 50 includes a die bond film.

[0168] In one embodiment, when the adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, the adhesive film includes a first adhesive film and a second adhesive film (not shown) located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

[0169] In this embodiment, the first adhesive film is connected to the first semiconductor chip and mainly serves to bond the chips together. The second adhesive film is connected to the second semiconductor chip stack structure and mainly serves to prevent chip warping. Since the second adhesive film has a high elastic modulus, warping will not occur during the packaging process. The first adhesive film has a low elastic modulus and will not affect the bonding force between the first semiconductor chip and the second semiconductor chip stack structure in subsequent processes.

[0170] In one embodiment, the first semiconductor chip 20 and the second semiconductor chip stack structure 30 communicate wirelessly. For example, a wireless coil (not shown) is provided in each DRAM in the second semiconductor chip stack structure 30, and correspondingly, a corresponding wireless coil is provided at the position of the aforementioned coil on the first semiconductor chip 20.

[0171] The first semiconductor chip and the second semiconductor chip stacked structure communicate wirelessly, which can effectively solve the communication difficulties caused by the increase in the number of stacked layers of the second semiconductor chip.

[0172] Next, see Figure 6d and Figure 6e Step 504 is executed, providing a second substrate 40; the second substrate 40 is located along the stacking direction on the side of the second semiconductor chip stack structure 30 where the first lead 32 is formed, and the signal line 41 in the second substrate 40 is connected to the first lead 32.

[0173] See Figure 6d and Figure 6e The provision of the second substrate 40 includes:

[0174] The second substrate 40 is cut to form a second conductive bump 42 on the second substrate, so that the surface of the second substrate 40 on which the second conductive bump 42 is formed is flush with the surface of the second semiconductor chip stack structure 30 near the first semiconductor chip 20, and the signal line 41 is exposed.

[0175] Specifically, the second semiconductor chip stack structure 30 is first connected to the second substrate 40 via the first lead 32, and then the second substrate 40 is cut to a suitable size, for example, cut to be flush with the surface of the second semiconductor chip stack structure 30 near the first semiconductor chip 20, and then the remaining second substrate 40' is removed.

[0176] It should be noted that, in Figure 6d In the illustrated embodiment, the surface of the second substrate 40 where the second conductive bump 42 is formed is flush with the surface of the second semiconductor chip stack structure 30 near the first semiconductor chip 20, forming a surface where... Figure 2 In the embodiment of the semiconductor packaging structure shown, the surface of the second substrate 40 where the second conductive bump 42 is formed is flush with the surface of the first semiconductor chip 20 where the first conductive bump 21 is formed.

[0177] Next, see Figure 6e A second conductive bump 42 is formed on the surface of the cut second substrate 40 that exposes the signal line 41, and the second conductive bump 42 is connected to the signal line 41.

[0178] In one embodiment, the signal line 41 includes a ground line 411 and a power line 412, and the first lead 32 includes a first sub-lead 321 and a second sub-lead 322;

[0179] The grounding wire 411 is electrically connected to the first sub-lead 321, and the power supply wire 412 is electrically connected to the second sub-lead 322.

[0180] In this embodiment, the ground signal of the second semiconductor chip stack structure 30 is led out to the ground line 411 through the first sub-lead 321, and the power signal of the second semiconductor chip stack structure 30 is led out to the power line 412 through the second sub-lead 322. Then, the ground line 411 and the power line 412 are electrically connected to the first substrate 10 through the second conductive bump 42. Thus, the first substrate 10 supplies power to the second semiconductor chip stack structure 30 through the second conductive bump 42, the ground line 411, and the power line 412.

[0181] like Figure 4 As shown, a first sub-lead 321 is spaced between two adjacent second sub-leads 322. Because the first sub-lead 321 is connected to the ground signal and the second sub-lead 322 is connected to the power signal, crosstalk between different power signals can be reduced and the power shielding can be enhanced.

[0182] Specifically, a first pad 34 is formed on the second semiconductor chip stack structure 30. The first pad includes a first sub-pad 341 and a second sub-pad 342. A second pad 43 is formed on the second substrate 40. The second pad 43 includes a third sub-pad 431 and a fourth sub-pad 432. The first sub-pad 341 is connected to the third sub-pad 431 through a first sub-lead 321, and the second sub-pad 342 is connected to the fourth sub-pad 432 through a second sub-lead 322.

[0183] In one embodiment, such as Figure 3 As shown, the formation of the second semiconductor chip stack structure 30 includes:

[0184] Form at least one first chip stack structure 301 and at least one second chip stack structure 303;

[0185] The method further includes:

[0186] After the first semiconductor chip 20 is formed, the first chip stacking structure 301 and the second chip stacking structure 302 are arranged side by side on the first semiconductor chip 20 along the stacking direction, and the surfaces away from the first lead 32 along the stacking direction are arranged opposite to each other.

[0187] After providing the second substrate 40, the first chip stack structure 301 and the second chip stack structure 302 are respectively connected to one of the second substrates 40.

[0188] In this embodiment, the first chip stack structure and the second chip stack structure, with the first leads formed on one side, are respectively powered by a second substrate. Compared to powering multiple second semiconductor chip stack structures from only one side, this better solves the voltage drop problem caused by a large number of stacked layers, thereby improving the performance of the second semiconductor chip stack structure. Furthermore, it ensures that the power supplies for the first and second chip stack structures are consistent, reducing the impact of power supply voltage drop on the chips.

[0189] In one embodiment, the first chip stack structure 301 and the second chip stack structure 302 are connected by the adhesion film 50.

[0190] Next, see Figure 6f Step 505 is executed, providing a first substrate 10; connecting the first semiconductor chip 20 to the first substrate 10; and connecting the second substrate 40 to the first substrate 10.

[0191] In one embodiment, the first substrate 10 may be a printed circuit board (PCB) or a redistributed substrate.

[0192] The first substrate 10 may include a first substrate (not shown) and a first upper insulating dielectric layer and a first lower insulating dielectric layer (not shown) located on the upper and lower surfaces of the first substrate, respectively.

[0193] The first substrate can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, SOI (silicon on insulator) substrate, or GOI (germanium on insulator) substrate, etc. It can also be a substrate including other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., gallium nitride substrate or gallium arsenide substrate, etc.), and can also be a stacked structure, such as Si / SiGe, etc., or other epitaxial structures, such as SGOI (germanium on silicon), etc.

[0194] The first upper insulating dielectric layer and the first lower insulating dielectric layer can be solder resist layers, for example, the materials of the first upper insulating dielectric layer and the first lower insulating dielectric layer can be green paint.

[0195] A substrate connection bump 12 is formed on the lower surface of the first substrate 10. The substrate connection bump 12 can electrically connect the semiconductor package structure to an external device, receive at least one of control signals, power signals and ground signals for operating the first semiconductor chip and the second semiconductor chip from the external device, or receive data signals to be stored in the first semiconductor chip and the second semiconductor chip from the external device, and can also provide data in the first semiconductor chip and the second semiconductor chip to the external device.

[0196] The substrate connection bump 12 comprises a conductive material. In this embodiment, the substrate connection bump 12 is a solder ball. It is understood that the shape of the substrate connection bump provided in this embodiment is only one lower-level, feasible specific implementation and does not constitute a limitation on this disclosure. The substrate connection bump can also be other shapes and structures. The number, spacing, and position of the substrate connection bumps are not limited to any specific arrangement and can be modified in various ways.

[0197] In one embodiment, specifically, the first semiconductor chip 20 is connected to the first substrate 10 via a first conductive bump 21, and the second substrate 40 is connected to the first substrate 10 via a second conductive bump 42.

[0198] In one embodiment, such as Figure 6f As shown, a groove 101 is formed in the first substrate 10; the first semiconductor chip 20 is placed in the groove 101.

[0199] In this embodiment, placing the first semiconductor chip in the groove of the first substrate can reduce the packaging height of the semiconductor package structure.

[0200] In some other embodiments, such as Figure 2 As shown, the first semiconductor chip 20 is located on the first substrate 10, and the first conductive bump 21 is located between the first semiconductor chip 20 and the first substrate 10.

[0201] In this embodiment, the first semiconductor chip is located above the first substrate. As a result, the first substrate does not need to be provided with a groove, thus simplifying the process. Furthermore, the gap between the first semiconductor chip and the first substrate can increase the heat dissipation effect of the first semiconductor chip.

[0202] The first semiconductor chip 20 is electrically connected to the first substrate 10 through the first conductive bump 21. The first substrate 10 supplies power to the first semiconductor chip and exchanges signals via a wired connection.

[0203] The first conductive bump 21 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the first semiconductor chip 20 can interact with external devices through the substrate connection bump 12.

[0204] The second conductive bump 42 is also connected to the substrate connection bump 12 through the lead 11 in the first substrate 10. In this way, the second semiconductor chip stack structure 30 can interact with external devices through the substrate connection bump 12.

[0205] Next, see Figure 6g The method further includes: forming an encapsulation compound structure 80 on the first substrate 10, the encapsulation compound structure 80 at least encapsulating the second semiconductor chip stack structure 30 and the second substrate 40.

[0206] exist Figure 2 In the embodiment shown, the encapsulation compound structure 80 also encapsulates the first semiconductor chip 20.

[0207] The encapsulation compound structure 80 includes a silicon-containing compound. The silicon-containing compound may be spin-on glass (SOG), silicon-containing spin-on dielectric (SOD), or other silicon-containing spin-on materials.

[0208] By forming an encapsulation compound structure 80, and the material of the encapsulation compound structure 80 including a silicon-containing compound, the warpage problem of the second semiconductor chip stack structure 30 can be reduced.

[0209] Next, the method further includes: forming a filling layer 70, the filling layer 70 being located between the second semiconductor chip stack structure 30 and the second substrate 40, and / or between the first semiconductor chip 20 and the first substrate 10.

[0210] In some embodiments, the filling layer 70 may also be located between the second substrate 40 and the first substrate 10.

[0211] For example, in one embodiment, such as Figure 6g As shown, when the first semiconductor chip 20 is located in the groove of the first substrate 10, the filling layer 70 may be located between the second semiconductor chip stack structure 30 and the second substrate 40, and / or between the second substrate 40 and the first substrate 10.

[0212] In another embodiment, such as Figure 2As shown, when the first semiconductor chip 20 is located above the first substrate 10, the filling layer 70 may be located between the first semiconductor chip 20 and the first substrate 10, and / or between the second substrate 40 and the first substrate 10, and / or between the second semiconductor chip stack structure 30 and the second substrate 40.

[0213] For a three-dimensional stacked second semiconductor chip structure, because its thickness along the stacking direction is relatively thin, the warpage of the second semiconductor chip stack structure is relatively high. When erected on the first semiconductor chip, the high warpage makes it difficult to solder the second semiconductor chip stack structure to the second substrate. Therefore, providing a filler layer between the second semiconductor chip stack structure and the second substrate, and between the first substrate and the first semiconductor chip, can effectively reduce the impact caused by the mismatch of the overall temperature expansion characteristics between the chip and the substrate or external forces, thereby increasing the reliability of the semiconductor packaging structure.

[0214] In one embodiment, the filler layer 70 is made of epoxy resin.

[0215] Epoxy resin can be applied to the edge of the chip using the capillary action principle, allowing it to penetrate to the bottom of the chip or substrate, and then cured by heating. Because epoxy resin can effectively improve the mechanical strength of the solder joint, it can extend the lifespan of the chip.

[0216] In one embodiment, the Young's modulus of the filler layer 70 is greater than that of the encapsulated compound structure 80.

[0217] Young's modulus is a physical quantity that describes the ability of a solid material to resist deformation. The larger the Young's modulus, the greater the resistance to deformation. However, if the Young's modulus is too low, it will be difficult to maintain the rigidity of the encapsulation structure, and problems such as deformation, warping, or breakage will easily occur. Therefore, in the embodiments of this disclosure, by forming a filler layer, and the Young's modulus of the filler layer is greater than that of the Young's modulus of the encapsulation compound structure, the filler layer can have sufficient strength to support the entire encapsulation structure, making the encapsulation structure less prone to deformation, warping, or breakage.

[0218] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: First substrate; A first semiconductor chip is connected to the first substrate; A second semiconductor chip stack structure is located on the first semiconductor chip. The second semiconductor chip stack structure includes a plurality of second semiconductor chips stacked sequentially along a first direction. A first lead is formed on the outermost second semiconductor chip along the first direction. The first direction is a direction parallel to the plane of the first substrate. The second substrate has signal lines connected to the first lead; the second substrate is connected to the first substrate along a direction perpendicular to the plane of the first substrate.

2. The semiconductor packaging structure according to claim 1, characterized in that: The first semiconductor chip includes a logic chip, and the second semiconductor chip stack structure includes a DRAM chip.

3. The semiconductor packaging structure according to claim 1, characterized in that, The second semiconductor chip stack structure includes at least one first chip stack structure and at least one second chip stack structure, wherein the first chip stack structure and the second chip stack structure are arranged side by side on the first semiconductor chip along a first direction, and the surfaces away from the first lead along the first direction are disposed opposite to each other. The first chip stack structure and the second chip stack structure are respectively connected to a second substrate.

4. The semiconductor packaging structure according to claim 3, characterized in that, Also includes: An adhesive film is located between the first semiconductor chip and the second semiconductor chip stack structure, and / or between the first chip stack structure and the second chip stack structure.

5. The semiconductor packaging structure according to claim 4, characterized in that, The adhesive film includes a first adhesive film and a second adhesive film located on the first adhesive film, wherein the elastic modulus of the second adhesive film is greater than that of the first adhesive film.

6. The semiconductor packaging structure according to claim 1, characterized in that, The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

7. The semiconductor packaging structure according to claim 1, characterized in that, A groove is formed in the first substrate, the first semiconductor chip is located in the groove, the first semiconductor chip is connected to the first substrate through a first conductive bump, and the second substrate is connected to the first substrate through a second conductive bump.

8. The semiconductor packaging structure according to claim 1, characterized in that, The first semiconductor chip is located on the first substrate, and the first semiconductor chip is connected to the first substrate through a first conductive bump, and the second substrate is connected to the first substrate through a second conductive bump.

9. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: Multiple through-silicon vias, wherein the through-silicon vias penetrate the second semiconductor chip along a first direction; Multiple third conductive bumps are located between two adjacent second semiconductor chips and are connected to the vias. The second semiconductor chip stack structure is connected by hybrid bonding.

10. The semiconductor packaging structure according to claim 9, characterized in that, Also includes: A connector, located on the outermost surface of the second semiconductor chip along the first direction of the second semiconductor chip stack structure, connects a plurality of through-silicon vias of the second semiconductor chip stack structure to a first lead.

11. The semiconductor packaging structure according to claim 1, characterized in that, The signal line includes a ground line and a power line, and the first lead includes a first sub-lead and a second sub-lead; The grounding wire is electrically connected to the first sub-lead, and the power supply wire is electrically connected to the second sub-lead.

12. The semiconductor packaging structure according to claim 11, characterized in that, There is a first sub-lead between each two adjacent second sub-leads.

13. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A filling layer is located between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

14. The semiconductor packaging structure according to claim 13, characterized in that, Also includes: An encapsulated compound structure is located on the first substrate; The encapsulation compound structure at least encapsulates the second semiconductor chip stack structure and the second substrate; The Young's modulus of the filling layer is greater than that of the Young's modulus of the encapsulated compound structure.

15. A method for fabricating a semiconductor packaging structure as described in any one of claims 1-14, characterized in that, include: A second semiconductor chip stack structure is formed, the second semiconductor chip stack structure comprising a plurality of second semiconductor chips stacked sequentially; Forming the first semiconductor chip; The surface of the second semiconductor chip stack structure perpendicular to the stacking direction is connected to the surface of the first semiconductor chip. Provide a second substrate; The second substrate is located on the side of the second semiconductor chip stack structure where the first lead is formed along the stacking direction, and the signal line in the second substrate is connected to the first lead; a first substrate is provided; The first semiconductor chip is connected to the first substrate, and the second substrate is connected to the first substrate.

16. The method according to claim 15, characterized in that, The formation of the second semiconductor chip stack structure includes: Form at least one first chip stack structure and at least one second chip stack structure; The method further includes: After the first semiconductor chip is formed, the first chip stack structure and the second chip stack structure are arranged side by side on the first semiconductor chip along the stacking direction, and the surfaces away from the first lead along the stacking direction are arranged opposite each other. After providing the second substrate, the first chip stack structure and the second chip stack structure are respectively connected to a second substrate.

17. The method according to claim 15, characterized in that, A groove is formed within the first substrate; The first semiconductor chip is placed in the groove.

18. The method according to claim 15, characterized in that, Also includes: An adhesion film is formed to connect the second semiconductor chip stack structure and the first semiconductor chip through the adhesion film, and / or to connect the first semiconductor chip stack structure and the second semiconductor chip stack structure.

19. The method according to claim 15, characterized in that, The first semiconductor chip and the second semiconductor chip stack structure communicate wirelessly.

20. The method according to claim 15, characterized in that, Also includes: A filling layer is formed between the second semiconductor chip stack structure and the second substrate, and / or between the first semiconductor chip and the first substrate.

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