Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method of the semiconductor structure, the semiconductor structure comprising: a substrate, the substrate having a power supply port; a storage module located on the upper surface of the substrate; the storage module comprising a plurality of storage chips stacked in a first direction, the first direction being parallel to the upper surface of the substrate; each of the storage chips having a power supply signal line, at least one of the plurality of storage chips having a power supply wiring layer, the power supply signal line being electrically connected with the power supply wiring layer; the power supply wiring layer being located in the storage module, and the power supply wiring layer being exposed by the storage module away from the end surface of the substrate; the end surface further having a solder bump; and a lead frame being electrically connected with the solder bump and the power supply port. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] To improve the integration of semiconductor structures, more than one memory chip can be placed within the same package. HBM (High Bandwidth Memory) is a new type of memory. Memory chip stacking technology, represented by HBM, extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thereby significantly increasing the density of memory chips and achieving large capacity and high bandwidth.

[0003] However, HBM's performance needs improvement as the number of stacking layers increases. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which at least helps to improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a power supply port; a memory module located on the upper surface of the substrate; the memory module including a plurality of memory chips stacked in a first direction parallel to the upper surface of the substrate; each memory chip having a power supply signal line, at least one of the plurality of memory chips having a power supply wiring layer, the power supply signal line being electrically connected to the power supply wiring layer; the power supply wiring layer being located within the memory module, and an end face of the power supply wiring layer away from the substrate being exposed by the memory module; the end face also having a solder bump; a lead frame connected to the solder bump; the lead frame also being electrically connected to the power supply port.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate having a power supply port; providing a memory module; the memory module including a plurality of memory chips stacked in a first direction; each memory chip having a power supply signal line, at least one of the plurality of memory chips having a power supply wiring layer, the power supply signal line being electrically connected to the power supply wiring layer; the power supply wiring layer being located within the memory module, and an end face of the power supply wiring layer away from the substrate being exposed by the memory module; the end face also having a solder bump; fixing the memory module onto the substrate, with the first direction parallel to the upper surface of the substrate; providing a lead frame; connecting the lead frame to the solder bump and electrically connecting the lead frame to the power supply port.

[0007] The technical solution provided in this disclosure has at least the following advantages: the stacking direction of multiple memory chips is parallel to the substrate, therefore, the communication distance of the multiple memory chips is the same, which is beneficial for unifying communication latency and improving operating speed. Furthermore, the power supply wiring layer within the memory chip can lead the power supply signal lines out of the memory chip, thereby realizing wired power supply. Wired power supply has higher stability and reliability. In addition, the solder bumps are connected to the lead frame, thereby improving the structural strength. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 A schematic diagram of a semiconductor structure is shown;

[0010] Figures 2-6 Cross-sectional views of different semiconductor structures provided in an embodiment of this disclosure are shown respectively;

[0011] Figure 7 A schematic diagram of the active surface of a memory chip provided in an embodiment of the present disclosure is shown;

[0012] Figures 8-9 Top views of different semiconductor structures provided in one embodiment of this disclosure are shown respectively;

[0013] Figures 10-11 A schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure is shown. Detailed Implementation

[0014] refer to Figure 1 As the background technology indicates, the performance of HBM needs improvement. Analysis revealed that the main reason is that HBM uses a parallel stacking method, meaning the front faces of multiple memory chips 200 are parallel to the upper surface of the substrate 300; in other words, the arrangement direction of the multiple memory chips 200 is perpendicular to the upper surface of the substrate 300. When the number of stacked layers is large, the communication distance between the topmost and bottommost memory chips 200 and the logic chip 400 differs significantly, resulting in substantial differences in communication latency between different memory chips 200 and the logic chip 400, thus affecting the product's operating speed. Furthermore, the power supply method of the semiconductor structure also affects its performance.

[0015] This disclosure provides a semiconductor structure in which multiple memory chips are stacked in a direction parallel to the upper surface of a substrate, i.e., the arrangement direction of the multiple memory chips is parallel to the upper surface of the substrate. Therefore, the communication distance of the multiple memory chips is the same, which facilitates uniform communication latency and improves operating speed. Furthermore, the power supply wiring layer can change the layout of the power supply signal lines and lead the power supply signal lines out of the memory module, i.e., improving power supply reliability through wired power supply. In addition, solder bumps make the connection between the lead frame and the memory module more robust, and the lead frame can standardize the layout of the power supply path, thereby ensuring power supply stability.

[0016] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0017] like Figures 2-9 As shown, one embodiment of this disclosure provides a semiconductor structure, which includes: a substrate 9 having a power supply port 92; a storage module 100 located on the upper surface of the substrate 9; the storage module 100 includes a plurality of storage chips 1 stacked in a first direction X, the first direction X being parallel to the upper surface of the substrate 9; each storage chip 1 having a power supply signal line 12, at least one of the plurality of storage chips 1 having a power supply wiring layer 2, the power supply signal line 12 being electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 being located within the storage module 100, and the end face 14 of the power supply wiring layer 2 away from the substrate 9 being exposed by the storage module 100; the end face 14 also having a solder bump 8 and being connected to the solder bump 8; a lead frame 7 connected to the solder bump 8; the lead frame 7 also being electrically connected to the power supply port 92.

[0018] Such a design includes at least the following effects:

[0019] First, the power supply wiring layer 2 can lead out power supply signal lines 12 to provide wired power to the memory chip 1, thereby improving power supply stability. Specifically, the surface of the memory chip 1 includes a front side and a back side, and a side side connecting the two, with the area of ​​the front side and the back side being larger than the area of ​​the side side. The plane containing the power supply wiring layer 21 is perpendicular to the upper surface of the substrate 9; in other words, the power supply wiring layer 21 can be located on either the front or back side of the memory chip 1 for connecting the power supply signal lines 12.

[0020] Secondly, the welding bump 1 can not only electrically connect the power supply wiring layer 2 to the lead frame 2, but also fix the lead frame 2, thereby improving the structural strength.

[0021] Third, the lead frame 7 has high strength and is not easily deformed, thus ensuring the proper routing of the wired power supply path.

[0022] Fourth, multiple memory chips 1 are stacked along the first direction X, that is, the arrangement direction of the multiple memory chips 1 is parallel to the substrate 9. As a result, the side of the memory chip 1 faces the substrate 9. Since the side area of ​​the memory chip 1 is small, the area occupied on the upper surface of the substrate 9 is small, which is beneficial to increasing the number of memory chips 1 stacked.

[0023] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0024] First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z. Among them, the first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the substrate 9; and the third direction Z is perpendicular to the upper surface of the substrate 9.

[0025] refer to Figures 2-6 Multiple memory chips 1 can be stacked using a hybrid bonding method. For example, the surface of memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together by forces such as molecular forces. In addition, the surface of memory chip 1 can also have bonding portions 42, and adjacent bonding portions 42 are bonded together under heating conditions. That is, the dielectric layer 43 is an insulating material, which can play an isolation role; the bonding portion 42 is a conductive material, which can play an electrical connection role. Furthermore, the dielectric layer 43 also exposes the end face 4 of the power supply wiring layer 2 facing away from the substrate 9 and covers the surface of the power supply wiring layer 2 except for the end face 4.

[0026] The memory chip 1 can be a DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory) chip. In some embodiments, adjacent memory chips 1 can be stacked with their front sides facing each other, which facilitates a unified bonding process for the memory chips 1 and simplifies the manufacturing process. In some embodiments, the stacking of adjacent memory chips 1 can also include front-to-front or back-to-back arrangements. The front side of the memory chip 1 can also be understood as the active surface 13, and the back side of the memory chip 1 can be understood as the non-active surface opposite to the active surface 13.

[0027] The following will provide a detailed description of power supply wiring layer 2 and power supply signal line 12.

[0028] refer to Figures 2-6The power supply wiring layer 2 can be located on the front side of the memory chip 1, that is, extending along the active surface 13 of the memory chip 1. Therefore, after the components within the memory chip 1 are manufactured, the power supply wiring layer 2 can be manufactured using existing back-end processes, simplifying the process. Furthermore, the power supply wiring layer 2 can extend only at the edge near the active surface 13 of the memory chip 1, without covering the entire active surface 13 of the memory chip 1. Therefore, the contact area between the power supply wiring layer 2 and the memory chip 1 is small, reducing the impact of heat generated by the power supply wiring layer 2 on the memory chip 1.

[0029] refer to Figure 7 , Figure 7 This is a schematic diagram of the active surface 13 of a memory chip 1. Each memory chip 1 has multiple power supply signal lines 12, which extend from the memory chip 1 to the active surface 13 for connection to the power supply wiring layer 2. Different power supply signal lines 12 can provide different voltage signals, such as digital or analog signals, to the components within the memory chip 1. The power supply signal lines 12 can be ground signal lines 12G or power signal lines 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

[0030] Each power supply cabling layer 2 includes multiple spaced power supply cabling lines 20. Each power supply cabling line 20 is electrically connected to a power supply signal line 12. Different power supply signal lines 12 have different voltage signals, and correspondingly, different power supply cabling lines 20 have different voltage signals. The power supply cabling layer 2 includes ground cabling 20G and power supply cabling 20P. Ground cabling 20G is electrically connected to ground signal line 12G, and power supply cabling 20P is electrically connected to power signal line 12P.

[0031] In some embodiments, reference Figure 2 and Figures 4-6 Each memory chip 1 has a power supply wiring layer 2, and the power supply wiring layer 2 within each memory chip 1 is correspondingly connected to the power supply signal line 12. That is, the power supply signal lines 12 of different memory chips 1 are independent of each other and do not need to be electrically connected together through conductive vias 41 and bonding portions 42; the power supply signal lines 12 within each memory chip 1 can be led out through the power supply wiring layer 2 of the memory chip 1 itself, without needing to borrow the power supply wiring layer 2 of other memory chips 1. Since the power supply signal line 12 of each memory chip 1 can be led out individually, it is beneficial to improve the stability of the power supply. Furthermore, conductive vias 41 (see reference) can be omitted. Figure 3 This reduces production costs by streamlining the fabrication process. Furthermore, since the multiple memory chips are independent of each other, bonding portions 42 may not be required between adjacent memory chips 1.

[0032] Figure 8 for Figure 2 , Figures 4-6 The top view of the semiconductor structure shown is for greater clarity. Figure 8 Only the lead frame 7 and the solder bump 8 are shown. (See reference) Figure 8 Since each memory chip 1 has a power supply wiring layer 2, each memory chip 1 also has solder bumps 8. That is, the number of solder bumps 8 is relatively large, which can enhance the connection strength between the lead frame 7 and the memory module 100, thereby improving the stability of the structure.

[0033] In other embodiments, reference is made to Figure 3 The number of power supply wiring layers 2 can also be less than the number of memory chips 1. Specifically, each memory chip 1 has a conductive via 41 connected to a power supply signal line 12; adjacent memory chips 1 have bonding portions 42 connected to the conductive vias 41 within the adjacent memory chips 1. In other words, power supply signal lines 12 with the same voltage signal in different memory chips 1 can be connected together through the conductive vias 41 and bonding portions 42. For example, power supply signal lines 12 with the same voltage signal in two adjacent memory chips 1 are electrically connected; thus, only one of the two memory chips 1 needs to have a power supply wiring layer 2.

[0034] In other words, multiple memory chips 1 can share a single power supply wiring layer 2. If a memory chip 1 has its own power supply wiring layer 2, then the power supply signal line 12 of this memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have its own power supply wiring layer 2, this memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby leading out the power supply signal line 12 through the power supply wiring layer 2 of other memory chips 1.

[0035] Figure 9 for Figure 3 The top view of the semiconductor structure shown is for greater clarity. Figure 9 Only the lead frame 7 and solder bump 8 are shown. (Reference) Figure 9 Since multiple memory chips 1 can share a single power supply wiring layer 2, the number of power supply wiring layers 2 is relatively small. Consequently, the number of solder bumps 8 is also relatively small, thereby increasing the spacing between adjacent solder bumps 8 to avoid incorrect electrical connections between adjacent solder bumps 8.

[0036] The lead frame 7 will be described in detail below.

[0037] refer to Figures 8-9The lead frame 7 includes a plurality of spaced frame bars 70, and the plurality of frame bars 70 are arranged in a second direction Y; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the substrate 9; each power supply wiring layer 2 includes a plurality of power supply wirings 20, and different power supply wirings 20 have different voltages; different frame bars 70 are connected to power supply wirings 20 with different voltages.

[0038] The welding bumps 8 with the same voltage signal can be arranged in a straight line in the first direction X, that is, the power supply wirings 20 with the same voltage signal in the multiple power supply wiring layers 2 are directly opposite each other in the first direction X. As a result, the orthographic projection of the frame strip 70 on the substrate 9 can be a straight line, which makes it easier to align the frame strip 70 with the welding bumps 8, simplifies the welding process, and saves material of the frame strip 70.

[0039] Continue to refer to Figures 8-9 The frame strip 70 includes a grounding frame strip 70G and a power frame strip 70P, wherein the grounding frame strip 70G is electrically connected to the grounding wiring 20G, and the power frame strip 70P is electrically connected to the power wiring 20P. In some embodiments, the grounding frame strip 70G and the power frame strip 70P are arranged alternately in the second direction Y. Correspondingly, the grounding wiring 20G and the power wiring 20P are arranged alternately in the second direction Y. This helps to reduce electromagnetic interference between adjacent power supply wirings 20 and adjacent frame strips 70.

[0040] In some embodiments, multiple frame bars 70 are arranged at equal intervals, which helps to improve the uniformity of the structure and avoid incorrect electrical connections caused by adjacent frame bars 70 being too close together.

[0041] refer to Figures 2-6 The lead frame 7 includes a connected support frame 71 and a soldering frame 72; the support frame 71 extends in a direction perpendicular to the upper surface of the substrate 9; the soldering frame 72 extends in a direction parallel to the upper surface of the substrate 9 and is soldered to the soldering bump 8. That is, the soldering bump 8 can fix the soldering frame 72 above the storage module 100, thereby enabling the storage module 100 to support the lead frame 7 and improve the stability of the structure.

[0042] In some embodiments, there are at least two support frames 71, which are located on opposite sides of the storage module 100 and connected to opposite ends of the welding frame 72. Multiple support frames 71 improve the stability of the lead frame 7, thereby increasing the reliability of power supply. In other embodiments, the lead frame 7 may also have only one support frame 71, which helps save materials.

[0043] refer to Figures 5-6The lead frame 7 may also have a groove 7a, and the solder bump 8 is directly opposite and soldered to the groove 7a. That is, the groove 7a is located within the soldering frame 72. It should be noted that the top surface of the solder bump 8 also has a solder layer 83 to connect the solder bump 8 and the lead frame 7. The groove 7a can accommodate more solder to improve the soldering strength and reduce the contact resistance between the solder bump 8 and the lead frame 7.

[0044] In some embodiments, the width of the welding bracket 72 in the second direction Y can be greater than the width of the welding bump 8 in the second direction Y, and the opening area of ​​the groove 7a is greater than the top surface area of ​​the welding bump 8. This results in a larger solder capacity and a stronger weld; furthermore, the larger opening facilitates alignment of the welding bump 8 with the groove 7a. In other embodiments, the width of the welding bracket 72 in the second direction Y can also be less than or equal to the width of the welding bump 8.

[0045] In some embodiments, reference Figure 5 Each frame strip 70 has multiple grooves 7a, and each groove 7a corresponds one-to-one with a multiple welding protrusion 8. Thus, the grooves 7a can guide the flow direction of the solder during the welding process, that is, guide the solder to flow into the grooves 7a, and avoid electrical connection between adjacent welding protrusions 8.

[0046] In other embodiments, reference is made to... Figure 6 Each frame strip 70 has a groove 7a, which corresponds to a plurality of welding protrusions 8, and the groove 7a extends in the first direction X. This simplifies the manufacturing process.

[0047] Furthermore, in some embodiments, the groove 7a may penetrate the lead frame 7, thereby allowing the groove 7a to accommodate more solder. In other embodiments, the bottom surface of the groove 7a may be located within the lead frame 7, i.e., not penetrating the lead frame 7, so that the bottom surface of the groove 7a can also contact the solder, thereby increasing the contact area and reducing the contact resistance.

[0048] refer to Figures 2-3 The lead frame 7 also includes an extension frame 73, which is connected to the side of the support frame 71 away from the soldering frame 72; the cross-sectional area of ​​the extension frame 73 is larger than the cross-sectional area of ​​the support frame 71, and the cross-sections of the extension frame 73 and the support frame 71 are parallel to the upper surface of the substrate 9; the semiconductor structure also includes a lead 74, which is connected between the extension frame 73 and the power supply port 92.

[0049] That is, the extension frame 73 extends in a direction parallel to the upper surface of the substrate 9. The extension frame 73 helps to increase the welding area between the lead 74 and the lead frame 7, so as to facilitate welding. In addition, the lead 74 can improve the flexibility of connecting the lead frame 7 and the power supply port 92.

[0050] In some embodiments, the first and last ends of the extension frame 73, the support frame 71, and the welding frame 72 are connected sequentially, that is, a strip of conductive material is bent into multiple segments to serve as the extension frame 73, the support frame 71, and the welding frame 72 respectively, which simplifies the manufacturing process.

[0051] In other embodiments, reference is made to Figures 4-6 The semiconductor structure also includes: a power supply line 75 connected to the side of the support frame 71 away from the soldering frame 72; the substrate 9 also has a through-hole 93, which serves as a power supply port 92; the power supply line 75 is disposed within the through-hole 93. Thus, the connection between the lead frame 7 and the power supply port 92 is simpler; furthermore, since the sides of the power supply line 75 are surrounded by the through-hole 93, the contact area between them is larger, and the contact resistance is lower.

[0052] The cross-sectional area of ​​the power supply line 75 is smaller than that of the support frame 71, and the cross-sections of both the power supply line 75 and the support frame 71 are parallel to the upper surface of the substrate 9. When the cross-sectional area of ​​the support frame 71 is larger, it is beneficial to improve the structural strength of the lead frame 7; when the cross-sectional area of ​​the power supply line 75 is smaller, it is beneficial to reduce the volume occupied by the power supply line 75 in the substrate 9, thereby avoiding encroachment on the space of other components in the substrate 9.

[0053] It is worth noting that since the lead frame 7 includes multiple spaced frame bars 70, it can be understood that each frame bar 70 may include structures such as a welding frame 72, a support frame 71, or an extension frame 73.

[0054] refer to Figures 2-6 The welding bump 8 includes a first bump 81 and a second bump 82 stacked together; the first bump 81 is connected to the power supply wiring layer 2; the second bump 82 is welded to the lead frame 7; the cross-sectional area of ​​the first bump 81 is larger than the cross-sectional area of ​​the second bump 82, and the cross-sections of the first bump 81 and the second bump 82 are both parallel to the upper surface of the substrate 9.

[0055] The larger cross-sectional area of ​​the first bump 81 helps to increase the contact area between the welding bump 8 and the power supply wiring layer 2, thereby reducing the contact resistance. The smaller cross-sectional area of ​​the second bump 82 helps to increase the distance between adjacent welding bumps 8, thereby avoiding incorrect electrical connections between adjacent welding bumps 8.

[0056] For example, in the first direction X, the ratio of the width of the first bump 81 to the width of the memory chip 1 is 0.8 to 1.2. When the widths of both are kept within the above range, it is beneficial to ensure that the solder bump 8 and the power supply wiring layer 2 have sufficient contact area, and to ensure that adjacent solder bumps 8 have a suitable distance, so as to avoid incorrect electrical connection between adjacent solder bumps 8.

[0057] Continue to refer to Figures 2-6 The semiconductor structure also includes a first sealing layer 51, which surrounds the storage module 100 and exposes the surface of the storage module 100 away from the substrate 9. The first sealing layer 51 can protect the storage module 100 from the influence of the external environment, such as resisting external moisture and solvents, and can also resist thermal shock and mechanical vibration during the installation of the semiconductor structure.

[0058] The semiconductor structure also includes a second sealing layer 52, which covers the memory module 100, lead frame 7, solder bumps 8, and the first sealing layer 51. The second sealing layer 52 provides fixation for the solder bumps 8 and lead frame 7, ensuring structural strength. In other words, the second sealing layer 52 enhances protection and isolation, thus guaranteeing the performance of the semiconductor structure.

[0059] In one embodiment, the first sealing layer 51 and the second sealing layer 52 may be made of the same material. For example, the first sealing layer 51 and the second sealing layer 52 may be epoxy resin.

[0060] In one embodiment, the materials of the first sealing layer 51 and the second sealing layer 52 may be different. For example, the thermal conductivity of the second sealing layer 52 is higher than that of the first sealing layer 51. With this arrangement, the heat introduced into the second sealing layer 52 through the lead frame 7 can be transferred to the external environment more quickly, reducing the adverse effects of high temperature environment on storage module 100.

[0061] refer to Figures 2-6 The semiconductor structure also includes: a logic chip 3 located between the substrate 9 and the memory module 100, the logic chip 3 having a first wireless communication unit 31; and the memory chip 1 having a second wireless communication unit 11, the second wireless communication unit 11 communicating wirelessly with the first wireless communication unit 31.

[0062] Since the multiple memory chips 1 are equidistant from the logic chip 3, the delay of wireless communication between the multiple memory chips 1 and the logic chip 3 remains consistent. In some embodiments, the second wireless communication unit 11 is located on the side of the memory chip 1 facing the logic chip 3. This reduces the distance between the first wireless communication unit 31 and the second wireless communication unit 11, thereby improving the quality of wireless communication.

[0063] It should be noted that if the arrangement direction of multiple memory chips 1 is perpendicular to the upper surface of the logic chip 3, the communication delay between memory chips 1 and logic chip 3 in different layers will differ significantly. Furthermore, as the number of layers increases, the number of through-silicon vias (TSVs) used for communication increases proportionally, thus sacrificing wafer area. In this embodiment, the stacking direction and communication method of the memory chips 1 are changed, thereby improving communication quality and saving wafer area.

[0064] Continue to refer to Figures 2-6 The side of the memory chip 1 faces the logic chip 3, and its area is relatively small. Using wireless communication eliminates the need for a wired communication unit between the memory chip 1 and the logic chip 3, thus reducing manufacturing complexity and providing ample space for the connection structure, improving structural strength. Furthermore, the lower side of the memory module 100 is used for wireless communication, while the upper side is used for the wired power supply path. This reduces electromagnetic interference from the current in the wired power supply path to the coils in the wireless communication unit, preventing signal loss.

[0065] In some embodiments, an adhesive layer 6 is also provided between the storage module 100 and the logic chip 3. That is, the storage module 100 and the logic chip 3 are connected together by adhesive bonding to form a memory chip. For example, the adhesive layer 6 can be a die attach film (DAF). The bonding process is relatively simple and can save costs. In addition, the adhesive layer 6 can also be doped with metal ions to improve the heat dissipation effect of the storage module 100 and the logic chip 3. In other embodiments, a solder layer (not shown in the figure) can be provided between the storage module 100 and the logic chip 3, that is, the storage module 100 and the logic chip 3 are connected together by soldering.

[0066] In other words, by extending the power supply signal line 12 from the top of the storage module 100, sufficient space is left below the storage module 100 to connect the logic chip 3, thereby improving the structural strength.

[0067] Continue to refer to Figures 2-6 The logic chip 3 is further connected to the substrate 9 by pads 84 and solder paste layer 85, meaning the logic chip 3 is soldered onto the substrate 9 using flip-chip bonding. This allows the substrate 9 to supply power and exchange signals to the logic chip 3 via a wired connection, offering higher reliability. Furthermore, the bottom of the substrate 9 has solder balls 91, enabling the semiconductor structure to be connected to peripheral devices.

[0068] In summary, in this embodiment, the use of welded bumps 8 on the upper side of the storage module 100 improves the connection stability between the lead frame 7 and the storage module 100. The use of either lead wires 74 or power supply lines 75 on the lower side of the storage module 100 provides a simpler structure and greater flexibility. The combination of these two connection methods ensures that the wired power supply path offers both flexibility and stability.

[0069] like Figures 10-11 and Figure 2 As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure provided in the foregoing embodiments. Detailed description of this semiconductor structure can be found in the foregoing embodiments.

[0070] refer to Figures 10-11 The storage module 100 is provided; the storage module 100 includes a plurality of storage chips 1 stacked in a first direction X; each storage chip 1 has a power supply signal line 12, at least one of the plurality of storage chips 1 has a power supply wiring layer 2, the power supply signal line 12 is electrically connected to the power supply wiring layer 2; the power supply wiring layer 2 is located within the storage module 100, and the end face 14 of the power supply wiring layer 2 away from the substrate 9 is exposed by the storage module 100; the end face 14 also has a solder bump 8.

[0071] Specifically, refer to Figure 10 The system provides multiple memory chips 1; a power supply wiring layer 2 is formed on at least one of the memory chips 1, and after forming the power supply wiring layer 2, the multiple memory chips 1 are stacked. For example, the power supply signal lines 12 of each layer of memory chips 1 are led out to the edge of the memory chip 1 through the power supply wiring layer 2, and the multilayer memory chips 1 are stacked using a hybrid bonding method. It should be noted that the memory chips 1 are placed horizontally during the bonding process.

[0072] refer to Figure 11 The storage module 100 is rotated 90° so that each storage chip 1 is perpendicular to the logic chip 3, and the storage chip 1 and the logic chip 3 are fixed by a DAF film. Multiple storage modules 100 are reconstructed through a first molding process to form a reconstructed wafer. A first bump 81 is processed on the top surface of the reconstructed wafer through a redistribution process. A second bump 82 is then formed on the first bump 81, and the first bump 81 and the second bump 82 constitute a solder bump 8, on which a solder layer 83 is formed. Subsequently, the reconstructed wafer is diced to form memory chips, each memory chip including one storage module 100 and one logic chip 3.

[0073] refer to Figure 2A substrate 9 is provided, the substrate 9 having a power supply port 92; a storage module 100 is fixed on the substrate 9, and a first direction X is parallel to the upper surface of the substrate 9; a lead frame 7 is provided; the lead frame 7 is electrically connected to the solder bump 8 and the power supply port 92.

[0074] Specifically, the memory chip is flip-chip soldered onto the substrate 9, and the lead frame 7 is soldered onto the solder bump 8 on the top surface of the memory chip. Then, the lead frame 7 is connected to the power supply port 92 via wire connection, realizing the connection of power supply signals between the memory chip 1 and the substrate 9. Subsequently, a second sealing layer 52 covering the memory module 100, lead frame 7, and other structures is formed through a second molding process.

[0075] It is worth noting that the reason for employing two molding processes is that the first molding process connects multiple storage modules 100 together, allowing the second wiring layer 22 to be formed simultaneously on multiple storage modules 100, thus reducing the number of process steps. Furthermore, while individual storage modules 100 are relatively small, the overall volume of multiple connected modules 100 is larger, resulting in greater stability and reducing the likelihood of tipping over. Additionally, the first sealing layer 51 formed in the first molding process protects and secures the storage modules 100 during subsequent steps such as forming the welding bumps 8 and flip-chip welding, preventing collapse or damage and thus ensuring the performance of the storage modules 100. Moreover, the two molding processes improve the sealing effect.

[0076] In summary, the multilayer memory chip 1 and the logic chip 3 are vertically stacked to form a memory chip, and the power supply wiring layer 2 is led out to the substrate 9 for packaging via the lead frame 7. Signal communication between the memory chip 1 and the logic chip 3 is achieved wirelessly, which effectively solves the communication difficulties caused by the increasing number of stacked layers of memory chip 1 in parallel stacking, and ensures the reliability of power supply.

[0077] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0078] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a power supply port; A storage module is located on the upper surface of the substrate; The storage module includes a plurality of storage chips stacked in a first direction, which is parallel to the upper surface of the substrate. Each of the memory chips has a power supply signal line, and at least one of the plurality of memory chips has a power supply wiring layer, wherein the power supply signal line is electrically connected to the power supply wiring layer. The power supply wiring layer is located within the storage module, and the end face of the power supply wiring layer away from the substrate is exposed by the storage module; the end face also has solder bumps; The lead frame is electrically connected to the welding bump and the power supply port; The lead frame includes a plurality of spaced frame bars, and the plurality of frame bars are arranged in a second direction; the second direction is perpendicular to the first direction and parallel to the upper surface of the substrate; Each of the power supply wiring layers includes multiple power supply wirings, and different power supply wirings have different voltages; The different frame bars are connected to the power supply wiring with different voltages.

2. The semiconductor structure according to claim 1, characterized in that, The lead frame includes a connected support frame and a welding frame; The support frame extends in a direction perpendicular to the upper surface of the substrate; The welding frame extends in a direction parallel to the upper surface of the substrate and is welded to the welding bump.

3. The semiconductor structure according to claim 2, characterized in that, There are at least two support frames, which are located on opposite sides of the storage module and connected to opposite ends of the welding frame.

4. The semiconductor structure according to claim 2, characterized in that, The lead frame further includes an extension frame connected to the side of the support frame away from the welding frame; The cross-sectional area of ​​the extension frame is larger than that of the support frame, and the cross-sections of both the extension frame and the support frame are parallel to the upper surface of the substrate. It also includes: a lead wire, which connects the extension frame to the power supply port.

5. The semiconductor structure according to claim 2, characterized in that, Also includes: The power supply lines are respectively connected to the side of the support frame away from the welding frame; The substrate also has a through hole, which serves as the power supply port; the power supply line is disposed within the through hole.

6. The semiconductor structure according to claim 5, characterized in that, The cross-sectional area of ​​the power supply line is smaller than that of the support frame, and the cross-sections of both the power supply line and the support frame are parallel to the upper surface of the substrate.

7. The semiconductor structure according to claim 1, characterized in that, The lead frame also has a groove, and the welding protrusion is aligned with and welded to the groove.

8. The semiconductor structure according to claim 7, characterized in that, The opening area of ​​the groove is larger than the top surface area of ​​the welding protrusion.

9. The semiconductor structure according to claim 1, characterized in that, The power supply wiring includes grounding wiring and power supply wiring. The frame strip includes a grounding frame strip and a power supply frame strip. The grounding frame strip is electrically connected to the grounding wiring, and the power supply frame strip is electrically connected to the power supply wiring. The grounding frame strip and the power supply frame strip are arranged alternately in the second direction.

10. The semiconductor structure according to claim 1, characterized in that, The frame strips are arranged at equal intervals.

11. The semiconductor structure according to claim 1, characterized in that, Each of the memory chips has a power supply wiring layer, and the power supply wiring layer in each memory chip is connected to the power supply signal line.

12. The semiconductor structure according to claim 1, characterized in that, The welding bump includes a first bump and a second bump stacked together; the first bump is connected to the power supply wiring layer; the second bump is welded to the lead frame; The cross-sectional area of ​​the first bump is greater than that of the second bump, and the cross-sections of both the first bump and the second bump are parallel to the upper surface of the substrate.

13. The semiconductor structure according to claim 12, characterized in that, In the first direction, the ratio of the width of the first bump to the width of the memory chip is 0.8 to 1.

2.

14. The semiconductor structure according to claim 1, characterized in that, Also includes: A logic chip is located between the substrate and the memory module, and the logic chip has a first wireless communication unit; The memory chip has a second wireless communication unit, which communicates wirelessly with the first wireless communication unit.

15. The semiconductor structure according to claim 1, characterized in that, The power supply signal lines having the same voltage signal in different memory chips are electrically connected.

16. The semiconductor structure according to claim 1, characterized in that, The multiple memory chips are electrically connected via bonding sections.

17. The semiconductor structure according to claim 16, characterized in that, The power supply signal lines with the same voltage signal in different memory chips are electrically connected through the bonding portion.

18. The semiconductor structure according to claim 16, characterized in that, The power supply signal lines with the same voltage signal in the two memory chips are electrically connected through the bonding portion, and one of the two memory chips has the power supply wiring layer.

19. A method for manufacturing a semiconductor structure as described in any one of claims 1-18, characterized in that, include: A substrate is provided, the substrate having a power supply port; Provide storage modules; The storage module includes multiple storage chips stacked in a first direction; Each of the memory chips has a power supply signal line, and at least one of the memory chips has a power supply wiring layer, the power supply signal line being electrically connected to the power supply wiring layer; the power supply wiring layer is located within the memory module, and the end face of the power supply wiring layer away from the substrate is exposed by the memory module; the end face also has solder bumps; The storage module is fixed on the substrate, and the first direction is parallel to the upper surface of the substrate; Provide a lead frame; electrically connect the lead frame to the solder bump and the power supply port.

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