Semiconductor device

Abstract

A semiconductor device that suppresses snapback of a diode portion and mitigates electric field intensity at a lower end of a trench portion. The semiconductor device includes a plurality of trench portions provided from an upper surface of a semiconductor substrate to a position deeper than a base region and arranged in parallel along a first direction on the upper surface of the semiconductor substrate, and a first lower end region of a second conductivity type arranged at a first depth position and provided in contact with lower ends of two or more of the trench portions, and a second lower end region arranged at the first depth position and arranged at a position not overlapping the first lower end region, the second lower end region including at least one of a region of a first conductivity type and a region of the second conductivity type having a lower doping concentration than a doping concentration of the first lower end region.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Previously, semiconductor devices with trench gate structures were known (see, for example, Patent Documents 1-3).

[0003] Existing technical documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2011-181886

[0005] Patent Document 2: Japanese Patent Application Publication No. 2014-75582

[0006] Patent Document 3: Japanese Patent Application Publication No. 2019-91892 Summary of the Invention

[0007] Technical issues

[0008] It suppresses the sudden return of the diode section and moderates the electric field strength at the lower end of the trench section.

[0009] Technical solution

[0010] To address the aforementioned problems, a semiconductor device is provided in a first aspect of the present invention. The semiconductor device may include a semiconductor substrate. The semiconductor substrate has an upper surface and a lower surface, and a drift region of a first conductivity type may be included between the upper surface and the lower surface. The semiconductor substrate may be provided with a diode portion. In any of the above-described semiconductor devices, the diode portion may include a cathode region of a first conductivity type, disposed between the lower surface of the semiconductor substrate and the drift region, and having a higher doping concentration than the drift region. In any of the above-described semiconductor devices, the diode portion may include a base region of a second conductivity type, disposed between the upper surface of the semiconductor substrate and the drift region. In any of the above-described semiconductor devices, the diode portion may include a plurality of trench portions disposed from the upper surface of the semiconductor substrate to a position lower than the base region, and arranged side-by-side along a first direction on the upper surface of the semiconductor substrate. In any of the above-described semiconductor devices, the diode portion may include a first lower end region of a second conductivity type, disposed at a first depth position, and grounded to the lower ends of two or more of the trench portions. In any of the aforementioned semiconductor devices, the diode portion may include a second lower region disposed at the first depth position and at a position that does not overlap with the first lower region. In any of the aforementioned semiconductor devices, the second lower region may include at least one of a region of a first conductivity type and a region of a second conductivity type with a doping concentration lower than that of the first lower region.

[0011] In any of the aforementioned semiconductor devices, the effective dose obtained by integrating the doping concentration of the first lower region along the depth direction can be 3 × 10⁻⁶. 11 / cm 2 The above. In any of the above semiconductor devices, the second lower region may be a region of the first conductivity type. In any of the above semiconductor devices, the second lower region may be a region with an effective dose of less than 3 × 10⁻⁶ obtained by integrating the doping concentration along the depth direction. 11 / cm 2 The region of the second conductivity type.

[0012] In any of the above semiconductor devices, the diode portion may have an intermediate region of a first conductivity type disposed between the first depth position and the base region.

[0013] In any of the above semiconductor devices, the doping concentration of the intermediate region can be higher than the doping concentration of the drift region.

[0014] In any of the above semiconductor devices, the first lower region and the second lower region may be arranged side by side in the first direction.

[0015] In any of the aforementioned semiconductor devices, the diode portion may have multiple mesa portions, each mesa portion being sandwiched between two trench portions within the semiconductor substrate. In any of the aforementioned semiconductor devices, the multiple mesa portions may include one or more first mesa portions, each first mesa portion having a first lower end region disposed grounded with the lower ends of two adjacent trench portions. In any of the aforementioned semiconductor devices, the multiple mesa portions may include one or more second mesa portions, each second mesa portion having a second lower end region disposed grounded with the lower ends of two adjacent trench portions. In any of the aforementioned semiconductor devices, the first mesa portions and the second mesa portions may be arranged side-by-side in the first direction.

[0016] In any of the aforementioned semiconductor devices, at least one of the second facepieces may be configured to be sandwiched between two of the first facepieces in the first direction.

[0017] Any of the aforementioned semiconductor devices may include an upper surface electrode disposed above the upper surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, at least one of the second face plates may be connected to the upper surface electrode.

[0018] In any of the aforementioned semiconductor devices, at least one of the first face plates may be insulated from the upper surface electrode.

[0019] In any of the aforementioned semiconductor devices, at least one of the first faceplates may be connected to the upper surface electrode.

[0020] In any of the aforementioned semiconductor devices, the plurality of mesa facets may include a third mesa facet, which has a first lower end region disposed grounded to the lower end of one of the two adjacent trench portions, and a second lower end region disposed grounded to the lower end of the other of the two adjacent trench portions. In any of the aforementioned semiconductor devices, the first mesa facet, the second mesa facet, and the third mesa facet may be arranged side by side in the first direction.

[0021] In any of the aforementioned semiconductor devices, the third facepiece may be disposed between the first facepiece and the second facepiece in the first direction.

[0022] In any of the aforementioned semiconductor devices, a transistor portion may be provided on the semiconductor substrate, the transistor portion being arranged side-by-side with the diode portion in the first direction, and a collector region of a second conductivity type is provided on the lower surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, the transistor portion may include a plurality of mesa portions. In any of the aforementioned semiconductor devices, the first lower end region may be provided on the mesa portion closest to the diode portion among the plurality of mesa portions of the transistor portion.

[0023] Any of the aforementioned semiconductor devices may have a boundary mesa portion disposed on the semiconductor substrate and positioned above the boundary between the cathode region and the collector region in the first direction. Any of the aforementioned semiconductor devices may have a top surface electrode disposed above the top surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, the boundary mesa portion may be a first mesa portion connected to the top surface electrode. In any of the aforementioned semiconductor devices, the boundary mesa portion is a first mesa portion insulated from the top surface electrode.

[0024] In any of the above semiconductor devices, the doping concentration of the first lower region of the transistor portion may be different from the doping concentration of the first lower region of the diode portion.

[0025] In any of the aforementioned semiconductor devices, each of the trench portions may have a length on the upper surface of the semiconductor substrate in a second direction different from the first direction. In any of the aforementioned semiconductor devices, the first lower end region and the second lower end region may be arranged side by side in the second direction.

[0026] In any of the above semiconductor devices, at least one of the second lower end regions can be configured to be sandwiched by the first lower end region in the second direction.

[0027] Any of the aforementioned semiconductor devices may include a top surface electrode disposed above the top surface of the semiconductor substrate. Any of the aforementioned semiconductor devices may include an interlayer insulating film disposed between the top surface electrode and the semiconductor substrate, and have contact holes connecting the top surface electrode and the semiconductor substrate. In any of the aforementioned semiconductor devices, at least one of the second lower end regions may have a portion that overlaps with the contact holes when viewed from above.

[0028] In any of the aforementioned semiconductor devices, the diode portion may include a contact region of a second conductivity type, which is disposed between the base region and the upper surface of the semiconductor substrate, and has a higher doping concentration than the base region. In any of the aforementioned semiconductor devices, at least one of the second lower end regions may have a portion that overlaps with the contact region when viewed from above.

[0029] In any of the above semiconductor devices, the first lower region and the second lower region can be arranged side by side in both the first direction and the second direction.

[0030] The above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0031] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0032] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0033] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0034] Figure 4 This is a diagram showing another example of the ee section.

[0035] Figure 5 This is a diagram showing another example of the ee section.

[0036] Figure 6 This is a diagram showing an example of the configuration of the first lower end region 201 and the second lower end region 202 in the diode section 80 in the X-axis direction.

[0037] Figure 7 This is a diagram showing an example of the configuration of the first lower region 201 and the second lower region 202 in the platform surface 61.

[0038] Figure 8 It is shown Figure 7A diagram of an example of the ff section.

[0039] Figure 9 It is shown Figure 7 A diagram of an example of the gg section.

[0040] Figure 10 This is a diagram showing another configuration example of the contact hole 54 in the platform surface 61.

[0041] Figure 11 It is shown Figure 10 A diagram of an example of the hh section.

[0042] Figure 12 It is shown Figure 10 A diagram of an example of the kk section.

[0043] Figure 13 This is a diagram showing an example of the equivalent circuit of the diode section 80.

[0044] Figure 14 This is a diagram illustrating an example of the forward conduction characteristics of the diode section 80.

[0045] Figure 15 This is a graph showing the relationship between the effective dose and the trigger voltage VBO in the first lower region 201.

[0046] Figure 16 This is a diagram illustrating an example of the forward conduction characteristics of the diode section 80.

[0047] Figure 17 This is a diagram illustrating the effective dose in the first lower region 201.

[0048] Figure 18 It is shown Figure 2 Another example of the ee section is shown in the figure.

[0049] Symbol Explanation

[0050] 10: Semiconductor substrate; 11: Well region; 12: Emitter region; 14: Base region; 15: Contact region; 16: Accumulation region; 18: Drift region; 20: Buffer zone; 21: Upper surface; 22: Collector region; 23: Lower surface; 24: Collector; 29: Linear portion; 30: Dummy trench portion; 31: Front end portion; 32: Dummy insulating film; 34: Dummy conductive portion; 38: Interlayer insulating film; 39: Linear portion; 40: Gate trench portion; 41: Front end portion; 42: Gate insulating film; 44: Gate conductive portion; 52: Emitter region. 54: Contact hole; 60, 61: Mesa section; 61-1: First mesa section; 61-2: Second mesa section; 61-3: Third mesa section; 64: Boundary mesa section; 70: Transistor section; 80: Diode section; 81: Extension region; 82: Cathode region; 90: Edge termination structure section; 100: Semiconductor device; 130: Peripheral gate wiring; 131: Active side gate wiring; 160: Active section; 162: End edge; 164: Gate pad; 201: First lower end region; 202: Second lower end region. Detailed Implementation

[0051] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0052] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the actual mounting direction of the semiconductor device.

[0053] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes only determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis does not necessarily represent the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are mutually opposite directions. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to the +Z-axis and -Z-axis.

[0054] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. An axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, including the X-axis and Y-axis, the direction parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0055] Sometimes the region extending from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is called the top surface side. Similarly, sometimes the region extending from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is called the bottom surface side.

[0056] In this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors are, for example, within 10%.

[0057] In this specification, the conductivity type of the doped region containing impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate to create a semiconductor exhibiting N-type conductivity or P-type conductivity.

[0058] In this specification, doping concentration refers to the concentration of donors or acceptors under thermal equilibrium conditions. In this specification, net doping concentration refers to the concentration obtained by adding the donor concentration (as positive ions) and the acceptor concentration (as negative ions), taking into account charge polarity. For example, if the donor concentration is set to N... D Let the number of valence electrons of its unit ion be n. D Set the acceptor concentration to N A Let the number of valence electrons of its unit ion be n. A Then the net doping concentration at any position is n. D ×N D -n A ×N A In this specification, net doping concentration is sometimes referred to simply as doping concentration.

[0059] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of taking electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron-supplying donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0060] In this specification, the semiconductor substrate is uniformly distributed with N-type body donors. Body donors are donors formed by dopants that are substantially uniformly contained within the ingot during the manufacture of the ingot that forms the basis of the semiconductor substrate. In this example, the body donors are elements other than hydrogen. Dopants for body donors can be, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the body donor is phosphorus. The body donors are also contained within the P-type regions. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip formed by monolithically combining wafers. The semiconductor ingot can be manufactured using any of the following methods: Czochralski (CZ) method, magnetic crystal pulling (MCZ) method, and zone melting (FZ) method. In this example, the ingot is manufactured using the MCZ method. The oxygen concentration in the substrate manufactured using the MCZ method is 1 × 10⁻⁶. 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10⁻⁶. 15 ~5×10 16 / cm 3 High oxygen concentrations tend to promote the formation of hydrogen donors. The bulk donor concentration can be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or a value between 90% and 100% of that chemical concentration. It should be noted that the concentrations in this invention can be values ​​at room temperature. As an example, values ​​at room temperature can be those at 300 K (Kelvin) (approximately 26.9°C).

[0061] In this specification, when referred to as P+ or N+ type, it means a doping concentration higher than that of P- or N- type; when referred to as P- or N- type, it means a doping concentration lower than that of P- or N- type. Similarly, when referred to as P++ or N++ type, it means a doping concentration higher than that of P+ or N+ type. Unless otherwise stated, the units used in this specification are SI units. Sometimes length is expressed in cm, but all calculations should be converted to meters (m).

[0062] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by extended resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be set to a value under thermal equilibrium conditions. Furthermore, in the N-type region, the donor concentration is much larger than the acceptor concentration; therefore, the carrier concentration in this region can also be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0063] When the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of the donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is approximately uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of the donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atoms / cm³. 3 or / cm 3 This unit is used to indicate the concentration of donors or acceptors, or the chemical concentration, within a semiconductor substrate. The "atoms" designation can also be omitted.

[0064] The carrier concentration measured by the SR method can also be lower than the donor or acceptor concentration. Within the range where current flows during the measurement of extended resistance, the carrier mobility of the semiconductor substrate is sometimes lower than that in the crystalline state. This decrease in carrier mobility is due to carrier scattering caused by crystal structure disorder (disorder) resulting from lattice defects, etc.

[0065] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which are donors) or the acceptor concentration of boron (which is an acceptor) is about 99% of their chemical concentration. On the other hand, in silicon semiconductors, the donor concentration of hydrogen (which is a donor) is about 0.1% to 10% of the chemical concentration of hydrogen.

[0066] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 The image shows the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10. Figure 1 In this diagram, only a portion of the components of the semiconductor device 100 are shown, while the components of the other portion are omitted.

[0067] Semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" refers to viewing from the upper surface side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that face each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to one of the end edges 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0068] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter is provided above the active portion 160, but... Figure 1 The term "active part 160" can refer to the region that overlaps with the emitter when viewed from above. Additionally, the region sandwiched by the active part 160 when viewed from above can also be included within the active part 160.

[0069] The active section 160 includes a transistor section 70 containing transistor elements such as IGBTs (Insulated Gate Bipolar Transistors) and a diode section 80 containing diode elements such as freewheeling diodes (FWDs). Figure 1 In this example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conduction type IGBT (RC-IGBT).

[0070] exist Figure 1 In this specification, the area where the transistor section 70 is configured is labeled with the symbol "I", and the area where the diode section 80 is configured is labeled with the symbol "F". In this specification, a direction different from the first direction when viewed from above is designated as the second direction. The second direction can be a direction perpendicular to the first direction. As an example, the second direction is the Y-axis direction. The transistor section 70 and the diode section 80 may each have a long side in the Y-axis direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The Y-axis direction of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0071] The diode section 80 has an N+ type cathode region in the area that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, sometimes the extension region 81 extending the diode section 80 in the Y-axis direction to the gate wiring described later is also included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0072] The transistor section 70 has a P+ type collector region in the region that is in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0073] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near the edge 162. "Near the edge 162" refers to the area between edge 162 and the emitter when viewed from above. During actual installation of semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0074] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, the shaded lines are used to mark the gate wiring.

[0075] The gate wiring in this example includes an outer peripheral gate wiring 130 and an active-side gate wiring 131. The outer peripheral gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. In this example, the outer peripheral gate wiring 130 surrounds the active portion 160 when viewed from above. Alternatively, the area surrounded by the outer peripheral gate wiring 130 when viewed from above may be designated as the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the base region. Alternatively, the area surrounded by the well region when viewed from above may be designated as the active portion 160.

[0076] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum, etc.

[0077] An active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the deviation in wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0078] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 can be wiring formed from semiconductors such as polysilicon doped with impurities.

[0079] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 is arranged to extend from one outer peripheral gate wiring 130 sandwiching the active portion 160 to another outer peripheral gate wiring 130 in the X-axis direction, such that it crosses the active portion 160 approximately at the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, transistor portions 70 and diode portions 80 can be alternately arranged in the X-axis direction in each divided region.

[0080] The semiconductor device 100 may include a temperature sensing unit (not shown) and / or a current sensing unit (not shown), wherein the temperature sensing unit is a PN junction diode formed of polysilicon or the like, and the current sensing unit simulates the operation of the transistor unit provided in the active unit 160.

[0081] Viewed from above, the semiconductor device 100 of this example has an edge termination structure 90 between the active portion 160 and the edge 162. In this example, the edge termination structure 90 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a protective ring surrounding the active portion 160 in an annular shape, a field plate, and a surface electric field reduction structure.

[0082] Figure 2 yes Figure 1 An enlarged view of region D is shown. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 in this example includes an emitter 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter 52 and the active-side gate wiring 131 are disposed separately from each other. The emitter 52 is an example of an upper surface electrode.

[0083] An interlayer insulating film is provided between the emitter 52 and the upper surface of the semiconductor substrate 10, and between the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but... Figure 2 (Omitted). In this example, the interlayer insulating film has contact holes 54 provided in a manner that penetrates the interlayer insulating film. Figure 2 In the middle, the shading lines of the oblique lines marked on each contact hole 54 are shown.

[0084] An emitter 52 is disposed above the gate trench 40, the dummy trench 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Furthermore, the emitter 52 is connected to a dummy conductive portion within the dummy trench 30 through a contact hole disposed in the interlayer insulating film. The emitter 52 can be connected to the dummy conductive portion of the dummy trench 30 at its front end in the Y-axis direction.

[0085] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at the front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0086] The emitter 52 is formed of a material containing metal. Figure 2 The diagram shows the area where the emitter 52 is provided. For example, at least a portion of the emitter 52 is formed of aluminum or an aluminum-silicon alloy, such as AlSi, AlSiCu, or other metal alloys. The emitter 52 may have a barrier metal formed of titanium, titanium compounds, or the like in the layer beneath the area formed of aluminum or the like. Furthermore, it may also have a plug formed by embedding tungsten or the like in a contact hole in a manner that contacts the barrier metal and the aluminum or the like.

[0087] The well region 11 is disposed overlapping with the active-side gate wiring 131. The well region 11 also extends with a predetermined width in a region that does not overlap with the active-side gate wiring 131. In this example, the well region 11 is disposed separately from the end of the contact hole 54 in the Y-axis direction towards the active-side gate wiring 131. The well region 11 is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+ type.

[0088] The transistor section 70 and the diode section 80 each have a first direction (in Figure 2Multiple trench portions are arranged along the X-axis (in the middle direction). In the transistor section 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the X-axis. In the diode section 80 of this example, multiple dummy trench portions 30 are provided along the X-axis. In the diode section 80 of this example, no gate trench portion 40 is provided.

[0089] In this example, the gate trench portion 40 may have two straight portions 39 (the portion of the trench that is straight along the Y-axis direction) extending along the Y-axis direction perpendicular to the X-axis direction, and a front end portion 41 connecting the two straight portions 39. In this specification, one straight portion 39 is treated as a gate trench portion 40.

[0090] Preferably, at least a portion of the front end portion 41 is curved when viewed from above. The front end portion 41 is able to mitigate the electric field concentration at the ends of the two straight portions 39 by connecting their ends in the Y-axis direction to each other.

[0091] In the transistor section 70, dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. One dummy trench section 30 may be provided between each straight section 39, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a straight line shape extending in the Y-axis direction, and may also have a straight section 29 and a front end portion 31, similar to the gate trench section 40. In this specification, one straight section 29 is treated as one dummy trench section 30. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31 and a dummy trench portion 30 with a front end portion 31.

[0092] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located within the well region 11 when viewed from above. That is, at the Y-axis end of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0093] In the X-axis direction, mesa-shaped areas are provided between each trench portion. A mesa-shaped area refers to a region within the semiconductor substrate 10 that is held between trench portions. For example, the upper end of the mesa-shaped area is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped area has the same depth as the lower end of the trench portion. In this example, the mesa-shaped areas extend along the trench in the Y-axis direction on the upper surface of the semiconductor substrate 10. In this example, a mesa-shaped area 60 is provided in the transistor portion 70, and a mesa-shaped area 61 is provided in the diode portion 80. A boundary mesa-shaped area 64 can be provided at the boundary between the transistor portion 70 and the diode portion 80 when viewed from above. In the X-axis direction, the boundary between the cathode region 82 and the collector region 22 can be treated as the boundary between the transistor portion 70 and the diode portion 80. In this specification, when simply referred to as mesa-shaped areas, it refers to mesa-shaped area 60, mesa-shaped area 61, and boundary mesa-shaped area 64, respectively.

[0094] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 that is closest to the active-side gate wiring 131 is designated as base region 14-e. Figure 2 The diagram shows a base region 14-e disposed at one end of each isthmus in the Y-axis direction, but a base region 14-e is also disposed at the other end of each isthmus. In each isthmus, the area sandwiched between the base regions 14-e when viewed from above can be provided with at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 can be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0095] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is grounded to the gate trench portion 40. The mesa portion 60 connected to the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0096] The contact area 15 and the emission area 12 in the platform 60 are respectively provided from one groove portion to another in the X-axis direction. As an example, the contact area 15 and the emission area 12 of the platform 60 are alternately arranged along the length direction (Y-axis direction) of the groove portion.

[0097] In another example, the contact area 15 and the emission area 12 of the surface 60 can be arranged in a stripe pattern along the length direction (Y-axis direction) of the groove. For example, the emission area 12 is provided in the area that is in contact with the groove, and the contact area 15 is provided in the area sandwiched by the emission area 12.

[0098] The emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. On the upper surface of the mesa 61, in the area sandwiched between the base regions 14-e, a contact region 15 may be provided grounded to each of the base regions 14-e. On the upper surface of the mesa 61, in the area sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be disposed throughout the entire area sandwiched between the contact regions 15.

[0099] A contact hole 54 is provided above each stage surface. The contact hole 54 is disposed in the area sandwiched between the base regions 14-e. In this example, the contact hole 54 is disposed above each of the contact region 15, the base region 14, and the emitter region 12. In addition, the contact hole 54 is disposed in such a way that it penetrates the contact region 15 and the emitter region 12 and is connected to the base region 14. The contact hole 54 is not disposed in the region corresponding to the base region 14-e and the sink region 11. The contact hole 54 may be disposed at the center of the stage surface in the X-axis direction.

[0100] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in the region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are disposed between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. Figure 2 In the diagram, the boundary between the cathode region 82 and the collector region 22 is represented by a dashed line.

[0101] The cathode region 82 is disposed separately from the well region 11 in the Y-axis direction. Therefore, the P-type region (well region 11), which has a relatively high doping concentration and forms to a deep position, does not become a field-controlled drain (FWD) structure due to the presence of the collector region 22 directly below it. Thus, by ensuring a sufficient distance between the well region 11 and the cathode region 82, less carrier injection from the well region 11 is required when the FWD is turned on, thereby improving the dynamic breakdown voltage from turn-on to turn-off. In this example, the end of the cathode region 82 in the Y-axis direction is disposed further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0102] Figure 3 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter 52, and a collector 24 in this cross section.

[0103] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass with added impurities such as boron or phosphorus, a thermally oxidized film, and other insulating films. The interlayer insulating film 38 has a... Figure 2 Contact hole 54 as described in the text.

[0104] The emitter 52 is disposed above the interlayer insulating film 38. The emitter 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter 52 and the collector 24 is referred to as the depth direction.

[0105] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift regions 18 are respectively disposed in the transistor section 70 and the diode section 80.

[0106] On the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P-type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region 16 may be disposed on the mesa 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0107] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is grounded to the gate trench portion 40. The emitter region 12 can be connected to the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0108] The base region 14 is located below the transmitter region 12. In this example, the base region 14 is grounded to the transmitter region 12. The base region 14 can be connected to the grooves on both sides of the stage surface 60.

[0109] Accumulation region 16 is disposed below base region 14. Accumulation region 16 is an N-type region with a higher doping concentration than drift region 18. That is, the donor concentration of accumulation region 16 is higher than that of drift region 18. By providing a high-concentration accumulation region 16 between drift region 18 and base region 14, the carrier injection promotion effect (IE effect) can be improved, and the on-state voltage can be reduced. Accumulation region 16 can be disposed in such a way that it covers the entire lower surface of base region 14 in each mesa 60.

[0110] A P-type base region 14 is provided in the mesa 61 of the diode section 80, grounded to the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided in the mesa 61 between the base region 14 and the drift region 18.

[0111] In each of the transistor section 70 and the diode section 80, an N-type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 may have a concentration peak with a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 may be the average doping concentration in a region with a roughly flat doping concentration distribution.

[0112] The buffer 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer 20 may, for example, be set at the same depth as the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer 20 may function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0113] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0114] In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donors of the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0115] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. In various figures, the gate trench portion 40 is sometimes labeled with the symbol G, and the dummy trench portion 30 is sometimes labeled with the symbol E. Each trench portion extends from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and extends below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and accumulation region 16 is provided, each trench portion also extends through these doped regions. The trench portion extending through the doped region is not limited to the order in which the trench portion is formed after the doped region is formed. The case where the doped region is formed between the trench portions after the trench portion is formed is also included in the case where the trench portion extends through the doped region.

[0116] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In another example, a portion of the dummy trench section 30 of the diode section 80 can be replaced with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0117] The gate trench portion 40 includes a gate trench disposed on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position closer to the inner side of the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0118] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 at this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0119] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench disposed on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter 52. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0120] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0121] The diode section 80 includes one or more first lower end regions 201. In this example, the first lower end region 201 is a P-type region. Each first lower end region 201 is connected to the lower end of two or more trench sections (e.g., two or more dummy trench sections 30) arranged side by side in the X-axis direction. Each first lower end region 201 is provided covering the entire X-axis direction of at least one mesa section 61. At least one first lower end region 201 may be connected to the lower end of three or more trench sections. In this case, the first lower end region 201 is provided covering the entire X-axis direction of at least two mesa sections 61.

[0122] Each first lower region 201 is disposed at a first depth position Z1. The first lower region 201 being disposed at the first depth position Z1 means that the first lower region 201 has a portion disposed at the first depth position Z1. The first depth position Z1 can be the position where it connects to the lower end of the trench portion. The first depth position Z1 can be defined as the position where the doping concentration distribution in the depth direction of the first lower region 201 reaches its maximum value. The first lower region 201 can have a width in the depth direction (Z-axis direction). The width of the first lower region 201 in the depth direction can be 0.5 μm or more, 1 μm or more, 1.5 μm or more, or 2 μm or more. The width of the first lower region 201 in the depth direction can be measured at the position where it connects to the lower end of the trench portion, or at the center position in the X-axis direction of the mesa 61. The width of the first lower region 201 in the depth direction can be smaller than the width of the base region 14 in the depth direction. An N-type intermediate region is provided between the first lower region 201 and the base region 14. The doping concentration in the intermediate region can be higher than that in drift region 18. Figure 3 In this example, the accumulation zone 16 is the intermediate region. In other examples, a drift zone 18 can also be set as the intermediate region.

[0123] The doping concentration of the first lower region 201 can be lower or higher than that of the base region 14. The doping concentration of the first lower region 201 can be the same as that of the base region 14. The potential of the first lower region 201 can be different from that of the emitter 52. That is, the first lower region 201 can be floated relative to the emitter 52. The first lower region 201 may not be connected to either the base region 14 or the well region 11.

[0124] The diode section 80 includes one or more second lower end regions 202. The second lower end region 202 is disposed at a first depth position Z1 and at a position that does not overlap with the first lower end region 201 when viewed from above. The second lower end region 202 may be disposed side-by-side with the first lower end region 201 in the X-axis direction, side-by-side with the first lower end region 201 in the Y-axis direction, or side-by-side with the first lower end region 201 in other directions. The second lower end region 202 may also be disposed side-by-side with the first lower end region 201 in two directions in the XY plane. Figure 3 In the example, the first lower region 201 and the second lower region 202 are arranged side by side in the X-axis direction.

[0125] The second lower region 202 includes at least one of a region of a first conductivity type (N-type in this example) and a region of a second conductivity type (P-type in this example) with a lower doping concentration than the first lower region 201. Figure 3 In this example, the second lower region 202 is an N-type drift region 18 remaining at the first depth position Z1 of the diode section 80 where the first lower region 201 is not provided. The second lower region 202 can be an N-type region with a higher doping concentration than the drift region 18. The second lower region 202 can be an accumulation region 16 provided at the first depth position Z1. The width of the second lower region 202 in the depth direction can be the same as the width of the first lower region 201 in the depth direction.

[0126] Each second lower end region 202 may be connected to the lower end of two or more trench portions arranged side-by-side in the X-axis direction. These two or more trench portions may include dummy trench portions 30 or gate trench portions 40. The second lower end region 202 disposed on the diode portion 80 may be connected to the lower end of two or more dummy trench portions 30. At least one second lower end region 202 may be connected to the lower end of a single trench portion. Each second lower end region 202 may be disposed covering the entire X-axis direction of at least one mesa portion 61, or may be disposed on a portion of one mesa portion 61. At least one second lower end region 202 may be connected to the lower end of three or more trench portions. In this case, the second lower end region 202 is disposed covering the entire X-axis direction of at least two mesa portions 61.

[0127] Because the diode section 80 has a first lower end region 201, the electric field concentration at the lower end of the trench section connected to the first lower end region 201 can be mitigated. However, if the first lower end region 201 is provided, in the reverse conduction mode when the diode section 80 is conducting, the PN junction of the N-type region such as the accumulation region 16 and the first lower end region 201 is reverse biased. In this case, no current flows in the PN junction until at least one of the accumulation region 16 and the first lower end region 201 is completely depleted. Therefore, in the forward conduction characteristic (forward voltage-current characteristic) of the diode section 80, a sudden return of a large current is likely to occur after a predetermined trigger voltage is applied to the diode section 80, with a small current flowing until a predetermined trigger voltage is applied. In this regard, because the diode section 80 has a second lower end region 202, current easily flows through the second lower end region 202, thus suppressing the sudden return in the diode section 80.

[0128] When viewed from above, the area occupied by the first lower region 201 can be larger or smaller than the area occupied by the second lower region 202. The area occupied by the first lower region 201 can be the same as the area occupied by the second lower region 202. The area occupied by the second lower region 202 in the diode section 80 can be less than 75% or less of the area of ​​the diode section 80. The area occupied by the second lower region 202 in the diode section 80 can be more than 10% or more of the area of ​​the diode section 80.

[0129] In the diode section 80, a mesa 61 with a first lower end region 201 grounded to the lower ends of two adjacent trench sections is designated as a first mesa 61-1. That is, the first lower end region 201 is provided in the first mesa 61-1, extending throughout the entire X-axis direction. The diode section 80 may have one or more first mesa 61-1s.

[0130] In the diode section 80, a platform 61 with a second lower end region 202 disposed grounded to the lower ends of two adjacent trench sections is designated as a second platform 61-2. That is, the second lower end region 202 is provided in the second platform 61-2 throughout the entire X-axis direction. The diode section 80 may have one or more second platform 61-2s.

[0131] In this example, the first facet 61-1 and the second facet 61-2 are arranged side-by-side in the X-axis direction. The first facet 61-1 and the second facet 61-2 can be two facets 61 arranged adjacent to each other, or two facets 61 arranged separately. Since the diode section 80 has the first facet 61-1, the electric field concentration near the lower ends of the two trench sections sandwiching the first facet 61-1 can be mitigated. In addition, since the diode section 80 has the second facet 61-2, sudden backflow in reverse conduction mode is suppressed.

[0132] In the diode section 80, a third platform section 61 is provided as a platform section 61, which has a first lower end region 201 grounded to the lower end of one of the two adjacent trench sections and a second lower end region 202 grounded to the lower end of the other of the two adjacent trench sections. Both the first lower end region 201 and the second lower end region 202 are provided on the lower surface of the third platform section 61-3.

[0133] In this example, the first face unit 61-1, the second face unit 61-2, and the third face unit 61-3 are arranged side by side in the X-axis direction. A third face unit 61-3 may be arranged between the first face unit 61-1 and the second face unit 61-2.

[0134] At least one second faceplate 61-2 is connected to the emitter 52. The emitter 52 can be connected to the second faceplate 61-2 via a contact hole 54 in the interlayer insulating film 38. Thus, the second faceplate 61-2 can operate as a diode. All of the second faceplates 61-2 can be connected to the emitter 52.

[0135] At least one first faceplate 61-1 can be insulated from the emitter 52. That is, no contact hole 54 is provided in the interlayer insulating film 38 covering the first faceplate 61-1. No current flows in the first faceplate 61-1 that is not connected to the emitter 52. All the first faceplates 61-1 can be insulated from the emitter 52. In this case, backflow caused by the first faceplate 61-1 will not occur. By adjusting the ratio of the first faceplate 61-1 to the second faceplate 61-2, the amount of current flowing in the diode section 80 can be adjusted. At least one first faceplate 61-1 can be connected to the emitter 52. In this case, since the second faceplate 61-2 is provided, backflow can also be suppressed. In addition, the first faceplate 61-1 can be connected to the emitter 52 by remote contact. Remote contact means, for example, the first faceplate 61-1 is only connected to the emitter 52 by remote contact. Figure 2The base region 14-e at the end of the diode portion 80 is connected to the emitter 52 via a contact hole 54. Alternatively, the first facet 61-1 can also be connected to the emitter 52 via the contact hole 54 at constant intervals along the trench length direction (Y-axis direction). This constant interval can be, for example, more than 10 times, more than 20 times, or more than 30 times the width of the facet in the X-axis direction. The connection between the third facet 61-3 and the emitter 52 can be any of the methods described as the connection method between the first facet 61-1 and the emitter 52.

[0136] Above the boundary between the cathode region 82 and the collector region 22 in the X-axis direction, a boundary mesa 64 can be provided. The boundary mesa 64 can have the same structure as the first mesa 61-1, the same structure as the second mesa 61-2, or the same structure as the third mesa 61-3. Figure 3 In the example, the boundary platform 64 has the same structure as the first platform 61-1. That is, the boundary platform 64 is provided with a base region 14, an accumulation region 16, and a first lower end region 201.

[0137] By providing a first lower region 201 on the boundary mesa 64, hole injection from the boundary mesa 64 into the drift region 18 is suppressed. Holes can also be injected from the base region 14 of the transistor section 70 into the drift region 18 of the diode section 80. Therefore, sometimes excessive hole injection into the diode section 80 occurs. By suppressing hole injection from the boundary mesa 64, the amount of hole injection into the diode section 80 can be adjusted.

[0138] The boundary mesa 64 can be connected to the emitter 52. This allows for potential stabilization at the boundary between the transistor section 70 and the diode section 80. In the diode section 80, a third mesa 61-3 can be disposed between the boundary mesa 64 and the second mesa 61-2.

[0139] A first lower end region 201 may also be provided in the transistor section 70. The first lower end region 201 may be provided on the mesa 60 closest to the diode section 80 among the plurality of mesa sections 60 of the transistor section 70. That is, the lower surface of this mesa 60 may be covered by the first lower end region 201, which is connected to the lower ends of two adjacent trench sections. A first lower end region 201 may be provided connected to the lower ends of all trench sections of the transistor section 70. The first lower end region 201 may be provided throughout the entire X-axis direction of the transistor section 70. A second lower end region 202 may be provided in the transistor section 70. Because the first lower end region 201 is provided in the transistor section 70, the electric field concentration near the lower ends of the trench sections of the transistor section 70 can be mitigated.

[0140] The doping concentration of the first lower region 201 of the transistor section 70 can be the same as or different from the doping concentration of the first lower region 201 of the diode section 80. For example, the doping concentration of the first lower region 201 of the diode section 80 can be higher than that of the first lower region 201 of the transistor section 70. This further mitigates the electric field concentration near the lower end of the trench portion of the diode section 80. While increasing the doping concentration of the first lower region 201 of the diode section 80 may lead to a tendency for backlash to occur, in this example, the diode section 80 has a second lower region 202. Therefore, even if the doping concentration of the first lower region 201 of the diode section 80 is increased, the occurrence of backlash can be sufficiently suppressed. The doping concentration of the first lower region 201 of the diode section 80 can be more than twice, or more than five times, the doping concentration of the first lower region 201 of the transistor section 70.

[0141] Figure 4 This is a diagram showing another example of the ee cross-section. The configuration of the contact hole 54 of the semiconductor device 100 in this example is similar to... Figure 3 The examples differ. Other structures are different. Figure 3 The same applies to any of the methods described herein.

[0142] exist Figure 3 In this example, no contact hole 54 is provided for the first faceplate 61-1. In this example, at least one first faceplate 61-1 is connected to the emitter 52 via the contact hole 54. All first faceplates 61-1 can be connected to the emitter 52. When the first faceplate 61-1 is connected to the emitter 52, the base region 14, accumulation region 16, first lower end region 201, and drift region 18 provided in the first faceplate 61-1 and the region below it operate as thyristors.

[0143] If forward current flows through the second facet 61-2 in reverse conduction mode, the potential of the drift region 18 rises, or the base current flows through the NPN diode with the first lower region 201 as its base, and the thyristor becomes conductive. Thus, current can still flow in the region where the first facet 61-1 is located, and more current can flow through the diode section 80.

[0144] exist Figure 3 In this example, no contact hole 54 is provided for the third faceplate 61-3. In this example, at least one third faceplate 61-3 can be connected to the emitter 52 via the contact hole 54. All third faceplates 61-3 can be connected to the emitter 52. This allows more current to flow in the diode section 80.

[0145] Figure 5This is a diagram showing another example of the ee cross-section. In this example, the configuration of the contact hole 54 of the semiconductor device 100 relative to the boundary mesa 64 is... Figure 3 or Figure 4 The examples differ. Other structures are different. Figure 3 or Figure 4 The same applies to any of the methods described herein.

[0146] In this example, the boundary mesa 64 is insulated from the emitter 52. The other structures of the boundary mesa 64 are the same as those of the first mesa 61-1. This structure suppresses hole injection from the boundary mesa 64 and allows adjustment of the hole injection amount into the diode section 80. Furthermore, the boundary mesa 64 can make the aforementioned remote electrical contact with the emitter 52.

[0147] Figure 6 This is a diagram showing an example of the configuration of the first lower end region 201 and the second lower end region 202 in the diode section 80 in the X-axis direction. Figure 6 The XZ cross-section of the semiconductor substrate 10 is shown. Figure 6 In this design, the interlayer insulating film 38, emitter 52, and collector 24 are omitted. The structure, except for the configuration of the first lower region 201 and the second lower region 202, is similar to... Figures 3-5 The same applies to any of the methods described herein.

[0148] In this example, at least one second lower region 202 is configured to be sandwiched between two first lower regions 201 in the X-axis direction. Furthermore, at least one first lower region 201 is configured to be sandwiched between two second lower regions 202 in the X-axis direction. That is, the first lower regions 201 and the second lower regions 202 are configured alternately more than twice in the X-axis direction. By alternately configuring the first lower regions 201 and the second lower regions 202, the occurrence of sudden oscillations caused by the placement of the first lower regions 201 is easily suppressed.

[0149] At least one second faceplate 61-2 is configured to be sandwiched between two first faceplates 61-1 in the X-axis direction. Additionally, at least one first faceplate 61-1 is configured to be sandwiched between two second faceplates 61-2 in the X-axis direction. A third faceplate 61-3 may be configured between the first faceplates 61-1 and the second faceplates 61-2. By alternately and repeatedly configuring the first faceplates 61-1 and the second faceplates 61-2, the occurrence of sudden changes in the first faceplate 61-1 is easily suppressed.

[0150] Figure 7 This is a diagram showing an example of the configuration of the first lower end region 201 and the second lower end region 202 in the platform surface 61. Figures 3 to 6In this example, the first lower end region 201 and the second lower end region 202 are arranged side-by-side in the X-axis direction. In this example, the first lower end region 201 and the second lower end region 202 are arranged side-by-side in the Y-axis direction. This mitigates the electric field concentration near the lower end of the trench and suppresses the occurrence of sudden backlash. The structure, except for the Y-axis arrangement of the first lower end region 201 and the second lower end region 202, is similar to... Figures 1-6 The same applies to any of the methods described herein.

[0151] In all mesa sections 61 of the diode section 80, the first lower end region 201 and the second lower end region 202 can be arranged side-by-side in the Y-axis direction. In another example, in a portion of the mesa section 61 of the diode section 80, the first lower end region 201 and the second lower end region 202 can be arranged side-by-side in the Y-axis direction. For example, in... Figures 3-6 In the first facepiece 61-1 and the third facepiece 61-3 described herein, the first lower end region 201 and the second lower end region 202 can be arranged side by side in the Y-axis direction. That is, in Figures 3-6 The first lower region 201 described herein can be discretely arranged in the Y-axis direction. A second lower region 202 is provided in the region where the first lower region 201 is not provided. In the second mesa 61-2, the first lower region 201 may be omitted, while the second lower region 202 may be provided. In this case, the first lower region 201 and the second lower region 202 are arranged side by side in both the X-axis and Y-axis directions. This makes it easier to suppress the occurrence of sudden backsliding. In addition, in the mesa 64 of the boundary mesa 64 and the mesa 60 of the transistor section 70, the first lower region 201 and the second lower region 202 may also be arranged side by side in the Y-axis direction.

[0152] At least one second lower region 202 can be configured by being sandwiched between two first lower regions 201 in the Y-axis direction. Additionally, at least one first lower region 201 can be configured by being sandwiched between two second lower regions 202 in the Y-axis direction. That is, the first lower regions 201 and the second lower regions 202 can be alternately and repeatedly configured more than twice in the Y-axis direction. By alternately and repeatedly configuring the first lower regions 201 and the second lower regions 202, it is easy to suppress the occurrence of sudden retracements caused by the setting of the first lower regions 201. Figure 7 As shown, the platform surface 61 can be sandwiched between two well regions 11 in the Y-axis direction. The first lower end region 201 and the second lower end region 202 can be alternately arranged between the two well regions 11 in the Y-axis direction.

[0153] Above the platform 61 in this example, multiple contact holes 54 can be discretely arranged in the Y-axis direction. The distance Y1 between adjacent contact holes 54 in the Y-axis direction can be 10 μm or more, 100 μm or more, or 1000 μm or more. The distance Y1 can be less than half, less than 1 / 4, or less than 1 / 10 of the length of the platform 61 in the Y-axis direction. The distance Y1 can be greater than, less than, or the same as the length Y2 of a contact hole 54 in the Y-axis direction.

[0154] At least one second lower region 202 may have a portion that overlaps with the contact hole 54 when viewed from above. The second lower region 202 may be configured to cover the entire contact hole 54 when viewed from above. The first lower region 201 may have a portion that does not overlap with the contact hole 54 when viewed from above. The first lower region 201 may also be configured so that even a portion of it does not overlap with the contact hole 54 when viewed from above.

[0155] Figure 8 It is shown Figure 7 A diagram showing an example of the ff section. The ff section is the YZ plane of the dummy groove 30 opposite to the contact hole 54 in the X-axis direction. (See diagram for example.) Figure 8 As shown, the first lower end region 201 and the second lower end region 202 are alternately arranged in the Y-axis direction in such a way that they are connected to the lower end of the dummy groove portion 30.

[0156] Figure 9 It is shown Figure 7 A diagram showing an example of the gg section. The gg section is the YZ plane through the contact hole 54. As described above, at least one second lower end region 202 is configured to overlap with the contact hole 54. This facilitates the attraction of holes passing through the second lower end region 202 to the emitter 52, and facilitates current flow through the second lower end region 202. Therefore, it is possible to further suppress backflow.

[0157] A P+ type contact region 15 with a higher doping concentration than the base region 14 can be provided on the mesa 61. The contact region 15 and the base region 14 can be alternately arranged in the Y-axis direction. The contact region 15 is disposed between the base region 14 and the upper surface 21 of the semiconductor substrate 10. The contact region 15 is connected to the emitter 52 through a contact hole 54.

[0158] At least one second lower region 202 may have a portion that overlaps with the contact region 15 when viewed from above. All of the second lower regions 202 may have portions overlapping with the contact region 15. By providing the second lower region 202 below the contact region 15, holes passing through the second lower region 202 are easily attracted to the collector 24, facilitating current flow through the second lower region 202. Therefore, rapid backflow can be further suppressed.

[0159] Figure 10 This is a diagram showing other configuration examples of the contact hole 54 in the platform surface 61. The structure other than the contact hole 54 is similar to that in... Figures 1-9 The same applies to any of the methods described herein. In this example, the contact hole 54 is arranged to overlap with two or more second lower end regions 202 arranged in the Y-axis direction. For example... Figure 10 As shown, a single contact hole 54 may be provided on the platform surface 61, overlapping with the entire second lower end region 202 provided on the platform surface 61. In the platform surface 61, the first lower end regions 201 located at both ends in the Y-axis direction may or may not overlap with the contact hole 54. The contact hole 54 does not overlap with the well region 11.

[0160] Figure 11 It is shown Figure 10 A diagram illustrating an example of the hh section. The hh section is the YZ plane of a dummy groove 30 opposite a second lower end region 202 in the X-axis direction. (See diagram for example.) Figure 11 As shown, the first lower end region 201 and the second lower end region 202 are alternately arranged in the Y-axis direction in such a way that they are connected to the lower end of the dummy groove portion 30.

[0161] Figure 12 It is shown Figure 10 The diagram shows an example of the kk cross section. The kk cross section is the YZ plane passing through the first lower end region 201 and the second lower end region 202. In this example, the second lower end region 202 is configured to overlap with the contact hole 54. This facilitates the attraction of holes passing through the second lower end region 202 to the collector 24, and facilitates current flow in the second lower end region 202. Therefore, it is possible to further suppress backflow. In this example, it is also related to... Figure 9 Similarly, a contact area 15 overlapping with the second lower region 202 may be provided on the surface 61, or a contact area 15 overlapping with the second lower region 202 may not be provided.

[0162] Figure 13 This is a diagram showing an example of the equivalent circuit of the diode section 80. Figure 13The diagram shows the circuitry of the first facet 61-1, the second facet 61-2, and the regions below these facets. The second facet 61-2 is represented by a diode D and a resistor R. The diode D is a diode comprising a PN junction including a base region 14 and an accumulation region 16. The resistor R is the on-resistance component in the second lower region 202 and the drift region 18. Figure 4 As shown, in this example, the first faceplate 61-1 is connected to the emitter 52. In this case, the first faceplate 61-1 and the region below it operate as a thyristor. Figure 13 In this diagram, the thyristors are referred to as Tr1 and Tr2. Thyristor Tr1 is a PNP transistor comprising a base region 14, an accumulation region 16, and a first lower region 201. Thyristor Tr2 is an NPN transistor comprising an accumulation region 16, a first lower region 201, and a drift region 18. The base of thyristor Tr2 corresponds to the first lower region 201.

[0163] In this example, if a forward current flows through the second section 61-2, the base potential of the thyristor Tr2 rises due to the resistance R, and a base current is supplied to the thyristor Tr2. Consequently, the thyristor in the first section 61-1 becomes conductive, and current flows through the first section 61-1. Therefore, the current flowing through the diode section 80 can be increased.

[0164] Figure 14 This is a diagram illustrating an example of the forward conduction characteristics of the diode section 80. Figure 14 The horizontal axis represents the anode-cathode voltage Vak (V) of the diode section 80, and the vertical axis represents the anode-cathode current Iak (A) of the diode section 80. Figure 14 In the diagram, dashed lines represent characteristics of the comparative example, and solid lines represent characteristics of the embodiment. The diode section 80 of the comparative example is a first mesa 61-1 whose entire mesa 61 is covered by a first lower end region 201. The embodiment has… Figure 3 The diode section 80 of the structure shown.

[0165] like Figure 14 As shown in the comparative example, if all mesa sections 61 of the diode section 80 are designated as the first mesa section 61-1, the anode-cathode current Iak(A) is suppressed until the anode-cathode voltage Vak reaches the trigger voltage VBO due to the quick-return phenomenon. In the comparative example, a quick-return characteristic is exhibited where a large anode-cathode current Iak(A) flows after the anode-cathode voltage Vak reaches the trigger voltage VBO. In contrast, in this embodiment, by designating a portion of the mesa section 61 of the diode section 80 as the second mesa section 61-2, the quick-return characteristic seen in the comparative example is not exhibited, and the normal diode characteristics are observed.

[0166] Figure 15 This is a graph showing the relationship between the effective dose and the trigger voltage VBO in the first lower region 201. Figure 15 The horizontal axis represents the effective dose ( / cm²) of the first lower region 201. 2 The vertical axis represents the trigger voltage VBO (V) for the cyclic phenomenon. The effective dose of the first lower region 201 refers to the dose ( / cm²) of dopant ions (e.g., acceptor ions) per unit area in a direction parallel to the upper surface 21 of the semiconductor substrate 10 after the formation of the first lower region 201. 2 The amount of impurities (e.g., bulk donors) already present in the semiconductor substrate 10 per unit area ( / cm²) 2 The effective dose is obtained by multiplying the type and polarity of the impurity by the number of valence charges (electrons or holes) per unit ion, and then adding or subtracting the dose and the amount of impurity. For example, when both the dopant and the existing impurity have a valence charge of 1 per unit ion and opposite polarities (P-type and N-type), the effective dose is obtained by subtracting the amount of impurity from the dose of the dopant ions. The effective dose of the first lower region 201 can also be the net doping concentration ( / cm²) of the first lower region 201 in the depth direction. 3 The value is obtained by integration. When the first lower region 201 is formed in the trench through ion implantation and diffusion processes, the effective dose may differ from the dose from the ion implanter and the dose in the semiconductor immediately after implantation due to the shadow effect of the trench sidewall and diffusion. Figure 15 The effective dose is the value at each position of the first face 61-1, assuming that the distribution in the depth direction at each position of the first lower end region 201 in the X-axis direction other than the end is formed approximately uniformly.

[0167] exist Figure 15 In the diagram, dashed lines indicate the characteristics of the comparative examples, and solid lines indicate the characteristics of the embodiments. The structures of the comparative examples and embodiments are similar to those of the embodiments. Figure 14 The examples are the same. In the comparative example, when the effective dose exceeds 3.0 × 10⁻⁶. 11 / cm 2 At this time, the trigger voltage VBO increases according to the effective dose. However, in this embodiment, the trigger voltage VBO remains low regardless of the effective dose. That is, in this embodiment, no sudden return occurs regardless of the effective dose in the first lower region 201. Therefore, in this embodiment, the degree of freedom in setting the effective dose in the first lower region 201 can be increased.

[0168] The effective dose in the first lower region 201 can be 3×10 11 / cm 2The above describes how increasing the effective dose in the first lower region 201 can mitigate the electric field concentration near the lower end of the trench portion connected to the first lower region 201. In this embodiment, since a second lower region 202 is provided parallel to the first lower region 201, the electric field concentration near the lower end of the trench portion connected to the first lower region 201 can be mitigated. Figure 15 As shown, even increasing the effective dose of the first lower region 201 can suppress the sudden return. The effective dose of the first lower region 201 can be 5 × 10⁻⁶. 11 / cm 2 The above can also be 1×10 12 / cm 2 The above can also be 5×10 12 / cm 2 above.

[0169] The trigger voltage VBO corresponds to the voltage at which at least one of the first lower region 201 forming the PN junction and the accumulation region 16 is completely depleted. Therefore, as shown in the characteristics of the comparative example, the trigger voltage VBO varies according to the effective dose in the first lower region 201. If the width of the first lower region 201 in the depth direction is constant, and the doping concentration of the first lower region 201 is uniform in the depth direction, then even when the doping concentration of the first lower region 201 is uniform in the depth direction, the trigger voltage VBO will vary. Figure 15 When the horizontal axis is set as the doping concentration of the first lower region 201, the same characteristics can be obtained. However, the concentration distribution in the width and depth directions of the first lower region 201 can be varied. By specifying the amount of impurities in the first lower region 201 with an effective dose, the relationship between the amount of impurities and the trigger voltage VBO can be determined regardless of the shape of the concentration distribution in the width and depth directions of the first lower region 201.

[0170] Figure 16 This is a diagram illustrating an example of the forward conduction characteristics of the diode section 80. Figure 16 The axes in the graph are linearly scaled and labeled with... Figure 14 The markers are the same. Figure 16 In the middle, it is shown with solid lines. Figure 3 The features of the illustrated embodiment are shown in dashed lines. Figure 4 The characteristics of the illustrated embodiment. As in Figure 13 As explained in, in Figure 4 In the illustrated embodiment, the first facepiece 61-1 operates as a thyristor. Therefore, as Figure 16 As shown, in Figure 4 In the embodiments, with Figure 3 Compared to the previous embodiment, the anode-cathode current Iak flowing in the diode section 80 can be increased.

[0171] Figure 17 This is a diagram illustrating the effective dose in the first lower region 201. Figure 17It shows Figure 3 The net doping concentration distribution at the mm line is shown. In this example, the doping concentration distribution could be, for example, the carrier concentration distribution measured by the SR method using a monitoring wafer with a large first lower region 201, or a process monitoring region. The doping concentration distribution can be calculated by obtaining the SIMS distribution from the opposite side of the emitter-anode side after thinning the monolithized finished product from the cathode side. The mm line is a line parallel to the Z-axis at the lower end of the trench portion connected to the first facet 61-1. Figure 17 The horizontal axis indicates the depth position in the semiconductor substrate 10, and the vertical axis indicates the net doping concentration.

[0172] In this example, the upper position of the first lower region 201 is the first depth position Z1, and the lower position of the first lower region 201 is the second depth position Z2. The second depth position Z2 is the position of the PN junction interface between the first lower region 201 and the drift region 18. The second depth position Z2 can be the position where the doping concentration between the first lower region 201 and the drift region 18 reaches a minimum value.

[0173] Figure 17 The area of ​​the shaded region marked with a diagonal line represents the effective dose. The effective dose can be obtained by integrating the doping concentration from the first depth position Z1 to the second depth position Z2.

[0174] In this example, the mm line passes through the lower end of the trench portion, but in other examples, the mm line may also pass through the center of the first face portion 61-1 in the X-axis direction. In this case, the upper end position of the first lower end region 201 may be the position of the PN junction interface between the first lower end region 201 and the accumulation region 16. If a drift region 18 is provided instead of the accumulation region 16, the upper end position of the first lower end region 201 may be the position of the PN junction interface between the first lower end region 201 and the drift region 18 disposed above the first lower end region 201. In these cases, the effective dose may also be the value obtained by integrating the doping concentration from the upper end position to the lower end position of the first lower end region 201.

[0175] Figure 18 It is shown Figure 2 Another example of the ee cross-section is shown in the figure. In this example, the semiconductor device 100 has a P-type region as a second lower region 202 with a lower doping concentration than the first lower region 201. Other structures are similar to... Figures 1 to 17The same applies to any of the methods described herein. In this example, the second lower end region 202 also allows current to flow more easily than the first lower end region 201. Therefore, it is possible to suppress the backflow in the diode section 80. In addition, by providing a P-type region as the second lower end region 202, it is possible to mitigate the electric field concentration near the lower end of the trench section connected to the second lower end region 202. The second lower end region 202 may also have Figure 3 The N-type region and as shown Figure 18 The P-shaped regions shown are both. For example, the second lower region 202 may have [a certain feature] in the portion that connects with the first lower region 201. Figure 18 The P-shaped region shown has the following characteristics in the portion sandwiched by the P-shaped region: Figure 3 The N-type region shown.

[0176] The effective dose in the second lower region 202 can be less than 3.0 × 10⁻⁶. 11 / cm 2 .like Figure 15 As shown, even when an effective dose of less than 3.0 × 10 is placed below the platform 61, 11 / cm 2 In the P-type region, no sudden return will occur. Therefore, by making the effective dose of the second lower region 202 less than 3.0 × 10⁻⁶, 11 / cm 2 It can suppress sudden return. The effective dose of the second lower region 202 can be 1.0 × 10⁻⁶. 11 / cm 2 The following can also be 5.0×10 10 / cm 2 The effective dose in the second lower region 202 can be 1.0 × 10⁻⁶. 10 / cm 2 above.

[0177] The effective dose in the second lower region 202 and in Figure 17 Similarly, the example described can be obtained by integrating the doping concentration in the depth direction at the mm line. The mm line can pass through the lower end of the trench portion connected to the second face 61-2, or through the center in the X-axis direction of the second face 61-2.

[0178] exist Figures 1 to 18In the manufacturing process of the semiconductor device 100 described herein, after forming the trench portions of each trench portion and before forming the dummy insulating film 32 and the dummy conductive portion 34 (or the gate insulating film 42 and the gate conductive portion 44), dopant ions can be implanted from the lower end of the trench portion to form a first lower end region 201. By performing heat treatment after implanting the dopant ions, the dopant implanted into the lower end of each trench portion diffuses in the X direction, and a first lower end region 201 spanning two or more trench portions can be formed. In another example, dopant ions can also be implanted from the upper surface of the semiconductor substrate 10 into the entire area where the first lower end region 201 is to be formed before forming the trench portion. In the case where an N-type region is provided as a second lower end region 202, P-type dopant ions can be selectively implanted within the area where the first lower end region 201 is to be formed, thereby using the remaining drift region 18 as the second lower end region 202. In another example, after implanting P-type dopant ions over the entire area where the first lower region 201 and the second lower region 202 are to be formed, N-type dopant ions can be reverse-doped over the area where the second lower region 202 is to be formed, thereby forming an N-type second lower region 202. Alternatively, when a P-type region is provided as the second lower region 202, P-type dopant ions can be selectively implanted into the regions of the first lower region 201 and the second lower region 202 at different doses. In another example, after implanting dopant ions at a uniform dose over the entire area where the first lower region 201 and the second lower region 202 are to be formed, P-type dopant ions can be additionally implanted over the area where the first lower region 201 is to be formed.

[0179] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As clearly understood from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0180] It should be noted that the execution order of actions, sequences, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specification, and drawings can be implemented in any order, unless explicitly stated as "before" or "earlier," and as long as the results of previous processes are not used in subsequent processes. Regarding the flow of actions in the claims, specification, and drawings, although terms such as "firstly" and "next" are used for convenience, this does not imply that the actions must be performed in that order.

Claims

1. A semiconductor device, characterized in that, The device includes a semiconductor substrate having an upper surface and a lower surface, a drift region of a first conductivity type being included between the upper surface and the lower surface, and a diode portion being disposed thereon. The diode section includes: A cathode region of a first conductivity type is disposed between the lower surface of the semiconductor substrate and the drift region, and has a higher doping concentration than the drift region. A base region of a second conductivity type is disposed between the upper surface of the semiconductor substrate and the drift region; Multiple trench portions are disposed from the upper surface of the semiconductor substrate to a position lower than the base region, and are arranged side by side along a first direction on the upper surface of the semiconductor substrate; as well as The first lower end region of the second conductive type is disposed at a first depth position and is grounded to the lower ends of two or more of the trench portions; The second lower region is located at the first depth position and is positioned in a location that does not overlap with the first lower region. The second lower region includes at least one of a region of a first conductivity type and a region of a second conductivity type with a lower doping concentration than the first lower region.

2. The semiconductor device according to claim 1, characterized in that, The effective dose obtained by integrating the doping concentration of the first lower region along the depth direction is 3 × 10⁻⁶. 11 / cm 2 above.

3. The semiconductor device according to claim 1, characterized in that, The second lower region is a region of the first conductivity type.

4. The semiconductor device according to claim 1, characterized in that, The second lower region is obtained by integrating the doping concentration along the depth direction, resulting in an effective dose of less than 3 × 10⁻⁶. 11 / cm 2 The region of the second conductivity type.

5. The semiconductor device according to claim 1, characterized in that, The diode portion further includes an intermediate region of a first conductivity type disposed between the first depth position and the base region.

6. The semiconductor device according to claim 5, characterized in that, The doping concentration in the intermediate region is higher than that in the drift region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The first lower region and the second lower region are arranged side by side in the first direction.

8. The semiconductor device according to claim 7, characterized in that, The diode portion also includes multiple mesa portions, each of which is held within the semiconductor substrate by two trench portions. The plurality of platform surfaces include: One or more first face sections, each having a first lower end region disposed in contact with the lower ends of two adjacent groove sections; and One or more second face sections, each having a second lower end region disposed in contact with the lower ends of two adjacent groove sections. The first faceplate and the second faceplate are arranged side by side in the first direction.

9. The semiconductor device according to claim 8, characterized in that, At least one of the second facepieces is configured to be sandwiched between two of the first facepieces in the first direction.

10. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes an upper surface electrode disposed above the upper surface of the semiconductor substrate. At least one of the second faceplates is connected to the upper surface electrode.

11. The semiconductor device according to claim 10, characterized in that, At least one of the first faceplates is insulated from the upper surface electrode.

12. The semiconductor device according to claim 10, characterized in that, At least one of the first faceplates is connected to the upper surface electrode.

13. The semiconductor device according to claim 8, characterized in that, The plurality of platform surfaces includes a third platform surface, which has a first lower end region disposed in contact with the lower end of one of the two adjacent groove portions, and a second lower end region disposed in contact with the lower end of the other of the two adjacent groove portions. The first faceplate, the second faceplate, and the third faceplate are arranged side by side along the first direction.

14. The semiconductor device according to claim 13, characterized in that, The third facepiece is positioned between the first facepiece and the second facepiece in the first direction.

15. The semiconductor device according to claim 8, characterized in that, The semiconductor substrate also includes a transistor portion, which is arranged side-by-side with the diode portion in the first direction, and a collector region of a second conductivity type is provided on the lower surface of the semiconductor substrate. The transistor section includes a plurality of said mesa sections. The first lower region is provided on the mesa closest to the diode portion among the plurality of mesa portions of the transistor portion.

16. The semiconductor device according to claim 15, characterized in that, The semiconductor device also includes: A boundary mesa portion, disposed on the semiconductor substrate and positioned above the boundary between the cathode region and the collector region in the first direction; and An upper surface electrode is disposed above the upper surface of the semiconductor substrate. The boundary platform is the first platform connected to the upper surface electrode.

17. The semiconductor device according to claim 15, characterized in that, The semiconductor device also includes: A boundary mesa portion, disposed on the semiconductor substrate and positioned above the boundary between the cathode region and the collector region in the first direction; and An upper surface electrode is disposed above the upper surface of the semiconductor substrate. The boundary platform is the first platform that is insulated from the upper surface electrode.

18. The semiconductor device according to claim 15, characterized in that, The doping concentration of the first lower region of the transistor portion is different from the doping concentration of the first lower region of the diode portion.

19. The semiconductor device according to any one of claims 1 to 5, characterized in that, Each of the trench portions has a length on the upper surface of the semiconductor substrate in a second direction different from the first direction. The first lower region and the second lower region are arranged side by side in the second direction.

20. The semiconductor device according to claim 19, characterized in that, At least one of the second lower regions is configured to be sandwiched between the first lower region in the second direction.

21. The semiconductor device according to claim 19, characterized in that, The semiconductor device also includes: An upper surface electrode, disposed above the upper surface of the semiconductor substrate; and An interlayer insulating film is disposed between the upper surface electrode and the semiconductor substrate, and has contact holes for connecting the upper surface electrode and the semiconductor substrate. At least one of the second lower end regions has a portion that overlaps with the contact hole when viewed from above.

22. The semiconductor device according to claim 19, characterized in that, The diode portion further includes a contact region of a second conductivity type, which is disposed between the base region and the upper surface of the semiconductor substrate, and has a higher doping concentration than the base region. At least one of the second lower regions has a portion that overlaps with the contact area when viewed from above.

23. The semiconductor device according to claim 19, characterized in that, The first lower region and the second lower region are arranged side by side in the first direction and the second direction.

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