Shielded gate field effect transistor and method for manufacturing the same

Abstract

The present invention discloses a shielded gate field effect transistor and a preparation method, belonging to the field of semiconductor technology. The shielded gate field effect transistor comprises: a substrate layer; an epitaxial layer; a body region; a first trench; a source region; a second trench; and a Schottky contact barrier metal. The present invention integrates a Schottky barrier diode in a shielded gate field effect transistor, that is, a plurality of second trenches are arranged next to the shielded gate field effect transistor, and a gate structure is arranged in each second trench. When the shielded gate field effect transistor is powered on, the Schottky contact barrier metal, the gate structure and the epitaxial layer of the first conductivity type distributed around the gate structure are short-circuited to form a MOS structure shielding electric field, thereby reducing the reverse leakage current of the Schottky diode, thereby effectively reducing the conduction voltage of the freewheeling diode, and further reducing the conduction loss.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a shielded gate field effect transistor and a preparation method thereof. Background Art

[0002] Shielded gate field effect transistors play an indispensable role in the field of semiconductor technology and are crucial to the development of integrated circuit design, electronic device manufacturing and semiconductor technology. However, due to the high complexity of the field of semiconductor technology, the parasitic diode of the traditional shielded gate trench field effect transistor is a PN junction diode composed of its P-type body base region and N-type epitaxial layer, which has a high turn-on voltage problem.

[0003] Therefore, how to turn on the diode with a lower turn-on voltage to effectively reduce the turn-on voltage of the freewheeling diode of the shielded gate trench field effect transistor and reduce the conduction loss of the freewheeling diode has become an urgent problem to be solved. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a shielded gate field effect transistor and a method for preparing the same, in order to solve the problem that the parasitic diode of the current shielded gate trench field effect transistor is a PN junction diode composed of its P-type body base region and N-type epitaxial layer, and has a high turn-on voltage.

[0005] In a first aspect, an embodiment of the present application provides a shielded gate field effect transistor and a method for manufacturing the same, including:

[0006] a substrate layer of a first conductivity type;

[0007] An epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer;

[0008] A body region of a second conductivity type, the body region being located on a first region on the epitaxial layer;

[0009] a plurality of first trenches, each of which penetrates the body region in a depth direction and extends into a first region on the epitaxial layer, each of which is provided with a shielding gate structure and a control gate structure, and the control gate structure is located above the shielding gate structure;

[0010] a source region of a first conductivity type, the source region being located on the body region;

[0011] a plurality of second trenches, each of which extends into a second region on the epitaxial layer along a depth direction, and each of which is provided with a gate structure;

[0012] A Schottky contact barrier metal is located in the second region on the epitaxial layer and on each of the gate structures.

[0013] Optionally, the shielding gate structure includes: a first dielectric layer located on the first trench, and a first gate located on the first dielectric layer.

[0014] Optionally, the control gate structure includes: a second dielectric layer located on the shielding gate structure, and a second gate located on the second dielectric layer.

[0015] Optionally, the gate structure includes: a first dielectric layer located on the second trench, and a first gate located on the first dielectric layer.

[0016] Optionally, a metal hole is located on the body region, an ohmic contact barrier metal is arranged in the metal hole, and a hole-filling metal is located on the ohmic contact barrier metal, and the thickness of the ohmic contact barrier metal is less than the thickness of the Schottky contact barrier metal.

[0017] Optionally, an interlayer dielectric layer is located on the source region, the control gate structure and a portion of the second region on the epitaxial layer.

[0018] Optionally, a front metal and a back metal, the front metal is located on the interlayer dielectric layer, the ohmic contact barrier metal, the hole filling metal and the Schottky contact barrier metal, and the back metal is located below the substrate layer.

[0019] In a second aspect, an embodiment of the present application provides a method for preparing a shielded gate field effect transistor, comprising:

[0020] providing a substrate layer of a first conductivity type;

[0021] forming an epitaxial layer of a first conductivity type on the substrate layer;

[0022] forming a plurality of first trenches in a first region on the epitaxial layer, and forming a plurality of second trenches in a second region on the epitaxial layer;

[0023] forming a shielding gate structure in the first trench; forming a gate structure in the second trench; forming a control gate structure in the first trench, wherein the control gate structure is located above the shielding gate structure;

[0024] forming a body region of a second conductivity type in the first region on the epitaxial layer, so that the first trench penetrates the body region in a depth direction and extends into the first region on the epitaxial layer;

[0025] forming a source region of a first conductivity type on the body region;

[0026] forming an interlayer dielectric layer on the source region, the control gate structure and a second region on a portion of the epitaxial layer;

[0027] Forming a metal hole inside the interlayer dielectric layer, part of the source region, and part of the body region, wherein the metal hole is provided with an ohmic contact barrier metal and a hole-filling metal located on the ohmic contact barrier metal;

[0028] A Schottky contact barrier metal is formed on the gate structure and a second region on a portion of the epitaxial layer.

[0029] Optionally, forming a shield gate structure in the first trench and forming a gate structure in the second trench includes:

[0030] Growing a first dielectric layer on the inner wall of the first trench, depositing a first gate on the first dielectric layer, and etching a portion of the first gate and a portion of the first dielectric layer to obtain the shielding gate structure and the gate structure respectively;

[0031] A first dielectric layer is grown on the inner wall of the second trench, a first gate is deposited on the first dielectric layer, and a portion of the first gate and a portion of the first dielectric layer are etched to obtain the gate structure.

[0032] Optionally, forming a control gate structure in the first trench includes:

[0033] A second dielectric layer is grown on the shielding gate structure, a second gate is deposited on the second dielectric layer, and a portion of the second gate is etched to obtain the control gate structure.

[0034] Compared with the prior art, the embodiments of the present application have the following beneficial effects: by integrating a Schottky barrier diode in a shielded gate field effect transistor, that is, by setting a plurality of second grooves next to the shielded gate field effect transistor, each second groove is provided with a gate structure, and when the shielded gate field effect transistor is powered on, the Schottky contact barrier metal, the gate structure and the first conductive type epitaxial layer distributed around the gate structure are short-circuited to form a MOS structure shielding electric field, thereby reducing the reverse leakage current of the Schottky diode, thereby effectively reducing the conduction voltage of the freewheeling diode, and further reducing the conduction loss. In addition, since the turn-on voltage of the Schottky barrier diode integrated in the shielded gate field effect transistor is about 0.4V, the power consumption generated during reverse freewheeling is lower than that of a conventional shielded gate field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0036] Figure 1 A schematic diagram of a shielded gate field effect transistor structure provided by an embodiment of the present invention;

[0037] Figure 2 A flow chart of a method for preparing a shielded gate field effect transistor provided by one embodiment of the present invention;

[0038] Figure 3-Figure 30 It is a schematic diagram of the corresponding structure obtained in each preparation process of a shielded gate field effect transistor provided by an embodiment of the present invention;

[0039] Description of labels:

[0040] 101. substrate layer; 102. epitaxial layer; 103. body region; 104. first region; 105. first trench; 106. shielding gate structure; 107. control gate structure; 108. source region; 109. second trench; 110. second region; 111. gate structure; 112. Schottky contact barrier metal; 113. hard mask dielectric layer; 114. photoresist; 115. first dielectric layer; 116. first gate; 117. second dielectric layer; 118. second gate; 119. metal hole; 120. ohmic contact barrier metal; 121. hole-filling metal; 122. interlayer dielectric layer; 123. front metal; 124. back metal; 125. contact hole; 127. MOS structure shielding electric field. DETAILED DESCRIPTION

[0041] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0042] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0043] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0044] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0045] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0046] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0047] It should be understood that the size of the serial numbers of the steps in the following embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0048] In order to illustrate the technical solution of the present application, a specific embodiment is provided below for illustration.

[0049] In one embodiment, if Figure 1 As shown, a shielded gate field effect transistor is provided, comprising:

[0050] A substrate layer 101 of a first conductivity type;

[0051] An epitaxial layer 102 of a first conductivity type, the epitaxial layer 102 being located on the substrate layer 101;

[0052] A body region 103 of a second conductivity type, the body region 103 being located on a first region 104 on the epitaxial layer 102;

[0053] A plurality of first trenches 105, each of which penetrates the body region 103 in the depth direction and extends to the first region 104 on the epitaxial layer 102, and each of which is provided with a shielding gate structure 106 and a control gate structure 107, wherein the control gate structure 107 is located above the shielding gate structure 106;

[0054] A source region 108 of a first conductivity type, the source region 108 being located on the body region 103;

[0055] A plurality of second trenches 109 , each of which extends along a depth direction into a second region 110 on the epitaxial layer 102 , and a gate structure 111 is disposed in each of the second trenches 109 ;

[0056] The Schottky contact barrier metal 112 is located on the second region 110 on the epitaxial layer 102 and on each gate structure 111 .

[0057] In the above-mentioned shielded gate field effect transistor, the substrate layer 101 is of the first conductivity type, which can be N-type or P-type. The ions doped in the substrate layer 101 are N-type heavily doped ions, which can be aluminum ions, boron ions, indium (In), gallium (Ga), etc.

[0058] In the above shielded gate field effect transistor, the epitaxial layer 102 is of the first conductivity type, and the ions doped in the epitaxial layer 102 are N-type lightly doped ions, which may be nitrogen ions, phosphorus ions, and the like.

[0059] In the above-mentioned shielded gate field effect transistor, the body region 103 usually has a conductivity type opposite to that of the epitaxial layer 102. For example, in the N-type body region, doping materials such as phosphorus (P) are usually added, and in the P-type body region, doping materials such as boron (B) are usually added.

[0060] In the shielded gate field effect transistor described above, the first trench 105 is etched according to a preset shape, passes through the body region 103 of the semiconductor device, and extends to the inside of the epitaxial layer 102. The trench is usually formed by a manufacturing process such as photolithography or etching. Photolithography is used to define the shape of the trench, and etching is used to carve the trench into the semiconductor material along a preset direction. The depth and shape of the trench depend on the design of the device and the required function.

[0061] In the above shielded gate field effect transistor, the source region 108 is of N type, and its conductivity type is the same as that of the substrate layer 101 and the epitaxial layer 102 , which are both of the first conductivity type.

[0062] In the shielded gate field effect transistor described above, the second trench 109 is etched according to a preset shape, passes through the body region 103 of the semiconductor device, and extends to the inside of the epitaxial layer 102. For example, trenches are usually used to isolate different parts of the device and define the boundary or shape of the electronic component. In semiconductor devices, trenches are generally used to separate different electronic components to ensure that the electronic components do not interfere with each other.

[0063] In the above shielded gate field effect transistor, the Schottky contact barrier metal 112 can be grown by a method such as PVD physical vapor deposition to form a barrier layer metal.

[0064] In this embodiment, the epitaxial layer 102 is divided into a first region 104 on the left and a second region 110 on the right. A shielded gate field effect transistor structure is formed on the first region 104, and a Schottky barrier diode structure is formed on the second region 110, that is, the Schottky barrier diode structure is next to the shielded gate field effect transistor structure.

[0065] A shielded gate field effect transistor in an embodiment of the present application integrates a Schottky barrier diode in the shielded gate field effect transistor, that is, a plurality of second trenches 109 are arranged next to the shielded gate field effect transistor, and a gate structure 111 is arranged in each second trench 109. When the shielded gate field effect transistor is powered on, the Schottky contact barrier metal 112, the gate structure 111 and the first conductive type epitaxial layer 102 distributed around the gate structure 111 are short-circuited to form a MOS structure shielding electric field, thereby reducing the reverse leakage current of the Schottky diode, thereby effectively reducing the conduction voltage of the freewheeling diode, and further reducing the conduction loss. In addition, since the turn-on voltage of the Schottky barrier diode integrated in the shielded gate field effect transistor is about 0.4V, the power consumption generated during reverse freewheeling is lower than that of a conventional shielded gate field effect transistor.

[0066] In one embodiment, if Figure 1 As shown, the shielded gate structure 106 of the shielded gate field effect transistor includes: a first dielectric layer 115 located on the first trench 105 , and a first gate 116 located on the first dielectric layer 115 .

[0067] Specifically, the first dielectric layer 115 may be made of silicon dioxide, or polysilicon, metal, or other oxide materials. The first gate 116 may be made of polysilicon, metal, or other materials.

[0068] In a shielded gate field effect transistor according to an embodiment of the present application, the first dielectric layer 115 can reduce capacitance and increase or decrease withstand voltage, and the first gate 116 can control or adjust the conduction and cutoff of the electron channel by applying an appropriate electric field.

[0069] In one embodiment, if Figure 1As shown, the control gate structure 107 of the shielded gate field effect transistor includes: a second dielectric layer 117 located on the shielded gate structure 106 , and a second gate 118 located on the second dielectric layer 117 .

[0070] Specifically, a U-shaped second dielectric layer 117 is formed by growth, deposition, etc., and the second dielectric layer includes a bottom dielectric layer and two sidewall dielectric layers, wherein the second dielectric layer may be U-shaped or in other shapes. A second gate 118 is formed by chemical mechanical polishing, etching, etc., and the specific thickness and number of growth, deposition, chemical mechanical polishing, and etching may be determined according to the device that actually requires a voltage platform.

[0071] A shielded gate field effect transistor in an embodiment of the present application forms a control gate structure 107 by growth, deposition, chemical mechanical polishing, etching, etc., so as to obtain a structure and performance that meet design requirements in subsequent steps.

[0072] In one embodiment, if Figure 1 As shown, the gate structure 111 of the shielded gate field effect transistor includes: a first dielectric layer 115 located on the second trench 109 , and a first gate 116 located on the first dielectric layer 115 .

[0073] Specifically, the thickness of the first dielectric layer 115 is The thickness of the first gate 116 is For example, the thickness of the first dielectric layer 115 may be etc., the thickness of the first gate 116 can be Etc., the specific thickness is determined according to the device that actually requires a voltage platform.

[0074] A shielded gate field effect transistor according to an embodiment of the present application can form a MOS structure shielding electric field 127 in a subsequent step by providing a gate structure 111, thereby reducing the reverse leakage current of the Schottky diode.

[0075] In one embodiment, if Figure 1 As shown, the shielded gate field effect transistor is also provided with: a metal hole 119, the metal hole 119 is located on the body region 103, an ohmic contact barrier metal 120 is provided in the metal hole 119, and a hole filling metal 121 is located on the ohmic contact barrier metal 120, and the thickness of the ohmic contact barrier metal 120 is less than the thickness of the Schottky contact barrier metal 112.

[0076] Specifically, the shape of the metal hole 119 can be pre-designed according to the specific situation. The shape of the metal hole 119 can be a regular quadrilateral, or an irregular polygon, a circle, etc. The thickness of the ohmic contact barrier metal 120 is less than The annealing temperature is above 700°C, and the thickness of the hole-filling metal 121 is in the range of The thickness of the Schottky contact barrier metal 112 is greater than The annealing temperature is 500°C to 700°C. For example, the thickness of the hole-filling metal 121 is The thickness of the ohmic contact barrier metal 120 The thickness of the Schottky contact barrier metal 112 is

[0077] A shielded gate field effect transistor of an embodiment of the present application forms a low-resistance ohmic contact with silicon after annealing, and forms a Schottky contact barrier metal 112 after annealing, wherein the annealing temperature of the ohmic contact barrier metal 120 is above 700C, and the annealing temperature of the Schottky contact barrier metal 112 is 500C to 700C, that is, different annealing temperatures will have a certain impact on the contact resistance of the metal and the semiconductor. For the ohmic contact barrier metal 120, a small resistance is required, and the thicker the metal, the greater the resistance. For the Schottky contact barrier metal 112, a stable Schottky contact barrier is required. If the metal is too thin, the process is unstable, and the formed Schottky contact barrier is too low, it will cause a large reverse leakage. Therefore, the thickness of the ohmic contact barrier metal 120 is set to be less than the thickness of the Schottky contact barrier metal 112.

[0078] In one embodiment, if Figure 1 As shown, the shielded gate field effect transistor is further provided with an interlayer dielectric layer 122 , and the interlayer dielectric layer 122 is located on the source region 108 , the control gate structure 107 and a portion of the second region 110 on the epitaxial layer 102 .

[0079] Specifically, the interlayer dielectric layer 122 may be formed by CVD chemical vapor deposition, and the interlayer dielectric layer 122 may be made of silicon dioxide, silicon nitride, or other materials. For example, the thickness of the interlayer dielectric layer 122 is in the range of

[0080] A shielded gate field effect transistor according to an embodiment of the present application provides an interlayer dielectric layer 122 on the source region 108 , the control gate structure 107 and a second region 110 on a portion of the epitaxial layer 102 , so as to obtain a structure and performance that meet design requirements in subsequent steps.

[0081] In one embodiment, if Figure 1 As shown, the shielded gate field effect transistor is also provided with: a front metal 123 and a back metal 124 , the front metal 123 is located on the interlayer dielectric layer 122 , the ohmic contact barrier metal 120 , the hole filling metal 121 and the Schottky contact barrier metal 112 , and the back metal 124 is located below the substrate layer 101 .

[0082] Specifically, the materials of the front metal 123 and the back metal 124 can be aluminum, silicon, copper alloy, etc. For example, the front metal 123 and the back metal 124 can be grown by deposition, wherein the thickness of the front metal 123 is more than 4um, and the thickness of the back metal 124 is more than 1um.

[0083] In a shielded gate field effect transistor according to an embodiment of the present application, the front metal 123 and the back metal 124 are generally used to lead out electron flow so as to input or output current to the semiconductor device.

[0084] In one embodiment, if Figure 2 As shown, a method for preparing a shielded gate field effect transistor is provided, comprising the following steps:

[0085] Step S21, providing a substrate layer 101 of a first conductivity type;

[0086] like Figure 3 As shown, the first conductive type substrate layer 101 is an N-type heavily doped substrate with a doping concentration of 1e19-4e19. For example, the substrate layer 101 can be a semiconductor material such as silicon (Si) or silicon carbide (SiC).

[0087] Step S22, forming an epitaxial layer 102 of a first conductivity type on the substrate layer 101;

[0088] like Figure 3 As shown, the first conductivity type epitaxial layer 102 is an N-type low-doping concentration epitaxial layer 102. For example, the doping concentration of the epitaxial layer 102 is 1e15-1e17, and the specific doping concentration can be determined according to the device that actually requires a voltage platform.

[0089] Step S23, forming a plurality of first trenches 105 in the first region 104 on the epitaxial layer 102, and forming a plurality of second trenches 109 in the second region 110 on the epitaxial layer 102;

[0090] like Figure 4 As shown, a hard mask dielectric layer 113 is grown on the surface of the epitaxial layer 102, and the hard mask dielectric layer 113 is used as a barrier layer for subsequent etching of the first trench 105 and the second trench 109. For example, the growth range of the hard mask dielectric layer 113 can be The specific growth range can also be determined according to the actual trenches to be etched and the ratio of the dielectric layer to the gate to be etched when etching the trenches.

[0091] like Figure 5 As shown, photoresist 114 is coated on the hard mask dielectric layer 113 through a photolithography process to define the groove pattern to be etched. Figure 6As shown, the hard mask dielectric layer 113 of the exposed area is etched and the pattern is transferred to the hard mask dielectric layer 113. The photoresist 114 is removed and the trench is etched. Figure 7 As shown, a plurality of first trenches 105 and a plurality of second trenches 109 are formed. For example, the width of the etched trenches ranges from 0.2 um to 2 um.

[0092] Step S24, forming a shielding gate structure 106 in the first trench 105; forming a gate structure 111 in the second trench 109; forming a control gate structure 107 in the first trench 105, the control gate structure 107 being located above the shielding gate structure 106;

[0093] The specific process of forming the gate structure 111 is as follows:

[0094] like Figure 8 As shown, a first dielectric layer 115 is grown in the first trench 105 and the second trench 109. For example, the thickness of the first dielectric layer 115 is like Fig. 9 As shown, a first gate electrode 116 is deposited on the first dielectric layer 115. For example, the thickness of the first gate electrode 116 is like Fig.10 As shown, a portion of the first gate 116 is removed by chemical mechanical polishing. The first dielectric layer 115 is etched by CMP or etching. Fig.11 As shown, a gate structure 111 is formed in the second trench 109 .

[0095] The specific process of forming the shielding gate structure 106 is as follows:

[0096] A photoresist 114 is coated on the surface of the gate structure 111, and the first gate 116 in the first trench 105 is partially etched. Fig.12 As shown. For example, the etching depth ranges from 0.8um to 1um. The first dielectric layer 115 in the first trench 105 is partially etched. During the etching process, the etching depth of the first dielectric layer 115 in the first trench 105 is ensured to be the same as the etching depth of the first gate 116 in the first trench 105, so that the first dielectric layer 115 in the first trench 105 and the first gate 116 in the first trench 105 remain flush. For example, if the etching depth of the first gate 116 in the first trench 105 is 0.9um, the etching depth of the first dielectric layer 115 in the first trench 105 is also 0.9um, and then the photoresist 114 is removed to obtain the shielding gate structure 106 of the first trench 105, as shown in FIG. Fig.13 shown.

[0097] The specific process of forming the control gate structure 107 is as follows:

[0098] After obtaining the shielding grid structure 106, as Fig.14 As shown, a second dielectric layer 117 is grown on the shielding gate structure 106, and the thickness of the second dielectric layer 117 is like Fig.15 As shown, a second gate 118 is grown on the second dielectric layer 117, and the thickness of the second gate 118 is like Fig.16 As shown, a portion of the second gate 118 is removed by chemical mechanical polishing, so that the growth thickness of the second gate 118 on the shielding gate structure 106 is less than the growth thickness of the first gate 116 on the gate structure 111. A second dielectric layer 117 is grown on the surface of the second gate 118 to obtain a control gate structure 107, as shown in FIG. Fig.17 As shown, the depth of the control gate structure 107 is 0.8 um-1 um.

[0099] Step S25, forming a body region 103 of the second conductivity type in the first region 104 on the epitaxial layer 102, so that the first trench 105 penetrates the body region 103 along the depth direction and extends into the first region 104 on the epitaxial layer 102;

[0100] Specifically, after obtaining the shielding gate structure 106, the control gate structure 107 and the gate structure 111, as shown in FIG. Fig.18 As shown, firstly, a photoresist 114 is coated on the gate structure 111, and P-type ions are implanted downward from the surface of the first region 104, with the ion concentration being 1e17-1e18. The photoresist 114 is removed, and the implanted ions are activated by furnace annealing to form the body region 103, as shown in FIG. Fig.19 As shown, the depth of the body region 103 is 0.6 um-0.8 um, wherein the depth of the body region 103 is less than the depth of the control gate structure 107 .

[0101] Step S26, forming a source region 108 of the first conductivity type on the body region 103;

[0102] Specifically, firstly, a photoresist 114 is coated on the gate structure 111 and the second region 110, and the region where ions need to be implanted is defined on the body region 103 using the photoresist 114, and N-type ions are implanted downward from the surface of the first region 104, such as Fig. 20 The photoresist 114 is removed, and the implanted ions are activated by furnace annealing to form a source region 108, as shown in FIG. Fig.21 As shown. For example, the implanted ions may be arsenic ions or phosphorus ions. The depth of the source region 108 is about 0.1 um, and the ion concentration is 1e19-1e20.

[0103] Step S27, forming an interlayer dielectric layer 122 on the source region 108, the control gate structure 107 and a portion of the second region 110 on the epitaxial layer 102;

[0104] like Fig. 22 As shown, CVD chemical vapor deposition is used to grow silicon dioxide to form an interlayer dielectric layer 122. For example, the thickness of the interlayer dielectric layer 122 is

[0105] Step S28, forming a metal hole 119 inside the interlayer dielectric layer 122, a portion of the source region 108, and a portion of the body region 103, wherein the metal hole 119 is provided with an ohmic contact barrier metal 120 and a hole-filling metal 121 located on the ohmic contact barrier metal 120;

[0106] The specific process of forming the metal hole 119 is as follows:

[0107] First, a photoresist 114 is coated on the interlayer dielectric layer 122, and the pattern of the contact hole 125 to be etched above the body region 103 and the source region 108 is defined by the photoresist 114, and then etching is performed. Fig.23 As shown. The width of the contact hole 125 is 0.2um-0.4um. The photoresist 114 is removed, and silicon is further etched downward from the surface of the source region 108 to form the contact hole 125, as shown. Fig.24 As shown, for example, the etching depth exceeds the depth of the source region 108, and the depth of the contact hole 125 is 0.2um-0.4um.

[0108] Then, a barrier metal layer is grown on the contact hole 125 and the interlayer dielectric layer 122 by PVD physical vapor deposition, and after annealing, a low resistivity ohmic contact barrier metal 120 is formed with silicon. Fig.25 As shown. For example, the thickness of the ohmic contact barrier metal 120 is less than A layer of metal with strong step coverage capability is grown on the ohmic contact barrier metal 120 to form a hole-filling metal 121, such as Fig.26 As shown. For example, the thickness of the hole-filling metal 121 is Part of the hole-filling metal 121 is removed by CMP chemical mechanical polishing or etching to form a metal hole 119, such as Fig. 27 shown.

[0109] Step S29 , forming a Schottky contact barrier metal 112 on the gate structure 111 and a portion of the second region 110 on the epitaxial layer 102 .

[0110] After forming the metal hole 119, a photoresist 114 is coated on the interlayer dielectric layer 122 and the metal hole 119, wherein the coated photoresist 114 is a negative resist to form an inverted trapezoidal structure. The interlayer dielectric layer 122 on the gate structure 111 is etched, such as Fig.28Then, a barrier metal layer is grown on the photoresist 114 and the gate structure 111 by PVD physical vapor deposition, and then the photoresist 114 on the interlayer dielectric layer 122 and the metal hole 119 and the barrier metal layer on the photoresist 114 are removed by lift-off process, and annealed to form a Schottky contact barrier metal 112, as shown in FIG. Fig.29 shown.

[0111] The preparation method of this embodiment integrates a Schottky barrier diode in a shielded gate field effect transistor, that is, a plurality of second trenches 109 are arranged next to the shielded gate field effect transistor, and a gate structure 111 is arranged in each second trench 109. When the shielded gate field effect transistor is powered on, the Schottky contact barrier metal 112, the gate structure 111 and the first conductive type epitaxial layer 102 distributed around the gate structure 111 are short-circuited to form a MOS structure shielding electric field, thereby reducing the reverse leakage current of the Schottky diode, thereby effectively reducing the conduction voltage of the freewheeling diode, and further reducing the conduction loss. In addition, since the turn-on voltage of the Schottky barrier diode integrated in the shielded gate field effect transistor is about 0.4V, the power consumption generated during reverse freewheeling is lower than that of the conventional shielded gate field effect transistor.

[0112] In one embodiment, after forming the Schottky contact barrier metal 112, the method for preparing the shielded gate field effect transistor further includes:

[0113] Metal is deposited on the interlayer dielectric layer 122, the metal hole 119 and the Schottky contact barrier metal 112 to form a front metal 123. Metal is deposited below the substrate layer 101 to form a back metal 124, such as Fig.30 The thickness of the front metal 123 is greater than that of the back metal 124. For example, the thickness of the front metal 123 is greater than 4um, and the thickness of the back metal 124 is in the range of 1um-4um.

[0114] In one embodiment, forming the shielding gate structure 106 in the first trench 105 and forming the gate structure 111 in the second trench 109 includes:

[0115] A first dielectric layer 115 is grown on the inner wall of the first trench 105, a first gate 116 is deposited on the first dielectric layer 115, and a portion of the first gate 116 and a portion of the first dielectric layer 115 are etched to obtain a shielding gate structure 106 and a gate structure 111;

[0116] like Figure 8-Figure 13As shown, a first dielectric layer 115 is grown in the first trench 105 and the second trench 109, a first gate 116 is deposited on the first dielectric layer 115, and a portion of the first gate 116 is removed by chemical mechanical polishing. The first dielectric layer 115 is etched by chemical mechanical polishing or etching to obtain a gate structure 111 formed in the second trench 109. A photoresist 114 is coated on the surface of the gate structure 111, the first gate 116 in the first trench 105 is partially etched, the first dielectric layer 115 in the first trench 105 is partially etched, and the photoresist 114 is removed to obtain a shielding gate structure 106 of the first trench 105.

[0117] The preparation method of the embodiment of the present application is to grow a first dielectric layer 115 on the inner wall of the first trench 105, deposit a first gate 116 on the first dielectric layer 115, and etch a portion of the first gate 116 and a portion of the first dielectric layer 115 to obtain a gate structure 111 and a shielding gate structure 106.

[0118] In one embodiment, forming the control gate structure 107 in the first trench 105 includes:

[0119] A second dielectric layer 117 is grown on the shielding gate structure 106 , a second gate 118 is deposited on the second dielectric layer 117 , and a portion of the second gate 118 is etched to obtain the control gate structure 107 .

[0120] like Figure 14-17 As shown, a second dielectric layer 117 is grown on the shielding gate structure 106 , a second gate 118 is grown on the second dielectric layer 117 , a portion of the second gate 118 is removed by chemical mechanical polishing, and a second dielectric layer 117 is grown on the surface of the second gate 118 to obtain the control gate structure 107 .

[0121] The preparation method of the embodiment of the present application is to grow the second dielectric layer 117, deposit the second gate 118 on the second dielectric layer 117, and respectively etch a portion of the second gate 118 and a portion of the second dielectric layer 117 to obtain the control gate structure 107.

[0122] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A shielded gate field effect transistor, characterized in that: include: a substrate layer of a first conductivity type; An epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer; A body region of a second conductivity type, the body region being located on a first region on the epitaxial layer; a plurality of first trenches, each of which penetrates the body region in a depth direction and extends into a first region on the epitaxial layer, each of which is provided with a shielding gate structure and a control gate structure, and the control gate structure is located above the shielding gate structure; a source region of a first conductivity type, the source region being located on the body region; a plurality of second trenches, each of which extends into a second region on the epitaxial layer along a depth direction, and each of which is provided with a gate structure; A Schottky contact barrier metal, wherein the Schottky contact barrier metal is located in the second region on the epitaxial layer and on each of the gate structures; When the shielded gate field effect transistor is powered on, the Schottky contact barrier metal, the gate structure and the first conductivity type epitaxial layer distributed around the gate structure are short-circuited to form a MOS structure shielding electric field.

2. The shielded gate field effect transistor according to claim 1, wherein: The shielding gate structure includes: a first dielectric layer located on the first trench, and a first gate located on the first dielectric layer.

3. The shielded gate field effect transistor according to claim 1, wherein: The control gate structure includes: a second dielectric layer located on the shielding gate structure, and a second gate located on the second dielectric layer.

4. The shielded gate field effect transistor according to claim 1, wherein: The gate structure includes: a first dielectric layer located on the second trench, and a first gate located on the first dielectric layer.

5. The shielded gate field effect transistor according to claim 1, wherein: Also includes: A metal hole is located on the body region, an ohmic contact barrier metal is arranged in the metal hole, and a hole-filling metal is located on the ohmic contact barrier metal, and the thickness of the ohmic contact barrier metal is less than the thickness of the Schottky contact barrier metal.

6. The shielded gate field effect transistor according to claim 5, characterized in that: Also includes: An interlayer dielectric layer is located on the source region, the control gate structure and a portion of the second region on the epitaxial layer.

7. The shielded gate field effect transistor according to claim 6, wherein: Also includes: A front metal and a back metal, wherein the front metal is located on the interlayer dielectric layer, the ohmic contact barrier metal, the hole-filling metal and the Schottky contact barrier metal, and the back metal is located below the substrate layer.

8. A method for preparing a shielded gate field effect transistor, characterized in that: The following steps are involved: providing a substrate layer of a first conductivity type; forming an epitaxial layer of a first conductivity type on the substrate layer; forming a plurality of first trenches in a first region on the epitaxial layer, and forming a plurality of second trenches in a second region on the epitaxial layer; forming a shield gate structure in the first trench; forming a gate structure in the second trench; forming a control gate structure in the first trench, wherein the control gate structure is located above the shielding gate structure; forming a body region of a second conductivity type in the first region on the epitaxial layer, so that the first trench penetrates the body region in a depth direction and extends into the first region on the epitaxial layer; forming a source region of a first conductivity type on the body region; forming an interlayer dielectric layer on the source region, the control gate structure and a second region on a portion of the epitaxial layer; Forming a metal hole inside the interlayer dielectric layer, part of the source region, and part of the body region, wherein the metal hole is provided with an ohmic contact barrier metal and a hole-filling metal located on the ohmic contact barrier metal; A Schottky contact barrier metal is formed on the gate structure and a second region on a portion of the epitaxial layer. When the shielded gate field effect transistor is powered on, the Schottky contact barrier metal, the gate structure and the first conductive type epitaxial layer distributed around the gate structure are short-circuited to form a MOS structure shielding electric field.

9. The preparation method according to claim 8, characterized in that: Forming a shielding gate structure in the first trench and forming a gate structure in the second trench comprises: A first dielectric layer is grown on the inner wall of the first trench, a first gate is deposited on the first dielectric layer, and a portion of the first gate and a portion of the first dielectric layer are etched respectively to obtain the shielding gate structure and the gate structure.

10. The preparation method according to claim 8, characterized in that: Forming a control gate structure in the first trench includes: A second dielectric layer is grown on the shielding gate structure, a second gate is deposited on the second dielectric layer, and a portion of the second gate is etched to obtain the control gate structure.

Images