A driving circuit structure of a common cathode vertical cavity surface emitting laser array
Patent Information
- Application Number
- CN202311495808.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-10
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2043-11-10
AI Technical Summary
用户通过配置驱动电路Imod和Itotal电流源的电流值大小，从而间接配置VCSEL所需的偏置电流Ibias，配置过程较为繁琐
[0016]本发明将输入电压型差分信号转换成激光器VCSEL所需的调制电流和偏置电流信号，其两种电流信号可以分别由驱动器内置的两个电流源独立配置，有效降低配置过程的复杂度，配置过程中只需要一份Imod电流和一份Ibias电流，总消耗电流较小。
Smart Images
Figure CN117650426B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a driving circuit structure for a common cathode vertical cavity surface-emitting laser array. Background Technology
[0002] Optical modules are one of the core components of fiber optic communication systems, serving as the fundamental unit for data center interconnects, 5G bearer networks, and all-optical access networks. Optical transmission modules contain lasers, laser drivers, and various passive components. In short-distance, high-density optical interconnect applications, large data capacity, low threshold, small size, and low cost VCSEL arrays are typically chosen as the lasers for optical transmission modules.
[0003] For a VCSEL to function properly, the laser driver circuit must provide modulation and bias currents. The magnitudes of these currents determine two crucial parameters of the VCSEL: optical power and extinction ratio. To control these parameters, the modulation current Imod and bias current Ibias provided by the laser driver circuit must be configured by the user.
[0004] A typical driving circuit structure for driving a common-cathode VCSEL array is as follows: Figure 1As shown, this driving circuit provides the VCSEL with a modulation current Imod and a bias current Ibias, converting the input differential voltage signal (INP-INN) into the current signals Imod and Ibias required by the VCSEL. Its working principle is as follows: the circuit has a built-in configurable modulation current source Imod and a total current source Itotal. When the driving circuit is working, the differential input signals INP and INN control the on / off state of the differential input transistors QA and QB. If QA is off and QB is on, the modulation current source Imod draws current from the total current source through transistor QB, with the drawn current value being Imod. At this time, the current flowing into the VCSEL is Ibias = Itotal - Imod. If QA is on and QB is off, all the current provided by the total current source Itotal flows into the VCSEL, and the current obtained by the VCSEL is Itotal, i.e., Ibias + Imod. Therefore, the current provided by the driving circuit to the VCSEL switches back and forth between Ibias and Itotal, with the switching value being Imod. Users indirectly configure the bias current Ibias required by the VCSEL by configuring the current values of the Imod and Itotal current sources in the driver circuit, which is a rather cumbersome configuration process. Furthermore, because this driver circuit includes Itotal and Imod current sources, the total current consumption can reach a maximum of Itotal + Imod = (Ibias + Imod) + Imod, meaning it requires two Imod currents and one Ibias current, resulting in significant overall power consumption. Summary of the Invention
[0005] The purpose of this invention is to provide a driving circuit structure for a common cathode vertical cavity surface emission laser array. This driving circuit structure has built-in mutually independent configurable modulation current source Imod1 and bias current source Ibias1 to simplify the configuration process of modulation current and bias current and reduce total current consumption.
[0006] To solve the above technical problems, the present invention provides a driving circuit structure for a common cathode vertical cavity surface emission laser array, including: amplifier one, amplifier two, modulation current source, bias current source, resistor one, and NPN transistor one;
[0007] The non-inverting and inverting input terminals of amplifier one serve as the differential input terminals of the drive circuit; the output terminal of amplifier one is connected to the base of NPN transistor one; the collector of NPN transistor one is connected to one end of resistor one, and simultaneously to the non-inverting input terminal of amplifier two and the output terminal of the modulation current source; the emitter of NPN transistor one is grounded; the inverting input terminal of amplifier two is connected to the other end of resistor one, and simultaneously to the output terminal of the bias current source, serving as the output terminal of the drive circuit; the output terminal of amplifier two is connected to the power supply terminal of amplifier one; the input terminals of the modulation current source and the bias current source are both connected to the power supply.
[0008] Preferably, the amplifier one includes: a non-inverting input terminal, an inverting input terminal, an output terminal, an NPN transistor two, an NPN transistor three, a resistor two, a resistor three, and a tail current source one; the base of the NPN transistor two is the non-inverting input terminal; the collector of the NPN transistor two is connected to one end of the resistor two; the emitter of the NPN transistor two is connected to the emitter of the NPN transistor three, and is also connected to the input terminal of the tail current source one; the output terminal of the tail current source one is grounded; the base of the NPN transistor three is the inverting input terminal; the collector of the NPN transistor three is connected to one end of the resistor three, and also serves as the output terminal of the amplifier one; the other ends of the resistors two and three are connected to a power supply terminal.
[0009] Preferably, the amplifier two includes: a non-inverting input terminal, an inverting input terminal, an output terminal, NMOS transistors one, two, three, four, five, and six, PMOS transistors one, two, three, four, and five, a tail current source two, and a resistor four; the gate of NMOS transistor one is the inverting input terminal, the drain of NMOS transistor one is connected to the gate and drain of PMOS transistor one, and simultaneously connected to the gate of PMOS transistor three; the source of NMOS transistor one is connected to the input terminal of tail current source two, and simultaneously connected to the source of NMOS transistor two; the output terminal of the tail current source is grounded; the gate of NMOS transistor two is the non-inverting input terminal, the drain of NMOS transistor two is connected to the gate and drain of PMOS transistor two, and simultaneously connected to the PMOS transistor three. The gate of PMOS transistor 4; the sources of PMOS transistors 1, 2, 3, and 4 are all connected to the power supply; the drain of PMOS transistor 3 is connected to the gate and drain of NMOS transistor 3, and also to the gate of NMOS transistor 4; the drain of PMOS transistor 4 is connected to the drain of NMOS transistor 4; the sources of NMOS transistors 3, 4, and 5 are all grounded; the drains of PMOS transistor 4 and NMOS transistor 4 are connected to the gates of PMOS transistor 5 and NMOS transistor 6; the source of NMOS transistor 6 is connected to the source of PMOS transistor 5 and serves as the output terminal; the drain of NMOS transistor 6 is connected to one end of resistor 4, and the other end of resistor 4 is connected to the power supply; the drain of PMOS transistor 5 is connected to the gate and drain of NMOS transistor 5.
[0010] Preferably, the driving circuit consists of two parts: a data path and a feedback loop; wherein the data path consists of amplifier one, NPN transistor one, a modulation current source and a bias current source; and the feedback loop consists of amplifier two and resistor one.
[0011] Preferably, the DC component of the output signal of the amplifier and the DC operating point of the NPN transistor are both determined by the power supply voltage.
[0012] Preferably, the amplifier drives the NPN transistor, so that when the NPN transistor is turned on, the current allowed to flow into the NPN transistor is controlled by the power supply, and the magnitude of this current should be the modulation current.
[0013] Preferably, the current at the output of the driving circuit is the bias current or the sum of the bias current and the modulation current.
[0014] Preferably, when using this drive circuit, the user can directly configure independent modulation current and bias current.
[0015] Compared with the prior art, the present invention has the following beneficial effects:
[0016] This invention converts the input voltage-type differential signal into the modulation current and bias current signals required by the VCSEL laser. The two current signals can be independently configured by two current sources built into the driver, which effectively reduces the complexity of the configuration process. Only one Imod current and one Ibias current are needed during the configuration process, resulting in a small total current consumption. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a typical driving circuit structure for driving a common cathode VCSEL array.
[0018] Figure 2 This is a schematic diagram of the common cathode VCSEL array driving circuit provided by the present invention.
[0019] Figure 3 This is a schematic diagram of amplifier A1 in the common cathode VCSEL array driving circuit structure provided by the present invention.
[0020] Figure 4 This is a schematic diagram of amplifier A2 in the common cathode VCSEL array driving circuit structure provided by the present invention.
[0021] Figure 5 This is a schematic diagram illustrating the working principle of the common cathode VCSEL array driving circuit structure provided by the present invention. Detailed Implementation
[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0023] like Figure 2-5 As shown in the figure, this embodiment of the invention specifically provides a driving circuit structure for a common cathode vertical cavity surface-emitting laser array, the structure of which is as follows: Figure 2 As shown, it includes differential input terminals INP1 and INN1, output terminal VCSEL, amplifiers A1 and A2, modulation current source Imod1, bias current source Ibias1, resistor R1 and NPN transistor Q1;
[0024] The non-inverting input INP1 and inverting input INN1 of amplifier A1 are the differential inputs of the driver circuit. The output of amplifier A1 is connected to the base of NPN transistor Q1. The collector of NPN transistor Q1 is connected to the first terminal of resistor R1, and also to the non-inverting input of amplifier A2 and the output of the modulation current source. The emitter of NPN transistor Q1 is grounded to GND. The inverting input of amplifier A2 is connected to the second terminal of resistor R1, and also to the output of bias current source Ibias1, which is the output of the driver circuit, VCSEL. The output of amplifier A2 is connected to the power supply VC terminal of amplifier A1. The inputs of modulation current source Imod1 and bias current source Ibias1 are connected to the power supply VCC.
[0025] Please refer to the structure of amplifier A1. Figure 3 As shown, amplifier A1 includes differential input terminals INP1 and INN1, output terminal OUT1, NPN transistors Q2 and Q3, resistors R2 and R3, and tail current source I1; the base of transistor Q2 is the non-inverting input terminal INP1; the collector of transistor Q2 is connected to the first terminal of resistor R2; the emitter of transistor Q2 is connected to the emitter of transistor Q3, and also to the input terminal of tail current source I1; the output terminal of tail current source I1 is grounded to GND; the base of transistor Q3 is the inverting input terminal INN1; the collector of transistor Q3 is connected to the first terminal of resistor R3, this node is the output terminal OUT1 of amplifier A1; the second terminals of resistors R2 and R3 are connected to power supply VC.
[0026] Please refer to the structure of amplifier A2. Figure 4As shown, amplifier A2 includes differential input terminals INP2 and INN2, output terminal OUT2, NMOS transistors MN1-MN6, PMOS transistors MP1-MP5, tail current source I2, and resistor R4. The gate of NMOS transistor MN1 is the inverting input terminal INN2. The drain of MN1 is connected to the gate and drain of PMOS transistor MP1, and also to the gate of PMOS transistor MP3. The source of NMOS transistor MN1 is connected to the input terminal of current source I2, and also to the source of NMOS transistor MN2. The output terminal of current source I2 is grounded (GND). The gate of NMOS transistor MN2 is the non-inverting input terminal INP2. The drain of MN2 is connected to the gate and drain of PMOS transistor MP2, and also to the gate of PMOS transistor MP4. PMOS transistors MP1-MN6... All sources of MP4 are connected to the power supply VCC; the drain of PMOS transistor MP3 is connected to the gate and drain of NMOS transistor MN3, and also to the gate of NMOS transistor MN4; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4; the sources of NMOS transistors MN3 to MN5 are grounded to GND; the drains of PMOS transistor MP4 and NMOS transistor MN4 are connected to the gates of PMOS transistor MP5 and NMOS transistor MN6; the source of NMOS transistor MN6 and the source of PMOS transistor MP5 are connected together as the output terminal OUT2; the drain of NMOS transistor MN6 is connected to the first end of resistor R4, and the second end of resistor R4 is connected to the power supply VCC; the drain of PMOS transistor MP5 is connected to the gate and drain of NMOS transistor MN5.
[0027] The driving circuit structure of this invention consists of two parts: a data path and a feedback loop. The data path includes amplifier A1, NPN transistor Q1, modulation current source Imod1, and bias current source Ibias1. The feedback loop consists of amplifier A2 and resistor R1.
[0028] like Figure 5As shown, the output terminal of amplifier A2 is connected to the power supply voltage VC terminal of amplifier A1, meaning amplifier A2 provides the power supply voltage VC to amplifier A1. Therefore, the DC component of the output signal of amplifier A1 is determined by the power supply voltage VC. Furthermore, amplifier A1 drives transistor Q1. Therefore, the DC operating point of transistor Q1 is also determined by the voltage value of VC. Thus, when transistor Q1 is turned on, the current allowed to flow into Q1 is controlled by VC. This current value should be Imod. The reason is that the feedback loop utilizes the "virtual short circuit" principle at the differential input terminal of amplifier A2. A2 forces the voltage across resistor R1 to zero, meaning no current flows through R1. If part of the Ibias current flows into transistor Q1 through R1, the voltage value at the inverting input terminal of amplifier A2 will be higher than the voltage value at the non-inverting input terminal. The voltage value of VC at the output terminal of A2 will decrease, meaning the power supply voltage of amplifier A1 will decrease. Simultaneously, the DC component of the output signal of amplifier A1 decreases, thereby lowering the DC operating point of transistor Q1. The current flowing into transistor Q1 becomes smaller. Therefore, the feedback loop is used to suppress Ibias from flowing into transistor Q1 through resistor R1, so the current value of transistor Q1 is only Imod.
[0029] Amplifier A1 converts the input differential non-return-to-zero (NRZ) voltage signal into a single-ended NRZ voltage signal to drive NPN transistor Q1. If amplifier A1 outputs a high level, transistor Q1 conducts, and current Imod flows to ground through Q1, while current Ibias flows into the VCSEL. At this time, the current in the VCSEL is Ibias. If amplifier A1 outputs a low level, transistor Q1 is cut off, and current Imod flows into the VCSEL through resistor R1, while current Ibias flows directly into the VCSEL. At this time, the current in the VCSEL is Ibias + Imod.
[0030] Therefore, the current driving the VCSEL using this drive circuit structure is either Ibias or Ibias + Imod. Users can directly configure the independent modulation current Imod and bias current Ibias, effectively reducing the complexity of the configuration process. Furthermore, since the two current sources are independent, only one Imod current and one Ibias current are needed to meet the current requirements of the VCSEL, reducing the total current consumption of the circuit.
[0031] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A driving circuit structure for a common-cathode vertical-cavity surface-emitting laser array, characterized in that, include: Amplifier 1 (A1), Amplifier 2 (A2), Modulation current source (Imod1), Bias current source (Ibias1), Resistor 1 (R1), and NPN transistor 1 (Q1); The non-inverting input (INP1) and inverting input (INN1) of amplifier one (A1) are the differential inputs of the drive circuit; the output of amplifier one (A1) is connected to the base of NPN transistor one (Q1); the collector of NPN transistor one (Q1) is connected to one end of resistor one (R1), and simultaneously to the non-inverting input of amplifier two (A2) and the output of modulation current source (Imod1); the emitter of NPN transistor one (Q1) is grounded (GND); the inverting input of amplifier two (A2) is connected to the other end of resistor one (R1), and simultaneously to the output of bias current source (Ibias1), serving as the output of the drive circuit (VCSEL); the output of amplifier two (A2) is connected to the power supply (VC) of amplifier one (A1); the inputs of modulation current source (Imod1) and bias current source (Ibias1) are both connected to the power supply (VCC).
2. The driving circuit structure of a common-cathode vertical-cavity surface-emitting laser array as described in claim 1, characterized in that, The amplifier (A1) includes: a non-inverting input terminal (INP1), an inverting input terminal (INN1), an output terminal (OUT1), an NPN transistor (Q2), an NPN transistor (Q3), a resistor (R2), a resistor (R3), and a tail current source (I1); the base of the NPN transistor (Q2) is the non-inverting input terminal (INP1); the collector of the NPN transistor (Q2) is connected to one end of the resistor (R2); the output of the NPN transistor (Q2) is... The emitter is connected to the emitter of NPN transistor Q3, and also to the input terminal of tail current source I1; the output terminal of tail current source I1 is grounded (GND); the base of NPN transistor Q3 is the inverting input terminal (INN1); the collector of NPN transistor Q3 is connected to one end of resistor R3, and also serves as the output terminal (OUT1) of amplifier A1; the other ends of resistors R2 and R3 are connected to the power supply terminal (VC).
3. The driving circuit structure of a common-cathode vertical-cavity surface-emitting laser array as described in claim 1, characterized in that, The amplifier two (A2) includes: a non-inverting input terminal (INP2), an inverting input terminal (INN2), an output terminal (OUT2), NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6, PMOS transistors MP1, MP2, MP3, MP4, and MP5, a tail current source I2, and a resistor R4; the NMOS transistors... The gate of NMOS transistor MN1 is the inverting input terminal (INN2). The drain of NMOS transistor MN1 is connected to the gate and drain of PMOS transistor MP1, and also to the gate of PMOS transistor MP3. The source of NMOS transistor MN1 is connected to the input terminal of tail current source I2, and also to the source of NMOS transistor MN2. The output terminal of tail current source I2 is grounded (GND). The gate of NMOS transistor MN2 is the non-inverting input terminal (INP2), and the drain of NMOS transistor MN2 is connected to the gate and drain of PMOS transistor MP2. The source of each of the PMOS transistors (MP1, MP2, MP3, and MP4) is connected to the power supply (VCC). The drain of the PMOS transistor (MP3) is connected to both the gate and drain of the NMOS transistor (MN3), and also to the gate of the NMOS transistor (MN4). The drain of the PMOS transistor (MP4) is connected to the drain of the NMOS transistor (MN4). The NMOS transistors (MN3, MN4, and MN5) are connected to the gate of the NMOS transistor (MN5). The sources of the PMOS transistors are grounded together (GND); the drains of the PMOS transistor 4 (MP4) and the NMOS transistor 4 (MN4) are connected to the gates of the PMOS transistor 5 (MP5) and the NMOS transistor 6 (MN6); the source of the NMOS transistor 6 (MN6) is connected to the source of the PMOS transistor 5 (MP5) and serves as the output terminal (OUT2); the drain of the NMOS transistor 6 (MN6) is connected to one end of the resistor 4 (R4), and the other end of the resistor 4 (R4) is connected to the power supply (VCC); the drain of the PMOS transistor 5 (MP5) is connected to the gate and drain of the NMOS transistor 5 (MN5).
4. The driving circuit structure of a common-cathode vertical-cavity surface-emitting laser array as described in claim 1, characterized in that, The driving circuit consists of two parts: a data path and a feedback loop. The data path consists of amplifier one (A1), NPN transistor one (Q1), modulation current source (Imod1), and bias current source (Ibias1). The feedback loop consists of amplifier two (A2) and resistor one (R1).
5. The driving circuit structure of a common cathode vertical cavity surface-emitting laser array as described in claim 1, characterized in that, The DC component of the output signal of amplifier A1 and the DC operating point of NPN transistor Q1 are both determined by the voltage value of the power supply terminal (VC).
6. The driving circuit structure of a common cathode vertical cavity surface-emitting laser array as described in claim 5, characterized in that, The amplifier (A1) drives the NPN transistor (Q1), so that when the NPN transistor (Q1) is turned on, the current allowed to flow into the NPN transistor (Q1) is controlled by the power supply terminal (VC), and the magnitude of this current should be the modulation current (Imod).
7. The driving circuit structure of a common-cathode vertical-cavity surface-emitting laser array as described in claim 6, characterized in that, The current at the output terminal (VCSEL) of the drive circuit is either the bias current (Ibias) or the sum of the bias current (Ibias) and the modulation current (Imod).
8. The driving circuit structure of a common-cathode vertical-cavity surface-emitting laser array as described in claim 7, characterized in that, When using this driver circuit, users can directly configure the modulation current (Imod) and bias current (Ibias) that are independent of each other.