A non-isolated resonant gate drive circuit

Abstract

This invention provides a non-isolated resonant gate drive circuit, including a PMOS drive network, an NMOS clamping circuit, and an inductor. The PMOS drive network and the NMOS clamping circuit are both connected in parallel across the inductor. The input signal to the PMOS drive network is provided by a function generator followed by a driver chip. After processing by the PMOS drive network, the NMOS clamping circuit, and the inductor, the input signal is output from port v. gsr1 and output port v gsr2 The output drive signal and the NMOS clamping circuit are used to control the output port v. gsr1 and output port v gsr2 The state changes, and the inductor is connected to the gate capacitor C in the NMOS clamping circuit. gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover the energy from the turn-off process of the drive circuit for use during the turn-on process. This invention uses fewer components, saving cost and space, and is beneficial for miniaturization and integration. Furthermore, the control signal of this invention is simple, reducing its complexity and improving system stability.

Description

Technical Field

[0001] This invention belongs to the field of power transistor driving technology, specifically relating to a non-isolated resonant gate driving circuit. Background Technology

[0002] The increased frequency of switching power supplies allows for the use of smaller inductors and capacitors, reducing the overall size of the power supply system and lowering production costs. However, high-frequency switching increases the proportion of switching losses of power transistors in the total system power loss, leading to a greater overall loss. Therefore, reducing the drive losses of power transistors has become a key issue for high-frequency switching power supplies in terms of reducing losses and increasing power density.

[0003] Traditional gate drive circuits dissipate energy in the resistance of the charging and discharging path. Resonant gate drive circuits are highly efficient drive circuits with energy recovery capabilities. In existing power transistor resonant gate drive technologies, a dual-channel resonant gate drive circuit uses four switching transistors and an inductor connected at the midpoint of the bridge arm. It can output two symmetrical drive signals and recover most of the energy, but requires four signals to control the switching transistors, making control signal matching difficult and reducing the stability of the output drive signal. A transformer-magnetically isolated resonant gate drive technology adds a transformer to the drive circuit, allowing the output drive signal to simultaneously drive both the upper and lower transistors of the half-bridge, achieving a floating ground function for the drive signal. However, the use of a transformer increases the circuit complexity and footprint. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of low energy recovery rate, large number of control signals, difficult signal matching, large area occupation, and unfavorable miniaturization of the above-mentioned driving technology, and to provide a non-isolated resonant gate driving circuit.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a non-isolated resonant gate drive circuit, comprising: a PMOS drive network, an NMOS clamping circuit and an inductor, wherein the PMOS drive network and the NMOS clamping circuit are both connected in parallel across the two ends of the inductor;

[0006] Wherein: the input signal of the PMOS driving network is provided by a function generator followed by a driving chip, and the input signal is processed by the PMOS driving network, NMOS clamping circuit and inductor before being output from the output port v. gsr1 and output port v gsr2 The output drive signal, the NMOS clamping circuit is used to control the output port v gsr1 and output port v gsr2 The state changes, and the inductor is connected to the gate capacitor C in the NMOS clamping circuit. gsr1 and gate capacitance C gsr2An LC resonance is formed to recover the energy from the turn-off process of the drive circuit for the turn-on process.

[0007] Furthermore, the PMOS driving network includes: a first PMOS transistor and a second PMOS transistor, the sources of both the first and second PMOS transistors are connected to the power supply Vcc, the gate of the first PMOS transistor is connected to the PWM1 output port of the driving chip connected after the function generator, the drain of the first PMOS transistor is connected to one end of an inductor, the gate of the second PMOS transistor is connected to the PWM2 output port of the driving chip connected after the function generator, and the drain of the second PMOS transistor is connected to the other end of the inductor.

[0008] Furthermore, the NMOS clamping circuit includes: a first NMOS transistor, a second NMOS transistor, and a gate capacitor C. gsr1 and gate capacitance C gsr2 The gate of the first NMOS transistor, the drain of the second NMOS transistor, the other end of the inductor, and the output port v gsr2 The drain and gate capacitance C of the second PMOS gsr2 One end is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, one end of the inductor, and the output port v. gsr1 The drain and gate capacitance C of the first PMOS transistor gsr1 One end is connected, and the source and gate capacitors of the first NMOS transistor are connected. gsr1 The other end is connected to GND, and the gate of the second NMOS transistor is connected to one end of the inductor and the output port v. gsr1 The drain and gate capacitance C of the first PMOS transistor gsr1 The connection is made between the drain of the second NMOS transistor and the other end of the inductor, and the output port v. gsr2 The drain and gate capacitance C of the second PMOS gsr2 One end is connected, and the source and gate capacitors of the second NMOS transistor are connected. gsr2 The other end is connected to GND, and the gate capacitor C gsr1 One end is connected to one end of the inductor and the output port v gsr1 and the drain connection of the first PMOS transistor, the gate capacitor C gsr2 One end is connected to the other end of the inductor, the output port v gsr2 And the drain connection of the second PMOS.

[0009] Furthermore, the output port v gsr1 The output port v is connected to one end of the inductor and the drain of the first PMOS transistor. gsr2 It is connected to the other end of the inductor and the drain of the second PMOS transistor.

[0010] Beneficial effects:

[0011] 1. The present invention has a small number of devices. The entire non-isolated resonant gate drive circuit consists of two PMOS transistors, two NMOS transistors and one inductor. The magnetic components only require an inductor and do not require a transformer, which saves cost and space and is conducive to miniaturization and integration.

[0012] 2. The control signal of the present invention is simple. Two square waves with the same frequency and duty cycle, with a phase difference of 180 degrees, are provided by the function generator and the driver chip to control the two PMOS drive transistors. The gates of the two NMOS transistors do not need to be controlled by external signals, which simplifies the complexity of the control signal and improves the system stability. Attached Figure Description

[0013] Figure 1 This is the circuit diagram of the present invention.

[0014] Figure 2 This is a block diagram of the control signals of the present invention.

[0015] Figure 3 This is a circuit diagram of an LLC DC transformer to which this invention applies.

[0016] Figure 4 This is the key waveform timing diagram of the circuit of this invention.

[0017] Figure 5 This is a simulation diagram of the key waveforms of the circuit of this invention.

[0018] Figure 6 These are the current loops of different modes of the circuit of this invention.

[0019] In the diagram: 1. PMOS driving network; 2. NMOS clamping circuit. Detailed Implementation

[0020] The invention will now be further explained with reference to the accompanying drawings.

[0021] like Figure 1 This invention provides a non-isolated resonant gate drive circuit including a PMOS drive network 1, an NMOS clamping circuit 2, and an inductor L. A function generator is connected to a drive chip to generate PWM1 and PWM2 input signals. The PWM1 input signal controls the first PMOS transistor Q1, and the PWM2 input signal controls the first PMOS transistor Q2. The phase difference between the PWM1 and PWM2 input signals is 180 degrees, and the frequency and duty cycle can be adjusted according to the driven circuit. The NMOS clamping circuit 2 enables the output drive signal to be at port v. gsr1 and v gsr2 The voltage output range is 0-Vcc. The NMOS clamping circuit also participates in the resonance process, making the output port V...gsr1 and v gsr2 The state changes; inductor L plays a role in the resonance and excitation process energy transfer in the non-isolated resonant gate drive circuit, and inductor L is connected to the gate capacitor C in the NMOS clamping circuit 2. gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover the energy from the turn-off process of the drive circuit for the turn-on process.

[0022] like Figure 2 This is the control signal input module of the present invention. The function generator provides square wave signals PWM1 and PWM2 with adjustable frequency and duty cycle. The two input signals are provided to the input port of the non-isolated resonant gate drive circuit through the driver chip: the gate of the first PMOS transistor Q1... g_Q1 The gate v of the second PMOS transistor Q2 g_Q2 .

[0023] like Figure 3 This invention relates to an LLC DC transformer, whose output signal can provide gate drive signals for the low-voltage side switching transistors and secondary side synchronous rectifier transistors of the primary full-bridge of the LLC DC transformer. Figure 1 The output signal v gsr1 and v gsr2 and Figure 3 gate signal v gs2 v gs4 or v gsr1 v gsr2 Correspondingly, the switching on and off of primary-side low-voltage side switches S2 and S4, and the rectification function of secondary-side switches SR1 and SR2, are controlled. Switches S1, S2, S3, and S4 constitute the full-bridge topology. r1 L r2 For the leakage inductance of the transformer, L m1 L m2 C is the magnetizing inductance of the transformer. r For resonant capacitance, S R1 S R2 For secondary-side synchronous rectifier diodes, C o For output capacitor, R L For load.

[0024] like Figure 4 ,This is Figure 1 The key waveform timing diagram of the circuit includes control signals, output voltage signals, and key currents. The first line is the gate control signal of the first PMOS transistor Q1, the second line is the gate control signal of the second PMOS transistor Q2, and the third line is the output port V. gsr1 and v gsr2The output drive signals, i1 in the fourth row is the current flowing through the first PMOS transistor Q1, i2 in the fourth row is the current flowing through the first PMOS transistor Q2, and i3 in the fifth row is the current flowing through the first NMOS transistor Q3 and its gate capacitor C. gsr1 The current, i4 in the fifth row, is the current flowing through the second NMOS transistor Q4 and its gate capacitor C. gsr2 The current, i in the sixth line L The current flowing through inductor 3 is such that the direction of the current is as follows: Figure 1 The direction marked in the middle indicates positive current.

[0025] like Figure 5 To follow the instructions on the SIMetrix software Figure 1 circuits and Figure 4 Simulation waveform diagram of control signal, simulation waveform and Figure 4 The analyzed waveform timing diagrams are identical, further verifying the feasibility of the circuit of the present invention.

[0026] like Figure 6 This is with Figure 4 The corresponding current loop diagrams for different time stages will be presented below in conjunction with... Figure 4 and Figure 6 To analyze the input port v of the non-isolated resonant gate drive circuit. g_Q1 v g_Q2 The signal changes generate eight different circuit modes.

[0027] During the period t0-t1, the gate capacitance C gsr2 The initial voltage across is Vcc, and the capacitor is C. gsr1 The initial voltage is zero, the first NMOS transistor Q3 is turned on, and the other three MOS transistors are turned off. The gate capacitance C gsr2 Resonance is formed with inductor L, and gate capacitance C gsr2 Discharging in a resonant manner, inductor L charging in a resonant manner, output port v gsr2 As the voltage drops, the current in the resonant inductor rises. Energy is transferred from the gate capacitance to the inductor until the gate capacitance C... gsr2 Complete discharge.

[0028] During the period t1-t2, the gate capacitance C gsr1 and C gsr2 The initial voltages on all transistors are zero. The second NMOS transistor Q4 is turned on, and the other three MOS transistors are turned off. The gate capacitance C gsr1 The inductor L resonates with the gate capacitance C, and the inductor L discharges in a resonant manner. gsr1 Charging via resonant method, output port v gsr1 As the voltage rises, the current in the resonant inductor decreases. Energy is transferred from the inductor L to the gate capacitance C. gsr1Up, until the gate capacitance C gsr1 The voltage rises to Vcc.

[0029] During the period t2-t3, the first PMOS transistor Q1 and the second NMOS transistor Q4 are turned on, and the gate capacitance C... gsr1 The voltage across the gate is maintained at Vcc, and the gate capacitor Cgsr2 remains at zero voltage, making the output port V... gsr1 Keep the output port V high. gsr2 Maintain a low level. The energy in inductor L is recovered by the power supply Vcc, and current flows to the power supply until the current decreases to zero.

[0030] During the period t3-t4, the switching state of the MOSFET and the output port voltage are the same as during the period t2-t3, but the current direction is reversed. The power supply Vcc charges the inductor, and the current flowing through the inductor increases until the first PMOS transistor Q1 is turned off.

[0031] During the period t4-t5, the gate capacitance C gsr1 The initial voltage across is Vcc, and the capacitor is C. gsr2 The initial voltage is zero, the second NMOS transistor Q4 is turned on, and the other three MOS transistors are turned off. The gate capacitance C gsr1 Resonance is formed with inductor L, and gate capacitance C gsr1 Discharging in a resonant manner, inductor L charging in a resonant manner, output port v gsr1 As the voltage drops, the current in the resonant inductor increases. Energy is transferred from the gate capacitance C. gsr1 The transfer continues onto inductor L until the gate capacitance C is reached. gsr1 Complete discharge.

[0032] During the period t5-t6, the gate capacitance C gsr1 and C gsr2 The initial voltages on all transistors are zero. The first NMOS transistor Q3 is turned on, and the other three MOS transistors are turned off. The gate capacitance C gsr2 The inductor L resonates with the gate capacitance C, and the inductor L discharges in a resonant manner. gsr2 Charging via resonant method, output port v gsr2 As the voltage rises, the current in the resonant inductor decreases. Energy is transferred from the inductor L to the gate capacitance C. gsr2 Up, until the gate capacitance C gsr2 The voltage rises to Vcc.

[0033] During the period t6-t7, the second PMOS transistor Q2 and the first NMOS transistor Q3 are turned on, and the gate capacitance C gsr2 The voltage is maintained at Vcc, and the gate capacitance is C. gsr1 Maintaining zero voltage at the output port v gsr2 Keep the output port V high.gsr1 Maintain a low level. The energy in inductor L is recovered by the power supply Vcc, and current flows to the power supply until the current decreases to zero.

[0034] During the period t7-t8, the switching state of the MOSFET and the output port voltage are the same as during the period t6-t7, but the current direction is reversed. The power supply Vcc charges the inductor, and the current flowing through the inductor increases until the second PMOS transistor Q2 is turned off.

[0035] In summary, this invention uses inductors to connect to the gate capacitor C in the NMOS clamping circuit. gsr1 and gate capacitance C gsr2 By forming an LC resonance, energy recovery is achieved, driving losses are greatly reduced, and the output driving signal provided can be used to drive the primary low-voltage side switching tube and the secondary synchronous rectifier tube of the LLC DC transformer.

[0036] Furthermore, the present invention has a small number of components. The entire non-isolated resonant gate drive circuit consists of two PMOS transistors, two NMOS transistors, and one inductor. The magnetic components only require an inductor and do not require a transformer, saving cost and space and facilitating miniaturization and integration. At the same time, the control signal of the present invention is simple. Two square waves with the same frequency and duty cycle and a 180-degree phase difference are provided by a function generator connected to a drive chip to control the two PMOS drive transistors. The gates of the two NMOS transistors do not require external signal control, simplifying the complexity of the control signal and improving system stability.

[0037] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A non-isolated resonant gate drive circuit, characterized in that, include: The system comprises a PMOS driving network, an NMOS clamping circuit, and an inductor, wherein the PMOS driving network and the NMOS clamping circuit are both connected in parallel across the inductor. Wherein: the input signal of the PMOS driving network is provided by a function generator followed by a driving chip, and the input signal is processed by the PMOS driving network, NMOS clamping circuit and inductor before being output from the output port v. gsr1 and output port v gsr2 The output drive signal, the NMOS clamping circuit is used to control the output port v gsr1 and output port v gsr2 The state changes, and the inductor is connected to the gate capacitor C in the NMOS clamping circuit. gsr1 and gate capacitance C gsr2 An LC resonance is formed to recover the energy from the turn-off process of the drive circuit for the turn-on process of the drive circuit; The PMOS driving network includes: a first PMOS transistor and a second PMOS transistor. The sources of both the first and second PMOS transistors are connected to the power supply Vcc. The gate of the first PMOS transistor is connected to the PWM1 output port of the driving chip connected after the function generator. The drain of the first PMOS transistor is connected to one end of an inductor. The gate of the second PMOS transistor is connected to the PWM2 output port of the driving chip connected after the function generator. The drain of the second PMOS transistor is connected to the other end of the inductor. The NMOS clamping circuit includes: a first NMOS transistor, a second NMOS transistor, and a gate capacitor C. gsr1 and gate capacitance C gsr2 The gate of the first NMOS transistor, the drain of the second NMOS transistor, the other end of the inductor, and the output port v gsr2 The drain and gate capacitance C of the second PMOS gsr2 One end is connected to the drain of the first NMOS transistor and the gate of the second NMOS transistor, one end of the inductor, and the output port v. gsr1 The drain and gate capacitance C of the first PMOS transistor gsr1 One end is connected, and the source and gate capacitors of the first NMOS transistor are connected. gsr1 The other end is connected to GND, and the gate of the second NMOS transistor is connected to one end of the inductor and the output port v. gsr1 The drain and gate capacitance C of the first PMOS transistor gsr1 The connection is made between the drain of the second NMOS transistor and the other end of the inductor, and the output port v. gsr2 The drain and gate capacitance C of the second PMOS gsr2 One end is connected, and the source and gate capacitors of the second NMOS transistor are connected. gsr2 The other end is connected to GND, and the gate capacitor C gsr1 One end is connected to one end of the inductor and the output port v gsr1 and the drain connection of the first PMOS transistor, the gate capacitor C gsr2 One end is connected to the other end of the inductor, the output port v gsr2 And the drain connection of the second PMOS.

2. The non-isolated resonant gate drive circuit according to claim 1, characterized in that, The output port v gsr1 The output port v is connected to one end of the inductor and the drain of the first PMOS transistor. gsr2 It is connected to the other end of the inductor and the drain of the second PMOS transistor.

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