Sram cell and method of forming the same, and sram device

Abstract

An SRAM cell and a forming method thereof, and an SRAM device, the SRAM cell comprising: a first inverter region, a second inverter region and a pass gate region each comprising adjacent active regions arranged along a first direction; a stack structure on a substrate of the active regions, the stack structure comprising a bottom doped layer, a channel layer and a top doped layer stacked in sequence along a direction perpendicular to the substrate; in the first inverter region and the second inverter region, the channel layers of the adjacent active regions are of different conductive types; in the pass gate region, the channel layers of the adjacent active regions are of the same conductive type; a first dielectric layer between the stack structures along the first direction and covering the top of the stack structures; a gate structure in the first dielectric layer between the adjacent active regions, the gate structure extending along the direction perpendicular to the substrate and being oppositely arranged with the channel layer. The embodiments of the present application reduce the area occupied by the SRAM cell, achieve a smaller distance between adjacent devices, and further facilitate the integration of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to an SRAM cell and a method for forming the same, as well as an SRAM device. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory, and analog circuits, with memory devices accounting for a significant proportion. With the development of semiconductor technology and the wider application of memory devices, it is necessary to integrate these memory devices with other components onto a single chip to form embedded semiconductor memory devices. For example, if the memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility between the memory device and the embedded CPU platform while maintaining the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the memory device needs to be compatible with embedded standard logic devices. Embedded semiconductor devices are typically divided into a logic region and a memory region. The logic region usually includes logic devices, while the memory region includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash memory. Due to its advantages such as low power consumption and fast operating speed, SRAM and its fabrication methods have received increasing attention.

[0004] However, the area of ​​SRAM devices still needs to be reduced. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide an SRAM cell and a method for forming the same, as well as an SRAM device, which reduces the area occupied by the SRAM, is beneficial to reducing the size of the SRAM device, is beneficial to achieving a smaller distance between adjacent devices, and is thus beneficial to improving the integration of the device.

[0006] To address the aforementioned problems, embodiments of the present invention provide an SRAM cell, comprising: a substrate, including a first inverter region, a second inverter region, and a gate region arranged along a first direction; each of the first inverter region, the second inverter region, and the gate region includes adjacent active regions arranged along the first direction; a stacked structure located on the substrate of the active regions, the stacked structure including a bottom doped layer, a channel layer, and a top doped layer stacked sequentially along a direction perpendicular to the substrate, the bottom doped layer and the top doped layer having the same doping type; in the first inverter region and the second inverter region, the channel layers of adjacent active regions have different conductivity types; in the gate region, the channel layers of adjacent active regions have the same conductivity type; a first dielectric layer located between the stacked structures along the first direction and covering the top of the stacked structures; and a gate structure located in the first dielectric layer between adjacent active regions, the gate structure extending along a direction perpendicular to the substrate and disposed opposite to the channel layer.

[0007] Accordingly, this embodiment of the invention also provides an SRAM device, including: a plurality of SRAM cells arranged in an array, wherein the SRAM cells are the SRAM cells provided in this embodiment.

[0008] Accordingly, embodiments of the present invention also provide a method for forming an SRAM cell, comprising: providing a substrate including an SRAM cell region, a first inverter region, a second inverter region, and a gate region arranged along a first direction in the SRAM cell region; the first inverter region, the second inverter region, and the gate region each including adjacent active regions arranged along the first direction; forming a stacked structure located in the active regions on the substrate, and a first dielectric layer located between the stacked structures along the first direction and covering the top of the stacked structure, the stacked structure including a bottom doped layer, a channel layer, and a top doped layer stacked sequentially along a direction perpendicular to the substrate, the bottom doped layer and the top doped layer having the same doping type; in the first inverter region and the second inverter region, the channel layers of adjacent active regions have different conductivity types; in the gate region, the channel layers of adjacent active regions have the same conductivity type; forming a gate structure in the first dielectric layer between adjacent active regions, the gate structure extending along a direction perpendicular to the substrate and disposed opposite to the channel layer.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] The SRAM cell provided in this embodiment of the invention has a stacked structure in which the bottom doped layer, the channel layer, and the top doped layer are stacked sequentially along a direction perpendicular to the substrate. The gate structure is located in the first dielectric layer between adjacent active regions. The gate structure and the adjacent stacked structure are used to form a MOS device. Compared with planar devices and devices in which the gate structure surrounds or encloses the channel layer, in the SRAM cell provided in this embodiment of the invention, the gate structure extends along a direction perpendicular to the substrate and is disposed opposite to the channel layer. Furthermore, in the first inverter region, the second inverter region, and the gate region, adjacent active regions share the gate structure, which is beneficial to reducing the area occupied by the SRAM cell and correspondingly beneficial to reducing the device size. Moreover, the provision of the first dielectric layer can, on the one hand, provide mechanical support for the vertically stacked stacked structure, reducing the probability of the stacked structure collapsing during the semiconductor structure formation process. On the other hand, it can also allow for smaller spacing between adjacent devices, thereby improving the device integration density.

[0011] In the SRAM cell formation method provided in this embodiment of the invention, the first inverter region, the second inverter region, and the gate region all include adjacent active regions arranged along a first direction; a stacked structure located in the active regions and a first dielectric layer located between the stacked structures and covering the top of the stacked structures are formed on the substrate; the bottom doped layer, the channel layer, and the top doped layer in the stacked structure are stacked sequentially along a direction perpendicular to the substrate; and a gate structure is formed in the first dielectric layer of the adjacent active regions; the gate structure extends along a direction perpendicular to the substrate and is disposed opposite to the channel layer; the gate structure and the adjacent stacked structure are used to constitute a MOS device, which surrounds the planar device and the gate structure. Compared to devices surrounding a channel layer, in the SRAM cell formed in the embodiments of the present invention, the gate structure extends along a direction perpendicular to the substrate and is disposed opposite to the channel layer. Furthermore, in the first inverter region, the second inverter region, and the transmission gate region, adjacent active regions share the gate structure, which is beneficial to reducing the area occupied by the SRAM cell and correspondingly beneficial to reducing the device size. Moreover, the first dielectric layer can provide mechanical support for the vertically stacked stacked structure, reducing the probability of the stacked structure collapsing during the semiconductor structure formation process. On the other hand, it also allows for smaller spacing between adjacent devices, thereby improving the device integration density. Attached Figure Description

[0012] Figures 1 to 2 This is a schematic diagram of the structure of an embodiment of the SRAM cell of the present invention;

[0013] Figures 3 to 6 This is a schematic diagram of the structure of an embodiment of the SRAM cell of the present invention;

[0014] Figures 7 to 25This is a schematic diagram of the structure corresponding to each step in one embodiment of the SRAM cell formation method of the present invention. Detailed Implementation

[0015] As can be seen from the background technology, the area of ​​SRAM devices still needs to be reduced.

[0016] Specifically, an SRAM device typically includes multiple SRAM cells arranged in an array.

[0017] Reference Figure 1 and Figure 2 , Figure 1 A schematic diagram of an SRAM cell structure is shown. Figure 2 A schematic diagram of the circuit structure of an SRAM cell is shown.

[0018] like Figure 1 As shown, the SRAM cell includes: a substrate (not shown) and a plurality of fins 1 discretely disposed on the substrate. The substrate includes a first pull-down region 10D1, a first pull-up region 10U1, a first gate region 10G1, and a second pull-down region 10D2, a second pull-up region 10U2, and a second gate region 10G2. The first pull-down region 10D1, the first pull-up region 10U1, the first gate region 10G1, the second pull-down region 10D2, the second pull-up region 10U2, and the second gate region 10G2 are respectively applied to form a first pull-down transistor PD1, a first pull-up transistor PU1, a first gate transistor PG1, and a second pull-down transistor PD2, a second pull-up transistor PU1, a first gate transistor PG1, and a second pull-down transistor PD2, a second pull-up transistor PU1, a first gate transistor PG1, and a second gate transistor PD2, a second pull-up transistor PU1, a first pull-up transistor PU1, a first gate transistor PG1, and a second gate transistor PD2, a second pull-up transistor PU1, a second gate transistor PG1, and a second gate transistor PD2, a second gate ... a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor PG1, a second gate transistor Pull-up transistor PU2, second gate transistor PG2, first pull-down region 10D1, first pull-up region 10U1, and second gate region 10G2 are arranged along the arrangement direction of fin 1, and second pull-down region 10D2, second pull-up region 10U2, and first gate region 10G1 are arranged along the arrangement direction of multiple fins 1; gate structure 2 is located on the substrate and spans the fin 1, and the extension direction of gate structure 2 is perpendicular to the extension direction of fin 1; source / drain doped regions 3 are located in the fins 1 on both sides of gate structure 2; wherein, the source / drain doped region 3 located on one side of gate structure 2 is used as the source, and the source / drain doped region 3 located on the other side of gate structure 2 is used as the drain.

[0019] like Figure 1 and Figure 2 As shown, the source of the first pull-up transistor PU1 is connected to VDD, the drain of the first pull-up transistor PU1 is electrically connected to the drain of the first pull-down transistor PD1, the drain of the first transfer transistor PG1, and the gate structure 2 of the second pull-up transistor PU2 and the second pull-down transistor PD2, and the source of the first pull-down transistor PD1 is connected to VSS.

[0020] The source of the second pull-up transistor PU2 is connected to VDDCELL. The drain of the second pull-up transistor PU2 is electrically connected to the drain of the second pull-down transistor PD2, the drain of the second transfer transistor PG2, and the gate structure 2 of the first pull-up transistor PU1 and the first pull-down transistor PD1. The source of the second pull-down transistor PD2 is used to connect to VSSCELL.

[0021] The source access bit line (BLB or BL) of the first transmission gate transistor PG1 and the second transmission gate transistor PG2, and the gate access word line (WL).

[0022] like Figure 1 As shown, the source / drain doped region 3 on one side of the gate structure 2 serves as the source, and the source / drain doped region 3 on the other side of the gate structure 2 serves as the drain, meaning the source and drain are arranged parallel to the substrate. Furthermore, the gate structure 2 has cut-off positions, and there are significant gaps between the first pull-up region 10U1 and the second transmission gate region 10G2, as well as between the second pull-up region 10U2 and the first transmission gate region 10G1. All of these factors contribute to the large area occupied by the SRAM cells, resulting in a large area occupied by the SRAM device.

[0023] To address the technical problems, this invention provides an SRAM cell in which the bottom doped layer, channel layer, and top doped layer are stacked sequentially along a direction perpendicular to the substrate. The gate structure is located in a first dielectric layer between adjacent active regions. The gate structure and the adjacent stacked structure are used to form a MOS device. Compared with planar devices and devices in which the gate structure surrounds or encloses the channel layer, in the SRAM cell provided by this invention, the gate structure extends along a direction perpendicular to the substrate and is disposed opposite to the channel layer. Furthermore, in the first inverter region, the second inverter region, and the gate region, adjacent active regions share the gate structure, which helps to reduce the area occupied by the SRAM cell and correspondingly helps to reduce the device size. Moreover, the first dielectric layer provides mechanical support for the vertically stacked stacked structure, reducing the probability of the stacked structure collapsing during the semiconductor structure formation process. It also allows for smaller spacing between adjacent devices, thereby improving the device integration density.

[0024] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 3 to 6 The diagram shows a structural schematic of an embodiment of the SRAM cell of the present invention. Figure 3 A top view of multiple SRAM cells is shown. Figure 4 for Figure 3 The corresponding partial 3D image, Figure 5 for Figure 4A three-dimensional schematic diagram exposing the cross-section of the layered structure. Figure 6 for Figure 4 The corresponding top view.

[0025] In this embodiment, the SRAM cell includes: a substrate 100, including a substrate along a first direction (e.g., ... Figure 5 The first inverter region H1, the second inverter region H2, and the gate region PG are arranged in the X direction. Each of the first inverter region H1, the second inverter region H2, and the gate region PG includes adjacent active regions A arranged along the first direction. A stacked structure 110 is located on the substrate 100 of the active regions A. The stacked structure 110 includes a bottom doped layer 11, a channel layer 12, and a top doped layer 14 stacked sequentially along a direction perpendicular to the substrate 100. The doping types of the bottom doped layer 11 and the top doped layer 14 are similar. In the first inverter region H1 and the second inverter region H2, the channel layers 12 of adjacent active regions A have different conductivity types; in the gate region 100PG, the channel layers 12 of adjacent active regions have the same conductivity type; the first dielectric layer 200 is located between the stacked structures 110 along the first direction and covers the top of the stacked structures 110; the gate structure 230 is located in the first dielectric layer 200 between adjacent active regions A, and the gate structure 230 extends in a direction perpendicular to the substrate 100 and is disposed opposite to the channel layer 12.

[0026] Substrate 100 provides a process platform for the formation of SRAM cells. In this embodiment, substrate 100 is a silicon substrate, that is, the material of substrate 100 is single-crystal silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0027] The first inverter region H1 is used to form the first inverter; the second inverter region H2 is used to form the second inverter; and the gate region PG is used to form the gate transistor.

[0028] In this embodiment, the first inverter region H1, the second inverter region H2, and the transmission gate region PG each include adjacent active regions A arranged along the first direction. Among the first inverter region H1, the second inverter region H2, and the transmission gate region PG, the region located between adjacent active regions A along the first direction is the gate region G.

[0029] The active region A is used to form a stacked structure; the gate region G is used to form a gate structure.

[0030] In this embodiment, the active region A located on the first side of the gate region G is the first active region (not shown), and the active region A located on the second side of the gate region G is the second active region (not shown).

[0031] In this embodiment, the direction parallel to the substrate 100 and perpendicular to the first direction is the second direction (e.g., Figure 5center Y direction).

[0032] In this embodiment, the substrate 100 further includes an interconnect region (not shown) adjacent to the active region A along a second direction. The interconnect region is used to form a bottom interconnect layer 210 to achieve interconnection between the bottom doped layer 11 and external circuits or other film layers.

[0033] Specifically, in this embodiment, along the second direction, the interconnect region corresponds one-to-one with the bottom doped layer 11.

[0034] The stacked structure 110 and the gate structure 230 are used to form a MOS transistor.

[0035] In the stacked structure 110, the bottom doped layer 11, the channel layer 12, and the top doped layer 14 are stacked sequentially along a direction perpendicular to the substrate 100, which helps to save chip area.

[0036] In the stacked structure 110, either the bottom doped layer 11 or the top doped layer 14 is used as the source, and the other is used as the drain. The source and drain are used to provide carrier sources for the channel when the device is operating.

[0037] In one embodiment, in the stacked structure 110, the bottom doped layer 11 serves as the source and the top doped layer 14 serves as the drain. In other embodiments, the stacked structure may also have the bottom doped layer serving as the drain and the top doped layer serving as the source.

[0038] In this embodiment, the bottom doped layer 11 and the top doped layer 14 include stress layers doped with ions, and the bottom doped layer 11 and the top doped layer 14 are also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0039] Specifically, when forming an NMOS transistor, the bottom doped layer 11 and the top doped layer 14 are made of N-type ion-doped stress layers, including Si or SiC. These stress layers provide tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the bottom doped layer 11 and the top doped layer 14 are made of P-type ion-doped stress layers, including Si or SiGe. These stress layers provide compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility. The P-type ions are B-ions, Ga-ions, or In-ions.

[0040] When the device is in operation, the channel layer 12 is used as the channel region.

[0041] In this embodiment, the channel layer 12 is made of monocrystalline silicon. In other embodiments, the channel layer may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0042] In this embodiment, the channel layer 12 is also doped with ions, and the doping type of the channel layer 12 is different from that of the bottom doped layer 11 and the top doped layer 14. When forming an NMOS transistor, the channel layer 12 is doped with P-type ions; when forming a PMOS transistor, the channel layer 12 is doped with N-type ions.

[0043] In this embodiment, the channel layers 12 of adjacent active regions A have different conductivity types in the first inverter region H1 and the second inverter region H2. That is, in the first inverter region H1 and the second inverter region H2, the stacked structure 110 and the gate structure 230 located in the first active region are used to form a first type MOS transistor, and the stacked structure 110 and the gate structure 230 located in the second active region are used to form a second type MOS transistor. The channel conductivity types of the first type MOS transistor and the second type MOS transistor are different, so that the stacked structure 110 and the gate structure 230 on the adjacent first active region and the second active region form a CMOS (Complementary Metal Oxide Semiconductor) transistor, and thus form an inverter.

[0044] Correspondingly, in the first inverter region H1 and the second inverter region H2, the doping types of the bottom doped layer 11 located in the first active region and the bottom doped layer 11 located in the second active region are also different.

[0045] In this embodiment, the first inverter region H1 includes a first pull-down region PD1 and a first pull-up region PU1 arranged along a first direction. The first pull-down region PD1 is used to form a first pull-down transistor, and the first pull-up region PU1 is used to form a first pull-up transistor.

[0046] In this embodiment, the second inverter region H2 includes a second pull-down region PD2 and a second pull-up region PU2 arranged along the first direction. The second pull-down region PD2 is used to form a second pull-down transistor, and the second pull-up region PU2 is used to form a second pull-up transistor.

[0047] In this embodiment, the transmission gate region PG includes a first transmission region PG1 and a second transmission region PG2 arranged along a first direction. The first transmission region PG1 is used to form a first transmission gate transistor, and the second transmission region PG2 is used to form a second transmission gate transistor.

[0048] In this embodiment, in the stacked structure 110, either the bottom doped layer 11 or the top doped layer 14 is used as a source, and the other is used as a drain. The source and drain are used to provide carrier sources for the channel when the device is operating.

[0049] In this embodiment, the stacked structure 110 further includes a gradually changing doped layer 13 located between the channel layer 12 and the drain. The doping type of the gradually changing doped layer 13 is the same as that of the drain, and the doping concentration of the gradually changing doped layer 13 is lower than that of the drain.

[0050] The gradually changing doping layer 13 is used to create a gradually changing doping concentration gradient between the channel layer 12 and the drain, preventing the concentration gradient between the channel layer 12 and the drain from being too steep.

[0051] In this embodiment, the material of the gradually changing doped layer 13 is the same as the doping type of the drain electrode, and the doping ion type in the gradually changing doped layer 13 is also the same as the doping ion type of the drain electrode.

[0052] In the above embodiments, the first dielectric layer 200 provides mechanical support for the vertically stacked stacked structure 110, reducing the probability of the stacked structure 110 collapsing during the semiconductor structure formation process. On the other hand, it also allows for smaller spacing between adjacent devices, thereby improving the integration of the devices.

[0053] More specifically, the first dielectric layer 200 provides mechanical support for the stacked structure 110, which helps to reduce the collapse of the stacked structure 110 due to stress during the pattern transfer process.

[0054] In addition, the first dielectric layer 200 is also used to achieve electrical isolation between the top conductive structures 240.

[0055] The material of the first dielectric layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride.

[0056] When the device is in operation, the gate structure 230 is used to control the opening and closing of the conductive channel.

[0057] The gate structure 230 extends in a direction perpendicular to the substrate 100 and is disposed opposite to the channel layer 12. The gate structure 230 and the adjacent stacked structure 110 are used to form a MOS device. Compared with planar devices and devices in which the gate structure surrounds or encloses the channel layer, the SRAM cell provided in this embodiment occupies a smaller area, which is beneficial for reducing the device size.

[0058] In this embodiment, the gate structure 230 is located in the first dielectric layer 200 of the gate region G.

[0059] It should be noted that, along the direction parallel to the substrate 100, there is a gap between the gate structure 230 and the adjacent stacked structure 110, so that the first dielectric layer 200 located between the gate structure 230 and the adjacent stacked structure 110 can retain a portion of its thickness to serve as a gate dielectric layer, thereby achieving isolation between the gate structure 230 and the adjacent stacked structure 110.

[0060] As an example, the gate structure 230 is a metal gate structure. The gate structure 230 may include a metal electrode layer. The material of the metal electrode layer includes one or more of W, Al, Cu, Ag, Au, Pt, Ni, and Ti.

[0061] It should also be noted that in this embodiment, in the first inverter region H1, the second inverter region H2 and the transmission gate region PG, the adjacent active regions A share the gate structure 230, which is beneficial to further save the area of ​​the device.

[0062] In this embodiment, the SRAM cell further includes: a bottom interconnect layer 210, which is located on the substrate 100 on the side of the stacked structure 110 and the first dielectric layer 200, and is in contact with the sidewall of the bottom doped layer 11 along the second direction, exposing the channel layer 12; a bottom conductive structure 250, which is located on the bottom interconnect layer 210 and in contact with the bottom interconnect layer 210; and a top conductive structure 240, which is located in the first dielectric layer 200 on the top doped layer 14 and in contact with the top doped layer 14.

[0063] The bottom interconnect layer 210 is in contact with the sidewall of the bottom doped layer 11 to realize the electrical connection between the bottom doped layer 11 and external circuits or other film structures.

[0064] As an example, in the stacked structure 110, the bottom doped layer 11 serves as the source, the top doped layer 14 serves as the drain, and the bottom interconnect layer 210 serves as the power rail. The power rail is used to supply power to the bottom doped layer 11. Specifically, during device operation, the power rail is used to connect to VDD or VSS.

[0065] The bottom interconnect layer 210 is made of a conductive material. In this embodiment, the bottom interconnect layer 210 is made of a metallic material, such as copper, tungsten, cobalt, nickel, etc.

[0066] As an example, there is a gap between adjacent bottom interconnect layers 210.

[0067] The bottom interconnect layer 210 and the bottom conductive structure 250 enable the electrical properties of the bottom doped layer 11 to be brought out, thereby achieving electrical connection between the bottom doped layer 11 and external circuits or other film structures.

[0068] The bottom conductive structure 250 is made of a conductive material. As an example, the bottom conductive structure 250 is made of a metal, including one or more of copper, tungsten, cobalt, nickel, and aluminum.

[0069] In this embodiment, the bottom conductive structure 250 penetrates the second dielectric layer 220 located on top of the bottom interconnect layer 210.

[0070] In this embodiment, the SRAM cell further includes: a second dielectric layer 220 located on the substrate 100 on the side of the stacked structure 110 and the first dielectric layer 200 and covering the bottom interconnect layer 210; and a bottom conductive structure 250 penetrating the second dielectric layer 220 located on top of the bottom interconnect layer 210.

[0071] The second dielectric layer 220 is used to achieve isolation between adjacent device cell regions 100s along the second direction. After a bottom conductive structure is subsequently formed in the second dielectric layer 200 on top of the bottom interconnect layer 210, the second dielectric layer 220 is also used to achieve electrical isolation between the bottom conductive structures.

[0072] As an example, the top surface of the second dielectric layer 220 is flush with the top surface of the first dielectric layer 200.

[0073] As an example, the material of the second dielectric layer 220 is silicon oxide. In other embodiments, the second dielectric layer may also be an insulating material such as silicon nitride or silicon oxynitride.

[0074] It should be noted that, for ease of illustration and explanation, the second dielectric layer 220 is represented by a dashed box in the 3D diagram.

[0075] The top conductive structure 240 is used to achieve electrical connection between the top doped layer 14 and external circuits or other film structures. The material of the top conductive structure 240 is a conductive material. As an example, the material of the top conductive structure 240 is a metal, including one or more of copper, tungsten, cobalt, nickel, and aluminum.

[0076] As an example, in the stacked structure 110, the bottom doped layer 11 is used as the source and the top doped layer 14 is used as the drain.

[0077] In this embodiment, the bottom conductive structure 250 of the first pull-up region PU1 is connected to VDD, the top conductive structure 240 of the first pull-up region PU1 is electrically connected to the top conductive structure 240 of the first pull-down region PD1, the top conductive structure 240 of the first transmission region PG1, and the gate structure 230 of the second inverter region H2, and the bottom conductive structure 250 of the first pull-down region PD1 is connected to VSS.

[0078] In this embodiment, the bottom conductive structure 250 of the second pull-up region PU2 is connected to VDD, the top conductive structure 240 of the second pull-up region PU2 is electrically connected to the top conductive structure 240 of the second pull-down region PD2, the top conductive structure 240 of the second transmission region PG2 is electrically connected to the gate structure 230 of the first inverter region H1, and the bottom conductive structure 250 of the second pull-down region PD2 is used to connect to VSS.

[0079] In this embodiment, the bottom conductive structure 250 of the gate region PG is connected to the bit line (BL), and the gate structure 230 is connected to the word line (WL).

[0080] In other words, the source of the first pull-up transistor is connected to VDD, the drain of the first pull-up transistor is electrically connected to the drain of the first pull-down transistor, the drain of the first transfer transistor, and the gate structure 230 of the second pull-up transistor and the second pull-down transistor, and the source of the first pull-down transistor is connected to VSS.

[0081] In this embodiment, the source of the second pull-up transistor is connected to VDD, and the drain of the second pull-up transistor is electrically connected to the drain of the second pull-down transistor, the drain of the second transfer transistor, and the gate structure 230 of the first pull-up transistor and the first pull-down transistor. The source of the second pull-down transistor is used to connect to VSS.

[0082] In this embodiment, the sources of the first and second transmission transistors are connected to the bit line (BL), and the gate structure 230 of the first and second transmission transistors is connected to the word line (WL).

[0083] In this embodiment, the SRAM cell further includes: a first electrical connection structure (not shown), which electrically connects the top conductive structure of the first pull-up region to the top conductive structure of the first pull-down region, the top conductive structure of the first transmission region, and the gate structure of the second inverter region; and a second electrical connection structure, which electrically connects the top conductive structure 240 of the second pull-up region PU2 to the top conductive structure 240 of the second pull-down region PD2, and the top conductive structure 240 of the second transmission region PG2 to the gate structure 230 of the first inverter region H1.

[0084] The first and second electrical connection structures are made of conductive materials. In this embodiment, the first and second electrical connection structures are made of metallic materials, such as copper, tungsten, cobalt, nickel, etc.

[0085] In other embodiments, the bottom doped layer is used as the drain and the top doped layer is used as the source.

[0086] Accordingly, the top conductive structure of the first pull-up region is connected to VDD, and the bottom conductive structure of the first pull-up region is electrically connected to the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transmission region, and the gate structure of the second inverter region. The top conductive structure of the first pull-down region is connected to VSS. The top conductive structure of the second pull-up region is connected to VDD, and the bottom conductive structure of the second pull-up region is electrically connected to the bottom conductive structure of the second pull-down region, the bottom conductive structure of the second transmission region, and the gate structure of the first inverter region. The top conductive structure of the second pull-down region is connected to VSS. The top conductive structure of the transmission gate region is connected to the bit line, and the gate structure is connected to the word line.

[0087] Accordingly, the SRAM cell also includes: a third electrical connection structure, which electrically connects the bottom conductive structure of the first pull-up region to the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transfer region, and the gate structure of the second inverter region; and a fourth electrical connection structure, which electrically connects the bottom conductive structure of the second pull-up region to the bottom conductive structure of the second pull-down region, the bottom conductive structure of the second transfer region, and the gate structure of the first inverter region.

[0088] In this embodiment, the SRAM cell further includes a gate conductive structure 260, located on top of the gate structure 230 and in contact with the gate structure 230. The gate conductive structure 260 is used to realize the electrical connection between the gate structure 230 and external circuits or other film structures.

[0089] The gate conductive structure 260 is made of a conductive material. In this embodiment, the gate conductive structure 260 is made of a metallic material, such as copper, tungsten, cobalt, nickel, etc.

[0090] Accordingly, the present invention also provides an SRAM device comprising multiple arrayed SRAM cells, wherein the SRAM cells are the SRAM cells provided in the embodiments of the present invention.

[0091] In this embodiment, the SRAM cell occupies a smaller area, which is beneficial for reducing the size of the SRAM device. Moreover, the first dielectric layer can provide mechanical support for the vertically stacked structure, reducing the probability of the stacked structure collapsing or tilting. On the other hand, it can also help to achieve a smaller distance between adjacent devices, thereby improving the integration density of the SRAM device.

[0092] Accordingly, the present invention also provides a method for forming an SRAM cell. Figures 7 to 25 This is a schematic diagram of the structure corresponding to each step in one embodiment of the SRAM cell formation method of the present invention.

[0093] The method for forming the SRAM cell in this embodiment will be described in detail below with reference to the accompanying drawings.

[0094] refer to Figures 7 to 9 , Figure 7 This is a top view of an embodiment of an SRAM cell. Figure 8 for Figure 7 The corresponding partial 3D image, Figure 9 for Figure 8 The corresponding top view provides a substrate 100, including an SRAM cell region, the SRAM cell region including areas along a first direction (e.g., Figure 8 The first inverter region H1, the second inverter region H2, and the gate region PG are arranged in the X direction. The first inverter region H1, the second inverter region H2, and the gate region PG all include adjacent active regions A arranged along the first direction.

[0095] Substrate 100 is used to provide a process platform for subsequent processes. In this embodiment, substrate 100 is a silicon substrate, that is, the material of substrate 100 is single-crystal silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0096] The first inverter region H1 is used to form the first inverter; the second inverter region H2 is used to form the second inverter; and the gate region PG is used to form the gate transistor.

[0097] In this embodiment, the first inverter region H1, the second inverter region H2, and the transmission gate region PG each include an active region A and a gate region G arranged along the first direction.

[0098] The active region A is used to form a stacked structure in the future; the gate region G is used to form a gate structure in the future.

[0099] In this embodiment, the active region A located on the first side of the gate region G is the first active region (not shown), and the active region A located on the second side of the gate region G is the second active region (not shown).

[0100] Accordingly, when the gate structure is subsequently formed in the gate region G, the stacked structure located in the first active region and the stacked structure located in the second active region share the same gate structure.

[0101] In this embodiment, the first inverter region H1 includes a first pull-down region PD1 and a first pull-up region PU1 arranged along a first direction. The first pull-down region PD1 is used to form a first pull-down transistor, and the first pull-up region PU1 is used to form a first pull-up transistor.

[0102] In this embodiment, the second inverter region H2 includes a second pull-down region PD2 and a second pull-up region PU2 arranged along the first direction. The second pull-down region PD2 is used to form a second pull-down transistor, and the second pull-up region PU2 is used to form a second pull-up transistor.

[0103] In this embodiment, the transmission gate region PG includes a first transmission region PG1 and a second transmission region PG2 arranged along a first direction. The first transmission region PG1 is used to form a first transmission gate transistor, and the second transmission region PG2 is used to form a second transmission gate transistor.

[0104] In this embodiment, the direction parallel to the substrate 100 and perpendicular to the first direction is the second direction (e.g., Figure 8 shown in the Y direction).

[0105] In this embodiment, the SRAM cell region 100D further includes an interconnect region (not shown) adjacent to the active region A along a second direction. The interconnect region is used to subsequently form a bottom interconnect layer to achieve interconnection between the bottom doped layer and external circuits or other film layers.

[0106] Specifically, in this embodiment, along the second direction, the interconnect region corresponds one-to-one with the bottom doped layer 11.

[0107] refer to Figures 10 to 15 A stacked structure 110 located in the active region A is formed on the substrate 100, and a first dielectric layer 200 located between the stacked structures 110 and covering the top of the stacked structure 110 along a first direction. The stacked structure 110 includes a bottom doped layer 11, a channel layer 12 and a top doped layer 14 stacked sequentially along a direction perpendicular to the substrate 100. The bottom doped layer 11 and the top doped layer 14 have the same doping type. In the first inverter region H1 and the second inverter region H2, the channel layers 12 of adjacent active regions A have different conductivity types. In the gate region 100PG, the channel layers 12 of adjacent active regions have the same conductivity type.

[0108] After the gate structure is subsequently formed, the stacked structure 110 and the gate structure are used to form a MOS transistor.

[0109] In the stacked structure 110, the bottom doped layer 11, the channel layer 12, and the top doped layer 14 are stacked sequentially along a direction perpendicular to the substrate 100, which helps to save chip area.

[0110] In the stacked structure 110, either the bottom doped layer 11 or the top doped layer 14 is used as the source, and the other is used as the drain. The source and drain are used to provide carrier sources for the channel when the device is operating.

[0111] In one embodiment, in the stacked structure 110, the bottom doped layer 11 serves as the source and the top doped layer 14 serves as the drain. In other embodiments, the stacked structure may also have the bottom doped layer serving as the drain and the top doped layer serving as the source.

[0112] In this embodiment, the bottom doped layer 11 and the top doped layer 14 include stress layers doped with ions, and the bottom doped layer 11 and the top doped layer 14 are also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0113] Specifically, when forming an NMOS transistor, the bottom doped layer 11 and the top doped layer 14 are made of N-type ion-doped stress layers, including Si or SiC. These stress layers provide tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the bottom doped layer 11 and the top doped layer 14 are made of P-type ion-doped stress layers, including Si or SiGe. These stress layers provide compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility. The P-type ions are B-ions, Ga-ions, or In-ions.

[0114] When the device is in operation, the channel layer 12 is used as the channel region.

[0115] In this embodiment, the channel layer 12 is made of monocrystalline silicon. In other embodiments, the channel layer may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0116] In this embodiment, the channel layer 12 is also doped with ions, and the doping type of the channel layer 12 is different from that of the bottom doped layer 11 and the top doped layer 14. When forming an NMOS transistor, the channel layer 12 is doped with P-type ions; when forming a PMOS transistor, the channel layer 12 is doped with N-type ions.

[0117] In this embodiment, during the steps of forming the stacked structure 110 and the first dielectric layer 200, the channel layers 12 of adjacent active regions A in the first inverter region H1 and the second inverter region H2 have different conductivity types. That is, after the gate structure is subsequently formed in the gate region G, the stacked structure and gate structure located in the first active region are used to form a first type MOS transistor, and the stacked structure and gate structure located in the second active region are used to form a second type MOS transistor. The channel conductivity types of the first type MOS transistor and the second type MOS transistor are different, thereby enabling the stacked structure and gate structure on adjacent first and second active regions to form a CMOS (Complementary Metal Oxide Semiconductor) transistor, which in turn forms an inverter.

[0118] Correspondingly, in the first inverter region H1 and the second inverter region H2, the doping types of the bottom doped layer 11 located in the first active region and the bottom doped layer 11 located in the second active region are also different.

[0119] In this embodiment, in the stacked structure 110, either the bottom doped layer 11 or the top doped layer 14 is used as a source, and the other is used as a drain. The source and drain are used to provide carrier sources for the channel when the device is operating.

[0120] In this embodiment, during the step of forming the stacked structure 110, the stacked structure 110 further includes a gradually changing doped layer 13 located between the channel layer 12 and the drain. The doping type of the gradually changing doped layer 13 is the same as that of the drain, and the doping concentration of the gradually changing doped layer 13 is lower than that of the drain.

[0121] The gradually changing doping layer 13 is used to create a gradual doping concentration gradient between the channel layer 12 and the drain, preventing the concentration gradient between the channel layer 12 and the drain from being too steep.

[0122] In this embodiment, the material of the gradually changing doped layer 13 is the same as the doping type of the drain electrode, and the doping ion type in the gradually changing doped layer 13 is also the same as the doping ion type of the drain electrode.

[0123] The first dielectric layer 200 provides mechanical support for the vertically stacked stacked structure 110, reducing the probability of the stacked structure 110 collapsing in subsequent process manufacturing. On the other hand, it also allows for smaller spacing between adjacent devices, thereby improving the integration of the devices.

[0124] More specifically, the first dielectric layer 200 provides mechanical support for the stacked structure 110, which helps to reduce the collapse of the stacked structure 110 due to stress during the pattern transfer process.

[0125] The material of the first dielectric layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonate or silicon oxycarbonitride, boron nitride and boron carbonitride.

[0126] In this embodiment, the steps of forming the stacked structure 110 and the first dielectric layer 200 include:

[0127] refer to Figures 7 to 9 , Figure 7 This is a top view of an SRAM cell. Figure 8 for Figure 7 The corresponding partial 3D image, Figure 9 for Figure 8The corresponding top view shows that an initial stacked structure 115 located in the active region A and the interconnect region and an initial isolation wall 125 located between the initial stacked structure 115 along a first direction are formed on the substrate 100, and the initial stacked structure 115 and the initial isolation wall 125 extend along a second direction.

[0128] The initial stacked structure 115 is used to form subsequent stacked structures.

[0129] In this embodiment, the initial stacked structure 115 includes an initial bottom doped layer 101, an initial channel layer 102, and an initial top doped layer 104 stacked sequentially along a direction perpendicular to the substrate 100.

[0130] The initial bottom doped layer 101 is used for the subsequent formation of the bottom doped layer; the initial channel layer 102 is used for the subsequent formation of the channel layer; and the initial top doped layer 104 is used for the subsequent formation of the top doped layer.

[0131] Either the initial bottom doped layer 101 or the initial top doped layer 104 is used as the initial drain, and the initial stacked structure 115 also includes an initial slowly varying doped layer 103 located between the initial channel layer 102 and the initial drain.

[0132] The initial isolation wall 125 is used to form the subsequent isolation wall. The initial isolation wall 125 also serves to support the initial stacked structure 115.

[0133] As an example, the top surface of the initial isolation wall 125 is flush with the top surface of the initial stacked structure 115, so as to provide a flat top surface for subsequent processes and to ensure the supporting and isolation functions of the initial isolation wall 125 on the initial stacked structure 115.

[0134] As one embodiment, the steps of forming the initial stacked structure 115 and the initial isolation wall 125 include: forming discrete initial isolation walls 125 on the substrate 100 to expose the active region A; and forming the initial stacked structure 115 on the substrate between the initial isolation walls 125.

[0135] By forming the initial layered structure 115 after forming the initial isolation wall 125, it is easier to reduce the difficulty of forming the initial isolation wall 125 and obtain a smaller width of the initial isolation wall 125, which in turn helps to further reduce the distance between adjacent initial layered structures 115.

[0136] In this embodiment, the step of forming the initial isolation wall 125 may include: forming a first isolation film (not shown) on the substrate 100; patterning the first isolation film, and using the remaining first isolation film as the first initial isolation wall 125.

[0137] In this embodiment, the step of forming the initial stacked structure 115 may include: forming a first epitaxial layer using an epitaxial process, and in the process of forming the first epitaxial layer, self-doping ions in situ to form an initial bottom doped layer; after forming the initial bottom doped layer, forming a second epitaxial layer using an epitaxial process, and in the process of forming the second epitaxial layer, self-doping ions in situ to form an initial channel layer; after forming the initial channel layer, forming a third epitaxial layer using an epitaxial process, and in the process of forming the third epitaxial layer, self-doping ions in situ to form an initial top doped layer.

[0138] In specific implementation, when the initial bottom doped layer of the initial stacked structure 115 in different regions has different doping types, the corresponding initial stacked structure 115 is formed in the corresponding region in different steps.

[0139] In other embodiments, the steps of forming the initial isolation wall and the initial stacked structure may also include: forming the initial stacked structure on the substrate of the active region and the interconnect region; and forming the initial isolation wall on the substrate between the initial stacked structures.

[0140] refer to Figures 10 to 11 , Figure 10 For based on Figure 8 3D image, Figure 11 for Figure 9 The corresponding top view shows that an isolation layer 117 spanning the active region A is formed on top of the initial stacked structure 115 and the initial isolation wall 125, exposing the interconnection region I.

[0141] The isolation layer 117 serves as a mask for the initial stacked structure 115 and the initial isolation wall 125 exposed by the subsequent removal of the isolation layer 117. Furthermore, a top conductive structure is subsequently formed within the isolation layer 117 on the top doped layer 14, and the isolation layer 117 also serves to achieve electrical isolation between the top conductive structures.

[0142] In this embodiment, the isolation layer 117 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the isolation layer 117 is silicon oxide.

[0143] refer to Figures 12 to 14 , Figure 12 This is a top view of an SRAM cell. Figure 13 for Figure 12 A partial 3D view, Figure 14 for Figure 13In the corresponding top view, the initial stacked structure 115 and the initial isolation wall 125 exposed by the isolation layer 117 are removed. The remaining initial stacked structure 115 is used as the stacked structure 110, and the remaining initial isolation wall 125 is used as the isolation wall 118. The isolation wall 118 and the isolation layer 117 are used to form the first dielectric layer 200.

[0144] The initial stack structure 115 and the initial isolation wall 125 are exposed by removing the isolation layer 117, thereby enabling the initial stack structure 115 and the initial isolation wall 125 to be graphically represented, and also exposing the interconnect region I so that the bottom interconnect layer can be formed in the interconnect region I later.

[0145] As an example, an anisotropic dry etching process is used to remove the initial stacked structure 115 and the initial isolation wall 125 exposed by the isolation layer 117.

[0146] In this embodiment, for ease of illustration and explanation, the isolation layer 117 is not shown in the top view of the SRAM cell.

[0147] refer to Figures 15 to 18 The method of forming an SRAM cell further includes forming a bottom interconnect layer 210 on a substrate 100 on the side of the stacked structure 110 and the first dielectric layer 200, wherein the bottom interconnect layer 210 is in contact with the sidewall of the bottom doped layer 11 along the second direction and exposes the channel layer 12.

[0148] The bottom interconnect layer 210 is in contact with the sidewall of the bottom doped layer 11 to realize the electrical connection between the bottom doped layer 11 and external circuits or other film structures.

[0149] As an example, in the stacked structure 110, the bottom doped layer 11 serves as the source, the top doped layer 14 serves as the drain, and the bottom interconnect layer 210 serves as the power rail. The power rail is used to supply power to the bottom doped layer 11. Specifically, during device operation, the power rail is used to connect to VDD or VSS.

[0150] The bottom interconnect layer 210 is made of a conductive material. In this embodiment, the bottom interconnect layer 210 is made of a metallic material, such as copper, tungsten, cobalt, nickel, etc.

[0151] As an example, the steps for forming the bottom interconnect layer include: Figure 15 As shown, an interconnect material layer 140 is covered on the substrate 100 on the side of the stacked structure 110 and the first dielectric layer 200, exposing the channel layer 12 and the top doped layer 14; as Figures 16 to 18 As shown, Figure 16 This is a top view of an SRAM cell. Figure 17 for Figure 16 The corresponding partial 3D image, Figure 18 for Figure 17 In the corresponding top view, the interconnect material layer 140 located between interconnect regions I is removed, and the remaining interconnect material layer 140 located on interconnect region I is used as the bottom interconnect layer 210.

[0152] In this embodiment, the process for forming the interconnect material layer 140 includes one or more of physical vapor deposition, chemical vapor deposition, and electrochemical plating.

[0153] As an example, there is a gap between adjacent bottom interconnect layers 210.

[0154] Reference Figure 19 In this embodiment, the method for forming an SRAM cell further includes: after forming the bottom interconnect layer 210 and before forming the bottom conductive structure, forming a second dielectric layer 220 on the substrate 100 on the side of the stacked structure 110 and the first dielectric layer 200 to cover the bottom interconnect layer 210.

[0155] The second dielectric layer 220 is used to achieve isolation between adjacent device cell regions 100s along the second direction. After a bottom conductive structure is subsequently formed in the second dielectric layer 200 on top of the bottom interconnect layer 210, the second dielectric layer 220 is also used to achieve electrical isolation between the bottom conductive structures.

[0156] More specifically, in this embodiment, a second dielectric layer 220 is formed before the gate structure is formed.

[0157] As an example, the top surface of the second dielectric layer 220 is flush with the top surface of the first dielectric layer 200.

[0158] As an example, the material of the second dielectric layer 220 is silicon oxide. In other embodiments, the second dielectric layer may also be an insulating material such as silicon nitride or silicon oxynitride.

[0159] It should be noted that, for ease of illustration and explanation, the second dielectric layer 220 is represented by a dashed box in the perspective view in the following figures.

[0160] refer to Figures 20 to 22 , Figure 20 This is a top view of an SRAM cell. Figure 21 for Figure 20 The corresponding partial 3D image, Figure 22 for Figure 21 In the corresponding top view, a gate structure 230 is formed in the first dielectric layer 200 between adjacent active regions A. The gate structure 230 extends in a direction perpendicular to the substrate 100 and is disposed opposite to the channel layer 12.

[0161] When the device is in operation, the gate structure 230 is used to control the opening and closing of the conductive channel.

[0162] The gate structure 230 extends in a direction perpendicular to the substrate 100 and is disposed opposite to the channel layer 12. The gate structure 230 and the adjacent stacked structure 110 are used to form a MOS device. Compared with planar devices and devices in which the gate structure surrounds or encloses the channel layer, the SRAM cell provided in this embodiment of the invention occupies a smaller area, which is beneficial for reducing the device size.

[0163] It should be noted that, along the direction parallel to the substrate, there is a gap between the gate structure 230 and the adjacent stacked structure 110, so that the first dielectric layer 200 located between the gate structure 230 and the adjacent stacked structure 110 can retain a portion of its thickness to serve as a gate dielectric layer, thereby achieving isolation between the gate structure 230 and the adjacent stacked structure 110.

[0164] As an example, the gate structure 230 is a metal gate structure. The gate structure 230 may include a metal electrode layer. The material of the metal electrode layer includes one or more of W, Al, Cu, Ag, Au, Pt, Ni, and Ti.

[0165] In this embodiment, after forming the bottom interconnect layer 210, a gate structure 230 is formed in the first dielectric layer 200 of the gate region G, which helps to reduce the probability of the process steps of forming the gate structure 230 damaging the bottom interconnect layer 210.

[0166] More specifically, after the second dielectric layer 220 is formed, the gate structure 230 is formed.

[0167] It should also be noted that in this embodiment, in the first inverter region H1, the second inverter region H2 and the transmission gate region PG, the adjacent active regions A share the gate structure 230, which is beneficial to further save the area of ​​the device.

[0168] As an example, the steps of forming the gate structure 230 include: forming a gate trench (not shown) in the first dielectric layer 200 of the gate region G, with an overlapping region between the gate trench and the channel layer 12 along a projection plane perpendicular to the substrate 100, and with a gap between the sidewalls of the gate trench and the stacked structure 110; and forming the gate structure 230 within the gate trench.

[0169] The gate trench is used to provide spatial location for forming the gate structure 230.

[0170] Along the projection plane perpendicular to the substrate 100, there is an overlapping area between the gate trench and the channel layer 12, so that the gate structure subsequently formed in the gate trench can be positioned opposite to the channel layer 12, and thus, when the device is working, the gate structure can control the opening and closing of the conductive channel in the channel layer 12.

[0171] There is a gap between the sidewall of the gate trench and the stacked structure 110, thereby preventing the gate structure subsequently formed in the gate trench from contacting the stacked structure 110.

[0172] In this embodiment, the process of forming the gate structure 230 in the gate trench includes one or more of chemical vapor deposition, physical vapor deposition and electrochemical plating processes.

[0173] Continue to refer to Figures 20 to 22 In this embodiment, the method for forming an SRAM cell further includes: forming a top conductive structure 240 in a first dielectric layer 200 on the top doped layer 14, which is in contact with the top doped layer 14.

[0174] By forming the top conductive structure 240, electrical connections between the top doped layer 14 and external circuits or other film structures can be achieved.

[0175] As an example, after forming the gate structure 230, the top conductive structure 240 is formed.

[0176] The top conductive structure 240 is made of a conductive material. As an example, the top conductive structure 240 is made of a metal, including one or more of copper, tungsten, cobalt, nickel, and aluminum.

[0177] In this embodiment, the step of forming the top conductive structure 240 includes: forming a top interconnect trench (not shown) in the first dielectric layer 200 on the top doped layer 14 to expose the top doped layer 14; and forming the top conductive structure 240 in the top interconnect trench.

[0178] refer to Figures 23 to 25 , Figure 23 This is a top view of an SRAM cell. Figure 24 for Figure 23 The corresponding partial 3D image, Figure 25 for Figure 24 The corresponding top view shows that the method of forming the SRAM cell further includes: forming a bottom conductive structure 250 on the bottom interconnect layer 210, which is in contact with the bottom interconnect layer 210.

[0179] By forming a bottom interconnect layer 210 and a bottom conductive structure 250, the electrical properties of the bottom doped layer 11 can be brought out to achieve electrical connection between the bottom doped layer 11 and external circuits or other film structures.

[0180] The bottom conductive structure 250 is made of a conductive material. As an example, the bottom conductive structure 250 is made of a metal, including one or more of copper, tungsten, cobalt, nickel, and aluminum.

[0181] In this embodiment, the bottom conductive structure 250 penetrates the second dielectric layer 220 located on top of the bottom interconnect layer 210.

[0182] In this embodiment, the step of forming the bottom conductive structure 250 includes: forming a contact hole (not shown) through the second dielectric layer 220 on the bottom interconnect layer 210 to expose the bottom interconnect layer 210; and forming the bottom conductive structure 250 in the contact hole.

[0183] As an example, in the stacked structure 110, the bottom doped layer 11 is used as the source and the top doped layer 14 is used as the drain.

[0184] In this embodiment, the bottom conductive structure 250 of the first pull-up region PU1 is connected to VDD, and the bottom conductive structure 250 of the first pull-down region PD1 is connected to VSS.

[0185] In this embodiment, the bottom conductive structure 250 of the second pull-up region PU2 is connected to VDD, and the bottom conductive structure 250 of the second pull-down region PD2 is used to connect to VSS.

[0186] In this embodiment, the bottom conductive structure 250 of the gate region PG is connected to the bit line (BL), and the gate structure 230 is connected to the word line (WL).

[0187] In this embodiment, the method for forming an SRAM cell further includes: forming a first electrical connection structure (not shown), which electrically connects the top conductive structure 240 of the first pull-up region PU1 to the top conductive structure 240 of the first pull-down region PD1, the top conductive structure 240 of the first transfer region PG1, and the gate structure 230 of the second inverter region H2; and forming a second electrical connection structure (not shown), which electrically connects the top conductive structure 240 of the second pull-up region PU2 to the top conductive structure 240 of the second pull-down region PD2, and the top conductive structure 240 of the second transfer region PG2 to the gate structure 230 of the first inverter region H1.

[0188] The first and second electrical connection structures are made of conductive materials. In this embodiment, the first and second electrical connection structures are made of metallic materials, such as copper, tungsten, cobalt, nickel, etc.

[0189] In other words, the source of the first pull-up transistor is connected to VDD, the drain of the first pull-up transistor is electrically connected to the drain of the first pull-down transistor, the drain of the first transfer transistor, and the gate structure 230 of the second pull-up transistor and the second pull-down transistor, and the source of the first pull-down transistor is connected to VSS.

[0190] In this embodiment, the source of the second pull-up transistor is connected to VDD, and the drain of the second pull-up transistor is electrically connected to the drain of the second pull-down transistor, the drain of the second transfer transistor, and the gate structure 230 of the first pull-up transistor and the first pull-down transistor. The source of the second pull-down transistor is used to connect to VSS.

[0191] In this embodiment, the sources of the first and second transmission transistors are connected to the bit line (BL), and the gate structure 230 of the first and second transmission transistors is connected to the word line (WL).

[0192] In other embodiments, the bottom doped layer is used as the drain and the top doped layer is used as the source.

[0193] Accordingly, the top conductive structure of the first pull-up region is connected to VDD, and the bottom conductive structure of the first pull-up region is electrically connected to the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transmission region, and the gate structure of the second inverter region. The top conductive structure of the first pull-down region is connected to VSS. The top conductive structure of the second pull-up region is connected to VDD, and the bottom conductive structure of the second pull-up region is electrically connected to the bottom conductive structure of the second pull-down region, the bottom conductive structure of the second transmission region, and the gate structure of the first inverter region. The top conductive structure of the second pull-down region is connected to VSS. The top conductive structure of the transmission gate region is connected to the bit line, and the gate structure is connected to the word line.

[0194] Accordingly, the method for forming an SRAM cell further includes: forming a third electrical connection structure that electrically connects the bottom conductive structure of the first pull-up region with the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transmission region, and the gate structure of the second inverter region; and forming a fourth electrical connection structure that electrically connects the bottom conductive structure of the second pull-up region with the bottom conductive structure of the second pull-down region, and the bottom conductive structure of the second transmission region with the gate structure of the first inverter region.

[0195] In this embodiment, the method for forming an SRAM cell further includes forming a gate conductive structure 260 on the top of the gate structure 230, which is in contact with the gate structure 230. The gate conductive structure 260 is used to realize the electrical connection between the gate structure 230 and external circuits or other film structures.

[0196] The gate conductive structure 260 is made of a conductive material. In this embodiment, the gate conductive structure 260 is made of a metallic material, such as copper, tungsten, cobalt, nickel, etc.

[0197] Accordingly, this embodiment of the invention also provides an SRAM device, comprising multiple arrayed SRAM cells, wherein the SRAM cells are the SRAM cells provided in this embodiment of the invention.

[0198] In this embodiment, the SRAM cell occupies a smaller area, which is beneficial for reducing the size of the SRAM device. Moreover, the first dielectric layer can provide mechanical support for the vertically stacked structure, reducing the probability of the stacked structure collapsing or tilting. On the other hand, it can also help to achieve a smaller distance between adjacent devices, thereby improving the integration density of the SRAM device.

[0199] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An SRAM cell, characterized in that, include: The substrate includes a first inverter region, a second inverter region, and a gate region arranged along a first direction; the first inverter region, the second inverter region, and the gate region each include adjacent active regions arranged along the first direction. A stacked structure is located on the substrate of the active region. The stacked structure includes a bottom doped layer, a channel layer, and a top doped layer stacked sequentially along a direction perpendicular to the substrate. The bottom doped layer and the top doped layer have the same doping type. In the first inverter region and the second inverter region, the channel layers of adjacent active regions have different conductivity types. In the gate region, the channel layers of adjacent active regions have the same conductivity type; A first dielectric layer is located between the stacked structures along a first direction and covers the top of the stacked structures; A gate structure is located in a first dielectric layer between the adjacent active regions, the gate structure extending in a direction perpendicular to the substrate and disposed opposite to the channel layer.

2. The SRAM cell as described in claim 1, characterized in that, The SRAM cell further includes: a bottom interconnect layer, which is located on the substrate on the side of the stacked structure and the first dielectric layer, and in a second direction, the bottom interconnect layer is in contact with the sidewall of the bottom doped layer and exposes the channel layer; the second direction is parallel to the substrate and perpendicular to the first direction. A bottom conductive structure is located on and in contact with the bottom interconnect layer; The top conductive structure is located in the first dielectric layer on the top doped layer and is in contact with the top doped layer.

3. The SRAM cell as described in claim 2, characterized in that, In the stacked structure, the bottom doped layer serves as the source, the top doped layer serves as the drain, and the bottom interconnect layer serves as the power rail. The first inverter region includes a first pull-down region and a first pull-up region; the second inverter region includes a second pull-down region and a second pull-up region; the gate region includes a first transmission region and a second transmission region; The bottom conductive structure of the first pull-up region is connected to VDD, and the top conductive structure of the first pull-up region is electrically connected to the top conductive structure of the first pull-down region, the top conductive structure of the first transmission region, and the gate structure of the second inverter region. The bottom conductive structure of the first pull-down region is connected to VSS. The bottom conductive structure of the second pull-up region is connected to VDD, the top conductive structure of the second pull-up region is electrically connected to the top conductive structure of the second pull-down region, the top conductive structure of the second transmission region is electrically connected to the gate structure of the first inverter region, and the bottom conductive structure of the second pull-down region is used to connect to VSS. The bottom conductive structure of the portal area is connected to the bit line, and the gate structure is connected to the word line.

4. The SRAM cell as described in claim 2, characterized in that, In the stacked structure, the bottom doped layer is used as the drain and the top doped layer is used as the source. The first inverter region includes a first pull-down region and a first pull-up region; the second inverter region includes a second pull-down region and a second pull-up region; the gate region includes a first transmission region and a second transmission region; The top conductive structure of the first pull-up region is connected to VDD, the bottom conductive structure of the first pull-up region is electrically connected to the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transmission region, and the gate structure of the second inverter region, and the top conductive structure of the first pull-down region is connected to VSS. The top conductive structure of the second pull-up region is connected to VDD, the bottom conductive structure of the second pull-up region is electrically connected to the bottom conductive structure of the second pull-down region, the bottom conductive structure of the second transmission region is electrically connected to the gate structure of the first inverter region, and the top conductive structure of the second pull-down region is connected to VSS. The top conductive structure of the portal area is connected to the bit line, and the gate structure is connected to the word line.

5. The SRAM cell as claimed in claim 1, characterized in that, In the stacked structure, either the bottom doped layer or the top doped layer is used as the source, and the other is used as the drain. The stacked structure also includes a gradually changing doped layer located between the channel layer and the drain. The doping type of the gradually changing doped layer is the same as that of the drain, and the doping concentration of the gradually changing doped layer is lower than that of the drain.

6. The SRAM cell as described in claim 2, characterized in that, The SRAM cell further includes: a second dielectric layer located on a substrate on the side of the stacked structure and the first dielectric layer and covering the bottom interconnect layer; the bottom conductive structure extends through the second dielectric layer located on top of the bottom interconnect layer.

7. The SRAM cell as claimed in claim 1, characterized in that, The gate structure is spaced apart from the adjacent stacked structure.

8. An SRAM device, characterized in that, include: Multiple SRAM cells arranged in an array, wherein the SRAM cells are the SRAM cells as described in any one of claims 1 to 7.

9. A method for forming an SRAM cell, characterized in that, include: A substrate is provided, including an SRAM cell region, a first inverter region, a second inverter region, and a gate region arranged along a first direction; the first inverter region, the second inverter region, and the gate region each include adjacent active regions arranged along the first direction. A stacked structure located in the active region and a first dielectric layer located between the stacked structures and covering the top of the stacked structure are formed on the substrate. The stacked structure includes a bottom doped layer, a channel layer and a top doped layer stacked sequentially along a direction perpendicular to the substrate. The bottom doped layer and the top doped layer have the same doping type. In the first inverter region and the second inverter region, the channel layers of adjacent active regions have different conductivity types. In the gate region, the channel layers of adjacent active regions have the same conductivity type; The region located between adjacent active regions along the first direction is the gate region; A gate structure is formed in the first dielectric layer of the gate region, the gate structure extending in a direction perpendicular to the substrate and disposed opposite to the channel layer.

10. The method for forming an SRAM cell as described in claim 9, characterized in that, The direction parallel to the substrate and perpendicular to the first direction is the second direction. The method for forming the SRAM cell further includes: A bottom interconnect layer is formed on the substrate on the side of the stacked structure and the first dielectric layer. Along the second direction, the bottom interconnect layer is in corresponding contact with the sidewall of the bottom doped layer and exposes the channel layer. A top conductive structure is formed in the first dielectric layer on the top doped layer, and is in contact with the top doped layer; A bottom conductive structure is formed on the bottom interconnect layer and is in contact with the bottom interconnect layer.

11. The method for forming an SRAM cell as described in claim 10, characterized in that, In the stacked structure, the bottom doped layer serves as the source and the top doped layer serves as the drain; in the step of forming the bottom interconnect layer, the bottom interconnect layer serves as the power rail. The first inverter region includes a first pull-down region and a first pull-up region; the second inverter region includes a second pull-down region and a second pull-up region; the gate region includes a first transmission region and a second transmission region; The bottom conductive structure of the first pull-up area is used to connect to VDD, and the bottom conductive structure of the first pull-down area is used to connect to VSS; the bottom conductive structure of the second pull-up area is connected to VDD, and the bottom conductive structure of the second pull-down area is used to connect to VSS. The bottom conductive structure of the portal area is connected to the bit line, and the gate structure is connected to the word line. The method for forming the SRAM cell further includes: after forming the bottom conductive structure and the top conductive structure, forming a first electrical connection structure that electrically connects the top conductive structure of the first pull-up region with the top conductive structure of the first pull-down region, the top conductive structure of the first transmission region, and the gate structure of the second inverter region. A second electrical connection structure is formed, which electrically connects the top conductive structure of the second pull-up region with the top conductive structure of the second pull-down region, and the top conductive structure of the second transmission region with the gate structure of the first inverter region.

12. The method for forming an SRAM cell as described in claim 10, characterized in that, In the stacked structure, the bottom doped layer is used as the drain and the top doped layer is used as the source. The first inverter region includes a first pull-down region and a first pull-up region; the second inverter region includes a second pull-down region and a second pull-up region; the gate region includes a first transmission region and a second transmission region; The top conductive structure of the first pull-up area is connected to VDD, and the top conductive structure of the first pull-down area is connected to VSS; the top conductive structure of the second pull-up area is connected to VDD, and the top conductive structure of the second pull-down area is connected to VSS. The top conductive structure of the portal area is connected to the bit line, and the gate structure is connected to the word line. The method for forming the SRAM cell further includes: forming a third electrical connection structure that electrically connects the bottom conductive structure of the first pull-up region with the bottom conductive structure of the first pull-down region, the bottom conductive structure of the first transmission region, and the gate structure of the second inverter region; A fourth electrical connection structure is formed, which electrically connects the bottom conductive structure of the second pull-up region to the bottom conductive structure of the second pull-down region, and the bottom conductive structure of the second transmission region to the gate structure of the first inverter region.

13. The method for forming an SRAM cell as described in claim 10, characterized in that, The substrate further includes an interconnect region adjacent to the active region along a second direction; the step of forming the stacked structure and the first dielectric layer includes: forming an initial stacked structure located on the active region and the interconnect region and an initial isolation wall located between the initial stacked structure along a first direction on the substrate, the initial stacked structure and the initial isolation wall extending along the second direction; An isolation layer spanning the active region is formed on top of the initial stacked structure and the initial isolation wall, exposing the interconnection region; The initial stacked structure and the initial isolation wall exposed by the isolation layer are removed, and the remaining initial stacked structure is used as the stacked structure, and the remaining initial isolation wall is used as the isolation wall. The isolation wall and the isolation layer are used to form the first dielectric layer.

14. The method for forming an SRAM cell as described in claim 13, characterized in that, The steps of forming the initial stacked structure and the initial isolation wall include: forming discrete initial isolation walls on the substrate to expose the active region; and forming the initial stacked structure on the substrate between the initial isolation walls.

15. The method for forming an SRAM cell as described in claim 9, characterized in that, In the step of forming the stacked structure and the first dielectric layer, in the stacked structure, either the bottom doped layer or the top doped layer is used as the source and the other is used as the drain. In the step of forming the stacked structure, the stacked structure further includes a gradually changing doped layer located between the channel layer and the drain, wherein the doping type of the gradually changing doped layer is the same as that of the drain, and the doping concentration of the gradually changing doped layer is lower than that of the drain.

16. The method for forming an SRAM cell as described in claim 10, characterized in that, After the bottom interconnect layer is formed, a gate structure is formed in the first dielectric layer of the gate region.

17. The method for forming an SRAM cell as described in claim 13, characterized in that, The step of forming the bottom interconnect layer includes: covering an interconnect material layer on a substrate on the side of the stacked structure and the first dielectric layer to expose the channel layer and the top doped layer; removing the interconnect material layer located between the interconnect regions, and using the remaining interconnect material layer on the interconnect regions as the bottom interconnect layer.

18. The method for forming an SRAM cell as described in claim 10, characterized in that, The method for forming the SRAM cell further includes: after forming the bottom interconnect layer and before forming the bottom conductive structure, forming a second dielectric layer on the substrate on the side of the stacked structure and the first dielectric layer to cover the bottom interconnect layer; in the step of forming the bottom conductive structure, the bottom conductive structure penetrates the second dielectric layer located on top of the bottom interconnect layer.

19. The method for forming an SRAM cell as described in claim 9, characterized in that, The step of forming a gate structure in the first dielectric layer of the gate region includes: forming a gate trench in the first dielectric layer of the gate region, with an overlapping region between the gate trench and the channel layer along a projection plane perpendicular to the substrate, and a gap between the sidewall of the gate trench and the stacked structure; and forming the gate structure within the gate trench.

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