Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: forming a pattern material layer on a substrate, forming a first core material layer on the pattern material layer, the substrate including alternately arranged transistor regions and interval regions, the pattern material layer of the transistor regions being used to form target patterns; forming discrete and parallel first core layers on the first core material layer, the first core layers including first sub-core layers covering the interval regions, the line width of the first sub-core layers being the sum of the line width of the interval regions and twice the target line width of the target patterns; forming first side walls on the side walls of the first core layers; removing the first core layers; patterning the first core material layer with the first side walls as a mask to form second core layers; forming second side walls on the side walls of the second core layers, in the transistor regions, the second side walls located between adjacent second core layers being in contact; removing the second core layers; patterning the pattern material layer with the second side walls as a mask to form the target patterns. The method improves the design freedom of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Photolithography is a commonly used patterning method and one of the most critical production technologies in semiconductor manufacturing. As the critical dimension (CD) of patterns continues to shrink, self-aligned double patterning (SADP) can no longer meet current process requirements, leading to the development of self-aligned quadruple patterning (SAQP).

[0003] However, the traditional self-aligned quadruple patterning method has some limitations. In the same area, the line width of the target pattern must be uniform, and the pitch of two adjacent target patterns in the target pattern must also be uniform. Therefore, it is difficult to flexibly control the pitch of the target pattern, which also has great limitations on the production of various types of devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the design freedom of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a patterned material layer on the substrate, forming a first core material layer on the patterned material layer, the substrate including alternating transistor regions and spacer regions, the patterned material layer of the transistor regions being used to form target patterns; forming discrete and parallel first core layers on the first core material layer, the first core layer including a first sub-core layer covering the spacer regions, the linewidth of the first sub-core layer being the sum of the linewidth of the spacer regions and twice the target linewidth of the target pattern; forming a first sidewall on the sidewall of the first core layer; after forming the first sidewall, removing the first core layer; after removing the first core layer, patterning the first core material layer using the first sidewall as a mask to form a second core layer; forming a second sidewall on the sidewall of the second core layer, the second sidewalls located between adjacent second core layers in the transistor regions being in contact; after forming the second sidewall, removing the second core layer; after removing the second core layer, patterning the patterned material layer using the second sidewall as a mask to form multiple target patterns in the transistor regions.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the forming method provided by the embodiments of the present invention, discrete and parallel first core layers are formed on a first core material layer. The first core layer includes a first sub-core layer covering the interval area. The linewidth of the first sub-core layer is the sum of the linewidth of the interval area and twice the target linewidth of the target pattern. A first sidewall is formed on the sidewall of the first core layer. After forming the first sidewall, the first core layer is removed. After removing the first core layer, the first core material layer is patterned using the first sidewall as a mask to form a second core layer. A second sidewall is formed on the sidewall of the second core layer. In the transistor region, the second sidewalls located between adjacent second core layers are in contact. In this embodiment of the invention, by making the second sidewalls located between adjacent second core layers contact each other, a required number of second sidewalls (e.g., an odd number) can be formed, thereby obtaining a target pattern that meets the required number. Meanwhile, the linewidth of the first sub-core layer is the sum of the linewidth of the spacing region and twice the target linewidth of the target pattern. Therefore, by adjusting the linewidth of the first sub-core layer, the required linewidth of the spacing region can be obtained, reducing the influencing factors that need to be considered when adjusting the linewidth of the spacing region. This is beneficial to improving the adjustment accuracy of the linewidth of the spacing region, and can also meet the requirements of different types of processes, thereby increasing the design freedom of the semiconductor structure. Attached Figure Description

[0008] Figure 1 This is a schematic diagram showing the relative positional relationship between the core layer, the first sidewall, the second sidewall, and the target pattern in a method for forming a semiconductor structure.

[0009] Figure 2 This is a schematic diagram showing the relative positional relationship between the core layer, the first sidewall, the second sidewall, and the target pattern in one embodiment of the semiconductor structure formation method of the present invention.

[0010] Figures 3 to 12 This is a schematic diagram corresponding to an embodiment of the method for forming a semiconductor structure according to the present invention;

[0011] Figure 13 This is a schematic diagram illustrating the relative positional relationship between the core layer, the first sidewall, the second sidewall, and the target pattern in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] Currently, the design freedom of semiconductor structures needs to be improved. This paper analyzes the reasons why the design freedom of semiconductor structures needs to be improved by examining a semiconductor structure formation method.

[0013] Figure 1 This is a schematic diagram showing the relative positions of the core layer, the first sidewall, the second sidewall, and the target pattern in a method for forming a semiconductor structure.

[0014] refer to Figure 1A substrate (not shown) is provided, on which a patterned material layer (not shown) is formed, and on which a first core material layer (not shown) is formed. The substrate includes alternating transistor regions 10a and spacer regions 10b. The patterned material layer of transistor regions 10a is used to form the target pattern 14. A discrete and parallel first core layer 31 is formed on the first core material layer. A first sidewall 51 is formed on the sidewall of the first core layer 31. After forming the first sidewall 51, the first core layer 31 is removed. After removing the first core layer 31, the first core material layer is patterned using the first sidewall 51 as a mask to form a second core layer 22. A second sidewall 61 is formed on the sidewall of the second core layer 22. After forming the second sidewall 61, the second core layer 22 is removed. After removing the second core layer 22, the second sidewall 61 located in the spacer region 10b is removed (e.g., ...). Figure 1 (The second sidewall 61 is shown by the dashed line in the middle); after removing the second sidewall 61 located in the interval region 10b, the remaining second sidewall 61 is used as a mask to pattern the pattern material layer, and multiple target patterns 14 are formed in the transistor region 10a.

[0015] In the prior art, in order to obtain a sufficient number of target patterns 14 and correspondingly a sufficient number of second sidewalls 61, it is necessary to remove the second sidewalls 61 located in the spacing region 10b after forming the second sidewalls 61. This process is cumbersome. Moreover, in actual processes, the linewidth of the spacing region 10b usually needs to be adjusted according to actual requirements, especially in SRAM devices, where the linewidth of an SRAM cell region (such as...) Figure 1 In the dashed box shown in the middle, the linewidth of the spacing region 10b between adjacent transistor regions 10a is usually large. Adjusting the linewidth of the spacing region 10b to meet the requirements will be affected by the spacing between adjacent first core layers 31 and adjacent second core layers 22, making it difficult to adjust the linewidth of the spacing region 10b with precision, thus limiting the design freedom of the semiconductor structure.

[0016] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a patterned material layer on the substrate, forming a first core material layer on the patterned material layer, the substrate including alternating transistor regions and spacer regions, the patterned material layer of the transistor regions being used to form target patterns; forming discrete and parallel first core layers on the first core material layer, the first core layer including a first sub-core layer covering the spacer regions, the linewidth of the first sub-core layer being the sum of the linewidth of the spacer regions and twice the target linewidth of the target pattern; forming a first sidewall on the sidewall of the first core layer; after forming the first sidewall, removing the first core layer; after removing the first core layer, patterning the first core material layer using the first sidewall as a mask to form a second core layer; forming a second sidewall on the sidewall of the second core layer, the second sidewalls located between adjacent second core layers in the transistor regions being in contact; after forming the second sidewall, removing the second core layer; after removing the second core layer, patterning the patterned material layer using the second sidewall as a mask to form multiple target patterns in the transistor regions.

[0017] In this embodiment of the invention, by making the second sidewalls located between adjacent second core layers contact each other, a required number of second sidewalls (e.g., an odd number) can be formed, thereby obtaining a target pattern that meets the required number. Meanwhile, the linewidth of the first sub-core layer is the sum of the linewidth of the spacing region and twice the target linewidth of the target pattern. Therefore, by adjusting the linewidth of the first sub-core layer, the required linewidth of the spacing region can be obtained, reducing the influencing factors that need to be considered when adjusting the linewidth of the spacing region. This is beneficial to improving the adjustment accuracy of the linewidth of the spacing region, and can also meet the requirements of different types of processes, thereby increasing the design freedom of the semiconductor structure.

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Figure 2 This is a schematic diagram showing the relative positional relationship between the core layer, the first sidewall, the second sidewall, and the target pattern in one embodiment of the semiconductor structure formation method of the present invention. Figures 3 to 12 This is a schematic diagram of the steps corresponding to an embodiment of the method for forming a semiconductor structure according to the present invention, combined with... Figure 2 right Figures 3 to 12 A detailed explanation will be provided.

[0020] refer to Figure 3 A substrate 100 is provided, on which a pattern material layer 110 is formed, and a first core material layer 200 is formed on the pattern material layer 110. The substrate 100 includes alternating transistor regions 100a and spacer regions 100b. The pattern material layer 110 of the transistor regions 100a is used to form a target pattern 140.

[0021] The substrate 100 provides a process platform for subsequent manufacturing processes. Specifically, transistor region 100a is the region used to form devices, and spacer region 100b is the region used to obtain the spacing between devices.

[0022] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0023] In this embodiment, the substrate may also include other structures, such as gate structures, doped regions, shallow trench isolation structures, etc.

[0024] In this embodiment, the semiconductor structure includes a FinFET, a Forksheet transistor, a nanosheet FET, a Complementary Field Effect Transistor (CFET), or a Vertical Field Effect Transistor (VFET).

[0025] In this embodiment, taking a fin field-effect transistor as an example, the formation method is used to form a channel bump. Therefore, the pattern material layer 110 formed on the substrate 100 includes a channel material layer, which provides an operational basis for forming the channel bump. The target pattern 140 includes a channel bump structure. Specifically, the material of the channel material layer includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0026] In other embodiments, the forming method can also be used to form other types of patterns, such as forming a gate structure, i.e., the target pattern formed is a gate structure and the pattern material layer is a gate material layer, or the pattern material layer can also be an inter-metal dielectric layer and the target pattern formed is an interconnect trench in the inter-metal dielectric layer.

[0027] In this embodiment, the semiconductor structure is an SRAM device. The SRAM device typically includes multiple transistor regions 100a and spacer regions 100b located between the transistor regions 100a, which is particularly suitable for embodiments of the present invention.

[0028] In this embodiment, we continue to refer to Figure 2In the step of providing substrate 100, substrate 100 includes a plurality of SRAM cell regions 100c. SRAM cell regions 100c include transistor regions 100a spaced apart and spacer regions 100b located between transistor regions 100a. Transistor regions 100a are used to form PMOS transistors or NMOS transistors. Target pattern 140 is used to form a protrusion structure of transistor regions 100a.

[0029] This embodiment takes a 7.5T SRAM device as an example. In the SRAM cell region 100c, each transistor region 100a needs to form three bump structures, and the three bump structures constitute a transistor structure. Specifically, the transistor regions 100a spaced apart in the SRAM cell region 100c are used to form PMOS transistors and NMOS transistors, respectively. The linewidth of the spacing region 100b between adjacent transistor regions 100a is relatively large and needs to meet the actual design requirements.

[0030] The first core material layer 200 is used to form the second core layer in the future.

[0031] In this embodiment, the second core layer needs to be removed subsequently. Therefore, the first core material layer 200 is made of an easily removable material. The material of the first core material layer 200 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide. Specifically, the material of the first core material layer 200 is amorphous silicon.

[0032] In this embodiment, we continue to refer to Figure 3 In the step of providing the substrate 100, a first mask material layer 210 is also formed on the first core material layer 200.

[0033] The first mask material layer 210 is used to form the second mask layer in the future.

[0034] In this embodiment, the material of the first mask material layer 210 includes one or more of silicon oxide and silicon nitride, that is, the first mask material layer 210 can be a single-layer structure or a stacked structure. As an example, the material of the first mask material layer 210 is silicon nitride, that is, the first mask material layer 210 is a single-layer structure.

[0035] In this embodiment, during the step of providing the substrate 100, a second mask material layer 120 is also formed between the pattern material layer 110 and the first core material layer 200.

[0036] The second mask material layer 120 is used to form the third mask layer in the future.

[0037] In this embodiment, the material of the second mask material layer 120 includes one or more of silicon oxide and silicon nitride, that is, the second mask material layer 120 can be a single-layer structure or a multilayer structure. As an example, the material of the second mask material layer 120 is silicon oxide and silicon nitride, that is, the second mask material layer 120 is a multilayer structure, including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

[0038] Reference Figures 2 to 4 A discrete and parallel first core layer 310 is formed on the first core material layer 200. The first core layer 310 includes a first sub-core layer 320 covering the interval area 100b. The line width d0 of the first sub-core layer 320 is the sum of the line width d1 of the interval area 100b and twice the target line width d2 of the target pattern 140.

[0039] Subsequently, a first sidewall is formed on the side wall of the first core layer 310, and the first core layer 310 serves as a support for the subsequent formation of the first sidewall. The line width of the first core layer 310 and the spacing between adjacent first core layers 310 are also used to define the spacing between subsequent adjacent first sidewalls.

[0040] In this embodiment, the linewidth d0 of the first sub-core layer 320 is the sum of the linewidth d1 of the interval region 100b and twice the target linewidth d2 of the target pattern 140, thereby enabling the linewidth d1 of the interval region 100b to be defined by defining the linewidth d0 of the first sub-core layer 320.

[0041] The first core layer 310 needs to be removed subsequently. Therefore, the first core layer 310 is made of an easily removable material. The material of the first core layer 310 includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide. In this embodiment, the material of the first core layer 310 is amorphous silicon.

[0042] Specifically, please refer to Figure 3 The step of forming a discrete and parallel first core layer 310 on the first core material layer 200 includes: forming a second core material layer 300 covering the first core material layer 200.

[0043] The second core material layer 300 is used to form the first core layer 310.

[0044] In this embodiment, the material of the second core material layer 300 is amorphous silicon.

[0045] In this embodiment, a discrete first mask layer 400 is formed on the second core material layer 300.

[0046] The first mask layer 400 is used as an etching mask for forming the first core layer 310.

[0047] refer to Figure 4 The first core layer 310 is formed by patterning the second core material layer 300 using the first mask layer 400 as a mask.

[0048] In this embodiment, after forming the first core layer 310, the method further includes: removing the first mask layer 400.

[0049] In this process, the first mask layer 400 is removed to prepare for the subsequent formation of the first sidewall.

[0050] Reference Figure 5 and Figure 6 The first sidewall 510 is formed on the sidewall of the first core layer 310.

[0051] In this embodiment, the first sidewall 510 is used as an etching mask for the subsequent patterning of the first core material layer 200.

[0052] It should be noted that, for the sake of clarity in the subsequent illustrations, Figure 6 The figure shows a first sidewall 510 formed on the sidewalls of the first core layer 310 adjacent to both sides of the first core layer 310 shown in the figure (e.g., Figure 6 (As shown in the dashed outline of the first sidewall 510).

[0053] In this embodiment, the material of the first sidewall 510 includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the first sidewall 510 is titanium oxide. Since the first core layer 310 needs to be removed subsequently while retaining the first sidewall 510, titanium oxide and amorphous silicon have a high etching selectivity, which is beneficial for the first sidewall 510 to be retained in the subsequent step of removing the first core layer 310.

[0054] In this embodiment, in conjunction with the reference Figure 2 , Figure 5 and Figure 6 In the step of forming the first sidewall 510 on the sidewall of the first core layer 310, in the transistor region 100a, the spacing d3 between adjacent first sidewalls 510 is a preset spacing, and the preset spacing is equal to the target linewidth d2 of the target pattern 140.

[0055] The spacing d3 between adjacent first side walls 510 is the line width of the subsequent graphic converted into the second side wall, and the line width of the second side wall is the line width of the subsequent graphic converted into the target graphic 140. Thus, the spacing d3 between adjacent first side walls 510 is used to define the line width of the target graphic 140. Therefore, the preset spacing is equal to the target line width d2 of the target graphic 140, so that the target graphic 140 with the target line width d2 is obtained later.

[0056] Specifically, please refer to Figure 5The step of forming a first sidewall 510 on the sidewall of the first core layer 310 includes forming a first sidewall material layer 500 covering the top and sidewall of the first core layer 310 and the top of the first core material layer 200.

[0057] The first sidewall material layer 500 is used to form the first sidewall 510.

[0058] In this embodiment, the material of the first sidewall material layer 500 is titanium oxide.

[0059] In this embodiment, the atomic layer deposition process is used to form the first sidewall material layer 500, which is beneficial to improve the conformal coverage of the first sidewall material layer 500, as well as to improve the thickness uniformity of the first sidewall material layer 500 and reduce the difficulty of accurately controlling the thickness of the first sidewall material layer 500, thereby improving the linewidth uniformity of the first sidewall 510.

[0060] refer to Figure 6 Remove the first sidewall material layer 510 located on top of the first core layer 310 and the first core material layer 200, and retain the first sidewall material layer 500 located on the sidewall of the first core layer 310 as the first sidewall 510.

[0061] In this embodiment, an anisotropic dry etching process is used to remove the first sidewall material layer 510 located on top of the first core layer 310 and the first core material layer 200. The anisotropic dry etching process has the characteristics of anisotropic etching, thus enabling the removal of the first sidewall material layer 510 located on top of the first core layer 310 and the first core material layer 200 without a mask, while simultaneously retaining the first sidewall material layer 500 on the sidewalls of the first core layer 310.

[0062] refer to Figure 7 After the first sidewall 510 is formed, the first core layer 310 is removed.

[0063] In this embodiment, the first core layer 310 is removed in preparation for patterning the first core material layer 200 using the first sidewall 510 as a mask.

[0064] In this embodiment, a wet etching process is used to remove the first core layer 310.

[0065] The wet etching process has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the first sidewall 510 during the removal of the first core layer 310.

[0066] refer to Figure 8 After removing the first core layer 310, the first core material layer 200 is patterned using the first sidewall 510 as a mask to form the second core layer 220.

[0067] Subsequently, a second sidewall is formed on the sidewall of the second core layer 220, and the second core layer 220 serves to support the formation of the second sidewall. The line width of the second core layer 220 and the spacing between adjacent second core layers 220 are also used to define the spacing between adjacent second sidewalls.

[0068] It should be noted that, Figure 8 The second core layer 220 of the dashed outline is composed of Figure 7 The first side wall 510, with its dashed outline, is transmitted from here.

[0069] In this embodiment, we continue to refer to Figure 2 The spacing d3 between adjacent first side walls 510 is a preset spacing, and the preset spacing is equal to the target line width d2 of the target graphic 140. Correspondingly, the spacing between adjacent second core layers 220 is equal to the target line width d2 of the target graphic 140.

[0070] In this embodiment, an anisotropic etching process is used to pattern the first core material layer 200.

[0071] Anisotropic etching processes have the characteristics of anisotropic etching. Therefore, by selecting anisotropic etching processes, etching becomes more directional, which is beneficial to improving the dimensional accuracy of the second core layer 220.

[0072] In this embodiment, the material of the second core layer 220 is amorphous silicon.

[0073] In this embodiment, the step of patterning the first core material layer 200 using the first sidewall 510 as a mask to form the second core layer 220 includes: patterning the first mask material layer 210 using the first sidewall 510 as a mask to form the second mask layer (not shown); and patterning the first core material layer 200 using the second mask layer as a mask to form the second core layer 220.

[0074] By transferring the pattern to the first core material layer 200 through the second mask layer to obtain the second core layer 220, it is beneficial to improve the pattern transfer accuracy, thereby improving the pattern size accuracy of the second core layer 220.

[0075] In this embodiment, after forming the second core layer 220, the method further includes: removing the second mask layer.

[0076] In this embodiment, the removal of the second mask layer prepares for the subsequent formation of a second sidewall on the sidewall of the second core layer 220.

[0077] Reference Figure 9 and Figure 10A second sidewall 610 is formed on the sidewall of the second core layer 220, and the second sidewall 610 located between adjacent second core layers 220 in the transistor region 100a is in contact with each other.

[0078] The second sidewall 610 is used as an etching mask for the subsequent patterned material layer 110.

[0079] In this embodiment, by making the second sidewalls 610 located between adjacent second core layers 220 contact each other, a required number of second sidewalls 610 (e.g., an odd number) can be formed, and a target pattern 140 that meets the required number can be obtained accordingly. At the same time, the linewidth d0 of the first sub-core layer 320 is the sum of the linewidth d1 of the spacing region 100b and twice the target linewidth d2 of the target pattern 140. Therefore, by adjusting the linewidth of the first sub-core layer 320, the required linewidth d1 of the spacing region 100b can be obtained, reducing the influence factors that need to be considered when adjusting the linewidth d1 of the spacing region 100b. This is beneficial to improving the adjustment accuracy of the linewidth d1 of the spacing region 100b, and can also meet the requirements of different types of processes, thereby improving the design freedom of the semiconductor structure.

[0080] In this embodiment, we continue to refer to Figure 2 The spacing d3 between adjacent first sidewalls 510 is a preset spacing, and the preset spacing is equal to the target line width d2 of the target graphic 140. Correspondingly, the spacing between adjacent second core layers 220 is equal to the target line width d2 of the target graphic 140. The second sidewalls 610 located between adjacent second core layers 220 are in contact, so the line width of the second sidewalls 610 located between adjacent second core layers 220 is equal to the target line width d2. Moreover, the second sidewalls 610 have a preset line width, and the preset spacing is equal to the preset line width. Thus, the line width of the second sidewalls 610 is equal to the target line width d2. Therefore, in the subsequent step of using the second sidewalls 610 as a mask to pattern the graphic material layer 110, the target graphic 140 with the target line width d2 can be obtained.

[0081] In this embodiment, the material of the second sidewall 610 includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide. In this embodiment, the material of the second sidewall 610 is titanium oxide. Since the second core layer 220 needs to be removed subsequently while retaining the second sidewall 610, the titanium oxide material and the amorphous silicon material have a high etching selectivity, which is beneficial for the second sidewall 610 to be retained in the subsequent step of removing the second core layer 220.

[0082] In this embodiment, refer to Figure 9The step of forming a second sidewall 610 on the sidewall of the second core layer 220 includes: forming a second sidewall material layer 600 covering the top and sidewall of the second core layer 220 and the top of the pattern material layer 110, wherein the second sidewall material layers 600 located between adjacent second core layers 220 are in contact in the transistor region 100a.

[0083] In this embodiment, the second sidewall material layer 600 is used to form the second sidewall 610. The second sidewall material layer 600 located between adjacent second core layers 220 is in contact with each other, and correspondingly, the second sidewall 610 located between adjacent second core layers 220 is in contact with each other.

[0084] In this embodiment, the material of the second sidewall material layer 600 is titanium oxide.

[0085] In this embodiment, the atomic layer deposition process is used to form the second sidewall material layer 600, which is beneficial to improve the conformal coverage of the second sidewall material layer 600, as well as to improve the thickness uniformity of the second sidewall material layer 600 and reduce the difficulty of accurately controlling the thickness of the second sidewall material layer 600, thereby improving the linewidth uniformity of the second sidewall 610.

[0086] refer to Figure 10 Remove the second sidewall material layer 600 located on top of the second core layer 220 and the top of the graphic material layer 110, and retain the second sidewall material layer 600 located on the sidewall of the second core layer 220 as the second sidewall 610.

[0087] In this embodiment, an anisotropic dry etching process is used to remove the second sidewall material layer 600 located on top of the second core layer 220 and the pattern material layer 110. The anisotropic dry etching process has the characteristics of anisotropic etching, thus enabling the removal of the second sidewall material layer 600 located on top of the second core layer 220 and the pattern material layer 110 without a mask, while simultaneously retaining the second sidewall material layer 600 on the sidewalls of the second core layer 220.

[0088] refer to Figure 11 After the second sidewall 610 is formed, the second core layer 220 is removed.

[0089] In this embodiment, the second core layer 220 is removed in preparation for patterning the graphic material layer 110 using the second sidewall 610 as a mask.

[0090] In this embodiment, a wet etching process is used to remove the second core layer 220.

[0091] The wet etching process has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which is beneficial to reduce damage to the second sidewall 610 during the removal of the second core layer 220.

[0092] refer to Figure 12 After removing the second core layer 220, the second sidewall 610 is used as a mask to pattern the pattern material layer 110, and multiple target patterns 140 are formed in the transistor region 100a.

[0093] In this embodiment, the target pattern 140 is a channel protrusion structure.

[0094] In this embodiment, the step of using the second sidewall 610 as a mask to pattern the pattern material layer 110 includes: using the second sidewall 610 as a mask to pattern the second mask material layer 120 to form the third mask layer 130; and using the third mask layer 130 as a mask to pattern the pattern material layer 110 to form the target pattern 140.

[0095] The target graphic 140 is obtained by transferring the graphic to the graphic material layer 110 through the third mask layer 130, which helps to improve the accuracy of graphic transfer and thus improve the graphic size accuracy of the target graphic 140.

[0096] Figure 13 This is a schematic diagram illustrating the relative positional relationship between the core layer, the first sidewall, the second sidewall, and the target pattern in another embodiment of the semiconductor structure formation method of the present invention.

[0097] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the first core layer also includes a second sub-core layer located in the transistor region.

[0098] refer to Figure 13 In the step of forming discrete and parallel first core layers 301 on the first core material layer, the first core layer 301 further includes a second sub-core layer 321 located in the transistor region 101a. The linewidth d4 of the second sub-core layer 321 is equal to the spacing d5 of the adjacent target pattern 141 in the transistor region 101a. The spacing d6 between adjacent first core layers 301 is the sum of the target linewidth d2 of the target pattern 141 and the spacing d5 of the adjacent target pattern 140 in the transistor region 101a.

[0099] The spacing d6 between adjacent first core layers 301 refers to the adjacent first sub-core layer 311 and second sub-core layer 321, and the adjacent second sub-core layer 321 when there are multiple second sub-core layers 321 between adjacent first sub-core layers 311.

[0100] The first core layer 301 also includes a second sub-core layer 321 located in the transistor region 101a. By adjusting the number of the second sub-core layers 321, the number of the target pattern 141 can be adjusted. Correspondingly, for the SRAM device, the number of bump structures in the SRAM cell region 101c that meet the actual requirements can be obtained.

[0101] The linewidth d4 of the second sub-core layer 321 is used to define the distance between a portion of the adjacent target patterns 141 corresponding to the transistor region 101a, and the spacing d6 between adjacent first core layers 301 is used to define the distance between the remaining adjacent target patterns 141 corresponding to the transistor region 101a. In this embodiment, the linewidth d4 of the second sub-core layer 321 is equal to the spacing d5 between adjacent target patterns 141 in the transistor region 101a, and the spacing d6 between adjacent first core layers 301 is the sum of the target linewidth d2 of the target pattern 141 and the spacing d5 between adjacent target patterns 141 in the transistor region 101a, so that in the crystal... In the transistor region 101a, a structure is obtained in which the spacing d5 between adjacent target patterns 141 is equal. Moreover, the spacing d6 between adjacent first core layers 301 is the sum of the target linewidth d2 of the target pattern 141 and the spacing d5 between adjacent target patterns 141 in the transistor region 101a. This allows the second sidewalls 611 formed between adjacent second mask layers 221 in the transistor region 101a to contact each other. The preset linewidth of the second sidewalls 611 is equal to the target linewidth d2 of the target pattern 141. Accordingly, the target pattern 141 with the target linewidth d2 is obtained by pattern transfer through the second sidewalls 611.

[0102] For a detailed description of the formation method of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a patterned material layer is formed, and a first core material layer is formed on the patterned material layer. The substrate includes alternating transistor regions and spacer regions, and the patterned material layer of the transistor regions is used to form a target pattern. A discrete and parallel first core layer is formed on the first core material layer. The first core layer includes a first sub-core layer covering the interval area. The line width of the first sub-core layer is the sum of the line width of the interval area and twice the target line width of the target pattern. A first sidewall is formed on the sidewall of the first core layer; After the first sidewall is formed, the first core layer is removed; After removing the first core layer, the first core material layer is patterned using the first sidewall as a mask to form the second core layer. A second sidewall is formed on the sidewall of the second core layer, and in the transistor region, the second sidewalls located between adjacent second core layers are in contact. After the second sidewall is formed, the second core layer is removed; After removing the second core layer, the pattern material layer is patterned using the second sidewall as a mask to form multiple target patterns in the transistor region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The semiconductor structure is an SRAM device; In the step of providing a substrate, the substrate includes a plurality of SRAM cell regions, each SRAM cell region including the transistor regions spaced apart and the spacer regions located between the transistor regions, and the target pattern is used to form the protrusion structure of the transistor regions.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a first sidewall on the sidewall of the first core layer, in the transistor region, the spacing between adjacent first sidewalls is a preset spacing, and the preset spacing is equal to the target line width of the target pattern; The second sidewall has a preset line width, and the preset spacing is equal to the preset line width.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming discrete and parallel first core layers on the first core material layer, the first core layer further includes a second sub-core layer located in the transistor region. The linewidth of the second sub-core layer is equal to the spacing between adjacent target patterns in the transistor region, and the spacing between adjacent first core layers is the sum of the target linewidth of the target pattern and the spacing between adjacent target patterns in the transistor region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a discrete and parallel first core layer on the first core material layer includes: forming a second core material layer covering the first core material layer; A discrete first mask layer is formed on the second core material layer; The second core material layer is patterned using the first mask layer as a mask to form the first core layer; After forming the first core layer, the process also includes: removing the first mask layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a first sidewall on the sidewall of the first core layer includes: forming a first sidewall material layer covering the top and sidewall of the first core layer and the top of the first core material layer; Remove the first sidewall material layer located on top of the first core layer and the first core material layer, and retain the first sidewall material layer located on the sidewall of the first core layer as the first sidewall.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a first mask material layer is also formed on the first core material layer; The step of patterning the first core material layer using the first sidewall as a mask to form the second core layer includes: patterning the first mask material layer using the first sidewall as a mask to form the second mask layer; The first core material layer is patterned using the second mask layer as a mask to form the second core layer; After forming the second core layer, the process also includes: removing the second mask layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second sidewall on the sidewall of the second core layer includes: forming a second sidewall material layer covering the top and sidewall of the second core layer and the top of the pattern material layer, wherein the second sidewall material layers located between adjacent second core layers are in contact in the transistor region; Remove the second sidewall material layer located on top of the second core layer and the top of the graphic material layer, and retain the second sidewall material layer located on the sidewall of the second core layer as the second sidewall.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a second mask material layer is also formed between the pattern material layer and the first core material layer; The step of patterning the patterned material layer using the second sidewall as a mask includes: patterning the second mask material layer using the second sidewall as a mask to form a third mask layer; The pattern material layer is patterned using the third mask layer as a mask to form the target pattern.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the pattern material layer includes a channel material layer, and the target pattern includes a channel protrusion structure.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second sidewall includes titanium oxide, titanium nitride, silicon oxide, silicon nitride, or aluminum oxide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first core material layer includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second core layer includes one or more of amorphous silicon, polycrystalline silicon, monocrystalline silicon, silicon oxide, advanced patterning materials, spin-coated carbon, and silicon carbide.

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