Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes: a plurality of scan signal lines disposed on a substrate for providing scan signals to a plurality of rows of sub-pixels respectively; a gate driving circuit disposed on the substrate and located in a border region for outputting scan signals; a plurality of load compensation units disposed on the substrate and located in the border region, situated between the gate driving circuit and the plurality of pixel units; and a plurality of scan signal leads disposed on the substrate and located in the border region, the plurality of scan signal leads being used to transmit the scan signals output by the gate driving circuit to the plurality of scan signal lines respectively. At least one of the load compensation units includes a compensation capacitor, the compensation capacitor including a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode being located in a first conductive layer, the second compensation capacitor electrode being located in a semiconductor layer, and the orthographic projections of the first compensation capacitor electrode and the second compensation capacitor electrode on the substrate at least partially overlapping. The first compensation capacitor electrode is electrically connected to the scan signal leads.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the continuous development of technology, the demand for customized irregular-shaped displays is increasing. In irregular-shaped displays, the display panel has an irregularly shaped display area, and the number of sub-pixels in each row of pixel units in the irregular display area differs significantly from the number of sub-pixels in each row of pixel units in the normal display area. This significant difference in the number of sub-pixels in each row of pixel units can lead to large differences in the load between the normal display area and the irregular display area, or large differences in the load between adjacent rows of pixel units, which may cause display defects.

[0003] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising: a substrate including a display area and a border area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arrayed on the substrate along row and column directions, each pixel unit including a plurality of sub-pixels; a plurality of scan signal lines disposed on the substrate, the plurality of scan signal lines being used to provide scan signals to the plurality of rows of sub-pixels respectively; a gate driving circuit disposed on the substrate and located in the border area, the gate driving circuit being used to output scan signals; and a plurality of load compensation units disposed on the substrate and located in the border area, the plurality of load compensation units being located between the gate driving circuit and the plurality of pixel units. Between element units; and multiple scan signal leads disposed on the substrate and located in the border region, the multiple scan signal leads being used to transmit the scan signal output by the gate drive circuit to the multiple scan signal lines respectively, wherein at least one of the load compensation units includes a compensation capacitor, the compensation capacitor including a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode being located in a first conductive layer, the second compensation capacitor electrode being located in a semiconductor layer, the orthographic projection of the first compensation capacitor electrode on the substrate and the orthographic projection of the second compensation capacitor electrode on the substrate at least partially overlapping; and the first conductive layer being located on the side of the semiconductor layer away from the substrate, the first compensation capacitor electrode being electrically connected to the scan signal leads.

[0005] According to some exemplary embodiments, the display substrate includes N rows of pixel units, wherein the number of sub-pixels included in the n rows of pixel units in the N rows of pixel units is not consistent with each other, where N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 2 and less than or equal to N; for the n rows of pixel units, multiple scan signal leads that provide scan signals to each row of pixel units are electrically connected to their respective compensation capacitors, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is negatively correlated with the number of sub-pixels included in that row of pixel units.

[0006] According to some exemplary embodiments, for the n rows of pixel units, the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units in the row direction is negatively correlated with the number of sub-pixels included in that row of pixel units.

[0007] According to some exemplary embodiments, the n-row pixel unit includes the m-th row pixel unit and the (m+i)-th row pixel unit, and the multi-row pixel unit further includes the (m+j)-th row pixel unit, where m, i, and j are all positive integers greater than or equal to 1; the number of sub-pixels included in the m-th row pixel unit is less than the number of sub-pixels included in the (m+i)-th row pixel unit, and the number of sub-pixels included in the (m+i)-th row pixel unit is less than the number of sub-pixels included in the (m+j)-th row pixel unit; the scan signal lead providing the scan signal to the sub-pixels of the (m+j)-th row pixel unit is not electrically connected to the compensation capacitor, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the m-th row pixel unit is greater than the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the (m+i)-th row pixel unit.

[0008] According to some exemplary embodiments, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the m-th row pixel unit has a larger dimension in the row direction than at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the (m+i)-th row pixel unit in the row direction.

[0009] According to some exemplary embodiments, for the n rows of pixel units, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units has a substantially equal size in the column direction; and / or, for the n rows of pixel units, the ratio of the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of any two rows of pixel units in the row direction is between 1.3 and 400.

[0010] According to some exemplary embodiments, the scan signal line and the scan signal lead are located in the first conductive layer, and the first compensation capacitor electrode and the scan signal lead, which are electrically connected to each other, are a continuous, integral structure.

[0011] According to some exemplary embodiments, the display substrate further includes a first voltage signal lead located in a second conductive layer, the second conductive layer being located on the side of the first conductive layer away from the substrate; and the second compensation capacitor electrode being electrically connected to the first voltage signal lead.

[0012] According to some exemplary embodiments, the display substrate further includes a first conductive connection portion located in the second conductive layer, the first conductive connection portion extending from the first voltage signal lead toward the display area; and the first conductive connection portion being electrically connected to the second compensation capacitor electrode through at least one first via.

[0013] According to some exemplary embodiments, for at least one row of pixel units, the first conductive connection portion is electrically connected to the second compensation capacitor electrode through a plurality of first vias, the plurality of first vias being arranged in two rows in the column direction.

[0014] According to some exemplary embodiments, for the same compensation capacitor, the first conductive connection portion electrically connected to the second compensation capacitor electrode of the compensation capacitor and the scan signal lead electrically connected to the first compensation capacitor electrode of the compensation capacitor extend substantially parallel to each other.

[0015] According to some exemplary embodiments, for at least one compensation capacitor, the overlapping portion of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor is located in the column direction between the first conductive connection portion electrically connected to the first compensation capacitor electrode of the compensation capacitor and the scan signal lead electrically connected to the second compensation capacitor electrode of the compensation capacitor.

[0016] According to some exemplary embodiments, the multi-row pixel unit includes at least one pixel unit group, the pixel unit group includes k adjacent rows of pixel units, where k is a positive integer greater than or equal to 2; and for the k rows of pixel units, the number of sub-pixels included in each row of pixel units is the same, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is substantially equal.

[0017] According to some exemplary embodiments, for k rows of pixel units, the dimensions of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units are substantially equal in the row direction.

[0018] According to some exemplary embodiments, for k rows of pixel units, the first compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction; and / or, for k rows of pixel units, the second compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction.

[0019] According to some exemplary embodiments, the second compensation capacitor electrode includes a protrusion whose orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the substrate; and the first conductive connection portion is electrically connected to the protrusion through a plurality of vias.

[0020] According to some exemplary embodiments, the display substrate further includes a second conductive connection portion located in the second conductive layer; scan signal leads and scan signal lines that provide scan signals to the same row of pixel units are electrically connected through the second conductive connection portion.

[0021] According to some exemplary embodiments, one end of the scanning signal lead near the display area is electrically connected to one end of the second conductive connection portion through a second via, and the other end of the second conductive connection portion is electrically connected to one end of the scanning signal line through a third via.

[0022] According to some exemplary embodiments, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor has a hollow structure.

[0023] According to some exemplary embodiments, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor includes a plurality of solid portions and a plurality of hollow portions, wherein the plurality of solid portions and the plurality of hollow portions are arranged alternately along the row direction.

[0024] In another aspect, a display device is provided, comprising a display substrate as described above. Attached Figure Description

[0025] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0026] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure.

[0027] Figure 2 It is shown schematically. Figure 1 A schematic diagram of the pixel layout of the display device shown.

[0028] Figure 3A This is a schematic diagram illustrating the structure of a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure.

[0029] Figure 3B A cross-sectional view of a thin-film transistor in an embodiment of this disclosure is shown schematically.

[0030] Figure 4 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing one electrode of a compensation capacitor for a plurality of rows of pixel units.

[0031] Figure 5 yes Figure 4 A magnified view of region I in the image.

[0032] Figure 6 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing another electrode of the compensation capacitor for a plurality of rows of pixel units.

[0033] Figure 7 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing two electrodes of a compensation capacitor for a plurality of rows of pixel units.

[0034] Figure 8 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically illustrates the electrostatic protection structure of several rows of pixel units.

[0035] Figure 9 This is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure.

[0036] Figure 10 This is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure.

[0037] Figure 11 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing the compensation capacitors of several rows of pixel units.

[0038] Figure 12 yes Figure 11 A magnified view of region II in the image.

[0039] Figure 13 The equivalent circuit of the compensation capacitor and the electrostatic protection structure is schematically shown.

[0040] Figure 14 It is along Figure 12 The cross-sectional view taken from line BB' in the diagram.

[0041] Figure 15 This is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure.

[0042] Figure 16The display substrate according to some exemplary embodiments of the present disclosure is along Figure 3A The cross-sectional view taken from line AA' in the diagram. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0044] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0045] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0046] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0047] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0048] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0049] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0050] Those skilled in the art will understand that, unless otherwise stated herein, the expressions “continuous extension,” “monolithic structure,” “integral structure,” or similar expressions mean that multiple elements, components, structures, and / or portions are located on the same layer and are typically formed during manufacturing by the same patterning process, and that these elements, components, structures, and / or portions are continuous extensions without gaps or breaks between them.

[0051] It should be noted that in this article, "negative correlation" means that the two quantities change in opposite directions; for example, when one increases, the other decreases, and vice versa. "Positive correlation" means that the two quantities change in the same direction; for example, when one increases, the other increases, and vice versa.

[0052] This disclosure provides at least one display substrate and a display device. The display substrate includes: a substrate including a display area and a border area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arrayed along row and column directions on the substrate, each pixel unit including a plurality of sub-pixels; a plurality of scan signal lines disposed on the substrate, the plurality of scan signal lines being used to provide scan signals to the plurality of rows of sub-pixels respectively; a gate driving circuit disposed on the substrate and located in the border area, the gate driving circuit being used to output scan signals; a plurality of load compensation units disposed on the substrate and located in the border area, the plurality of load compensation units being located between the gate driving circuit and the plurality of pixel units; and Multiple scan signal leads are disposed on the substrate and located in the border area. These multiple scan signal leads are used to transmit the scan signal output by the gate driving circuit to the multiple scan signal leads respectively. At least one load compensation unit includes a compensation capacitor, which includes a first compensation capacitor electrode and a second compensation capacitor electrode. The first compensation capacitor electrode is located in a first conductive layer, and the second compensation capacitor electrode is located in a semiconductor layer. The orthographic projections of the first and second compensation capacitor electrodes on the substrate at least partially overlap. The first conductive layer is located on the side of the semiconductor layer away from the substrate, and the first compensation capacitor electrode is electrically connected to the scan signal leads. In embodiments of this disclosure, load compensation can be performed on pixel units in rows with inconsistent loads, making the load on the scan signal lines of each row of pixel units substantially consistent. This can at least improve or even eliminate display unevenness and other defects in various sub-display areas.

[0053] Figure 1 This is a plan view of a display device according to some exemplary embodiments of the present disclosure. Figure 2 It is shown schematically. Figure 1 A schematic diagram of the pixel layout of the display device shown.

[0054] Combined with reference Figure 1 , Figure 2 The display device 1000 may include a display substrate. The display substrate may include a substrate 100, which may include a display area AA and a border area NA located on at least one side of the display area. It should be noted that in... Figure 1 In the illustrated embodiment, the border region NA surrounds the display region AA. However, the embodiments of this disclosure are not limited to this. In other embodiments, the border region NA may be located on at least one side of the display region AA, but does not surround the display region AA.

[0055] The display substrate may include a plurality of pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit used to display an image. For example, the pixel unit P may include a light-emitting device that emits white light and / or colored light.

[0056] Pixel units P can be configured in multiple ways, arranged in a matrix along rows extending in a first direction (e.g., row direction) X and columns extending in a second direction (e.g., column direction) Y. However, embodiments of this disclosure do not specifically limit the arrangement of pixel units P, and pixel units P can be arranged in various forms. For example, pixel units P can be arranged such that the direction inclined relative to the first direction X and the second direction Y is the column direction, and the direction intersecting the column direction is the row direction.

[0057] A pixel unit P can include multiple sub-pixels. For example, a pixel unit P can include three sub-pixels: a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. As another example, a pixel unit P can include four sub-pixels: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For instance, the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, the third sub-pixel SP3 can be a blue sub-pixel, and the fourth sub-pixel can be a white sub-pixel.

[0058] In some exemplary embodiments, the display substrate may be a liquid crystal display substrate, such as an array substrate of a liquid crystal display panel. Figure 3A This is a schematic diagram illustrating the structure of a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure. (See reference 1) Figures 1 to 3AThe display substrate may include a first electrode E1, a second electrode E2, a data signal line DL, and a scan signal line GL disposed on the substrate 100. It should be understood that when the display panel is a liquid crystal display panel, the display panel may include a liquid crystal layer located between the array substrate and the color filter substrate. The specific structures of the array substrate, the color filter substrate, and the liquid crystal layer can refer to the structures of existing liquid crystal display panels, and will not be described in detail here. The first electrode E1 and the second electrode E2 can generate corresponding liquid crystal electric fields under the drive of a driving signal. The liquid crystal in the liquid crystal layer can be deflected under the action of the liquid crystal electric field, thereby realizing the corresponding display function. Exemplarily, the liquid crystal layer may be disposed between the first electrode E1 and the second electrode E2. One of the first electrode E1 and the second electrode E2 may be a pixel electrode, and the other may be a common electrode; for example, the first electrode E1 may be a common electrode, and the second electrode E2 may be a pixel electrode.

[0059] In some specific embodiments, at least one sub-pixel further includes a thin-film transistor T electrically connected to the data signal line DL. In the embodiments of this disclosure, the thin-film transistor T can be either a top-gate structure or a bottom-gate structure, whichever is determined according to actual needs and is not limited herein. The following description uses a top-gate structure for the thin-film transistor T as an example to illustrate the thin-film transistor T in the embodiments of this disclosure.

[0060] Figure 3B A cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure is schematically shown. Figure 16 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 3A The cross-sectional view taken from line AA' in the diagram. (Refer to reference...) Figure 3A , Figure 3B and Figure 16 The display substrate may include: a semiconductor layer ACT located on the substrate 100; a first conductive layer 10 located on the side of the semiconductor layer ACT away from the substrate 100; a second conductive layer 20 located on the side of the first conductive layer 10 away from the substrate 100; and a third conductive layer 30 located on the side of the second conductive layer 20 away from the substrate 100. For example, a thin-film transistor T may include an active layer CH, a gate GE1, a source SE1, and a drain DE1. The active layer CH of the thin-film transistor T may be located in the semiconductor layer ACT, the gate GE1 of the thin-film transistor T may be located in the first conductive layer 10, and the source SE1 and drain DE1 of the thin-film transistor T may be located in the second conductive layer 20. For example, a first electrode E1 (e.g., a common electrode) may be located in the third conductive layer 30.

[0061] like Figure 3AAs shown, the display substrate can adopt a 2-pixel-2-domain (2P2D) sub-pixel structure design. Each sub-pixel can include multiple strip-shaped pixel electrodes E2, which are separated by slits. The term "2-pixel-2-domain" means that the pixel electrodes E2 of adjacent rows of sub-pixels extend in different directions, and the pixel electrodes E2 of each adjacent row of sub-pixels are approximately symmetrical with respect to the scan signal line GL. Therefore, in the display substrate, for adjacent rows of sub-pixels, the pixel electrodes E2 and common electrode E1 of one row of sub-pixels can form a first domain electric field, and the pixel electrodes E2 and common electrode E1 of the other row of sub-pixels can form a second domain electric field. The directions of the first and second domain electric fields are different; in other words, the directions of the electric fields corresponding to each adjacent row of sub-pixels form a certain angle. Furthermore, the light emission directions of each adjacent row of sub-pixels can compensate for each other, which is beneficial for improving the display effect.

[0062] Return to reference Figure 1 The display substrate may have an irregular shape, which may include any irregular shape. It should be understood that the embodiments of this disclosure do not impose any particular limitation on the shape of the display substrate. Below, we will use... Figure 1 The irregular shapes shown are examples, and embodiments of this disclosure will be described in detail.

[0063] In embodiments of this disclosure, the display substrate includes N rows of pixel units, where N is a positive integer greater than or equal to 2. For example, refer to... Figure 1 In the display area AA, at least one row of pixel units is provided. Figure 1 In the illustrated embodiment, the number of sub-pixels included in each row of pixel units decreases irregularly from bottom to top. For example, the number of sub-pixels included in each row of pixel units located in the lower display area is greater than the number of sub-pixels included in each row of pixel units located in the middle display area, and the number of sub-pixels included in each row of pixel units located in the middle display area is greater than the number of sub-pixels included in each row of pixel units located in the upper display area.

[0064] For each row of pixel units, a scan signal line GL is provided to provide a scan signal to each sub-pixel of that row of pixel units. In the embodiments of this disclosure, there are n rows of pixel units in the N rows of pixel units, and the number of sub-pixels included in these n rows of pixel units is inconsistent, where n is a positive integer greater than or equal to 2 and less than or equal to N. The loads electrically connected to the scan signal lines GL of these n rows of pixel units are inconsistent. For example, the theoretical load of the scan signal lines of each row of pixel units can be calculated according to the design drawings of the display substrate. For the scan signal lines, the load can include resistive load and capacitive load.

[0065] The resistance R on the scan signal line of the i-th row of pixel units in the N rows of pixel units can be calculated using the following formula:

[0066] Ri = Rs * L / W, where L is the length of the scan signal line of the i-th row of pixels, W is the width of the scan signal line of the i-th row of pixels, and Rs is the sheet resistance of the metal material used for the scan signal line of the i-th row of pixels.

[0067] The capacitance Ci on the scan signal line of the i-th row of pixel units in the N rows of pixel units can be calculated using the following formula:

[0068] Ci = Ni * Cpixel, where Ni is the number of sub-pixels included in the i-th row pixel unit, and Cpixel is the capacitive load value of a single sub-pixel, which can be extracted by software or calculated based on the area of ​​the planar capacitor.

[0069] The inventors discovered through research that for pixel units in different rows with inconsistent loads, the charging voltage achieved within the same charging time is inconsistent. This may lead to uneven display in different sub-display areas during actual display.

[0070] In the embodiments of this disclosure, load compensation can be performed on the row of pixel units with inconsistent loads. For example, a load compensation unit can be electrically connected to the scan signal line of the row of pixel units that need load compensation, so that the load on the scan signal line of the row of pixel units is basically consistent. In this way, at least the display unevenness of each sub-display area can be improved or even eliminated.

[0071] Combined with reference Figures 1 to 3B According to some exemplary embodiments of the present disclosure, a display substrate may include: a substrate 100, the substrate 100 including a display area AA and a border area NA located on at least one side of the display area; a plurality of pixel units P located in the display area AA, the plurality of pixel units P being arrayed on the substrate 100 along the row direction X and the column direction Y, each row of pixel units P including a plurality of sub-pixels; a plurality of scan signal lines GL disposed on the substrate 100, the plurality of scan signal lines GL being used to provide scan signals to the plurality of rows of pixel units P respectively; a plurality of load compensation units 200 disposed on the substrate 100 and located in the border area NA, the plurality of load compensation units 200 being electrically connected to at least some of the plurality of scan signal lines GL respectively; and a common electrode E1 disposed on the substrate 100, at least a portion of the common electrode E1 being located in the display area AA, the common electrode E1 being connected to a common voltage signal.

[0072] It should be noted that, in this article, the common voltage signal can be referred to as the first voltage signal.

[0073] In embodiments of this disclosure, at least one of the load compensation units may include a compensation capacitor.

[0074] For example, the compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode. The first compensation capacitor electrode is electrically connected to the scan signal lead, and the second compensation capacitor electrode is connected to the first voltage signal. The orthographic projections of the first compensation capacitor electrode and the second compensation capacitor electrode on the substrate at least partially overlap. For the n rows of pixel units, multiple scan signal leads providing scan signals to each row of pixel units are electrically connected to their respective compensation capacitors. The overlap area between the first and second compensation capacitor electrodes of the compensation capacitors of each row of pixel units is negatively correlated with the number of sub-pixels included in that row of pixel units. For the at least n rows of pixel units, the dimension of at least one of the first and second compensation capacitor electrodes of the compensation capacitors of each row of pixel units in the row direction is negatively correlated with the number of sub-pixels included in that row of pixel units.

[0075] In the display substrate provided in this embodiment, the fewer the number of sub-pixels connected to the scan signal line corresponding to the load compensation unit, the larger the compensation load value of the load compensation unit. By using load compensation units with different compensation load values ​​to compensate scan signal lines with different numbers of sub-pixels, the load on different scan signal lines becomes uniform, avoiding display differences and ensuring display quality.

[0076] Figure 4 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing one electrode of a compensation capacitor for a plurality of rows of pixel units. Figure 5 yes Figure 4 A magnified view of region I in the image. Figure 6 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing another electrode of the compensation capacitor for a plurality of rows of pixel units. Figure 7 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing two electrodes of a compensation capacitor for a plurality of rows of pixel units. Figure 8 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, which schematically illustrates the electrostatic protection structure of several rows of pixel units. Figure 9 This is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure. Figure 10 This is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure. Figure 11This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing the compensation capacitors of several rows of pixel units. Figure 12 yes Figure 11 A magnified view of region II in the image. Figure 13 The equivalent circuit of the compensation capacitor and the electrostatic protection structure is schematically shown. Figure 14 It is along Figure 12 The cross-sectional view taken from line BB' in the diagram. Figure 15 This is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure.

[0077] According to some exemplary embodiments of this disclosure, the display substrate can employ GOA (Gate Driver on Array) technology. In GOA technology, the driving circuit is directly disposed on the array substrate or display substrate, replacing an external driving chip. Each GOA unit serves as a first-level shift register, and each shift register is connected to a scan signal line. By sequentially outputting turn-on voltages through each shift register, pixel-by-pixel scanning is achieved. In some embodiments, each shift register can also be connected to multiple scan signal lines. This adapts to the development trend of high resolution and narrow bezels in display substrates.

[0078] Combined with reference Figures 1 to 16 The display substrate includes: a substrate 100, the substrate including a display area AA and a border area NA located on at least one side of the display area; a plurality of pixel units P located in the display area, the plurality of pixel units being arrayed on the substrate along the row and column directions, each pixel unit including a plurality of sub-pixels; a plurality of scan signal lines GL disposed on the substrate, the plurality of scan signal lines being used to provide scan signals to the multiple rows of sub-pixels respectively; a gate driving circuit 120 disposed on the substrate and located in the border area, the gate driving circuit being used to output scan signals; a plurality of load compensation units disposed on the substrate and located in the border area, the plurality of load compensation units being located between the gate driving circuit 120 and the plurality of pixel units P; and a plurality of scan signal leads GLY disposed on the substrate and located in the border area, the plurality of scan signal leads being used to transmit the scan signals output by the gate driving circuit to the plurality of scan signal lines respectively.

[0079] In embodiments of this disclosure, at least one load compensation unit includes a compensation capacitor 200. The compensation capacitor includes a first compensation capacitor electrode 210 and a second compensation capacitor electrode 220. The first compensation capacitor electrode 210 is located in a first conductive layer 10, and the second compensation capacitor electrode 220 is located in a semiconductor layer ACT. The orthographic projections of the first compensation capacitor electrode 210 and the second compensation capacitor electrode 220 on the substrate at least partially overlap. The first compensation capacitor electrode 210 is electrically connected to the scan signal lead GLY.

[0080] For example, the n-row pixel unit includes the m-th row pixel unit and the (m+i)-th row pixel unit, and the multi-row pixel unit also includes the (m+j)-th row pixel unit, where m, i, and j are all positive integers greater than or equal to 1. The number of sub-pixels included in the m-th row pixel unit is less than the number of sub-pixels included in the (m+i)-th row pixel unit, and the number of sub-pixels included in the (m+i)-th row pixel unit is less than the number of sub-pixels included in the (m+j)-th row pixel unit. The scan signal lead providing the scan signal to the sub-pixels of the (m+j)-th row pixel unit is not electrically connected to the compensation capacitor, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the m-th row pixel unit is greater than the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the (m+i)-th row pixel unit.

[0081] It should be noted that "the scan signal lead is not electrically connected to the compensation capacitor" means that no corresponding compensation capacitor is provided for this scan signal lead, therefore, the scan signal lead is not electrically connected to the compensation capacitor. For example, in Figure 1 In the illustrated embodiment, the pixel unit in the (m+j)th row can be located in Figure 1 In the lower row of pixel units shown in the diagram, the number of sub-pixels in the (m+j)th row of pixel units is relatively large and requires load compensation. Therefore, it is not necessary to set a corresponding compensation capacitor for the scan signal lead of the (m+j)th row of pixel units. Thus, the scan signal lead of the (m+j)th row of pixel units is not electrically connected to the compensation capacitor.

[0082] For example, at least one of the first and second compensation capacitor electrodes of the compensation capacitor of the m-th row pixel unit has a larger dimension in the row direction than at least one of the first and second compensation capacitor electrodes of the compensation capacitor of the (m+i)-th row pixel unit in the row direction.

[0083] For example, for the n rows of pixel units, at least one of the first and second compensation capacitor electrodes of the compensation capacitor in each row of pixel units has a substantially equal size in the column direction. For the n rows of pixel units, the ratio of the size of at least one of the first and second compensation capacitor electrodes of the compensation capacitor in the row direction of any two rows of pixel units is between 1.3 and 400.

[0084] The scan signal line GL and the scan signal lead GLY are located in the first conductive layer 10, and the first compensation capacitor electrode 210 and the scan signal lead GLY, which are electrically connected to each other, are a continuous, integral structure.

[0085] The display substrate also includes a first voltage signal lead 300 located in the second conductive layer 20. The second compensation capacitor electrode 220 is electrically connected to the first voltage signal lead 300.

[0086] The display substrate further includes a first conductive connection portion 310 located in the second conductive layer 20, the first conductive connection portion 310 extending from the first voltage signal lead 300 toward the display area AA.

[0087] The first conductive connection portion 310 is electrically connected to the second compensation capacitor electrode 220 through at least one first through hole VH1.

[0088] like Figure 5 As shown, for at least one row of pixel units, the first conductive connection portion 310 is electrically connected to the second compensation capacitor electrode 220 through a plurality of first vias VH1, and the plurality of first vias VH1 are arranged in two rows in the column direction Y.

[0089] like Figure 6 As shown, for the same compensation capacitor, the first conductive connection portion 310, which is electrically connected to the second compensation capacitor electrode 220 of the compensation capacitor, and the scan signal lead GLY, which is electrically connected to the first compensation capacitor electrode of the compensation capacitor, extend substantially parallel to each other.

[0090] like Figure 7 As shown, for at least one compensation capacitor, the overlapping portion of the first compensation capacitor electrode 210 and the second compensation capacitor electrode 220 of the compensation capacitor is projected onto the substrate in the column direction Y between the first conductive connection portion 310 electrically connected to the first compensation capacitor electrode of the compensation capacitor and the scan signal lead GLY electrically connected to the second compensation capacitor electrode of the compensation capacitor.

[0091] like Figure 7As shown, the multi-row pixel unit includes at least one pixel unit group, and the pixel unit group includes k adjacent rows of pixel units, where k is a positive integer greater than or equal to 2. For the k rows of pixel units, the number of sub-pixels included in each row of pixel units is the same, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is substantially equal.

[0092] For k rows of pixel units, the dimensions of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units are basically equal in the row direction.

[0093] For k rows of pixel units, the first compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction; and / or, for k rows of pixel units, the second compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction.

[0094] like Figure 5 As shown, the second compensation capacitor electrode 220 includes a protrusion 201, the orthographic projection of the protrusion 201 on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion 310 on the substrate; and the first conductive connection portion 310 is electrically connected to the protrusion 201 through a plurality of vias.

[0095] like Figure 8 As shown, the display substrate further includes a second conductive connection portion 320 located in the second conductive layer 20. Scan signal leads GLY and scan signal lines GL, which provide scan signals to pixel units in the same row, are electrically connected through the second conductive connection portion 320.

[0096] One end of the scan signal lead GLY, near the display area AA, is electrically connected to one end of the second conductive connection portion 320 via a second via VH2. The other end of the second conductive connection portion 320 is electrically connected to one end of the scan signal line GL via a third via VH3. This conductive transition structure electrically connects the scan signal lead GLY and the scan signal line GL together. This layer-change design reduces the continuous length of the same conductive trace, thereby preventing electrostatic burns.

[0097] like Figure 15 As shown, at least one of the first and second compensation capacitor electrodes of the compensation capacitor has a hollow structure.

[0098] For example, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor includes a plurality of solid portions 410 and a plurality of hollow portions 420, wherein the plurality of solid portions 410 and the plurality of hollow portions 420 are arranged alternately along the row direction.

[0099] In the embodiments of this disclosure, by designing at least one of the first compensation capacitor electrode and the second compensation capacitor electrode as a conductive part with a hollow structure, while ensuring that it has a large conductive area, static electricity can be avoided from accumulating on the first compensation capacitor electrode and the second compensation capacitor electrode, which is beneficial for electrostatic protection.

[0100] At least some embodiments of this disclosure also provide a display panel, which includes the display substrate described above. For example, the display panel may be a liquid crystal display panel.

[0101] At least some embodiments of this disclosure also provide a display device. The display device may include the display substrate described above. The display device includes a display area AA and a bezel area NA, the bezel area NA having a small width, thereby realizing a narrow bezel display device.

[0102] The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0103] It should be understood that the display device according to the embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be found in the above description and will not be repeated here.

[0104] While some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, The display substrate includes: A substrate, the substrate including a display area and a border area located on at least one side of the display area; A plurality of pixel units located in the display area are arranged in an array along the row and column directions on the substrate, and each pixel unit includes a plurality of sub-pixels; Multiple scan signal lines disposed on the substrate are used to provide scan signals to multiple rows of sub-pixels respectively. A gate driving circuit disposed on the substrate and located in the border region, the gate driving circuit being used to output a scan signal; A plurality of load compensation units are disposed on the substrate and located in the border region, the plurality of load compensation units being located between the gate driving circuit and the plurality of pixel units; at least one of the load compensation units includes a compensation capacitor, the compensation capacitor including a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode being located in a first conductive layer, and the second compensation capacitor electrode being located in a semiconductor layer; the first conductive layer is located on the side of the semiconductor layer away from the substrate; the orthographic projections of the first compensation capacitor electrode and the second compensation capacitor electrode on the substrate at least partially overlap; Multiple scan signal leads are disposed on the substrate and located in the border area. The multiple scan signal leads are used to transmit the scan signal output by the gate drive circuit to the multiple scan signal leads respectively. The first compensation capacitor electrode is electrically connected to the scan signal leads. A first voltage signal lead is located in a second conductive layer, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the second compensation capacitor electrode is electrically connected to the first voltage signal lead. A first conductive connection portion is located in the second conductive layer, extending from the first voltage signal lead toward the display area; wherein, the second compensation capacitor electrode includes a protrusion, the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the substrate; the first conductive connection portion is electrically connected to the protrusion through a plurality of first vias.

2. The display substrate according to claim 1, wherein, The display substrate includes N rows of pixel units, and the number of sub-pixels included in the n rows of pixel units in the N rows of pixel units is not consistent with each other, where N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 2 and less than or equal to N. For the n rows of pixel units, multiple scan signal leads that provide scan signals to each row of pixel units are electrically connected to their respective compensation capacitors. The overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of each row of pixel units is negatively correlated with the number of sub-pixels included in that row of pixel units.

3. The display substrate according to claim 2, wherein, For the n rows of pixel units, the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units in the row direction is negatively correlated with the number of sub-pixels included in that row of pixel units.

4. The display substrate according to claim 3, wherein, The n-row pixel unit includes the m-th row pixel unit and the (m+i)-th row pixel unit, and the n-row pixel unit also includes the (m+j)-th row pixel unit, where m, i, and j are all positive integers greater than or equal to 1; The number of sub-pixels included in the m-th row pixel unit is less than the number of sub-pixels included in the (m+i)-th row pixel unit, and the number of sub-pixels included in the (m+i)-th row pixel unit is less than the number of sub-pixels included in the (m+j)-th row pixel unit. The scan signal lead that provides the scan signal to the sub-pixel of the (m+j)th row pixel unit is not electrically connected to the compensation capacitor, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the m-th row pixel unit is greater than the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of the (m+i)th row pixel unit.

5. The display substrate according to claim 4, wherein, At least one of the first and second compensation capacitor electrodes of the compensation capacitor of the m-th row pixel unit has a dimension in the row direction that is greater than the dimension in the row direction of at least one of the first and second compensation capacitor electrodes of the compensation capacitor of the (m+i)-th row pixel unit.

6. The display substrate according to claim 5, wherein, For the n rows of pixel units, at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units has a size that is substantially equal to each other in the column direction. And / or, For the n rows of pixel units, the ratio of the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of any two rows of pixel units in the row direction is between 1.3 and 400.

7. The display substrate according to any one of claims 1-6, wherein, The scan signal line and the scan signal lead are located in the first conductive layer, and the first compensation capacitor electrode and the scan signal lead, which are electrically connected to each other, are a continuous, integral structure.

8. The display substrate according to claim 1, wherein, For at least one row of pixel units, the first conductive connection portion is electrically connected to the protrusion portion through a plurality of first vias, the plurality of first vias being arranged in two rows in the column direction.

9. The display substrate according to claim 8, wherein, For the same compensation capacitor, the first conductive connection portion electrically connected to the second compensation capacitor electrode of the compensation capacitor and the scan signal lead electrically connected to the first compensation capacitor electrode of the compensation capacitor extend substantially parallel to each other.

10. The display substrate according to claim 9, wherein, For at least one compensation capacitor, the overlapping portion of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor is located in the column direction between the first conductive connection portion electrically connected to the first compensation capacitor electrode of the compensation capacitor and the scan signal lead electrically connected to the second compensation capacitor electrode of the compensation capacitor.

11. The display substrate according to claim 2, wherein, The n rows of pixel units include at least one group of pixel units, and the group of pixel units includes k adjacent rows of pixel units, where k is a positive integer greater than or equal to 2. as well as For k rows of pixel units, each row of pixel units includes the same number of sub-pixels, and the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode of each row of pixel units is basically equal.

12. The display substrate according to claim 11, wherein, For k rows of pixel units, the dimensions of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units are basically equal in the row direction.

13. The display substrate according to claim 12, wherein, For k rows of pixel units, the first compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction; And / or, For k rows of pixel units, the second compensation capacitor electrodes of the compensation capacitors of each row of pixel units are aligned in the column direction.

14. The display substrate according to claim 1, wherein, The display substrate further includes a second conductive connection portion located in the second conductive layer; The scan signal lead and scan signal line that provide scan signals to the pixel units in the same row are electrically connected through the second conductive connection.

15. The display substrate according to claim 14, wherein, One end of the scanning signal lead near the display area is electrically connected to one end of the second conductive connection part through a second via, and the other end of the second conductive connection part is electrically connected to one end of the scanning signal line through a third via.

16. The display substrate according to any one of claims 1-6, wherein, At least one of the first and second compensation capacitor electrodes of the compensation capacitor has a hollow structure.

17. The display substrate according to claim 16, wherein, At least one of the first and second compensation capacitor electrodes of the compensation capacitor includes multiple solid portions and multiple hollow portions, which are arranged alternately along the row direction.

18. A display device comprising a display substrate according to any one of claims 1-17.

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