Sine-cosine encoder and angle resolving method thereof

Abstract

The application provides a sine-cosine encoder and an angle resolving method thereof. The angle resolving method comprises four sine-cosine signal terminals, a gating logic circuit, a capacitor array circuit, a comparison circuit and a digital logic adjusting circuit. The gating logic circuit is used for outputting a first voltage signal and a second voltage signal. The capacitor array circuit is used for scaling the first voltage signal. The comparison circuit compares the scaled first voltage signal and the second voltage signal, and outputs a real-time voltage ratio value and a preliminary angle value. The digital logic adjusting circuit adjusts a preset scaling coefficient of the capacitor array circuit and a selection logic of the gating logic circuit. The application completes the arctangent calculation through the capacitor array circuit and the comparison circuit, and adjusts the preset scaling coefficient and the selection switch logic through feedback, so as to obtain a high-precision final angle value. In this way, the arctangent calculation processing is avoided by using two-way ADC, the power consumption, the delay and the digital resource are effectively reduced, and the size of the sine-cosine encoder is reduced.

Description

Technical Field

[0001] This application relates to the field of encoder technology, and in particular to a sine / cosine encoder and its angle analysis method. Background Technology

[0002] The integration and miniaturization of the chip industry have placed increasingly stringent demands on the performance indicators of sensors and other detection devices, such as size, speed, and power consumption. This typically involves converting analog signals into digital signals for processing, and then further processing the digital signals to improve performance. In the area of ​​angle analysis based on multiphase sine and cosine signals, existing angle analysis methods can be divided into open-loop and closed-loop methods.

[0003] Among these methods, the open-loop method offers better transient response and is more suitable for high-speed detection. Angle analysis based on the open-loop concept can be further divided into the tangent method and the pseudo-linear method. The tangent method samples the sine and cosine signals separately, performs division in the arctangent calculation, and then uses a lookup table to obtain the final angle value, thus achieving linear angle analysis. However, this method requires two ADCs (analog-to-digital converters) and a large amount of digital resources, resulting in high power consumption, high latency, and large chip size. The pseudo-linear method achieves linear approximation based on the partial linearity of the sine curve, but this method requires the participation of a compensation signal, still consuming a large amount of digital resources. Summary of the Invention

[0004] This application provides a sine and cosine encoder and its angle resolution method aimed at reducing power consumption, digital resources, and latency.

[0005] This application provides an angle resolution circuit for a sine / cosine encoder, comprising:

[0006] Four sine and cosine signal terminals used to provide four-phase input voltage signals respectively;

[0007] A selection logic circuit, connected to the sine and cosine signal terminals, is used to compare the four-phase input voltage signal with a preset voltage signal, and select to output a first voltage signal and a second voltage signal according to a preset condition that the condition is always met; the selection logic circuit includes a first output terminal for outputting the first voltage signal and a second output terminal for outputting the second voltage signal.

[0008] A capacitor array circuit, connected to the first output terminal, is used to scale the first voltage signal according to a preset scaling factor to output a first scaled voltage signal.

[0009] A comparator circuit, wherein the positive input terminal of the comparator circuit is connected to the capacitor array circuit, and the negative input terminal of the comparator circuit is connected to the second output terminal, is used to compare the first scaled voltage signal and the second voltage signal to output a corresponding real-time voltage ratio value, and to obtain a corresponding preliminary angle value based on the real-time voltage ratio value; and

[0010] A digital logic adjustment circuit, connected to the output of the comparator circuit, the capacitor array circuit, and the gating logic circuit, is used to output a final angle value based on the real-time voltage ratio value and the preliminary angle value, and by adjusting the preset scaling factor and the selection logic of the gating logic circuit through feedback.

[0011] Optionally, the capacitor array circuit includes:

[0012] The voltage input terminal is used to input the first voltage signal;

[0013] The voltage output terminal is used to output the first scaled voltage signal;

[0014] The system comprises a sampling switch, a sampling capacitor, at least eight charging capacitors, and at least eight control switches; wherein the sampling switch is connected between the voltage input terminal and the voltage output terminal; one end of each sampling capacitor is connected to the preset voltage signal, and the other end is connected between the sampling switch and the voltage output terminal; the upper plate of each charging capacitor is connected to each control switch, and the lower plate of each charging capacitor is connected between the sampling switch and the voltage output terminal; each control switch includes a first terminal, a second terminal, and a third terminal; the first terminal of each control switch is connected to the upper plate of each charging capacitor, the second terminal of each control switch is connected to the voltage input terminal, and the third terminal of each control switch is connected to the preset voltage signal.

[0015] Optionally, the at least eight charging capacitors are connected in parallel in sequence, wherein the capacitance values ​​of the first two charging capacitors are the same as the capacitance value of the sampling capacitor.

[0016] Furthermore, the capacitance value of each of the at least six said charging capacitors is twice the capacitance value of the previous said charging capacitor.

[0017] Optionally, the formula for calculating the preset scaling factor A is:

[0018] Q tot =C S V IN (1)

[0019] Q tot =(C s +C n VOUT +(C N -C n (V) OUT -V IN (2)

[0020] From formulas (1) and (2), we get:

[0021]

[0022] Among them, C TOT =C S +C N ;

[0023] Q tot This represents the total charge on all capacitors in the capacitor array circuit;

[0024] C S Indicates the sampling capacitance;

[0025] V IN Indicates the sampled voltage;

[0026] C n This represents the total capacitance of all capacitors connected to the preset voltage signal on the upstream board among all charging capacitors.

[0027] V OUT This indicates the voltage value of the upper plate of the capacitor after feedback adjustment;

[0028] C N This represents the total capacitance of all charging capacitors.

[0029] Optionally, the comparison circuit includes:

[0030] The comparison module has its positive input connected to the output of the capacitor array circuit and its negative input connected to the second output of the gating logic circuit. It is used to compare the first scaled voltage signal and the second voltage signal and output the comparison result.

[0031] Positive output nodes and negative output nodes;

[0032] A positive feedback module is connected to the comparison module, the positive output node, and the negative output node, and is used to make one of the positive output node and the negative output node output a high level and the other output a low level according to the comparison result.

[0033] Optionally, the comparison circuit further includes:

[0034] A startup module is connected to the comparison module and is connected to a clock signal, used to start the comparison module when the clock signal is high.

[0035] A reset module is connected to the positive feedback module and is connected to a clock signal. It is used to reset the positive feedback module to a high level when the clock signal is low.

[0036] Optionally, the comparison circuit further includes a current bias terminal for receiving a bias current and a current mirror module; the current mirror module is connected to the current bias terminal and connected to the comparison module through the startup module; the current mirror module causes the current in the comparison module to be biased by replicating the bias current.

[0037] Optionally, the constant compliance with the preset condition is that the first voltage signal is greater than the second voltage signal, and the second voltage signal is greater than the preset voltage signal.

[0038] Optionally, the four-phase input voltage signal includes a positive-phase sinusoidal voltage signal, a negative-phase sinusoidal voltage signal, a positive-phase cosine voltage signal, and a negative-phase cosine voltage signal; the four sinusoidal signal terminals include a positive-phase sinusoidal signal terminal for receiving the positive-phase sinusoidal voltage signal, a negative-phase sinusoidal signal terminal for receiving the negative-phase sinusoidal voltage signal, a positive-phase cosine signal terminal for receiving the positive-phase cosine voltage signal, and a negative-phase cosine signal terminal for receiving the negative-phase cosine voltage signal.

[0039] The gating logic circuit further includes at least eight gating switches, which include at least a first gating switch, a second gating switch, a third gating switch, a fourth gating switch, a fifth gating switch, a sixth gating switch, a seventh gating switch, and an eighth gating switch.

[0040] Wherein, the first gating switch and the second gating switch are selectively connected to either the positive phase sinusoidal signal terminal or the negative phase sinusoidal signal terminal;

[0041] The third gating switch and the fourth gating switch are selectively connected to either the positive phase cosine signal terminal or the negative phase cosine signal terminal;

[0042] The fifth selector switch is connected between the first selector switch or the second selector switch and the first output terminal; the sixth selector switch is connected between the first selector switch or the second selector switch and the second output terminal.

[0043] The seventh selector switch is connected between the third or fourth selector switch and the first output terminal; the eighth selector switch is connected between the third or fourth selector switch and the second output terminal.

[0044] This application also provides a sine / cosine encoder, including the angle resolution circuit as described above.

[0045] This application provides an angle resolution method for a sine and cosine encoder, comprising four sine and cosine signal terminals for providing four-phase input voltage signals respectively, a gating logic circuit, a capacitor array circuit, a comparator circuit, and a digital logic adjustment circuit. The gating logic circuit compares the four-phase input voltage signals with a preset voltage signal and selects to output a first voltage signal and a second voltage signal according to a preset condition of constant compliance. The capacitor array circuit scales the first voltage signal according to a preset scaling factor to output a first scaled voltage signal. The comparator circuit compares the first scaled voltage signal and the second voltage signal to output a corresponding real-time voltage ratio value and obtains a preliminary angle value based on the real-time voltage ratio value. The digital logic adjustment circuit adjusts the preset scaling factor and the selection logic of the gating logic circuit based on the real-time voltage ratio value and the preliminary angle value, and through feedback, to output a final angle value. This application completes the arctangent calculation through a capacitor array circuit and a comparator circuit, and uses a digital logic adjustment circuit to adjust the preset scaling factor and the selection logic of the gating logic circuit to obtain a high-precision final angle value. This avoids the need to use two ADCs for arctangent calculation, thereby effectively reducing power consumption, detection delay, and digital resources, and also helps to reduce the size of the sine and cosine encoders.

[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0047] Figure 1 This is a block diagram of the angle resolution circuit of a sine / cosine encoder according to an embodiment of this application.

[0048] Figure 2 for Figure 1 The circuit diagram shown is a selection logic circuit of the angle resolution circuit of a sine / cosine encoder according to one embodiment.

[0049] Figure 3 for Figure 1 The diagram shows a capacitor array circuit of the angle resolution circuit of a sine / cosine encoder according to one embodiment.

[0050] Figure 4 for Figure 1 The circuit diagram shown is a comparison circuit of the angle resolution circuit of a sine / cosine encoder according to one embodiment. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.

[0052] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. If only "a" is referred to, it will be separately stated. "A plurality" or "several" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and / or "upper," etc., are for ease of description only and are not limited to a location or spatial orientation. The terms "comprising" or "including," etc., mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms “connection” or “link” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0053] This application provides an angle resolution method for a sine and cosine encoder, comprising four sine and cosine signal terminals for providing four-phase input voltage signals respectively, a gating logic circuit, a capacitor array circuit, a comparator circuit, and a digital logic adjustment circuit. The gating logic circuit compares the four-phase input voltage signals with a preset voltage signal and selects to output a first voltage signal and a second voltage signal according to a preset condition. The capacitor array circuit scales the first voltage signal according to a preset scaling factor to output a first scaled voltage signal. The comparator circuit compares the first scaled voltage signal and the second voltage signal to output a corresponding real-time voltage ratio value and obtains a preliminary angle value based on the real-time voltage ratio value. The digital logic adjustment circuit adjusts the preset scaling factor and the selection logic of the gating logic circuit based on the real-time voltage ratio value and the preliminary angle value, and through feedback, to output the final angle value. This application completes the arctangent calculation through a capacitor array circuit and a comparator circuit, and uses a digital logic adjustment circuit to adjust the preset scaling factor and the selection logic of the gating logic circuit to obtain a high-precision final angle value. This avoids the need to use two ADCs for arctangent calculation, thereby effectively reducing power consumption, detection delay, and digital resources, and also helps to reduce the size of the sine and cosine encoders.

[0054] This application also provides a sine / cosine encoder, which includes an angle resolution circuit.

[0055] like Figure 1As shown, this application provides an angle resolution circuit 1 for a sine and cosine encoder, specifically including four sine and cosine signal terminals 2, a gating logic circuit 3, a capacitor array circuit 4, a comparison circuit 5, and a digital logic adjustment circuit 6. The four sine and cosine signal terminals 2 are used to provide four-phase input voltage signals. These four-phase input voltage signals include a positive-phase sine voltage signal +VSIN, a negative-phase sine voltage signal -VSIN, a positive-phase cosine voltage signal +VCOS, and a negative-phase cosine voltage signal -VCOS. The gating logic circuit 3 is connected to the sine and cosine signal terminals 2 and is used to compare the four-phase input voltage signals with a preset voltage signal VCM, and select and output a first voltage signal VIN1 and a second voltage signal VIN2 according to a constant compliance preset condition. This constant compliance preset condition is that the first voltage signal VIN1 is greater than the second voltage signal VIN2, and the second voltage signal VIN2 is greater than the preset voltage signal VCM, i.e., VIN1 > VIN2 > VCM. The gating logic circuit 3 includes a first output terminal 7 for outputting the first voltage signal VIN1 and a second output terminal 8 for outputting the second voltage signal VIN2. A capacitor array circuit 4 is connected to the first output terminal 7 and is used to scale the first voltage signal VIN1 according to a preset scaling factor to output a first scaled voltage signal V+. The positive input terminal + of the comparator circuit 5 is connected to the capacitor array circuit 4, and the negative input terminal - of the comparator circuit 5 is connected to the second output terminal 8. This is used to compare the first scaled voltage signal V+ and the second voltage signal VIN2 to output a corresponding real-time voltage ratio value, and to obtain a corresponding preliminary angle value based on the real-time voltage ratio value. A digital logic adjustment circuit 6 is connected to the output terminal of the comparator circuit 5, the capacitor array circuit 4, and the gating logic circuit 3. This is used to adjust the preset scaling factor and the selection logic of the gating logic circuit 3 based on the real-time voltage ratio value and the preliminary angle value, and through feedback, to output a final angle value.

[0056] In this embodiment, the selection logic circuit 3 compares the four-phase input voltage signal with a preset voltage signal VCM to obtain the polarity of the four-phase input voltage signal. Furthermore, based on a constant compliance with a preset condition, the first voltage signal VIN1 and the second voltage signal VIN2 are selected for output. Further, the capacitor array circuit 4 scales the first voltage signal VIN1 according to a preset scaling factor, thereby generating and outputting a first scaled voltage signal V+. This preset scaling factor is set based on the capacitance values ​​within the capacitor array circuit 4; different scaling ratios can be obtained by using different capacitor array logic. Further, the comparison circuit 5 compares the first scaled voltage signal V+ and the second voltage signal VIN2. This comparison involves division to obtain their ratio, which is the real-time voltage ratio value in this embodiment. Then, using an error compensation lookup table method, the real-time voltage ratio value is approximated to the arctangent calculated value, which is the preliminary angle value in this embodiment. Since the initial angle value obtained through a single arctangent calculation is inaccurate, a digital logic adjustment circuit 5 is used to adjust the preset scaling factor of the capacitor array circuit 4 and the selection logic of the gating logic circuit 3, thereby obtaining a more accurate angle value, which is the final angle value in this embodiment. Specifically, the digital logic adjustment circuit 5 adjusts the selection logic of the gating logic circuit 3 and the gating logic of the capacitors in the capacitor array circuit 4 based on the comparison result of the comparison circuit 5, thereby adjusting the first voltage signal VIN1 and the corresponding preset scaling factor of the first voltage signal VIN1. If the comparison result is high, it indicates that the first voltage signal VIN1 scaled by the current preset scaling factor is greater than the second voltage signal VIN2, and the preset scaling factor needs to be increased; if the comparison result is low, it indicates that the first voltage signal VIN1 scaled by the current preset scaling factor is less than the second voltage signal VIN2, and the preset scaling factor needs to be decreased, thereby obtaining a more accurate final angle value. In this way, the use of two ADCs for arctangent calculation is avoided, thereby effectively reducing power consumption, detection delay, and digital resources, and also helping to reduce the size of the sine and cosine encoders.

[0057] In some embodiments, the preset voltage signal VCM is the common-mode voltage signal of the four-phase input voltage signal.

[0058] like Figure 2As shown, in some embodiments, the four sine and cosine signal terminals 2 include a positive-phase sine signal terminal 9 for connecting the positive-phase sine voltage signal VSIN+, a negative-phase sine signal terminal 10 for connecting the negative-phase sine voltage signal VSIN-, a positive-phase cosine signal terminal 11 for connecting the positive-phase cosine voltage signal VCOS+, and a negative-phase cosine signal terminal 12 for connecting the negative-phase cosine voltage signal VCOS-. The gating logic circuit 3 further includes at least eight gating switches, which include at least a first gating switch S1, a second gating switch S1_B, a third gating switch S2, a fourth gating switch S2_B, a fifth gating switch S3, a sixth gating switch S3_B, a seventh gating switch S4, and an eighth gating switch S4_B. Specifically, the first gating switch S1 and the second gating switch S1_B are selectively connected to either the positive-phase sine wave signal terminal 9 or the negative-phase sine wave signal terminal 10, so as to receive either the positive-phase sine wave voltage signal VSIN+ or the negative-phase sine wave voltage signal VSIN-. The third gating switch S2 and the fourth gating switch S2_B are selectively connected to either the positive-phase cosine wave signal terminal 11 or the negative-phase cosine wave signal terminal 12, so as to receive either the positive-phase cosine wave voltage signal VCOS+ or the negative-phase cosine wave voltage signal VCOS-.

[0059] The fifth selector switch S3 is connected between the first selector switch S1 or the second selector switch S1_B and the first output terminal 7. Furthermore, an absolute value taking process is provided between the fifth selector switch S3 and the first selector switch S1 or the second selector switch S1_B, so that both the positive-phase sinusoidal voltage signal VSIN+ and the negative-phase sinusoidal voltage signal VSIN- form a sinusoidal intermediate signal |VSIN|, thereby causing the first output terminal 7 to output the sinusoidal intermediate signal |VSIN|. The sixth selector switch S3_B is connected between the first selector switch S1 or the second selector switch S1_B and the second output terminal 8, thereby causing the second output terminal 8 to output the sinusoidal intermediate signal |VSIN|.

[0060] The seventh selector switch S4 is connected between the third selector switch S2 or the fourth selector switch S2_B and the first output terminal 7. Furthermore, an absolute value taking process is provided between the seventh selector switch S4 and the third selector switch S2 or the fourth selector switch S2_B, so that both the positive-phase cosine voltage signal VCOS+ and the negative-phase cosine voltage signal VCOS- form a cosine intermediate signal |VCOS|, thereby causing the first output terminal 7 to output the cosine intermediate signal |VCOS|. The eighth selector switch S4_B is connected between the third selector switch S2 or the fourth selector switch S2_B and the second output terminal 8, thereby causing the second output terminal 8 to output the cosine intermediate signal |VCOS|.

[0061] In this embodiment, the polarity of the four-phase signals is obtained by comparing the positive-phase sinusoidal voltage signal VSIN+, the negative-phase sinusoidal voltage signal VSIN-, the positive-phase cosine voltage signal VCOS+, and the input negative-phase cosine voltage signal VCOS- with a preset voltage signal VCM. Furthermore, based on the control signal of the digital logic adjustment circuit 6 and at least eight selection switches, the first voltage signal VIN1 and the second voltage signal VIN2, which consistently meet the preset conditions, are selected, resulting in a simple circuit structure.

[0062] like Figure 3 As shown, in some embodiments, the capacitor array circuit 4 includes a voltage input terminal 13, a voltage output terminal 14, a sampling switch S_sample, a sampling capacitor Cs, at least eight charging capacitors 15, and at least eight control switches 16. The voltage input terminal 13 is used to input the first voltage signal VIN1. The voltage output terminal 14 is used to output the first scaled voltage signal V+. The sampling switch S_sample is connected between the voltage input terminal 13 and the voltage output terminal 14. One end of the sampling capacitor Cs is connected to the preset voltage signal VCM, and the other end is connected between the sampling switch S_sample and the voltage output terminal 14; the upper board of each charging capacitor 15 is connected to each control switch 16, and the lower board of each charging capacitor 15 is connected between the sampling switch S_sample and the voltage output terminal 14; each control switch 16 includes a first terminal, a second terminal, and a third terminal; the first terminal of each control switch 16 is connected to the upper plate of each charging capacitor 15, the second terminal of each control switch 16 is connected to the voltage input terminal 13, and the third terminal of each control switch 16 is connected to the preset voltage signal VCM.

[0063] Specifically, the at least eight charging capacitors 15 include at least the first capacitor C1p, the second capacitor C2p, the third capacitor C3p, the fourth capacitor C4p, the fifth capacitor C5p, the sixth capacitor C6p, the seventh capacitor C7p, and the eighth capacitor C8p. The at least eight control switches 16 include at least the first control switch S1p, the second control switch S2p, the third control switch S3p, the fourth control switch S4p, the fifth control switch S5p, the sixth control switch S6p, the seventh control switch S7p, and the eighth control switch S8p. The upper plate of the first capacitor C1p is connected to the first terminal of the first control switch S1p, and the lower plate of the first capacitor C1p is connected between the sampling switch S_sample and the voltage output terminal 14; the upper plate of the second capacitor C2p is connected to the first terminal of the second control switch S2p, and the lower plate of the second capacitor C2p is connected between the sampling switch S_sample and the voltage output terminal 14; the upper plate of the third capacitor C3p is connected to the first terminal of the third control switch S3p, and the lower plate of the third capacitor C3p is connected between the sampling switch S_sample and the voltage output terminal 14; the upper plate of the fourth capacitor C4p is connected to the first terminal of the fourth control switch S4p, and the lower plate of the fourth capacitor C4p is connected between the sampling switch S_sample and the voltage output terminal 14. The upper plate of the fifth capacitor C5p is connected to the first terminal of the fifth control switch S5p, and the lower plate of the fifth capacitor C5p is connected between the sampling switch S_sample and the voltage output terminal 14. The upper plate of the sixth capacitor C6p is connected to the first terminal of the sixth control switch S6p, and the lower plate of the sixth capacitor C6p is connected between the sampling switch S_sample and the voltage output terminal 14. The upper plate of the seventh capacitor C7p is connected to the first terminal of the seventh control switch S7p, and the lower plate of the seventh capacitor C7p is connected between the sampling switch S_sample and the voltage output terminal 14. The upper plate of the eighth capacitor C8p is connected to the first terminal of the eighth control switch S8p, and the lower plate of the eighth capacitor C8p is connected between the sampling switch S_sample and the voltage output terminal 14. The second terminal of the first control switch S1p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the second control switch S2p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the third control switch S3p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the fourth control switch S4p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the fifth control switch S5p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the sixth control switch S6p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM. The second terminal of the seventh control switch S7p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM.The second terminal of the eighth control switch S8p is connected to the voltage input terminal 13, and the third terminal is connected to the preset voltage signal VCM.

[0064] In this embodiment, the operation of the sampling switch S_sample includes a sampling phase and a feedback adjustment phase. The sampling phase involves the sampling switch S_sample closing, causing the first scaled voltage signal V+ at the voltage output terminal 14 to charge all charging capacitors. The feedback adjustment phase involves the sampling switch S_sample closing, and adjusting the selection logic of at least eight control switches to change the potential of the upper plate of each charging capacitor, thereby adjusting the charge distribution result of the lower plate, which in turn adjusts the preset scaling factor of the first voltage signal VIN1, further changing the first scaled voltage signal V+ at the voltage output terminal 14.

[0065] The preset scaling factor is determined by changing the number of charging capacitors connected to the preset voltage signal VCM during the redistribution phase. Specifically, the formula for calculating the preset scaling factor A is:

[0066] Q tot =C S V IN (1)

[0067] Q tot =(C s +C n V OUT +(C N -C n (V) OUT -V IN (2)

[0068] From equations (1) and (2), and the law of charge conservation, we obtain:

[0069]

[0070] Among them, C TOT =C S +C N Q tot C represents the total charge on all capacitors in the capacitor array circuit; S Indicates the sampling capacitor; V IN Indicates the sampled voltage; C n This represents the total capacitance of all capacitors connected to the preset voltage signal on the upstream board among all charging capacitors; V OUT This indicates the voltage value of the upper plate of the capacitor after feedback adjustment; C N This represents the total capacitance of all charging capacitors.

[0071] From the above formula (3), it can be seen that the voltage value V of the upper plate of the capacitor after feedback adjustment is OUTThis is the result of the first voltage signal VIN1 being reduced by a certain ratio. The voltage value V on the upper plate of the capacitor after this feedback adjustment... OUT That is, the first scaled voltage signal V+.

[0072] In this embodiment, the sampling phase begins by closing the sampling switch S_sample, allowing the initial scaled voltage signal V+ to charge all charging capacitors. Then, the feedback adjustment phase turns off the sampling switch S_sample and adjusts the selection logic of at least eight control switches, thereby changing the preset scaling factor and generating a new first scaled voltage signal V+ output. This improves the accuracy of the real-time voltage ratio value obtained by the subsequent comparison circuit 5.

[0073] In some embodiments, the at least eight charging capacitors 15 are connected in parallel sequentially, wherein the capacitance values ​​of the first two charging capacitors are the same as those of the sampling capacitor C. S The capacitance values ​​are the same. Furthermore, the capacitance value of each of the at least six charging capacitors is twice that of the preceding charging capacitor.

[0074] Specifically, the capacitance value of the first capacitor C1p is the same as that of the sampling capacitor Cs, and the capacitance value of the second capacitor C2p is the same as that of the first C1p. The capacitance value of the third capacitor C3p is twice that of the second capacitor C2p. The capacitance value of the fourth capacitor C4p is twice that of the third capacitor C3p. The capacitance value of the fifth capacitor C5p is twice that of the fourth capacitor Cp4. The capacitance value of the sixth capacitor C6p is twice that of the fifth capacitor C5p. The capacitance value of the seventh capacitor C7p is twice that of the sixth capacitor C6p. The capacitance value of the eighth capacitor C8p is twice that of the seventh capacitor C7p. In this embodiment, the capacitance values ​​of the charging capacitors are set according to binary, which is consistent with the logic of traditional SAR-ADC (successive approximation register-analog to digital converter). Such a regular proportional relationship is beneficial for layout drawing and improves the manufacturing accuracy of the circuit.

[0075] like Figure 4As shown, in some embodiments, the comparison circuit 5 includes a comparison module 20, a positive output node OUT+, a negative output node OUT-, and a positive feedback module 21. The positive input terminal + of the comparison module is connected to the output terminal of the capacitor array circuit 4, and the negative input terminal - is connected to the second output terminal 8 of the gating logic circuit 3, used to compare the first scaled voltage signal V+ and the second voltage signal VIN2, and output the comparison result. The positive feedback module 21 is connected to the comparison module 20, the positive output node OUT+, and the negative output node OUT-, used to set one of the positive output node OUT+ and the negative output node OUT- to a high level and the other to a low level according to the comparison result.

[0076] Specifically, the comparison module 20 includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The gate of the first NMOS transistor NM1 is connected to the output terminal of the capacitor array circuit 4, and its drain is connected to the positive feedback module 21. The gate of the second NMOS transistor NM2 is connected to the second output terminal 8, and its drain is connected to the positive feedback module 21. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected. The comparison module 20 compares the first scaled voltage signal V+ and the second voltage signal VIN2 using the first NMOS transistor NM1 and the second NMOS transistor NM2.

[0077] The positive feedback module 21 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The source of the first PMOS transistor PM1 is connected to the power supply terminal VCC, its drain is connected to the positive output node OUT+, and its gate is connected to the gate of the third NMOS transistor NM3 and the drain of the second PMOS transistor PM2. The source of the second PMOS transistor PM2 is connected to the power supply terminal VCC, its drain is connected to the negative output node OUT-, and its gate is connected to the gate of the fourth NMOS transistor NM4 and the drain of the first PMOS transistor PM1. The source of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM1. The source of the fourth NMOS transistor NM4 is connected to the drain of the second NMOS transistor NM2.

[0078] In this embodiment, the first PMOS transistor PM1 and the third NMOS transistor NM3 form an inverter. The second PMOS transistor PM2 and the fourth NMOS transistor NM4 form an inverter. These two inverters form positive feedback. When the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, the potentials of the first scaling voltage signal V+ and the second voltage signal VIN2 are inconsistent, resulting in the current flowing through the first NMOS transistor NM1 not being equal to the current flowing through the second NMOS transistor NM2. This leads to a difference in the discharge rates of the positive output node OUT+ and the negative output node OUT-. Thus, the two inverters in the positive feedback module 21 can accelerate the difference in discharge rates between the positive output node OUT+ and the negative output node OUT-, causing one of the positive output node OUT+ and the negative output node OUT- to output a high level and the other to output a low level.

[0079] In some embodiments, the comparison circuit 5 further includes a startup module 22 and a reset module 23. The startup module 22 is connected to the comparison module 20 and is connected to a clock signal CLK, used to start the comparison module 20 when the clock signal CLK is high. The reset module 23 is connected to the positive feedback module 21 and is connected to a clock signal CLK, used to reset the positive feedback module 21 to a high level when the clock signal CLK is low.

[0080] Specifically, the startup module 22 includes a fifth NMOS transistor NM5, whose gate is connected to the clock signal CLK, and whose drain is connected to the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2. When the clock signal CLK is high, the fifth NMOS transistor NM5 is turned on, allowing current to flow through the first NMOS transistor NM1 and the second NMOS transistor NM2, and the comparison module 20 starts working.

[0081] The reset module 23 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM6. The gates of the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are all connected to the clock signal CLK. The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are all connected to the power supply terminal VCC. The drain of the third PMOS transistor PM3 is connected to the source of the third NMOS transistor NM3. The drain of the fourth PMOS transistor PM4 is connected to the source of the fourth NMOS transistor NM4. The drain of the fifth PMOS transistor PM5 is connected between the drain of the first PMOS transistor PM1 and the drain of the third NMOS transistor NM3. The drain of the sixth PMOS transistor PM6 is connected between the drain of the second PMOS transistor PM2 and the drain of the fourth NMOS transistor NM4.

[0082] In this embodiment, when the clock signal CLK is low, the corresponding third PMOS transistor PM3, fourth PMOS transistor PM4, fifth PMOS transistor PM5, and sixth PMOS transistor PM6 are all turned on, thereby resetting the source-drain voltage of the third NMOS transistor NM3 and the source-drain voltage of the fourth PMOS transistor PM4 to a high level.

[0083] In some embodiments, the comparison circuit 5 further includes a current bias terminal 24 for receiving a bias current Ibias and a current mirror module 25. The current mirror module 25 is connected to the current bias terminal 24 and to the comparison module 20 via the startup module 22. The current mirror module 25 biases the current in the comparison module 20 by replicating the bias current Ibias.

[0084] Specifically, the current mirror module 25 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7. The drain of the sixth NMOS transistor NM6 is connected to the current bias terminal 24, its source is grounded, and its gate is shorted to its drain. The drain of the seventh NMOS transistor NM7 is connected to the source of the fifth PMOS transistor PM5, its gate is connected to the gate of the sixth NMOS transistor NM6, and its source is grounded. In this embodiment, the current mirror module 25 introduces a bias current Ibias into the comparison module 20, and stabilizes the bias current Ibias transmitted to the comparison module 20.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An angle analysis circuit for a sine / cosine encoder, characterized in that, include: Four sine and cosine signal terminals used to provide four-phase input voltage signals respectively; A selection logic circuit, connected to the sine and cosine signal terminals, is used to compare the four-phase input voltage signal with a preset voltage signal, and select to output a first voltage signal and a second voltage signal according to a preset condition that the condition is always met; the selection logic circuit includes a first output terminal for outputting the first voltage signal and a second output terminal for outputting the second voltage signal. A capacitor array circuit, connected to the first output terminal, is used to scale the first voltage signal according to a preset scaling factor to output a first scaled voltage signal. A comparator circuit, wherein the positive input terminal of the comparator circuit is connected to the capacitor array circuit and the negative input terminal of the comparator circuit is connected to the second output terminal, is used to compare the first scaled voltage signal and the second voltage signal to output a corresponding real-time voltage ratio value, and obtain a corresponding preliminary angle value based on the real-time voltage ratio value; and A digital logic adjustment circuit, connected to the output of the comparator circuit, the capacitor array circuit, and the gating logic circuit, is used to adjust the preset scaling factor and the selection logic of the gating logic circuit based on the real-time voltage ratio value and the preliminary angle value, and through feedback, to output the final angle value. The capacitor array circuit includes: The voltage input terminal is used to input the first voltage signal; The voltage output terminal is used to output the first scaled voltage signal; The system comprises a sampling switch, a sampling capacitor, at least eight charging capacitors, and at least eight control switches; wherein the sampling switch is connected between the voltage input terminal and the voltage output terminal; one end of each sampling capacitor is connected to the preset voltage signal, and the other end is connected between the sampling switch and the voltage output terminal; the upper plate of each charging capacitor is connected to each control switch, and the lower plate of each charging capacitor is connected between the sampling switch and the voltage output terminal; each control switch includes a first terminal, a second terminal, and a third terminal; the first terminal of each control switch is connected to the upper plate of each charging capacitor, the second terminal of each control switch is connected to the voltage input terminal, and the third terminal of each control switch is connected to the preset voltage signal.

2. The angle analysis circuit according to claim 1, characterized in that, The at least eight charging capacitors are connected in parallel in sequence, wherein the capacitance values ​​of the first two charging capacitors are the same as the capacitance value of the sampling capacitor. Furthermore, the capacitance value of each of the at least six said charging capacitors is twice the capacitance value of the previous said charging capacitor.

3. The angle analysis circuit according to claim 2, characterized in that, The formula for calculating the preset scaling factor A is as follows: ；(1) ； (2) From formulas (1) and (2), we get: ； in, ; This represents the total charge on all capacitors in the capacitor array circuit; Indicates the sampling capacitance; Indicates the sampled voltage; This represents the total capacitance of all capacitors connected to the preset voltage signal on the upstream board among all charging capacitors. This indicates the voltage value of the upper plate of the capacitor after feedback adjustment; This represents the total capacitance of all charging capacitors.

4. The angle analysis circuit according to claim 1, characterized in that, The comparison circuit includes: The comparison module has its positive input connected to the output of the capacitor array circuit and its negative input connected to the second output of the gating logic circuit. It is used to compare the first scaled voltage signal and the second voltage signal and output the comparison result. Positive output nodes and negative output nodes; A positive feedback module is connected to the comparison module, the positive output node, and the negative output node, and is used to make one of the positive output node and the negative output node output a high level and the other output a low level according to the comparison result.

5. The angle analysis circuit according to claim 4, characterized in that, The comparison circuit further includes: A startup module is connected to the comparison module and is connected to a clock signal, used to start the comparison module when the clock signal is high. A reset module is connected to the positive feedback module and is connected to a clock signal. It is used to reset the positive feedback module to a high level when the clock signal is low.

6. The angle analysis circuit according to claim 5, characterized in that, The comparison circuit further includes a current bias terminal for receiving a bias current and a current mirror module; the current mirror module is connected to the current bias terminal and connected to the comparison module through the startup module; the current mirror module causes the current in the comparison module to be biased by replicating the bias current.

7. The angle analysis circuit according to claim 1, characterized in that, The constant compliance with the preset condition is that the first voltage signal is greater than the second voltage signal, and the second voltage signal is greater than the preset voltage signal.

8. The angle analysis circuit according to claim 1, characterized in that, The four-phase input voltage signal includes a positive-phase sinusoidal voltage signal, a negative-phase sinusoidal voltage signal, a positive-phase cosine voltage signal, and a negative-phase cosine voltage signal; the four sinusoidal signal terminals include a positive-phase sinusoidal signal terminal for receiving the positive-phase sinusoidal voltage signal, a negative-phase sinusoidal signal terminal for receiving the negative-phase sinusoidal voltage signal, a positive-phase cosine signal terminal for receiving the positive-phase cosine voltage signal, and a negative-phase cosine signal terminal for receiving the negative-phase cosine voltage signal. The gating logic circuit further includes at least eight gating switches, which include at least a first gating switch, a second gating switch, a third gating switch, a fourth gating switch, a fifth gating switch, a sixth gating switch, a seventh gating switch, and an eighth gating switch. Wherein, the first gating switch and the second gating switch are selectively connected to either the positive phase sinusoidal signal terminal or the negative phase sinusoidal signal terminal; The third gating switch and the fourth gating switch are selectively connected to either the positive phase cosine signal terminal or the negative phase cosine signal terminal; The fifth selector switch is connected between the first selector switch or the second selector switch and the first output terminal; the sixth selector switch is connected between the first selector switch or the second selector switch and the second output terminal. The seventh selector switch is connected between the third or fourth selector switch and the first output terminal; the eighth selector switch is connected between the third or fourth selector switch and the second output terminal.

9. A sine / cosine encoder, characterized in that, Includes the angle resolution circuit as described in any one of claims 1-8 above.

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