Signal detection circuit, detection method, motor controller, compressor and vehicle

Abstract

The application discloses a signal detection circuit, a detection method, a motor controller, a compressor and a vehicle, wherein the circuit comprises: a lower bridge driving unit configured to output a first fault detection signal; an upper bridge driving unit configured to output a second fault detection signal; a switching unit configured to cut off transmission of the second fault detection signal in a stage in which a lower bridge switch tube is turned on to charge a bootstrap capacitor and a negative voltage capacitor of the upper bridge driving unit; and a control unit configured to control the switching unit to cut off transmission of the second fault detection signal, and control the switching unit to be turned on to simultaneously receive the first fault detection signal and the second fault detection signal when the bootstrap capacitor and the negative voltage capacitor of the upper bridge driving unit complete charging. The circuit can not only save IO resources, but also avoid the situation that the upper bridge driving unit outputs the fault detection signal in the charging stage to cause the controller to be unable to normally operate.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a signal detection circuit, detection method, motor controller, compressor, and vehicle. Background Technology

[0002] Third-generation semiconductors, represented by SiC (silicon carbide), have broad application prospects in fields such as electric vehicles due to their higher switching frequency, higher voltage and temperature resistance, lower loss under the same operating conditions, and smaller size than traditional Si (silicon) devices with the same performance.

[0003] For example, an electric vehicle is equipped with a motor and a motor controller. The motor controller includes a three-phase inverter bridge composed of power devices such as SiC, a driver chip with bootstrap and negative voltage capacitors, and an MCU (Micro Controller Unit). The MCU outputs drive signals to the driver chip, which drives the three-phase inverter bridge to operate and thus the motor. When a power device malfunctions, such as a short-circuit or overcurrent fault, the driver chip needs to promptly shut down the power device and output a fault signal to the MCU so that the MCU can take protective measures based on the fault signal to prevent the accident from escalating. However, in the initial state, the bootstrap and negative voltage capacitors in the driver chip need to be charged. During this time, the driver chip will continuously output fault signals to the MCU, causing the MCU to falsely activate its protection mechanism, thus preventing the motor controller from operating normally. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in the related art. Therefore, the first objective of this invention is to provide a fault protection signal detection circuit that not only saves I / O resources but also prevents the controller from malfunctioning due to the upper bridge drive unit outputting a fault detection signal during the charging phase.

[0005] The second objective of this invention is to provide a motor controller.

[0006] The third objective of this invention is to provide a compressor.

[0007] The fourth objective of this invention is to provide a vehicle.

[0008] The fifth objective of this invention is to propose a fault protection signal detection method.

[0009] To achieve the above objectives, a first aspect of the present invention provides a fault protection signal detection circuit, comprising: a lower bridge driving unit for driving the lower bridge switch to turn on or off, and outputting a first fault detection signal by detecting whether the lower bridge switch has failed; an upper bridge driving unit for driving the upper bridge switch to turn on or off, and outputting a second fault detection signal by detecting whether the upper bridge switch has failed; a switching unit for shutting off the transmission of the second fault detection signal during the stage when the lower bridge switch is turned on to charge the bootstrap and negative voltage capacitors of the upper bridge driving unit; and a control unit for driving the lower bridge switch to turn on via the lower bridge driving unit to charge the bootstrap and negative voltage capacitors of the upper bridge driving unit, controlling the switching unit to shut off the transmission of the second fault detection signal, and controlling the switching unit to turn on when the bootstrap and negative voltage capacitors of the upper bridge driving unit have finished charging, so as to simultaneously receive the first fault detection signal and the second fault detection signal.

[0010] According to an embodiment of the present invention, the fault protection signal detection circuit drives the lower bridge switch to turn on or off via the lower bridge drive unit, and outputs a first fault detection signal when a fault is detected in the lower bridge switch. It also drives the upper bridge switch to turn on or off via the upper bridge drive unit, and outputs a second fault detection signal when a fault is detected in the upper bridge switch. Furthermore, during the phase where the lower bridge switch is turned on via the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, the circuit controls the switch unit to turn off the transmission of the second fault detection signal. Finally, when the bootstrap and negative voltage capacitors of the upper bridge drive unit have completed charging, the circuit controls the switch unit to turn on, so as to simultaneously receive the first and second fault detection signals. This not only saves I / O resources but also avoids the situation where the controller malfunctions due to the upper bridge drive unit outputting a fault detection signal during the charging phase.

[0011] To achieve the above objectives, a second aspect of the present invention provides a motor controller, comprising: a three-phase inverter bridge; and a fault protection signal detection circuit according to a first aspect of the present invention.

[0012] According to the embodiments of the present invention, the motor controller, through the aforementioned fault protection signal detection circuit, can not only save IO resources, but also avoid the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction.

[0013] To achieve the above objectives, a third aspect of the present invention provides a compressor, comprising: a motor; and a motor controller according to a second aspect of the present invention, the motor controller being used to drive the motor to operate.

[0014] According to the compressor of the present invention, the aforementioned motor controller can not only save IO resources, but also avoid the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction and thus the compressor to malfunction.

[0015] To achieve the above objectives, a fourth aspect of the present invention provides a vehicle including a compressor according to a third aspect of the present invention.

[0016] According to the vehicle of the present invention, the aforementioned compressor not only saves IO resources, but also avoids the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction and thus the vehicle to malfunction.

[0017] To achieve the above objectives, a fifth aspect of the present invention provides a fault protection signal detection method applied to the aforementioned motor controller. The method includes: when the motor controller is powered on, driving the lower bridge switch transistor to conduct through the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, and controlling the switch unit to turn off the transmission of the second fault detection signal; when the bootstrap and negative voltage capacitors of the upper bridge drive unit have completed charging, controlling the switch unit to conduct to simultaneously receive the first fault detection signal and the second fault detection signal.

[0018] According to the fault protection signal detection method of the present invention, when the motor controller is powered on, the lower bridge drive unit drives the lower bridge switch to conduct, so as to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, and controls the switch unit to turn off the transmission of the second fault detection signal. When the bootstrap and negative voltage capacitors of the upper bridge drive unit have completed charging, the switch unit is controlled to conduct, so as to simultaneously receive the first fault detection signal and the second fault detection signal. This not only saves IO resources, but also avoids the situation where the upper bridge drive unit outputs a fault detection signal during the charging stage, causing the controller to malfunction.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] Figure 1 This is a block diagram of a fault protection signal detection circuit according to an embodiment of the present invention;

[0021] Figures 2-3 A circuit diagram of a fault signal detection circuit according to an embodiment of the present invention;

[0022] Figure 4 This is a block diagram of a motor controller according to an embodiment of the present invention;

[0023] Figure 5 This is a block diagram of a compressor according to an embodiment of the present invention;

[0024] Figure 6 A block diagram of a vehicle according to an embodiment of the present invention;

[0025] Figure 7 This is a flowchart illustrating a fault protection signal detection method according to an embodiment of the present invention. Detailed Implementation

[0026] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0027] Figure 1 This is a block diagram of a fault protection signal detection circuit according to an embodiment of the present invention.

[0028] like Figure 1 As shown, the fault protection signal detection circuit 100 includes: a lower bridge drive unit 110, an upper bridge drive unit 120, a switching unit 130, and a control unit 140.

[0029] The lower bridge drive unit 110 is used to drive the lower bridge switch Q2 to turn on or off, and outputs a first fault detection signal by detecting whether the lower bridge switch Q2 has failed. The upper bridge drive unit 120 is used to drive the upper bridge switch Q1 to turn on or off, and outputs a second fault detection signal by detecting whether the upper bridge switch Q1 has failed. The switch unit 130 is used to turn off the transmission of the second fault detection signal when the lower bridge switch Q2 is turned on and the bootstrap capacitor and negative voltage capacitor of the upper bridge drive unit 120 are charging. The control unit 140 is used to drive the lower bridge switch Q2 to turn on through the lower bridge drive unit 110 to charge the bootstrap capacitor and negative voltage capacitor of the upper bridge drive unit 120, and to control the switch unit 130 to turn off the transmission of the second fault detection signal. It also controls the switch unit 130 to turn on when the bootstrap capacitor and negative voltage capacitor of the upper bridge drive unit 120 have finished charging, so as to simultaneously receive the first and second fault detection signals.

[0030] It should be noted that, Figure 1 The bridge arm formed by the series connection of the upper bridge switch Q1 and the lower bridge switch Q2 shown can be one of the bridge arms in the three-phase inverter bridge of the motor controller, but it is not limited to this. For ease of description, the following explanation uses a motor controller as an example.

[0031] During the initialization phase of the motor controller, since the upper bridge drive unit 120 is a drive unit with a bootstrap capacitor and a negative voltage capacitor, it is necessary to charge the bootstrap capacitor and negative voltage capacitor in the upper bridge drive unit 120 first. At this time, the control unit 140 outputs a drive signal to the lower bridge drive unit 110, which drives the lower bridge switch Q2 to conduct. The upper bridge drive unit 120 charges its internal bootstrap capacitor and negative voltage capacitor through node X and the lower bridge switch Q2. During the charging phase, the upper bridge drive unit 120 continuously outputs a second fault detection signal (negative voltage not reaching the threshold) and inputs it to the switch unit 130. To prevent the second fault detection signal from being transmitted to the control unit 140 and causing the control unit 140 to falsely protect itself, the control unit 140 controls the switch unit 130 to turn off the transmission of the second fault detection signal, thereby avoiding false protection during the charging phase and preventing the motor controller from failing to operate normally.

[0032] When the bootstrap capacitor and negative voltage capacitor of the upper bridge drive unit 120 have finished charging, the control unit 140 controls the switching unit 130 to turn on. Since the upper bridge drive unit 120 will stop outputting the second fault detection signal after charging is complete, it will not cause the control unit 140 to falsely protect itself. It should be noted that whether the upper bridge drive unit 120 has finished charging can be determined by the control unit 140 based on empirical data or theoretical data. For example, if the charging process of the upper bridge drive unit 120 takes about 300us (not limited to this, the specific time depends on the actual situation), then the switching unit 130 can be turned on after 300us.

[0033] Subsequently, the motor controller enters the normal operation phase. The control unit 140 outputs drive signals to the upper bridge drive unit 120 and the lower bridge drive unit 110 according to control requirements. The upper bridge drive unit 120 and the lower bridge drive unit 110 then drive the upper bridge switch Q1 and the lower bridge switch Q2 to turn on or off. During this period, the upper bridge drive unit 120 also detects whether the upper bridge switch Q1 has failed, and outputs a second fault detection signal when a fault occurs (such as a short-circuit overcurrent fault). Simultaneously, the lower bridge drive unit 110 also detects whether the lower bridge switch Q2 has failed, and outputs a first fault detection signal when a fault occurs. The first and second fault detection signals can be transmitted to the control unit 140 through the switching unit 130, enabling the control unit 140 to perform protection based on the first and second fault detection signals, such as stopping the output of drive signals to the upper bridge drive unit 120 and the lower bridge drive unit 110, thereby protecting the upper bridge switch Q1 and the lower bridge switch Q2, and ultimately protecting the motor controller.

[0034] In the above embodiments, since the switching unit simultaneously receives the first fault detection signal and the second fault detection signal and transmits them to the control unit, the I / O (input / output) usage of the control unit can be reduced, saving I / O resources. At the same time, during the charging phase of the upper bridge drive unit, the switching unit shuts off the transmission of the second fault detection signal, thus avoiding the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the motor controller to malfunction.

[0035] In some embodiments, the control unit 140 is further configured to receive a first fault detection signal during the phase in which the lower bridge switch Q2 is turned on to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit 120.

[0036] Specifically, during the charging phase of the upper bridge drive unit 120, since the lower bridge drive unit 110 does not need to use a bootstrap capacitor, when the lower bridge drive unit 110 detects a fault in the lower bridge switch Q2, it transmits a first fault detection signal to the switch unit 130. At this time, the switch unit 130 is allowed to transmit the signal to the control unit 140 so that the control unit 140 can take corresponding protection measures when the lower bridge switch Q2 fails, thus preventing an accident caused by the failure of the lower bridge switch Q2 during the charging phase.

[0037] In some embodiments, when the lower bridge drive unit 110 detects a fault in the lower bridge switch Q2, it drives the lower bridge switch Q2 to turn off. When the upper bridge drive unit 120 detects a fault in the upper bridge switch Q1, it drives the upper bridge switch Q1 to turn off. When the control unit 140 determines that either the lower bridge switch Q2 or the upper bridge switch Q1 has failed based on the first fault detection signal and the second fault detection signal, it shuts down the drive signals output to the lower bridge drive unit 120 and the upper bridge drive unit 110.

[0038] For example, during the initialization phase of the motor controller, when a fault occurs in the lower bridge switch Q2, the lower bridge drive unit 110 will detect the fault, drive the lower bridge switch Q2 to turn off based on the fault, and simultaneously output a first fault detection signal to the switch unit 130, which will then transmit the signal to the control unit 140. When the control unit 140 receives the first fault detection signal, it will stop outputting drive signals to the lower bridge drive unit 120.

[0039] During normal operation of the motor controller, when a fault occurs in the lower bridge switch Q2, the lower bridge drive unit 110 will detect the fault, drive the lower bridge switch Q2 to turn off based on the fault, and simultaneously output a first fault detection signal to the switch unit 130. The switch unit 130 then transmits the signal to the control unit 140. When the control unit 140 receives the first fault detection signal, it stops outputting drive signals to the lower bridge drive unit 120 and the upper bridge drive unit 110 to protect the motor controller. Similarly, when a fault occurs in the upper bridge switch Q1, the upper bridge drive unit 120 will detect the fault, drive the upper bridge switch Q1 to turn off based on the fault, and simultaneously output a second fault detection signal to the switch unit 130. The switch unit 130 then transmits the signal to the control unit 140. When the control unit 140 receives the second fault detection signal, it stops outputting drive signals to the lower bridge drive unit 120 and the upper bridge drive unit 110 to protect the motor controller.

[0040] Therefore, the motor controller can be protected during both the charging and normal operation phases.

[0041] In some embodiments, reference Figure 2 As shown, the upper bridge drive unit 120 includes an isolation chip 121, a first diode D1, and an upper bridge drive chip 122. The first input pin IN1 of the isolation chip 121 is connected to the upper bridge drive signal output terminal of the control unit 140; the anode of the first diode D1 serves as the fault protection signal output terminal of the upper bridge drive unit 120, and the cathode of the first diode D1 is connected to the first output pin OUT2 of the isolation chip 121; the input pin IN of the upper bridge drive chip 122 is connected to the second output pin OUT1 of the isolation chip 121, and the output pin OUT of the upper bridge drive chip 122 is connected to the second input pin IN2 of the isolation chip 121, and is connected to the first preset power supply VCC1 through a first pull-up resistor R1; the drive output pin VOUT of the upper bridge drive chip 122 is connected to the control terminal of the upper bridge switch Q1.

[0042] Continue to refer to Figure 2 As shown, the lower bridge drive unit 110 includes: a lower bridge drive chip 111, the output pin OUT of the lower bridge drive chip 111 is connected to the second preset power supply VCC2 through the second pull-up resistor R2, and serves as the fault protection signal output terminal of the lower bridge drive unit 110, the input pin IN of the lower bridge drive chip 111 is connected to the lower bridge drive signal output terminal of the control unit 140, and the drive output pin VOUT of the lower bridge drive chip 111 is connected to the control terminal of the lower bridge switch Q2.

[0043] Specifically, since the upper bridge switch Q1 corresponds to the high voltage side, the upper bridge drive unit 120 adopts an isolation drive scheme to isolate the high voltage signal from the low voltage signal on the switch unit 130 and control unit 140 side, so as to prevent the high voltage signal from affecting the low voltage signal; since the lower bridge switch Q2 corresponds to the low voltage side, the lower bridge drive unit 110 can adopt a non-isolation drive scheme.

[0044] Both the upper bridge driver chip 122 and the lower bridge driver chip 111 are chips with bootstrapping, negative voltage, and desaturation detection functions. For example, when a short circuit fault occurs in the upper bridge switch Q1, the upper bridge driver chip 122 will detect the fault and perform hardware shutdown, while simultaneously outputting a second fault detection signal Fault2 to the isolation chip 121. After isolation by the isolation chip 121, the signal is transmitted to the switching unit 130, and then to the control unit 140 for protection. When a short circuit fault occurs in the lower bridge switch Q2, the lower bridge driver chip 111 will detect the fault and perform hardware shutdown, while simultaneously outputting a first fault detection signal Fault1 to the switching unit 130, and then to the control unit 140 for protection.

[0045] In some embodiments, the switching unit 130 includes any one of a transistor, a MOSFET, a silicon controlled rectifier (SCR), and an IGBT. (See reference) Figure 3 As shown, when the switching unit 130 includes an NMOS transistor Q3, the drain of the NMOS transistor Q3 is connected to the fault protection signal output terminal of the lower bridge drive unit 110, the source of the NMOS transistor Q3 is connected to the fault protection signal output terminal of the upper bridge drive unit 120, and the gate of the NMOS transistor Q3 is connected to the control signal output terminal IO2 of the control unit 140.

[0046] Further reference Figure 3 As shown, the switching unit 130 further includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected between the gate of the NMOS transistor Q3 and the control signal output terminal IO2 of the control unit 140; the second resistor R2 is connected between the gate and source of the NMOS transistor Q3. The first resistor R1 is the gate drive resistor of the NMOS transistor Q3, and the second resistor R2 is a pull-down resistor, used to ensure that the NMOS transistor Q3 can be reliably driven.

[0047] The switching unit 130 further includes a third resistor R3 and a first capacitor C1. The third resistor R3 is connected between the drain of the NMOS transistor Q3 and the signal input terminal IO1 of the control unit 140. One end of the first capacitor C1 is connected to the signal input terminal IO1 of the control unit 140, and the other end of the first capacitor C1 is grounded to GND1. The third resistor R3 and the first capacitor C1 constitute a low-pass filter circuit, and different cutoff frequencies can be set according to the parameters to filter the first fault detection signal Fault1.

[0048] Specifically, the upper bridge driver chip 122 and the lower bridge driver chip 111 will generally output fault detection signals in the following situations: 1) the negative voltage does not reach the threshold; 2) the positive voltage does not reach the threshold (undervoltage situation); 3) the switching transistor experiences overcurrent.

[0049] Combination Figures 2-3 As shown, during the initialization phase of the motor controller, the bootstrap capacitor and negative voltage capacitor of the upper bridge driver chip 122 need to be charged first. At this time, the control unit 140 outputs a drive signal to the lower bridge driver chip 111 to control the lower bridge switch Q2 to turn on. The upper bridge driver chip 122 charges its internal bootstrap capacitor and negative voltage capacitor through node X and the lower bridge switch Q2. During this period, since the negative voltage has not reached the threshold, the upper bridge driver chip 122 will continuously output a low-level second fault detection signal Fault2 to the isolation chip 121. The signal is then transmitted to the switching unit 130 through the isolation chip 121 and the first diode D1. At the same time, the control unit 140 outputs a low-level control signal to the NMOS transistor Q3 in the switching unit 130 through the control signal output terminal IO2 to turn it off. At this time, the low-level second fault detection signal Fault2 cannot enter the signal input terminal IO1 of the control unit 140 through the NMOS transistor Q3, and the control unit 140 will not perform protection. Since the lower bridge driver chip 111 does not require a bootstrap capacitor, when the lower bridge switch Q2 fails (such as overcurrent), the lower bridge driver chip 111 will output a low-level first fault detection signal Fault1 to the switching unit 130. Since there is no limitation from the NMOS transistor Q3, the low-level first fault detection signal Fault1 will directly enter the signal input terminal IO1 of the control unit 140. When the control unit 140 receives the low-level first fault detection signal Fault1, it will stop outputting drive signals to the lower bridge switch Q2, etc., to protect the motor controller.

[0050] When the upper bridge driver chip 122 finishes charging, for example, after 100ms, the control unit 140 outputs a high-level control signal to the NMOS transistor Q3 through the control signal output terminal IO2 to turn it on. At the same time, the upper bridge driver chip 122 outputs a high-level second fault detection signal Fault2. The motor controller enters the normal operation phase. During this period, if the upper bridge driver chip 122 detects a fault in the upper bridge switch Q1, it will output a low-level second fault detection signal Fault2. This low-level second fault detection signal Fault2 passes through the isolation chip 121, the first diode D1, and the NMOS transistor Q3 before entering the signal input terminal IO1 of the control unit 140. After receiving the low-level second fault detection signal Fault2, the control unit 140 will stop outputting drive signals to the upper bridge switch Q1 and the lower bridge switch Q2, etc., to protect the motor controller. Similarly, if the lower bridge driver chip 111 detects a fault in the lower bridge switch Q2, it will output a low-level first fault detection signal Fault1. This low-level first fault detection signal Fault1 enters the signal input terminal IO1 of the control unit 140. After receiving the low-level first fault detection signal Fault1, the control unit 140 will stop outputting drive signals to the upper bridge switch Q1 and the lower bridge switch Q2, etc., to protect the motor controller. Optionally, the control unit 140 can upload the low-level first fault detection signal Fault1 and the second fault detection signal Fault2 to the host computer to remind the user, which may include fault type reminders, etc.

[0051] In the above embodiments, fault signals of the upper and lower bridge switching transistors can be detected through a single I / O port. Meanwhile, because the upper bridge driver chip with bootstrap and negative voltage capacitors needs to establish voltage during the initial power-up phase, it continuously outputs fault signals during this period. Without the limitation of the switching unit, this fault signal would be detected after the control unit initialization, causing the motor controller to malfunction. However, by using the switching unit, this phase can be avoided. The limitation is released only after the upper bridge driver chip has finished charging, allowing for fault signal detection. This prevents the upper bridge driver unit from outputting fault detection signals during the charging phase, thus avoiding the controller malfunction. Furthermore, the structure is simple, and the program configuration is concise and efficient.

[0052] It should be noted that the above description only addresses the detection of fault signals for the upper and lower bridge switches of one bridge arm. In practical applications, it is not limited to one bridge arm. For example, a three-phase inverter bridge includes three bridge arms, each including an upper and lower bridge switch. In this case, an upper bridge drive unit can be set up for each upper bridge switch, and a lower bridge drive unit can be set up for each lower bridge switch. The second fault detection signal Fault2 corresponding to the three upper bridge switches is input in parallel to the switching unit 130, and the first fault detection signal Fault1 corresponding to the three lower bridge switches is input in parallel to the switching unit 130, as detailed below. Figure 3 As shown, the switching unit 130 can detect six fault detection signals through a single I / O port, effectively saving I / O resources. It also prevents the controller from malfunctioning due to the upper bridge drive unit outputting fault detection signals during the charging phase, simplifying software control and saving control unit resources. Furthermore, Figure 3 This is merely an illustrative description; simple modifications to the circuit structure, such as mirroring the circuit or replacing it with other switching transistors, are also within the scope of protection of this application. Furthermore, the first diode D1 serves an isolation function. For example, when a fault occurs in one arm of the three-phase inverter bridge, a low-level fault detection signal is output. Due to the presence of the first diode D1, the fault detection signals of other arms will not be pulled low.

[0053] In summary, the fault protection signal detection circuit according to the embodiments of the present invention drives the lower bridge switch to be turned on or off through the lower bridge drive unit, and outputs a first fault detection signal when a fault is detected in the lower bridge switch. It also drives the upper bridge switch to be turned on or off through the upper bridge drive unit, and outputs a second fault detection signal when a fault is detected in the upper bridge switch. Furthermore, during the stage where the lower bridge switch is turned on through the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, the circuit controls the switch unit to turn off the transmission of the second fault detection signal. Finally, when the bootstrap and negative voltage capacitors of the upper bridge drive unit have finished charging, the circuit controls the switch unit to turn on to simultaneously receive the first and second fault detection signals. This not only saves I / O resources but also avoids the situation where the controller malfunctions due to the upper bridge drive unit outputting a fault detection signal during the charging stage.

[0054] In some embodiments, a motor controller is also provided.

[0055] like Figure 4As shown, the motor controller 200 includes a three-phase inverter bridge 210 and the aforementioned fault protection signal detection circuit 100. The fault protection signal detection circuit 100 drives the lower bridge switch in the three-phase inverter bridge 210 to turn on or off via the lower bridge drive unit. When a fault is detected in the lower bridge switch, it outputs a first fault detection signal. It also drives the upper bridge switch in the three-phase inverter bridge 210 to turn on or off via the upper bridge drive unit. When a fault is detected in the upper bridge switch, it outputs a second fault detection signal. Furthermore, during the phase where the lower bridge switch is turned on via the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, the circuit controls the switch unit to turn off the transmission of the second fault detection signal. Finally, when the bootstrap and negative voltage capacitors of the upper bridge drive unit have finished charging, the circuit controls the switch unit to turn on to simultaneously receive the first and second fault detection signals.

[0056] According to the embodiments of the present invention, the motor controller, through the aforementioned fault protection signal detection circuit, can not only save IO resources, but also avoid the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction.

[0057] In some embodiments, a compressor is also provided. Figure 5 As shown, the compressor 300 includes a motor M and the aforementioned motor controller 200, which is used to drive the motor M to run.

[0058] In some embodiments, the compressor 300 can be an electric compressor including a drive unit and a compression unit. The drive unit in the electric compressor drives the compression unit to perform compression work. For example, the drive unit may include a motor M containing a rotor and a stator, and the aforementioned motor controller 200. The motor controller 200 drives the motor M to operate, thereby driving the compression unit to perform compression work. Additionally, in some embodiments, the electric compressor can be a low back pressure compressor, with the drive unit located in a low-pressure chamber communicating with the compressor's intake port, and the compression unit located in a high-pressure chamber communicating with the compressor's exhaust port. Furthermore, in some embodiments, the electric compressor can be a horizontal compressor, with the drive unit and compression unit arranged laterally, etc.

[0059] When the motor controller 200 drives the motor M to operate and drive the compression unit to perform compression work, the fault protection signal detection circuit in the motor controller 200 drives the lower bridge switch in the three-phase inverter bridge to turn on or off through the lower bridge drive unit. When a fault is detected in the lower bridge switch, it outputs a first fault detection signal. It also drives the upper bridge switch in the three-phase inverter bridge to turn on or off through the upper bridge drive unit. When a fault is detected in the upper bridge switch, it outputs a second fault detection signal. During the stage when the lower bridge switch is turned on through the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, the switch unit is controlled to turn off the transmission of the second fault detection signal. When the bootstrap and negative voltage capacitors of the upper bridge drive unit have finished charging, the switch unit is controlled to turn on to simultaneously receive the first fault detection signal and the second fault detection signal.

[0060] According to the compressor of the present invention, the aforementioned motor controller can not only save IO resources, but also avoid the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction and thus the compressor to malfunction.

[0061] In some embodiments, a vehicle is also provided. Figure 6 As shown, vehicle 400 includes the aforementioned compressor 300.

[0062] In embodiments of the present invention, vehicle 400 includes the compressor 300 described in any of the above embodiments. Vehicle 400 may be a new energy vehicle. In some embodiments, the new energy vehicle may be a pure electric vehicle with an electric motor as the main driving force. In other embodiments, the new energy vehicle may be a hybrid vehicle with both an internal combustion engine and an electric motor as the main driving force. Regarding the internal combustion engine and electric motor mentioned in the above embodiments that provide driving power for the new energy vehicle, the internal combustion engine may use gasoline, diesel, hydrogen, etc. as fuel, and the method of providing electrical energy to the electric motor may be a power battery, hydrogen fuel cell, etc., without special limitation. It should be noted that this is merely an exemplary description of the structure of new energy vehicles, etc., and is not intended to limit the scope of protection of the present invention.

[0063] According to the vehicle of the present invention, the aforementioned compressor not only saves IO resources, but also avoids the situation where the upper bridge drive unit outputs a fault detection signal during the charging phase, causing the controller to malfunction and thus the vehicle to malfunction.

[0064] In some embodiments, a fault protection signal detection method is also provided.

[0065] This method is applied to the aforementioned motor controller, such as... Figure 7 As shown, the method may include:

[0066] S101, when the motor controller is powered on, drives the lower bridge switch tube to conduct through the lower bridge drive unit to charge the bootstrap and negative voltage capacitor of the upper bridge drive unit, and controls the switch unit to turn off the transmission of the second fault detection signal.

[0067] S102, when the bootstrap and negative voltage capacitor of the upper bridge drive unit have completed charging, the control switch unit is turned on to simultaneously receive the first fault detection signal and the second fault detection signal.

[0068] It should be noted that other specific implementations of the fault protection signal detection method of the present invention can be found in the specific implementations of the fault protection signal detection circuit of the above embodiments of the present invention.

[0069] According to the fault protection signal detection method of the present invention, when the motor controller is powered on, the lower bridge drive unit drives the lower bridge switch to conduct, so as to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, and controls the switch unit to turn off the transmission of the second fault detection signal. When the bootstrap and negative voltage capacitors of the upper bridge drive unit have completed charging, the switch unit is controlled to conduct, so as to simultaneously receive the first fault detection signal and the second fault detection signal. This not only saves IO resources, but also avoids the situation where the upper bridge drive unit outputs a fault detection signal during the charging stage, causing the controller to malfunction.

[0070] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0071] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0072] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0073] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0074] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A fault protection signal detection circuit, characterized in that, include: The lower bridge drive unit is used to drive the lower bridge switch to turn on or off, and to output a first fault detection signal by detecting whether the lower bridge switch has failed. The upper bridge drive unit is used to drive the upper bridge switch to turn on or off, and to output a second fault detection signal by detecting whether the upper bridge switch has failed. A switching unit is used to turn off the transmission of the second fault detection signal during the phase when the lower bridge switch is turned on to charge the bootstrap and negative voltage capacitor of the upper bridge drive unit. The control unit is configured to drive the lower bridge switch to conduct through the lower bridge drive unit to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit, and control the switch unit to turn off the transmission of the second fault detection signal. When the bootstrap and negative voltage capacitors of the upper bridge drive unit have completed charging, the control unit is configured to conduct to simultaneously receive the first fault detection signal and the second fault detection signal. The switching unit includes any one of transistors, MOSFETs, silicon controlled rectifiers, and IGBTs; When the switching unit includes an NMOS transistor, the drain of the NMOS transistor is connected to the fault protection signal output terminal of the lower bridge drive unit, the source of the NMOS transistor is connected to the fault protection signal output terminal of the upper bridge drive unit, and the gate of the NMOS transistor is connected to the control signal output terminal of the control unit.

2. The circuit according to claim 1, characterized in that, The control unit is further configured to receive the first fault detection signal during the phase when the lower bridge switch is turned on to charge the bootstrap and negative voltage capacitors of the upper bridge drive unit.

3. The circuit according to claim 1, characterized in that, When the lower bridge drive unit detects a fault in the lower bridge switch, it drives the lower bridge switch to turn off. When the upper bridge drive unit detects a fault in the upper bridge switch, it drives the upper bridge switch to turn off. When the control unit determines that either the lower bridge switch or the upper bridge switch has failed based on the first fault detection signal and the second fault detection signal, it shuts down the drive signals output to the lower bridge drive unit and the upper bridge drive unit.

4. The circuit according to claim 1, characterized in that, The switching unit further includes: A first resistor is connected between the gate of the NMOS transistor and the control signal output terminal of the control unit. The second resistor is connected between the gate and source of the NMOS transistor.

5. The circuit according to claim 1, characterized in that, The switching unit further includes: The third resistor is connected between the drain of the NMOS transistor and the signal input terminal of the control unit; A first capacitor, one end of which is connected to the signal input terminal of the control unit, and the other end of which is grounded.

6. The circuit according to any one of claims 1-3, characterized in that, The upper bridge drive unit includes: An isolation chip, wherein the first input pin of the isolation chip is connected to the upper bridge drive signal output terminal of the control unit; The first diode has its anode serving as the fault protection signal output terminal of the upper bridge drive unit, and its cathode connected to the first output pin of the isolation chip. The upper bridge driver chip has its input pin connected to the second output pin of the isolation chip, its output pin connected to the second input pin of the isolation chip, and connected to a first preset power supply through a first pull-up resistor. The drive output pin of the upper bridge driver chip is connected to the control terminal of the upper bridge switch.

7. The circuit according to any one of claims 1-3, characterized in that, The lower bridge drive unit includes: The lower bridge driver chip has its output pin connected to a second preset power supply via a second pull-up resistor and serves as the fault protection signal output terminal of the lower bridge driver unit. The input pin of the lower bridge driver chip is connected to the lower bridge drive signal output terminal of the control unit, and the drive output pin of the lower bridge driver chip is connected to the control terminal of the lower bridge switch.

8. A motor controller, characterized in that, include: Three-phase inverter bridge; The fault protection signal detection circuit according to any one of claims 1-7.

9. A compressor, characterized in that, include: Electric motor; According to claim 8, the motor controller is used to drive the motor to operate.

10. A vehicle, characterized in that, Includes the compressor according to claim 9.

11. A fault protection signal detection method, characterized in that, Applied to the motor controller according to claim 8, the method includes: When the motor controller is powered on, the lower bridge drive unit drives the lower bridge switch to conduct, so as to charge the bootstrap and negative voltage capacitor of the upper bridge drive unit, and controls the switch unit to turn off the transmission of the second fault detection signal. When the bootstrap and negative voltage capacitor of the upper bridge drive unit complete charging, the switching unit is controlled to turn on so as to simultaneously receive the first fault detection signal and the second fault detection signal.

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