Privacy panel, mother panel, and method of manufacturing privacy panel

Abstract

The present application discloses a kind of privacy panels, privacy panels have active area and the peripheral zone being set outside active area, and privacy panel includes first substrate, second substrate, first transparent conductive layer, second transparent conductive layer and privacy medium layer.Second substrate is oppositely arranged with first substrate.First transparent conductive layer and second transparent conductive layer are arranged between first substrate and second substrate, and are directly contacted with first substrate and second substrate respectively, wherein first transparent conductive layer includes first privacy electrode and first alignment mark, second transparent conductive layer includes second privacy electrode, first privacy electrode and second privacy electrode are arranged in active area, and first alignment mark is arranged in peripheral zone.Privacy medium layer is arranged between first privacy electrode and second privacy electrode.

Description

Technical Field

[0001] This invention relates to a privacy panel, a motherboard, and a method for manufacturing a privacy panel, and particularly to a method for manufacturing a privacy panel, a motherboard, and a privacy panel that can reduce manufacturing costs and shorten manufacturing time. Background Technology

[0002] Electronic devices are indispensable products today, and those with display functions, such as screens, laptops, smartphones, wearable devices, smartwatches, and automotive displays, are widely used in many places. In recent years, electronic devices with display functions have integrated privacy features, making it difficult for users to view the information displayed on the device outside its designed viewing area, thus enhancing privacy and security. For example, privacy panels can be incorporated into electronic devices to provide privacy functionality. In recent years, the industry has focused on adjusting the structure and manufacturing process of privacy panels to reduce costs and / or shorten manufacturing time. Summary of the Invention

[0003] The purpose of this invention is to provide a privacy panel, a motherboard, and a method for manufacturing the privacy panel, which uses alignment marks made of transparent conductive material for alignment, thereby reducing manufacturing costs and shortening manufacturing time.

[0004] To address the aforementioned technical problems, the present invention provides a privacy panel. The privacy panel has an active area and a peripheral area disposed outside the active area. The privacy panel includes a first substrate, a second substrate, a first transparent conductive layer, a second transparent conductive layer, and a privacy dielectric layer. The second substrate is disposed opposite to the first substrate. The first transparent conductive layer is disposed between the first substrate and the second substrate and directly contacts the first substrate. The first transparent conductive layer includes a first privacy electrode and a first alignment mark. The first privacy electrode is disposed within the active area, and the first alignment mark is disposed in the peripheral area. The second transparent conductive layer is disposed between the first substrate and the second substrate and directly contacts the second substrate. The second transparent conductive layer includes a second privacy electrode, which is disposed within the active area. The privacy dielectric layer is disposed between the first privacy electrode and the second privacy electrode.

[0005] To solve the above-mentioned technical problems, the present invention provides a motherboard that includes a plurality of the above-mentioned privacy panels.

[0006] To address the aforementioned technical problems, the present invention provides a method for manufacturing a privacy panel, comprising: forming a first transparent conductive film on a first large plate; patterning the first transparent conductive film to form a first transparent conductive layer, wherein the first transparent conductive layer includes a first privacy electrode and an alignment mark, the first privacy electrode being located in a privacy panel area of ​​the first large plate, and the alignment mark being located in a non-privacy panel area or a privacy panel area of ​​the first large plate; forming a second transparent conductive film on a second large plate; patterning the second transparent conductive film to form a second transparent conductive layer, wherein the second transparent conductive layer includes a second privacy electrode, and the second privacy electrode being located in a privacy panel area of ​​the second large plate; and assembling the first large plate and the second large plate to form a mother plate, wherein a privacy dielectric layer is disposed between the first privacy electrode and the second privacy electrode.

[0007] The present invention uses two transparent conductive layers instead of opaque layers as the first film layers of two substrates, and at least one of the two transparent conductive layers includes an alignment mark. Therefore, compared with conventional privacy panels, the privacy panel of the present invention has fewer film layers, thereby reducing the number of patterning processes and thus reducing manufacturing costs. Attached Figure Description

[0008] Figure 1 The diagram shown is a top view of the privacy panel according to the first embodiment of the present invention.

[0009] Figure 2 The following is along Figure 1 A cross-sectional diagram of the A-A' section.

[0010] Figure 3 The diagram shown is a cross-sectional view of the privacy display device of the first embodiment of the present invention in the first state and the second state.

[0011] Figure 4 The diagram shows the relationship between the thickness of the transparent conductive layer, the light transmittance of the transparent conductive layer, and the light reflectance of the transparent conductive layer according to an embodiment of the present invention.

[0012] Figure 5 The diagram shows the relationship between the thickness of the transparent conductive layer, the a* of the transmitted light from the transparent conductive layer, and the a* of the reflected light from the transparent conductive layer according to an embodiment of the present invention.

[0013] Figure 6 The diagram shows the relationship between the thickness of the transparent conductive layer, the transmitted light b* of the transparent conductive layer, and the reflected light b* of the transparent conductive layer according to an embodiment of the present invention.

[0014] Figure 7 The diagram shows the relationship between the thickness of the transparent conductive layer and the sheet resistance of the transparent conductive layer according to an embodiment of the present invention.

[0015] Figure 8The diagram shown is a schematic of the device capturing the alignment mark of the present invention.

[0016] Figures 9 to 11 This is a schematic diagram of the structure of the privacy panel manufacturing method of the first embodiment of the present invention at different stages.

[0017] Figure 12 The diagram shown is a cross-sectional view of the privacy panel according to the second embodiment of the present invention.

[0018] Figure 13 The diagram shown is a top view of the transparent conductive layer and the frame adhesive layer of the privacy panel according to the third embodiment of the present invention.

[0019] Figure 14 The diagram shown is a top view of the privacy panel according to the third embodiment of the present invention.

[0020] Figure 15 The following is along Figure 14 A cross-sectional diagram of the B-B' section.

[0021] Figure 16 The following is along Figure 14 A cross-sectional diagram of the C-C' section.

[0022] Explanation of reference numerals in the attached drawings: 10 - Privacy display device; 100, 200, 300 - Privacy panel; 100m - Mother board; 110, 150 - Substrate; 110M, 150M - Large board; 120, 140 - Transparent conductive layer; 122, 142 - Privacy electrode; 122a - First part; 122b - Second part; 130 - Privacy dielectric layer; 162, 164 - Alignment film; 170 - Spacer; 172 - Main spacer; 174 - Sub-spacer; 272 - Spherical spacer; AM - Alignment mark; AM1 - First alignment mark; AM2 - Second alignment mark; AM3 - Third alignment mark; AM4 - Fourth alignment mark; AR - Active area; BL - Backlight module; CE1 - First connecting electrode; CE2 - Second connecting electrode; CP - Conductive particle; DP - Display panel; NH - Notch; NR - Non-privacy panel area; P1 P2 - Sealing pad; PR - Peripheral area; R - Privacy panel area; S1 - First electrical signal; S2 - Second electrical signal; SL - Frame adhesive layer; VA1 - First viewing angle range; VA2 - Second viewing angle range; X, Y, Z - Directions. Detailed Implementation

[0023] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, along with a detailed description of the invention's structure and desired effects in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are simplified schematic diagrams; therefore, only elements and combinations related to the present invention are shown to provide a clearer description of the basic structure or implementation method of the present invention, while the actual elements and layout may be more complex. Furthermore, for ease of explanation, the elements shown in the various drawings of the present invention are not drawn to scale according to the actual number, shape, and size; the detailed scale can be adjusted according to design requirements.

[0024] In the following description and claims, the terms "comprising," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Thus, when the terms "comprising," "containing," and / or "having" are used in the description of this invention, they specify the presence of the corresponding features, areas, steps, operations, and / or components, but do not exclude the presence of one or more of the corresponding features, areas, steps, operations, and / or components.

[0025] In the following description and claims, when “A1 component is formed by B1”, it means that the formation of A1 component includes or uses B1, and the formation of A1 component does not exclude the presence or use of one or more other features, areas, steps, operations and / or components.

[0026] In the following description and claims, the term "horizontal direction" refers to a direction parallel to a horizontal plane; the term "horizontal plane" refers to a surface parallel to directions X and Y in the drawings; and the term "vertical direction" refers to a direction parallel to direction Z in the drawings, wherein directions X, Y, and Z are perpendicular to each other. In the description and claims, the term "top view" refers to the result of viewing along the vertical direction, and the term "section" refers to the result of viewing a structure cut along the vertical direction from a horizontal perspective.

[0027] In the specification and claims, the term "parallel" means that the angle between two components may be less than or equal to a specific angle, such as 5 degrees, 3 degrees or 1 degree.

[0028] In the following description and claims, the term “overlap” means that two components overlap in the direction Z, and unless otherwise specified, the term “overlap” includes partial or complete overlap, wherein the two components may be in direct contact with each other or there may be a spacer between the two components.

[0029] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0030] It should be understood that the features described below can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0031] The privacy panel of this invention can be used in conjunction with a display panel. The privacy panel can be used to adjust the light emission path or the light input path of the display panel to form a display device with privacy protection functionality. The formed display device can be any suitable type of display. For example, the display panel of the display device can be a non-self-emissive display panel or a self-emissive display panel. Examples of non-self-emissive display panels include liquid crystal displays (LCDs), electrophoretic displays, or other suitable display panels. Examples of self-emissive display panels include light-emitting diodes (LEDs), such as organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (organicLEDs), mini LEDs, micro-LEDs, quantum dot LEDs (QLEDs, QDLEDs), or other suitable light-emitting diodes, but are not limited thereto. The shape of the privacy panel can be polygonal (e.g., rectangular), has curved edges (e.g., circular, elliptical), or other suitable shapes, but is not limited thereto.

[0032] Please refer to Figures 1 to 3 , Figure 1 The image shown is a top view of the privacy panel according to the first embodiment of the present invention. Figure 2 The following is along Figure 1 A cross-sectional diagram of the A-A' section. Figure 3 The diagram shown is a cross-sectional view of the privacy display device according to the first embodiment of the present invention in a first state and a second state. Figure 1As shown, the privacy panel 100 may have an active area AR and a peripheral area PR disposed on at least one outer side of the active area AR. The active area AR may have a privacy function, and elements assisting the active area AR (e.g., pads and / or connecting electrodes for electrically connecting the drive circuit) and a frame adhesive layer for bonding the two substrates of the privacy panel 100 may be disposed within the peripheral area PR. For example, the peripheral area PR may surround the active area AR, but is not limited thereto.

[0033] The privacy panel 100 may include a substrate 110 and a substrate 150, wherein the two substrates 110 and 150 are disposed opposite to each other. The materials of the two substrates 110 and 150 may be the same or different, and the two substrates 110 and 150 may each be a rigid substrate or a flexible substrate, and may include, depending on their type, materials such as glass, plastic, quartz, sapphire, polyimide (PI), polyethylene terephthalate (PET), other suitable materials or combinations thereof, but are not limited thereto. In addition, the shape and size of the two substrates 110 and 150 may be designed as needed. For example, in FIG. 1, the size of substrate 150 may be larger than the size of substrate 110, and pads (not shown) for electrically connecting the drive circuit may be disposed in the area of ​​substrate 150 not covered by substrate 110.

[0034] It should be noted that substrates 110 and 150 may be the upper substrate and the lower substrate, or the lower substrate and the upper substrate, respectively. Alternatively, the substrates may be referred to as the first substrate and the second substrate, or the second substrate and the first substrate, respectively. Furthermore, the normal directions of substrates 110 and 150 may be parallel to direction Z.

[0035] like Figure 2 As shown, the privacy panel 100 may include a privacy dielectric layer 130 disposed between two substrates 110 and 150. In this invention, the privacy dielectric layer 130 may include any suitable dielectric material. In this embodiment, the dielectric material contained in the privacy dielectric layer 130 may be adjusted in any suitable manner to achieve a privacy effect for the privacy panel 100. In some embodiments, the privacy state of the privacy dielectric layer 130 may be controlled by an electric field and / or an electrical signal. For example, the privacy dielectric layer 130 may include a liquid crystal material, but is not limited thereto.

[0036] In this invention, the privacy electrodes used to control the privacy media layer 130 can be designed according to requirements. For example, multiple privacy electrodes used to control the privacy media layer 130 can be disposed on opposite sides of the privacy media layer 130 (i.e., the privacy media layer 130 is disposed between two opposite privacy electrodes). In the following description, the privacy electrodes used to control the privacy media layer 130 are illustrated by the example of being disposed on opposite sides of the privacy media layer 130.

[0037] exist Figure 1 and Figure 2 In this configuration, the privacy panel 100 may include a transparent conductive layer 120 and another transparent conductive layer 140, wherein the two transparent conductive layers 120 and 140 are disposed between two substrates 110 and 150. For example, a privacy dielectric layer 130 may be disposed between the two transparent conductive layers 120 and 140, but is not limited thereto. Figure 2 In this configuration, transparent conductive layer 120 can directly contact substrate 110, and transparent conductive layer 140 can directly contact substrate 150. That is, transparent conductive layer 120 is the first film layer disposed on substrate 110, and transparent conductive layer 140 is the first film layer disposed on substrate 150. Therefore, all components contained in transparent conductive layer 120 can directly contact substrate 110, and all components contained in transparent conductive layer 140 can directly contact substrate 150. It should be noted that transparent conductive layers 120 and 140 can be referred to as the first transparent conductive layer and the second transparent conductive layer, or the second transparent conductive layer and the first transparent conductive layer, respectively.

[0038] In this invention, the materials of the transparent conductive layers 120 and 140 may include indium tin oxide (ITO), indium zinc oxide (IZO), other suitable transparent conductive materials, or combinations thereof. For example, the transparent conductive layers 120 and 140 of this embodiment may include indium tin oxide, but are not limited thereto.

[0039] like Figure 2 As shown, the transparent conductive layer 120 may include at least one privacy electrode 122 disposed in the active area AR, and the transparent conductive layer 140 may include at least one privacy electrode 142 disposed in the active area AR, wherein the privacy electrodes 122 and 142 are used to control the privacy state of the privacy medium layer 130 in the active area AR.

[0040] In this invention, the number of privacy electrodes 122 and 142 can be designed according to requirements. For example, in Figure 1 and Figure 2In the privacy panel 100, the number of privacy electrodes 122 and privacy electrodes 142 can both be one. At least a portion of either privacy electrode 122 or 142 can be disposed in the entire active area AR of the privacy panel 100, meaning the entire active area AR completely overlaps with the privacy electrodes 122 and 142. This allows the privacy electrodes 122 and 142 to control the state of the privacy medium layer 130 in the entire active area AR, thereby controlling whether the privacy panel 100 is in a privacy-protected or non-privacy-protected state, but this is not a limitation. For example (not shown), the number of privacy electrodes 122 and / or the number of privacy electrodes 142 can be greater than one, allowing the privacy electrodes 122 and 142 to control the state of the corresponding portion of the privacy medium layer 130, enabling the privacy panel 100 to provide zoned privacy protection, but this is not a limitation.

[0041] The privacy electrodes 122 and 142 can generate a corresponding electric field based on the received electrical signal, and the material in the privacy medium layer 130 (e.g., liquid crystal molecules) will change accordingly (e.g., rotate) according to the electric field to adjust the state of the privacy medium layer 130. In this embodiment, the privacy medium layer 130 can switch between a first state (or privacy-on state) and a second state (or privacy-off state). In the first state, the privacy panel 100 has a privacy function (i.e., the privacy panel 100 is in privacy mode), and in the second state, the privacy panel 100 does not have a privacy function (i.e., the privacy panel 100 is in sharing mode). When the privacy medium layer 130 is in the first state, the light entering the privacy medium layer 130 can be adjusted and / or filtered so that the path of the light emitted from the privacy medium layer 130 is limited to a specific angle and / or a specific range, but is not limited thereto. For example, when the privacy function is active, if the angle between the user's line of sight and the normal direction (e.g., direction Z) of the light-emitting surface of the display device equipped with the privacy panel 100 is greater than a certain angle, the user will not be able to see the display screen of the display device. When the privacy media layer 130 is in the second state, the privacy function is turned off, so that the range of the path of the light emitted from the privacy media layer 130 is greater than the range in the first state, that is, the viewing angle range in the second state is greater than the viewing angle range in the first state.

[0042] like Figure 3As shown, the privacy display device 10 includes a display panel DP, a privacy panel 100, and a backlight module BL, wherein the privacy panel 100 is used to adjust the light path of the light emitted from the display panel DP. In this embodiment, the display panel DP is located between the privacy panel 100 and the backlight module BL, but this is not a limitation. In other embodiments, the privacy panel 100 may be located between the display panel DP and the backlight module BL to adjust the light path of the light incident on the display panel DP. Furthermore, in embodiments where the display panel DP is a self-emissive display panel, the privacy display device 10 may not include the backlight module BL, and the privacy panel 100 may be located on the light-emitting side of the display panel DP. When the privacy panel 100 is in the second state, the user can view the screen displayed by the privacy display device 10 within the first viewing angle range VA1 (i.e., the privacy display device 10 has the first viewing angle range VA1). When the privacy panel 100 is in the first state, the user can view the screen displayed by the privacy display device 10 within the second viewing angle range VA2, wherein the first viewing angle range VA1 is greater than the second viewing angle range VA2 (i.e., the privacy display device 10 has the second viewing angle range VA2).

[0043] In the privacy display device 10, the display panel DP includes multiple gate lines, multiple data lines, and multiple pixels. Each pixel is electrically connected to its corresponding gate line and data line, and each pixel may include, for example, a thin-film transistor and a pixel electrode. The multiple gate lines are electrically connected to a gate driving circuit, and the multiple data lines are electrically connected to a source driving circuit. The source driving circuit transmits image signals to each pixel to display the corresponding image. The privacy panel 100 in the privacy display device 10 is used to adjust the light path of the incident or emitted light from the display panel DP to adjust the viewing angle range of the privacy display device 10. Figure 1 and Figure 2 In one embodiment, at least a portion of either the privacy electrode 122 or 142 may be disposed in the entire active area AR of the privacy panel 100, that is, in the privacy display device 10, either the privacy electrode 122 or 142 overlaps the area of ​​all pixels of the display panel DP. In an embodiment where the number of privacy electrodes 122 and 142 of the privacy panel 100 is greater than one to perform zoned privacy, either the privacy electrode 122 or 142 may overlap the area of ​​multiple pixels of the display panel DP.

[0044] like Figure 2As shown, the privacy panel 100 may include two alignment films 162 and 164 for aligning the privacy medium layer 130. Alignment film 162 is disposed between the transparent conductive layer 120 (privacy electrode 122) and the privacy medium layer 130, and alignment film 164 is disposed between the transparent conductive layer 140 (privacy electrode 142) and the privacy medium layer 130. In this embodiment, alignment films 162 and 164 may be disposed throughout the active area AR of the privacy panel 100. Alignment films 162 and 164 may include any suitable material for alignment; for example, alignment films 162 and 164 may include polyimide (PI), but are not limited thereto.

[0045] like Figure 2 As shown, the privacy panel 100 may include a plurality of spacers 170 disposed between two substrates 110 and 150, wherein the spacers 170 are used to separate the two substrates 110 and 150 and create a gap between the two substrates 110 and 150 so that the privacy media layer 130 can be disposed in the gap between the two substrates 110 and 150. For example, in Figure 2 In this configuration, the spacer 170 may be disposed between the two transparent conductive layers 120 and 140 (the two privacy electrodes 122 and 142), but is not limited thereto. For example, the spacer 170 may be disposed in the active region AR and / or the peripheral region PR, but is not limited thereto. Furthermore, the spacer 170 may comprise any suitable insulating material. For example, the spacer 170 may comprise photoresist, resin, other suitable insulating materials, or combinations thereof, but is not limited thereto. For example, in... Figure 2 In this embodiment, the spacer 170 may be formed on the substrate 110 first, and after the two substrates 110 and 150 are assembled, the spacer 170 may exist between the two substrates 110 and 150, but is not limited thereto. In some embodiments, the spacer 170 may be formed on the substrate 150 first, and after the two substrates 110 and 150 are assembled, the spacer 170 may exist between the two substrates 110 and 150.

[0046] exist Figure 2 In this embodiment, the spacer 170 may include a main spacer 172 and a sub-spacer 174, wherein the height of the main spacer 172 is greater than the height of the sub-spacer 174. In other embodiments, the spacer 170 may include the main spacer 172 but not the sub-spacer 174. In this embodiment, the height of the main spacer 172 is equal to or approximately equal to the gap between the two substrates 110 and 150, such that the main spacer 172 can provide support between the two substrates 110 and 150 and maintain the gap between the two substrates 110 and 150. In this embodiment, a gap may exist between the substrate 150 and the sub-spacer 174 to allow for deformation space when the substrate 110 and / or the substrate 150 is subjected to force.

[0047] In this embodiment, the privacy panel 100 may further include an adhesive layer (not shown) disposed and adhered between the two substrates 110 and 150 to assemble the two substrates 110 and 150, wherein the adhesive layer may be disposed within the peripheral area PR. For example, the adhesive layer may surround the active area AR, but is not limited thereto. Additionally, the adhesive layer may include any suitable adhesive material. For example, the adhesive layer may include silicone material, epoxy material, other suitable adhesive materials, or combinations thereof, but is not limited thereto. In this embodiment, the adhesive layer may or may not include conductive particles.

[0048] In this invention, the privacy panel 100 may also include any suitable film layer, element, and structure as needed. In some embodiments, the privacy panel 100 may also include optical film layers, such as anti-reflective film, brightness enhancement film, polarizer, or other suitable optical film layers, which may be disposed in suitable positions according to their respective needs. For example, the optical film layer (e.g., polarizer) may be disposed on the side of the substrate 110 opposite to the privacy medium layer 130 and / or on the side of the substrate 150 opposite to the privacy medium layer 130, but is not limited thereto.

[0049] In this invention, the peripheral area PR may be provided with alignment marks AM as alignment references when manufacturing the privacy panel 100. For example, the alignment marks AM may be alignment marks for film layer attachment (e.g., alignment marks for attaching optical films such as anti-reflective films, brightness enhancement films, and polarizers), alignment marks for coupling chips or circuit boards (e.g., alignment marks when coupling chips or flexible circuit boards to pads located on the substrate 150), alignment marks for forming films or structures (e.g., alignment marks for forming alignment films 162, 164, spacers 170, frame adhesive layers, etc.), alignment marks for patterned films, alignment marks for cutting, alignment marks for assembling two substrates 110, 150, other suitable alignment marks, or combinations thereof. The manufacturing method and process of the privacy panel 100 will be described in detail later.

[0050] In this invention, the alignment mark AM can be formed by transparent conductive layers 120 and 140 (i.e., the alignment mark AM can be included within the transparent conductive layers 120 and 140). Figure 1 and Figure 2 As shown, the transparent conductive layer 120 may include a first alignment mark AM1 disposed in the peripheral region PR and in direct contact with the substrate 110, and / or the transparent conductive layer 140 may include a second alignment mark AM2 disposed in the peripheral region PR and in direct contact with the substrate 150, wherein the number of the first alignment mark AM1 and the number of the second alignment mark AM2 can be designed according to requirements. Figure 1In this configuration, the first alignment mark AM1 may be adjacent to a corner of substrate 110, and the second alignment mark AM2 may be adjacent to a corner of substrate 150, but is not limited thereto. For example, in Figure 1 In this context, the number of first alignment markers AM1 and the number of second alignment markers AM2 can both be four, but the number of first alignment markers AM1 and second alignment markers AM2 is not limited to this. Two first alignment markers AM1 (e.g., located in...) Figure 1 The two first alignment marks AM1 on the upper part of the middle substrate 110 can overlap (e.g., completely overlap and / or completely coincide) in the Z direction with the two second alignment marks AM2 (e.g., located at...). Figure 1 The two second alignment marks AM2 on the upper part of the middle substrate 150, and the other two first alignment marks AM1 (e.g., located at...) Figure 1 The two first alignment marks AM1 at the lower part of the middle substrate 110 may not overlap with the second alignment mark AM2 in the Z direction, and the other two second alignment marks AM2 (e.g., located at...) Figure 1 The two second alignment marks (AM2) at the lower part of the middle substrate 150 may not overlap with the first alignment mark AM1 in the Z direction, but the positions of the first alignment mark AM1 and the second alignment mark AM2 are not limited thereto. In some embodiments, the first alignment mark AM1 may not overlap with the second alignment mark AM2 in the Z direction. Furthermore, in some embodiments, the privacy panel 100 may include only the first alignment mark AM1 but not the second alignment mark AM2, or the privacy panel 100 may include only the second alignment mark AM2 but not the first alignment mark AM1.

[0051] In this invention, the shape of the alignment mark AM can be polygonal (e.g., rectangle, cross, square, L-shape), shape with curved edges (e.g., circle, ellipse, concentric circles), or other suitable shape. This invention does not limit the shape of the alignment mark AM. For example, Figure 1 The first alignment mark AM1 and the second alignment mark AM2 shown are exemplified by rectangles, but are not limited to this. The shapes of the first alignment mark AM1 and the second alignment mark AM2 may be the same or different from each other.

[0052] For example, Figure 1The first alignment mark AM1 and the second alignment mark AM2 shown may be alignment marks for film layer attachment (e.g., alignment marks for attaching optical films such as anti-reflective films, brightness enhancement films, and polarizers), alignment marks for coupling chips or circuit boards (e.g., alignment marks when coupling chips or flexible circuit boards to pads located on substrate 150), alignment marks for forming films or structures (e.g., alignment marks for forming alignment films 162, 164, spacers 170, frame adhesive layers, etc.), alignment marks for patterned films, cut alignment marks, other suitable alignment marks, or combinations thereof, and may selectively be alignment marks for assembling two substrates 110, 150, but are not limited thereto.

[0053] For example, the first alignment mark AM1 and the second alignment mark AM2 can be alignment marks for attaching polarizers. In the process of attaching polarizers, the first alignment mark AM1 can be aligned to attach a polarizer on the side of the substrate 110 opposite to the privacy shield layer 130, and the second alignment mark AM2 can be aligned to attach another polarizer on the side of the substrate 150 opposite to the privacy shield layer 130. Alternatively, the second alignment mark AM2 can be an alignment mark for coupling a flexible circuit board. In the process of coupling a flexible circuit board, the second alignment mark AM2 can be aligned to couple the flexible circuit board to the pads disposed on the substrate 150.

[0054] In this invention, based on the principles of thin-film optics, the thickness design of the transparent conductive layers 120 and 140 (alignment markers AM) ensures that the alignment markers AM possess the desired optical properties. The equipment used in the manufacturing process can read the alignment markers AM due to their optical properties, allowing the equipment to perform alignment using the alignment markers AM formed by the transparent conductive layers 120 and 140. In this embodiment, the thickness design of the transparent conductive layers 120 and 140 (alignment markers AM) ensures that the transmitted light passing through the alignment markers AM has the desired color, and / or the reflected light reflected by the alignment markers AM has the desired color. This allows the equipment used in the manufacturing process to read the alignment markers AM using the transmitted light and / or reflected light, and then perform alignment using the alignment markers AM formed by the transparent conductive layers 120 and 140. For example, when the transmitted light passing through the alignment mark AM has a color that can be recognized by the alignment mark recognition module of the device and / or the reflected light reflected by the alignment mark AM has a color that can be recognized by the alignment mark recognition module of the device, the equipment used in the manufacturing process can detect the black or gray alignment mark AM based on the transmitted light and / or reflected light, so that the equipment used in the manufacturing process can perform alignment through the alignment mark AM formed by the transparent conductive layers 120 and 140, but is not limited thereto.

[0055] When the equipment used in the manufacturing process detects (reads) the position of the alignment mark AM using transmitted light that passes through it, the light emitter and light receiver of the equipment can be located on opposite sides of the alignment mark AM. When the equipment used in the manufacturing process detects (reads) the position of the alignment mark AM using reflected light reflected from it, the light emitter and light receiver of the equipment can be located on the same side of the alignment mark AM. However, the configuration of the light emitter and light receiver of the alignment mark identification module of the equipment is not limited to this. In some embodiments, the equipment can detect (read) the position of the alignment mark AM simultaneously using both transmitted light that passes through it and reflected light reflected from it.

[0056] It should be noted that, since the thickness of the transparent conductive layers 120 and 140 (alignment mark AM) is designed based on thin-film optics principles, the thickness of the transparent conductive layers 120 and 140 can be less than or equal to... (Angle, 10-10 meters (m)), but not limited to this. Furthermore, the thickness of the transparent conductive layers 120 and 140 is less than or equal to... This also avoids the increased difficulty and cost of the patterned transparent conductive layers 120 and 140.

[0057] The design of the thickness of the transparent conductive layers 120 and 140 (alignment mark AM) will be described in detail below, but the thickness of the transparent conductive layers 120 and 140 (alignment mark AM) of the present invention is not limited to the range described below.

[0058] Please refer to Figures 4 to 8 , Figure 4 The diagram shown illustrates the relationship between the thickness of the transparent conductive layer, the light transmittance of the transparent conductive layer, and the light reflectance of the transparent conductive layer according to an embodiment of the present invention. Figure 5 The diagram shown illustrates the relationship between the thickness of the transparent conductive layer, the transmitted light a* of the transparent conductive layer, and the reflected light a* of the transparent conductive layer according to an embodiment of the present invention. Figure 6 The diagram shown illustrates the relationship between the thickness of the transparent conductive layer, the transmitted light b*, and the reflected light b* of the transparent conductive layer according to an embodiment of the present invention. Figure 7 The diagram shown illustrates the relationship between the thickness of the transparent conductive layer and the sheet resistance of the transparent conductive layer according to an embodiment of the present invention. Figure 8 The diagram shown is a schematic of the device capturing the alignment mark of the present invention. Figures 4 to 7The optical properties and sheet resistance values ​​of the transparent conductive layer shown are illustrated using a transparent conductive layer formed of indium tin oxide as an example, but the materials, optical properties, and sheet resistance values ​​of the transparent conductive layer of the present invention are not limited thereto. It should be noted that, according to the CIE L*a*b* color model, a*>0 indicates a color bias towards red, a*<0 indicates a color bias towards green, b*>0 indicates a color bias towards yellow, and b*<0 indicates a color bias towards blue.

[0059] like Figure 4 As shown, the light transmittance and light reflectance of the transparent conductive layers 120 and 140 change accordingly with variations in their thickness. For example (e.g.) Figure 4 As shown), when the thickness of the transparent conductive layer is greater than and less than (Right now, <Thickness< ), and n R When the value is 0, 1, 2, or 3, the light transmittance of the transparent conductive layer can be less than the light reflectance of the transparent conductive layer; when the thickness of the transparent conductive layer is greater than... and less than (Right now, <Thickness< ), and n T When the value is 0, 1, or 2, the light transmittance of the transparent conductive layer can be greater than the light reflectance of the transparent conductive layer, but this is not a limitation.

[0060] like Figure 5 As shown, according to the CIE L*a*b* color model, the a* of the transmitted light passing through the transparent conductive layers 120 and 140 (alignment mark AM) and the a* of the reflected light reflected by the transparent conductive layers 120 and 140 (alignment mark AM) will change accordingly based on the thickness of the transparent conductive layers 120 and 140 (alignment mark AM). For example (e.g.) Figure 5 As shown), when the thickness of the transparent conductive layer (alignment marker AM) is greater than and less than (Right now, <Thickness< If n1 is 0, 1, 2, or 3, then according to the CIE L*a*b* color model, the a* of the transmitted light passing through the transparent conductive layer (alignment mark AM) is greater than 0, and the a* of the reflected light reflected by the transparent conductive layer (alignment mark AM) is less than 0, but this is not a limitation. For example (e.g.) Figure 5 As shown), when the thickness of the transparent conductive layer (alignment marker AM) is greater than and less than (Right now, <Thickness< If n2 is 0, 1, 2 or 3, then according to the CIE L*a*b* color model, the a* of the transmitted light that passes through the transparent conductive layer (alignment mark AM) is less than 0, and the a* of the reflected light that is reflected by the transparent conductive layer (alignment mark AM) is greater than 0, but this is not a limitation.

[0061] like Figure 6 As shown, according to the CIE L*a*b* color model, the b* of the transmitted light passing through the transparent conductive layers 120 and 140 (alignment mark AM) and the b* of the reflected light reflected by the transparent conductive layers 120 and 140 (alignment mark AM) will change accordingly based on the thickness of the transparent conductive layers 120 and 140 (alignment mark AM). For example (e.g.) Figure 6 As shown), when the thickness of the transparent conductive layer (alignment marker AM) is greater than and less than (Right now, <Thickness< If n3 is 0, 1, 2, 3, or 4, then according to the CIE L*a*b* color model, the b* of the transmitted light passing through the transparent conductive layer (alignment mark AM) is greater than 0, and the b* of the reflected light reflected by the transparent conductive layer (alignment mark AM) is less than 0, but this is not a limitation. For example (e.g.) Figure 6 As shown), when the thickness of the transparent conductive layer (alignment marker AM) is greater than and less than (Right now, <Thickness< If n4 is 0, 1, 2 or 3, then according to the CIE L*a*b* color model, the b* of the transmitted light that passes through the transparent conductive layer (alignment mark AM) is less than 0, and the b* of the reflected light reflected by the transparent conductive layer (alignment mark AM) is greater than 0, but not limited to this.

[0062] according to Figure 4 , Figure 5 and Figure 6 The relationship between the thickness of the aforementioned transparent conductive layer and its light transmittance, light reflectance, and light color is established. Based on the method of light detection used in the manufacturing process and the readout rate for light of various intensities and colors, the thickness of the transparent conductive layers 120 and 140 can be designed according to the intensity and color requirements of the light. In some embodiments, the device has a high readout rate for the color of transmitted light passing through the transparent conductive layers 120 and 140 (alignment mark AM) or the color of reflected light reflected by the transparent conductive layers 120 and 140 (alignment mark AM). For example, such as Figure 5 and Figure 6 As shown, the thickness of the transparent conductive layer (alignment marker AM) can be greater than or equal to... And can be less than or equal to Furthermore, n5 can be 0, 1, 2, 3, 4, or 5, such that most devices that detect (read) the position of the alignment mark AM by transmitting light that passes through the alignment mark AM, most devices that detect (read) the position of the alignment mark AM by reflecting light that is reflected by the alignment mark AM, and most devices that detect (read) the position of the alignment mark AM by both reflecting light that is reflected by the alignment mark AM and transmitting light that passes through the alignment mark AM can all detect (read) the position of the alignment mark AM (e.g., the alignment mark AM detected by the device is a gray pattern). In other words, the alignment mark AM of the present invention can be applied to various devices in each process step of manufacturing the privacy panel 100 (e.g., devices that detect the alignment mark AM by transmitting light, devices that detect the alignment mark AM by reflecting light, and devices that detect the alignment mark AM by both transmitting light and reflecting light), but are not limited thereto.

[0063] like Figure 8 As shown, in this invention, based on Figures 4 to 7 By selecting a preferred thickness of the transparent conductive layer, the device can successfully identify the alignment marks of the present invention (e.g., ...). Figure 8 The device displays "OK". Figure 8 In the process, the material of the transparent conductive layer includes indium tin oxide, and the thickness of the transparent conductive layer is... The alignment marker AM is cross-shaped and gray.

[0064] like Figure 7 As shown, under the same structure, the greater the thickness of the transparent conductive layers 120 and 140, the smaller the sheet resistance of the transparent conductive layers 120 and 140. This allows for a lower driving voltage to drive the structures within the transparent conductive layers 120 and 140, achieving effects such as power saving and / or low heat generation. Therefore, in some embodiments, the thickness of the transparent conductive layers 120 and 140 can be greater than a specific value to reduce the driving voltage. For example (e.g.) Figure 7 As shown), the thickness of the transparent conductive layers 120 and 140 formed by indium tin oxide can be greater than or equal to the thickness of the indium tin oxide layer. The sheet resistance of the transparent conductive layers 120 and 140 is less than or equal to 500Ω / □, but is not limited to this.

[0065] In some embodiments, if no driving voltage is considered, the thickness of the transparent conductive layers 120 and 140 may be greater than or equal to the thickness of the driving layers 120 and 140. However, this is not a limitation. It should be noted that, without considering the driving voltage and taking into account the thickness suitable for thin-film optics principles, the thickness of the transparent conductive layers 120 and 140 can be greater than or equal to... and less than or equal to However, this is not the only limit.

[0066] Please refer to Figures 9 to 11 And at the same time refer to Figure 1 , Figures 9 to 11 This is a schematic diagram illustrating the structure of the privacy panel manufacturing method of the first embodiment of the present invention at different stages. Figure 1 The privacy panel 100 of the first embodiment of the present invention after the manufacturing method is completed, wherein Figures 9 to 11 Each privacy panel area R shown is an area where a privacy panel 100 is expected to be formed, while areas outside the privacy panel areas R are defined as non-privacy panel areas NR. It should be noted that the manufacturing method of the present invention can manufacture a motherboard including at least one privacy panel 100, and the following description uses the manufacture of a motherboard including six privacy panels 100 as an example, but the present invention does not limit the number of privacy panels 100 in a motherboard. It should be noted that the manufacturing method of the present invention is not limited to the following description and the accompanying drawings. In some embodiments, any other suitable steps may be added before or after one of the existing steps of the manufacturing method, and / or some steps may be performed simultaneously or separately.

[0067] In the following manufacturing methods, the processes for forming the film and / or structure may include atomic layer deposition (ALD), chemical vapor deposition (CVD), coating processes, other suitable processes, or combinations thereof. Patterning processes may include, for example, photolithography, a combination of photolithography and etching processes, any other suitable processes, or combinations thereof, wherein the etching process may be a wet etching process, a dry etching process, any other suitable etching process, or combinations thereof.

[0068] like Figure 9 As shown, a large panel 110M and a large panel 150M are provided, wherein the large panel 110M may include a substrate 110 of a plurality of privacy panels 100. Figure 9 (Taking six substrates 110 as an example), the large board 150M may include substrates 150 of multiple privacy panels 100. Figure 9 (Taking six substrates 150 as an example). Specifically, the substrate 110 of each privacy panel 100 is part of the large panel 110M, and the substrate 150 of each privacy panel 100 is part of the large panel 150M. The materials of the large panels 110M and 150M can be the same as those of the substrates 110 and 150, respectively. That is, the large panels 110M and 150M can, depending on their type (e.g., rigid large panel or flexible large panel), include, for example, glass, plastic, quartz, sapphire, polyimide, polyethylene terephthalate, other suitable materials or combinations thereof, but are not limited thereto.

[0069] It should be noted that the 110M and 150M large boards can be the upper and lower large boards, or the lower and upper large boards, respectively. Furthermore, the 110M and 150M large boards can also be referred to as the first and second large boards, or the second and first large boards, respectively. Additionally, the normal direction of the 110M and 150M large boards can be parallel to direction Z.

[0070] like Figure 9 As shown, a transparent conductive film is formed on a large plate 110M, and a patterning process is used to pattern the transparent conductive film to form a transparent conductive layer 120. A transparent conductive film is also formed on a large plate 150M, and another patterning process is used to pattern the transparent conductive film to form a transparent conductive layer 140. The transparent conductive layer 120 can directly contact the large plate 110M, and the transparent conductive layer 140 can directly contact the large plate 150M. That is, the transparent conductive layer 120 is the first film layer disposed on the large plate 110M, and the transparent conductive layer 140 is the first film layer disposed on the large plate 150M. For example, the above patterning process may include forming photoresist on the transparent conductive film, then exposing the photoresist using a photomask, developing the photoresist to form a photoresist with openings, and exposing a portion of the transparent conductive film through these openings. Next, etching is used to remove a portion of the transparent conductive film to pattern the transparent conductive film and form the transparent conductive layer 120 or the transparent conductive layer 140. Specifically, the above-mentioned patterning process is the first patterning process using a photomask performed on a large 110M or 150M board.

[0071] As described above, the transparent conductive layer 120 may include a privacy electrode 122 and a first alignment mark AM1, and the transparent conductive layer 140 may include a privacy electrode 142. The transparent conductive layer 140 may also include a second alignment mark AM2 as needed. Details of the privacy electrodes 122 and 142, the first alignment mark AM1, and the second alignment mark AM2 can be found above and will not be repeated here.

[0072] In addition, such as Figure 9 As shown, the transparent conductive layer 120 may also selectively include a third alignment mark AM3 that directly contacts the large panel 110M (i.e., the first alignment mark AM1 and the third alignment mark AM3 are formed simultaneously in the same manufacturing process), and the transparent conductive layer 140 may also selectively include a fourth alignment mark AM4 that directly contacts the large panel 150M (i.e., the second alignment mark AM2 and the fourth alignment mark AM4 are formed simultaneously in the same manufacturing process), wherein the third alignment mark AM3 and the fourth alignment mark AM4 can be set in the non-peeping panel area NR, and the number of the third alignment mark AM3 and the number of the fourth alignment mark AM4 can be designed according to requirements.

[0073] The arrangement, position, quantity, and shape of the third alignment marker AM3 and the fourth alignment marker AM4 can be designed according to requirements. For example, such as Figure 9 As shown, the number of third alignment markers AM3 and the number of fourth alignment markers AM4 can both be eight, but this is not a limitation. For example, as Figure 9 As shown, the third alignment mark AM3 can be adjacent to the corner of the large board 110M and arranged in an L-shape, and the fourth alignment mark AM4 can be adjacent to the corner of the large board 150M and arranged in an L-shape, but is not limited thereto. For example, Figure 9 The third alignment marker AM3 and the fourth alignment marker AM4 shown may both be rectangular, but their shapes are not limited to this. Furthermore, the shapes of the third alignment marker AM3 and the fourth alignment marker AM4 may be the same or different from each other.

[0074] For example, Figure 9 The third alignment mark AM3 and the fourth alignment mark AM4 shown can be alignment marks for assembling two large 110M and 150M boards, but are not limited to this. Optionally, Figure 9 The third alignment mark AM3 and the fourth alignment mark AM4 shown can be alignment marks for film layer attachment (e.g., alignment marks for attaching optical films such as anti-reflective films, brightness enhancement films, and polarizers), alignment marks for forming films or structures (e.g., alignment marks for forming alignment films 162, 164, spacers 170, frame adhesive layers, etc.), alignment marks for patterning films, cutting alignment marks, other suitable alignment marks, or combinations thereof.

[0075] In embodiments where the third alignment mark AM3 and the fourth alignment mark AM4 serve as alignment marks for assembling two large boards 110M and 150M, during the process of assembling the two large boards 110M and 150M, the third alignment mark AM3 and the fourth alignment mark AM4 can be aligned before assembling the two large boards 110M and 150M, but this is not a limitation. For example, the shapes of the third alignment mark AM3 and the fourth alignment mark AM4 can be rectangular and square with a hollow area, respectively. In the process of assembling the two large boards 110M and 150M, the third alignment mark AM3 and the fourth alignment mark AM4 can be aligned (e.g., the rectangular third alignment mark AM3 is located in the hollow area of ​​the square-shaped fourth alignment mark AM4) before assembling the two large boards 110M and 150M, but this is not a limitation.

[0076] It should be noted that, Figure 9The patterns of the transparent conductive layers 120 and 140 are shown as examples and are not intended to limit the invention. For example, in some embodiments, the transparent conductive layer 140 may further include connection electrodes for transmitting electrical signals to the privacy electrodes 122 and 142 respectively and / or pads for electrically connecting to chips or circuit boards (not shown). In addition, in some embodiments, the privacy electrode 122 may also have a notch overlapping the frame adhesive layer (not shown) to prevent the privacy electrodes 122 and 142 from short-circuiting through the frame adhesive layer with conductive particles.

[0077] like Figure 10 As shown, before assembling the two large plates 110M and 150M, multiple spacers 170 can be formed on the large plate 110M, but are not limited thereto. The spacers 170 may include, for example... Figure 2 The main spacer 172 and sub-spacer 174 shown may include the main spacer 172 but exclude the sub-spacer 174. In other embodiments, a plurality of spacers 170 may be formed on the large plate 150M before assembling the two large plates 110M and 150M. In this invention, the spacers 170 may be formed in any suitable manner. For example, a spacer material layer may be formed on the large plate 110M first, and then alignment marks AM (e.g., first alignment mark AM1 and / or third alignment mark AM3) disposed on the large plate 110M may be aligned using a photomask, and the spacer material layer may be patterned using a patterning process to form the spacers 170, but this is not a limitation. For example, the material of the spacer material layer may include a photosensitive material, and the above-described patterning process includes exposing the spacer material layer using a photomask, followed by development of the spacer material layer to form the spacers 170. Specifically, the aforementioned patterning process is a second patterning process using a photomask performed on the large board 110M. In embodiments where the spacer 170 includes a main spacer 172 and a sub-spacer 174, the main spacer 172 and the sub-spacer 174 can be formed simultaneously using a single photomask patterning process (e.g., a half-tone photomask patterning process), but are not limited thereto.

[0078] In addition, before assembling the two large plates 110M and 150M, an alignment film 162 can be formed on the privacy panel area R on the large plate 110M, and an alignment film 164 can be formed on the privacy panel area R on the large plate 150M. The alignment film 162 covers the privacy electrode 122 and the spacer 170, and the alignment film 164 covers the privacy electrode 142. For example, if the process steps for forming alignment films 162 and 164 require alignment, alignment can be performed on alignment marks AM (e.g., first alignment mark AM1 and / or third alignment mark AM3) provided on the large board 110M to form alignment film 162 in the privacy panel area R of the large board 110M, and alignment can be performed on alignment marks AM (e.g., second alignment mark AM2 and / or fourth alignment mark AM4) provided on the large board 150M to form alignment film 164 in the privacy panel area R of the large board 150M, but this is not a limitation.

[0079] Additionally, before assembling the two large panels 110M and 150M, a frame adhesive layer can be formed on the privacy panel area R of the large panel 150M, wherein the frame adhesive layer can surround the privacy electrode 142 (i.e., the frame adhesive layer can be located within the peripheral area PR of the privacy panel 100 and surround the active area AR of the privacy panel 100). For example, if the process step of forming the frame adhesive layer requires alignment, the frame adhesive layer can be formed by aligning the alignment marks AM (e.g., the second alignment mark AM2 and / or the fourth alignment mark AM4) provided on the large panel 150M, but this is not a limitation.

[0080] like Figure 11 As shown, two large boards 110M and 150M are assembled, and a privacy shield layer 130 is placed between the two large boards 110M and 150M to form a mother board 100m including multiple privacy shield panels 100. In Figure 11, alignment can be performed by aligning the alignment marks AM located on different transparent conductive layers 120 and 140 (e.g., aligning the first alignment mark AM1 with the second alignment mark AM2 and / or aligning the third alignment mark AM3 with the fourth alignment mark AM4) to ensure that the two large boards 110M and 150M are assembled in the correct positions. For example, in Figure 11 In the process of assembling two large plates, 110M and 150M, the third alignment mark AM3 overlaps with and aligns with the fourth alignment mark AM4 in the Z direction, but this is not a limitation. Figure 11In the process of assembling two large panels 110M and 150M, multiple privacy panel areas R of the large panel 110M overlap with multiple privacy panel areas R of the large panel 150M in the Z direction to form multiple privacy panels 100. In addition, a privacy dielectric layer 130 can be disposed between two privacy electrodes 122 and 142 and between two alignment films 162 and 164 (the privacy dielectric layer 130 is disposed within the privacy panel area R), and the privacy dielectric layer 130 can be confined in the active area AR of the privacy panel 100 by the frame adhesive layer.

[0081] After assembling two large plates 110M and 150M to form a mother plate 100m, the spacer 170 and the frame adhesive layer are located between the two large plates 110M and 150M, the alignment film 162 is located between the privacy electrode 122 and the privacy medium layer 130, and the alignment film 164 is located between the privacy electrode 142 and the privacy medium layer 130.

[0082] exist Figure 11 In the process, the motherboard 100m may include multiple privacy panels 100, each privacy panel 100 may be located in a corresponding privacy panel area R, wherein the first alignment mark AM1 and the second alignment mark AM2 are located in the privacy panel area R of the motherboard 100m, and the third alignment mark AM3 and the fourth alignment mark AM4 are located in the non-privacy panel area NR of the motherboard 100m.

[0083] Next, a cutting process is performed to cut the motherboard 100m, thereby forming multiple privacy panels 100. Each privacy panel 100 may include a substrate 110, 150, privacy electrodes 122, 142, a privacy dielectric layer 130, a first alignment mark AM1, a second alignment mark AM2, a frame adhesive layer, spacers 170, alignment films 162, 164, and other structures. For example, Figure 11 The cutting motherboard shown can be cut into six pieces from 100m of the sample. Figure 1 The privacy panel 100 shown is not limited to this. For example, the cutting process can be performed by aligning the alignment marks AM (e.g., at least one of the first to fourth alignment marks AM1, AM2, AM3, AM4), but is not limited to this.

[0084] In traditional privacy panels, alignment marks are formed using an opaque layer. This opaque layer can be a light-shielding layer (e.g., a black matrix or a light-shielding film layer containing metal, photoresist, ink, resin, pigment, or a combination thereof), a conductive metal layer, or other suitable opaque layers. In this invention, a transparent conductive layer is used instead of an opaque layer to form the alignment mark AM, and according to... Figures 4 to 7 By selecting a preferred thickness of the transparent conductive layer, the device can still successfully identify the alignment marks of the present invention (e.g., ...). Figure 8(The device displays OK). Therefore, compared to conventional privacy panels, the privacy panel 100 of the present invention has fewer film layers (i.e., the patterned opaque layer conventionally used to form alignment marks AM can be omitted), thereby reducing the number of patterning processes (e.g., reducing the number of processes that use photomasks), and thus reducing manufacturing costs. Compared to conventional privacy panels, the privacy panel 100 of the present invention omits the separate fabrication of opaque layers containing alignment marks on two large plates, thus reducing at least two patterning processes using photomasks. For example, in Figure 1 , Figure 2 , Figures 9 to 11 In the illustrated embodiment, the first patterning process using a photomask on the two large panels 110M and 150M respectively manufactures transparent conductive layers 120 and 140 containing alignment marks AM and privacy electrodes 122 and 142. Therefore, compared to conventional privacy panels, at least two patterning processes using photomasks can be reduced. For example, in Figure 1 , Figure 2 , Figures 9 to 11 In the illustrated embodiment, only the transparent conductive layers 120, 140 and the spacer 170 require a patterning process using a photomask. Therefore, the privacy panel 100 in this embodiment only requires three patterning processes using a photomask, but this is not a limitation.

[0085] The privacy panel, the method for manufacturing the privacy panel, and the motherboard of the present invention are not limited to the above embodiments. Other embodiments and variations of the present invention will continue to be disclosed below. However, in order to simplify the description and highlight the differences between the embodiments and variations, the same reference numerals are used to refer to the same components below, and repeated parts will not be described again.

[0086] Please refer to Figure 12 , Figure 12 The image shown is a cross-sectional schematic diagram of the privacy panel according to a second embodiment of the present invention. Figure 12 As shown, the difference between this embodiment and the first embodiment lies in... Figure 12 In this design, spacer 170 is replaced by ballspacer 272. More specifically, details such as... Figure 10 The steps shown are as follows: forming multiple spacers 170 on the large plate 110M, and in such a way... Figure 11 Before assembling the two large boards 110M and 150M as shown in the manufacturing stage, the spherical spacer 272 can be placed directly on the large board (large board 110M or 150M), and then proceed as follows. Figure 11The steps shown involve assembling two large plates 110M and 150M, wherein after assembly, a spherical spacer 272 is positioned between the two plates 110M and 150M. Therefore, in this embodiment, only the manufacturing of the transparent conductive layers 120 and 140 requires a patterning process, meaning the privacy panel 200 only requires two patterning processes using photomasks, but this is not a limitation. Accordingly, the manufacturing cost of the privacy panel 200 can be reduced.

[0087] Please refer to Figures 13 to 16 , Figure 13 The diagram shown is a top view of the transparent conductive layer and the frame adhesive layer of the privacy panel according to the third embodiment of the present invention. Figure 14 The image shown is a top view of the privacy panel according to the third embodiment of the present invention. Figure 15 The following is along Figure 14 A schematic diagram of the cross section along line B-B', and Figure 16 The following is along Figure 14 A cross-sectional diagram of the C-C' section. (See diagram below.) Figure 13 As shown, a transparent conductive layer 140 is disposed on a substrate 150 and includes a privacy electrode 142, connecting electrodes (e.g., a first connecting electrode CE1 and a second connecting electrode CE2), pads P1 and P2, and a second alignment mark AM2. At least a portion of the privacy electrode 142 is disposed in the entire active region AR, and the first connecting electrode CE1, the second connecting electrode CE2, and pads P1 and P2 are disposed in the peripheral region PR. Pad P1 is electrically connected to the first connecting electrode CE1, the first connecting electrode CE1 is electrically connected to the privacy electrode 142, and pad P2 is electrically connected to the second connecting electrode CE2. A transparent conductive layer 120 is disposed on a substrate 110 and includes a privacy electrode 122 and a first alignment mark AM1. A first portion 122a of the privacy electrode 122 is disposed in the entire active region AR, and a second portion 122b of the privacy electrode 122 is disposed in the peripheral region PR. Figure 13 and Figure 14 As shown, after the substrates 110 and 150 are bonded together with the frame adhesive layer SL to form the privacy panel 300, the pads P1 and P2 are not covered by the substrate 110. The pads P1 and P2 are used to receive a first electrical signal and a second electrical signal, respectively. For example, the pads P1 and P2 can be coupled to a flexible circuit board, which is electrically connected to a system board. The drive circuit on the system board transmits the first and second electrical signals to the pads P1 and P2 respectively through the flexible circuit board, but this is not a limitation. Figures 13 to 16As shown, the pad P1 in the privacy panel 300 receives a first electrical signal S1, and the first electrical signal S1 can be transmitted to the privacy electrode 142 via the first connecting electrode CE1. The pad P2 in the privacy panel 300 receives a second electrical signal S2, and the second portion 122b of the privacy electrode 122, the frame adhesive layer SL, and the second connecting electrode CE2 overlap each other in the Z direction, wherein the frame adhesive layer SL includes conductive particles CP, therefore the second electrical signal S2 can be transmitted to the privacy electrode 122 via the second connecting electrode CE2 and the conductive particles CP in the frame adhesive layer SL. Figure 13 , Figure 15 As shown, in this embodiment, the privacy electrode 122 further includes a notch NH disposed in the peripheral area PR. The notch NH, the frame adhesive layer SL, and the first connecting electrode CE1 overlap each other in the Z direction to prevent the first electrical signal S1 from being transmitted to the privacy electrode 122 via the conductive particles CP in the first connecting electrode CE1 and the frame adhesive layer SL, thus preventing a short circuit. The privacy electrodes 122 and 142 respectively receive the first electrical signal S1 and the second electrical signal S2 to control the state of the privacy dielectric layer 130 located between the privacy electrodes 122 and 142, so that the privacy panel 300 can switch between a first state (or privacy open state) and a second state (or privacy closed state). The transparent conductive layer and the frame adhesive layer in this embodiment can be applied to the privacy panels 100 and 200 of the first and second embodiments, but are not limited thereto. The present invention does not limit the pattern of the transparent conductive layers 120 and 140 of the privacy panels 100 and 200 of the first and second embodiments.

[0088] In summary, the present invention uses two transparent conductive layers instead of opaque layers as the first film layers of two substrates, and at least one of the two transparent conductive layers includes alignment marks. Therefore, compared with conventional privacy panels, the privacy panel of the present invention has fewer film layers, thereby reducing the number of patterning processes and thus reducing manufacturing costs.

[0089] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A privacy panel, characterized in that, The privacy panel has an active area and a peripheral area disposed outside the active area, the privacy panel comprising: First substrate; A second substrate is disposed opposite to the first substrate; A first transparent conductive layer is disposed between the first substrate and the second substrate and in direct contact with the first substrate. The first transparent conductive layer includes a first privacy electrode and a first alignment mark. The first privacy electrode is disposed in the active area and the first alignment mark is disposed in the peripheral area. A second transparent conductive layer is disposed between the first substrate and the second substrate, and in direct contact with the second substrate. The second transparent conductive layer includes a second privacy electrode, which is disposed in the active area. A privacy shield layer is disposed between the first privacy shield electrode and the second privacy shield electrode; The first privacy electrode and the first alignment mark have the same thickness, and the thickness of the first privacy electrode and the first alignment mark is greater than or equal to 700+850n5Å and less than or equal to 1000+850n5Å, where n5 is 0, 1, 2, 3, 4 or 5.

2. The privacy panel as described in claim 1, characterized in that, The second transparent conductive layer includes a second alignment mark, and the second alignment mark is disposed in the peripheral area.

3. The privacy panel as described in claim 1, characterized in that, The thickness of the first transparent conductive layer is greater than or equal to 700+850n5Å and less than or equal to 1000+850n5Å.

4. The privacy panel as described in claim 1, characterized in that, The first alignment mark is an alignment mark used to attach the polarizer to the privacy panel.

5. A motherboard comprising multiple privacy panels, characterized in that, The mother plate includes: Multiple privacy panels as described in claim 1.

6. The mother plate as described in claim 5, characterized in that, The motherboard has multiple privacy panel areas and one non-privacy panel area, with each privacy panel located in its corresponding privacy panel area, and the motherboard further includes: A third alignment mark, The third alignment mark is located in the non-peeping panel area, the third alignment mark belongs to the first transparent conductive layer, and the third alignment mark and the first alignment mark are formed simultaneously in the same manufacturing process.

7. A method for manufacturing a privacy panel, characterized in that, Includes the following steps: A first transparent conductive film is formed on a first large plate; The first transparent conductive film is patterned to form a first transparent conductive layer, wherein the first transparent conductive layer includes a first privacy electrode and a pair of alignment marks, the first privacy electrode being located in a privacy panel area of ​​the first large plate, and the alignment marks being located in a non-privacy panel area of ​​the first large plate or in the privacy panel area; A second transparent conductive film is formed on a second large plate; The second transparent conductive film is patterned to form a second transparent conductive layer, wherein the second transparent conductive layer includes a second privacy electrode, and the second privacy electrode is located in a privacy panel area of ​​the second large plate; and The first large plate and the second large plate are assembled to form a mother plate, wherein a privacy shield medium layer is disposed between the first privacy shield electrode and the second privacy shield electrode; The first privacy electrode and the alignment mark have the same thickness, and the thickness of the first privacy electrode and the alignment mark is greater than or equal to 700+850n5Å and less than or equal to 1000+850n5Å, where n5 is 0, 1, 2, 3, 4 or 5.

8. The manufacturing method as described in claim 7, characterized in that, The manufacturing method further includes: A gap is formed on the first large plate. The step of forming the spacer is performed before the step of assembling the first large plate and the second large plate, and the spacer is located between the first large plate and the second large plate after the step of assembling the first large plate and the second large plate.

9. The manufacturing method as described in claim 8, characterized in that, The steps of forming the spacer include: A spacer material layer is formed on the first large plate; and The alignment marks are aligned, and the spacer material layer is patterned to form the spacer.

10. The manufacturing method as described in claim 7, characterized in that, The manufacturing method further includes: A first alignment film is formed on one surface of the first privacy electrode; and A second alignment film is formed on one surface of the second privacy electrode. The steps of forming the first alignment film and forming the second alignment film are performed before the step of assembling the first large plate and the second large plate, and after the step of assembling the first large plate and the second large plate, the first alignment film and the second alignment film are respectively located between the first privacy electrode and the privacy medium layer and between the second privacy electrode and the privacy medium layer.

11. The manufacturing method as described in claim 7, characterized in that, The manufacturing method further includes: A frame adhesive layer is formed on the second large plate, and the frame adhesive layer surrounds the second privacy electrode. The step of forming the frame adhesive layer is performed before the step of assembling the first large board and the second large board, and after the step of assembling the first large board and the second large board, the frame adhesive layer is located between the first large board and the second large board.

12. The manufacturing method as described in claim 7, characterized in that, The manufacturing method further includes: The motherboard is cut to form at least one privacy panel. The privacy panel includes a first privacy electrode, a second privacy electrode, and a privacy medium layer.

13. The manufacturing method as described in claim 7, characterized in that, The alignment mark may be an alignment mark for attaching a polarizer, an alignment mark for forming an alignment film, an alignment mark for applying frame adhesive, an alignment mark for coupling a circuit board, an alignment mark for assembling the first large board and the second large board, a cut alignment mark, or a combination of the above.

14. The manufacturing method as described in claim 7, characterized in that, The second transparent conductive layer also includes another alignment mark, which is located in a non-peeping panel area or in the privacy panel area of ​​the second large plate.

15. The manufacturing method as described in claim 14, characterized in that, The other alignment mark may be an alignment mark for attaching a polarizer, an alignment mark for forming an alignment film, an alignment mark for applying frame adhesive, an alignment mark for coupling a circuit board, an alignment mark for assembling the first large board and the second large board, a cutting alignment mark, or a combination thereof.

16. The manufacturing method as described in claim 14, characterized in that, The alignment mark and the other alignment mark are alignment marks for assembling the first large plate and the second large plate, wherein the step of assembling the first large plate and the second large plate includes aligning the alignment mark and the other alignment mark.

Images