Liquid crystal phase shifter and antenna device

Abstract

A liquid crystal phase shifter and antenna device. The liquid crystal phase shifter includes a first transistor, a storage capacitor, a phase modulation electrode, and a common electrode. A first end of the first transistor is electrically coupled to a source line, and a gate end of the first transistor is configured to receive a first control signal. A first end of the storage capacitor is electrically coupled to a second end of the first transistor, and a second end of the storage capacitor is electrically coupled to an auxiliary source line. The phase modulation electrode is electrically coupled to the second end of the transistor. The common electrode forms a liquid crystal capacitor with the phase modulation electrode, and the common electrode is configured to receive a ground voltage.

Description

Technical Field

[0001] This disclosure relates to a liquid crystal phase shifter and an antenna device, and more particularly to a liquid crystal phase shifter and an antenna device for a liquid crystal antenna. Background Technology

[0002] Today, antennas are used in numerous fields, such as advanced driver assistance system radar, beyond-line-of-sight drone flight, remote vital sign monitoring and emotion recognition, radio transmission, and 5G communication. With the increasingly widespread application of array antennas, improving antenna accuracy and reducing manufacturing costs have become important issues in this field. Summary of the Invention

[0003] This disclosure provides a liquid crystal phase shifter. The liquid crystal phase shifter includes a first transistor, a storage capacitor, a phase modulation electrode, and a common electrode. A first terminal of the first transistor is electrically coupled to a source line, and the gate terminal of the first transistor is used to receive a first control signal. A first terminal of the storage capacitor is electrically coupled to a second terminal of the first transistor, and the second terminal of the storage capacitor is electrically coupled to an auxiliary source line. The phase modulation electrode is electrically coupled to the second terminal of the transistor. The common electrode and the phase modulation electrode form a liquid crystal capacitor, and the common electrode is used to receive a ground voltage.

[0004] This disclosure provides a liquid crystal phase shifter. The liquid crystal phase shifter includes a phase control array, a first source line, a first auxiliary source line, and a common electrode. The phase control array includes a plurality of first phase shifting circuits arranged in a plurality of columns of an array. The first phase shifting circuits include a plurality of first transistors, a plurality of first storage capacitors, and a plurality of first phase modulation electrodes electrically coupled to a first terminal of the first storage capacitors. The first source line is electrically coupled to a first terminal of the first transistors, wherein the second terminals of the first transistors are respectively electrically coupled to a first terminal of the first storage capacitors. The first auxiliary source line is electrically coupled to a second terminal of the first storage capacitors. The common electrode and the first phase modulation electrodes form a plurality of first liquid crystal capacitors, wherein the common electrode is used to receive a ground voltage.

[0005] This disclosure provides an antenna device. The antenna device includes a feed board and a liquid crystal phase shifter. The feed board includes a circuit board, a microstrip feed line, and a ground layer. The ground layer and the microstrip feed line are disposed on opposite sides of the circuit board. The liquid crystal phase shifter is attached to the feed board and covers a portion of the microstrip feed line. The liquid crystal phase shifter includes a first substrate, a phase control array, a liquid crystal layer, a second substrate, and a common electrode. The phase control array is formed on the first substrate. The common electrode is formed on the second substrate, and the liquid crystal layer is disposed between the phase control array and the common electrode. The common electrode is electrically coupled to the ground layer.

[0006] In summary, this disclosure configures the common electrode of the liquid crystal phase shifter to receive ground voltage, thereby using it as the ground plane of a microstrip antenna, which reduces manufacturing costs and improves accuracy. Attached Figure Description

[0007] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0008] Figure 1A This is a schematic diagram of an antenna device according to some embodiments of the present disclosure.

[0009] Figure 1B This is a schematic diagram of cross sections 1-2 of the antenna device in FIG1 according to some embodiments of the present disclosure.

[0010] Figure 2 This is a schematic diagram of a substrate, a liquid crystal layer, and a power supply board according to some embodiments of the present disclosure.

[0011] Figure 3 This is a functional block diagram of a liquid crystal phase shifter according to some embodiments of the present disclosure.

[0012] Figure 4 This is a schematic diagram of a liquid crystal phase shifter according to some embodiments of the present disclosure.

[0013] Figure 5 This is a schematic diagram of a phase-shifting circuit according to some embodiments of the present disclosure.

[0014] Figure 6 Provided in accordance with some embodiments of this disclosure Figure 5 Timing diagrams of signal, voltage, and node potential changes in a phase-shifting circuit.

[0015] Figure 7A And 7B are embodiments based on this disclosure. Figure 5 A schematic diagram of the phase-shifting circuit during the setting period of the positive half-cycle and during the positive voltage period.

[0016] Figure 7C And the 7th is based on some embodiments of this disclosure. Figure 5 A schematic diagram of the phase-shifting circuit during the setting period of the negative half-cycle and during the negative voltage period.

[0017] The eighth figure is a schematic diagram of a phase control array according to some embodiments of the present disclosure.

[0018] Figure 9 Provided in accordance with some embodiments of this disclosure Figure 8 The timing diagram shows the signal, voltage, and node potential changes of a portion of the phase-shifting circuit in the phase-control array.

[0019] Figure 10This is a cross-sectional view of a portion of the antenna device of FIG1 according to some embodiments of the present disclosure.

[0020] Explanation of reference numerals in the attached figures:

[0021] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the appended symbols are explained as follows:

[0022] 100: Antenna device

[0023] 110: Liquid Crystal Phase Shifter

[0024] 112t, 112b: Substrate

[0025] 114: Common Electrode

[0026] 116: Liquid Crystal Layer

[0027] 118: Phase Control Array

[0028] 120: Feeder board

[0029] 122: Microstrip feeder

[0030] 124, 138: Circuit Board

[0031] 126: Grounding layer

[0032] 130: Cover plate

[0033] 132, 133: Connecting elements

[0034] 134: Conductive components

[0035] 136: Conductive layer

[0036] 140: Signal Generator

[0037] 210: Slot

[0038] 310: Drive circuit

[0039] 410: Timing Controller

[0040] 420: Gate drive circuit

[0041] 430: Source drive circuit

[0042] Mg1~Mgm,Mgj,Ms1~Ms1,Msj: Transistors

[0043] Sp1~Spm,Spj: Source pole lines

[0044] Ss1~Ssm,Ssj: Auxiliary source lines

[0045] G1~Gn,Gi: Gate lines

[0046] P11~Pnm,Pij,P11~P31,P12~P32: Phase-shifting circuit

[0047] T1, T11~T31, T12~T32: Transistors

[0048] SC1~SCn,SCg,SCs,SCi: Control signals

[0049] Ep, Ep11~Ep31, Ep12~Ep32: Phase modulation electrodes

[0050] Ec, Ec11~Ec31, Ec12~Ec32: Common electrode

[0051] CL, CL11~CL31, CL12~CL32: Liquid crystal capacitors

[0052] CS, CS11~CS31, CS12~CS32: Storage capacitors

[0053] GND: Grounding voltage

[0054] N1, N11~N31, N12~N32: Nodes

[0055] Va1~Va3, Vb1~Vb3, Vp1~Vp3: Voltage

[0056] Va1'~Va3',Vb1'~Vb3',Vp1'~Vp3': Voltage

[0057] BA: Adhesive Detailed Implementation

[0058] The following is a detailed description of embodiments with reference to the accompanying drawings. However, the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structure's operation is not intended to limit its execution order. Any structure resulting from the recombination of elements and producing an apparatus with equivalent technical effects is within the scope of this disclosure. Furthermore, the illustrations are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0059] Unless otherwise specified, the terms used throughout this specification and claims generally have their ordinary meaning in the context of this art, the disclosure, and the specific content. Furthermore, the terms “comprising,” “including,” “having,” “containing,” etc., as used herein, are open-ended terms, meaning “including but not limited to.” Additionally, the term “and / or” as used herein includes any one or more of the related listed items and all combinations thereof.

[0060] Please see Figure 1A , Figure 1A This is a schematic diagram of an antenna device 100 according to some embodiments of the present disclosure. Figure 1A As shown, the antenna device 100 includes a liquid crystal phase shifter 110, a feed plate 120, a cover plate 130, bonding elements 132 and 133, and a signal generator 140.

[0061] In some embodiments, the feed board 120 may be implemented using a printed circuit board (PCB). In some embodiments, the feed board 120 includes a microstrip feed line 122, and the microstrip feed line 122 may be implemented using printed circuitry. In some embodiments, the microstrip feed line 122 is made of a conductive material and is used to transmit signals provided by the signal generator 140. In some embodiments, the antenna arrangement 100 may be understood as a microstrip antenna.

[0062] In some embodiments, the signal generator 140 may be implemented using a monolithic microwave integrated circuit. In some embodiments, the signal generator 140 is electrically coupled to a microstrip feed line 122 and is used to feed a high-frequency signal to the microstrip feed line 122. In some embodiments, the high-frequency signal may be a radio frequency signal and / or a microwave signal. In some embodiments, the microstrip feed line 122 extends from the signal generator 140 to the liquid crystal phase shifter 110 on a horizontal projection plane.

[0063] In some embodiments, the liquid crystal phase shifter 110 covers a portion of the microstrip feed line 122. Thus, the liquid crystal phase shifter 110 changes the dielectric constant through liquid crystal control technology, thereby adjusting the resonant frequency of the microstrip antenna and modulating the field pattern and beam direction of the high-frequency signal. In some embodiments, because the fabrication cost of large-area element arrays in panel manufacturing is low and the fabrication accuracy is superior to that of traditional array antennas on printed circuit boards, the liquid crystal phase shifter 110 manufactured using panel manufacturing processes can achieve high accuracy and low cost.

[0064] In some embodiments, cover plate 130 covers a portion of the feed line in microstrip feed line 122. In some embodiments, cover plate 130 is adjacent to liquid crystal phase shifter 110 and is secured to feed plate 120 by bonding elements 132 and 133. Bonding elements 132 and 133 are made of conductive material. In some embodiments, bonding elements 132 and 133 are through-hole solder or screws. In other embodiments, bonding elements 132 and 133 may be implemented by other conductive elements, and this disclosure is not limited thereto.

[0065] Please see Figure 1Aas well as Figure 1B . Figure 1B According to some embodiments of this disclosure Figure 1A A schematic diagram of cross-section 1-2 of the antenna device 100 is shown. (See diagram 1-2.) Figure 1B As shown, the antenna device 100 further includes an adhesive BA, which secures the liquid crystal phase shifter 110 to the feed board 120. In some embodiments, the feed board 120 includes a microstrip feed line 122, a circuit board 124, and a ground layer 126. In some embodiments, the ground layer 126 and the microstrip feed line 122 are formed on opposite sides of the circuit board 124, and the ground layer 126 of the feed board 120 does not overlap with the liquid crystal phase shifter 110 in a horizontal projection.

[0066] In some embodiments, the liquid crystal phase shifter 110 includes substrates 112t and 112b, a phase control array 118, a liquid crystal layer 116, and a common electrode 114. In some embodiments, the phase control array 118 is formed on substrate 112b, and the common electrode 114 is formed on substrate 112t. In some embodiments, substrates 112t and 112b may be made of glass substrates, thereby possessing low-loss material properties. In some embodiments, the liquid crystal layer 116 is disposed between the phase control array 118 and the common electrode 114, so that the arrangement of liquid crystals in the liquid crystal layer 116 is determined by driving the potential of the phase control array 118, and the direction of the beam is modulated by the different dielectric constants of the liquid crystals under different arrangements.

[0067] In some embodiments, the cover plate 130 includes a circuit board 138 and a conductive layer 136 disposed on the circuit board 138, with the conductive layer 136 adjacent to the common electrode 114. In some embodiments, a conductive member 134 electrically connects the common electrode 114 of the liquid crystal phase shifter 110 to the conductive layer 136 of the cover plate 130. In some embodiments, the conductive member 134 is solder. In some embodiments, the conductive member 134 is a conductive material. Thus, the common electrode 114 of the liquid crystal phase shifter 110 is electrically coupled to the ground layer 126 of the feed board 120 via the conductive member 134, the conductive layer 136 of the cover plate 130, and the bonding element 132 to ground the common electrode 114 of the liquid crystal phase shifter 110. That is, the common electrode 114 of the liquid crystal phase shifter 110 receives a ground voltage GND (e.g., 0 volts) from the ground layer 126 along the electrical path of the conductive member 134, the conductive layer 136 of the cover plate 130, and the bonding element 132. In other embodiments, the common electrode 114 of the liquid crystal phase shifter 110 may be grounded by other connection methods and receive a ground voltage GND (e.g., 0 volts), which is not a limitation of this disclosure.

[0068] In some embodiments, the common electrode 114 of the liquid crystal phase shifter 110 is also used as the ground plane of the microstrip antenna, thereby forming a microstrip antenna together with the microstrip feed line 122 of the feed board. In this way, by integrating the ground plane of the microstrip antenna with the common electrode 114 of the liquid crystal phase shifter 110, the size and manufacturing process of the antenna device 100 can be reduced.

[0069] Please see Figure 1B as well as Figure 2 , Figure 2 This is a schematic diagram of substrates 112b and 112t, liquid crystal layer 116, and feed plate 120 according to some embodiments of the present disclosure. It should be noted that, in order to clearly show the phase control array 118 formed on substrate 112b, Figure 2 The front and rear sides of the substrate 112b are reversed. Specifically, in the liquid crystal phase shifter 110, the phase control array 118 formed on the substrate 112b faces the liquid crystal layer 116, and the common electrode 114 formed on the substrate 112b faces the liquid crystal layer 116.

[0070] like Figure 2 As shown, a phase control array 118 is formed on a substrate 112b, and the phase control array 118 includes phase shifting circuits P11 and P12. Each of the phase shifting circuits P11 and P12 includes a transistor, a storage capacitor, and a phase modulation electrode. The components and connections in the phase shifting circuits P11 and P12 will be described in detail in subsequent embodiments.

[0071] In some embodiments, a common electrode 114 is formed on a substrate 112t. In some embodiments, the common electrode 114 has a plurality of slots 210 (e.g., square slots), the center point of each slot 210 corresponding to one end of a microstrip feed line 122. In some embodiments, the length of each edge of the slot 210 of the common electrode 114 is proportional to the wavelength of the high-frequency wave, such that the common electrode 114 and the microstrip feed line 122 form a microstrip slot antenna.

[0072] Please see Figure 3 , Figure 3 This is a functional block diagram of a liquid crystal phase shifter 110 according to some embodiments of the present disclosure. For example... Figure 3 As shown, the liquid crystal phase shifter 110 includes a driving circuit 310 and a phase control array 118. The driving circuit 310 is electrically coupled to the phase control array 118 and is used to drive the phase control array 118. In order to use the common electrode 114 of the liquid crystal phase shifter 110 as the ground plane of the microstrip antenna, the common electrode 114 must be maintained at the ground voltage GND.

[0073] In order to use the common electrode 114 as the ground plane of the microstrip antenna, the liquid crystal phase shifter 110 cannot perform polarity reversal on the common electrode 114 to avoid inertial deformation of the liquid crystal. Furthermore, the output of the source driver is often in the positive domain. Therefore, subsequent embodiments will describe in detail how the antenna device 100 provides both positive and negative half-cycle operation while grounding the common electrode 114.

[0074] Please see Figure 4 , Figure 4 This is a schematic diagram of a liquid crystal phase shifter 110 according to some embodiments of the present disclosure. Figure 4 As shown, the liquid crystal phase shifter 110 includes a driving circuit 310, a phase control array 118, transistors Mg1-Mgm, transistors Ms1-Msm, and wires Gg and Gs. The driving circuit 310 includes a timing controller 410, a gate driving circuit 420, and a source driving circuit 430. In some embodiments, the gate driving circuit 420 and the source driving circuit 430 are controlled by the timing controller 410. In some embodiments, the gate driving circuit 420 may be implemented by a gate driving integrated circuit. In other embodiments, the gate driving circuit 420 may be implemented by a gate on array (GOA) circuit. In some embodiments, the source driving circuit 430 may be implemented by a source driving integrated circuit.

[0075] In some embodiments, the phase control array 118 includes phase shifting circuits P11 to P1m, P21 to P2m to Pn1 to Pnm, gate lines G1 to Gn, source lines Sp1 to Spm, and auxiliary source lines Ss1 to Ssm arranged in an array, wherein “n” and “m” are integers greater than or equal to 1.

[0076] In some embodiments, gate lines G1 to Gn determine which column of the phase-shifting circuits P11 to Pnm are located in the phase control array 118. For example, gate line G1 electrically couples the phase-shifting circuits P11 to Pn1 located in the first column to the gate drive circuit 420, and gate line G2 electrically couples the phase-shifting circuits P21 to Pn2 located in the second column to the gate drive circuit 420. Similarly, gate line Gn electrically couples the phase-shifting circuits Pn1 to Pnm located in the nth column to the gate drive circuit 420. Thus, the gate drive circuit 420 transmits control signals SC1 to SCn to the corresponding phase-shifting circuits P11 to Pnm via gate lines G1 to Gn.

[0077] In some embodiments, source lines Sp1 to Spm determine which row of the phase-shifting circuits P11 to Pnm are located in the phase control array 118. For example, source line Sp1 electrically couples the phase-shifting circuits P11 to Pn1 located in the first row to the source drive circuit 430, and source line Sp2 electrically couples the phase-shifting circuits P21 to P2n located in the second row to the source drive circuit 430. Similarly, source line Spm and auxiliary source line Ssm electrically couple the phase-shifting circuits P1m to Pnm located in the m-th row to the source drive circuit 430. Thus, the voltage provided by the source drive circuit 430 is transmitted to the corresponding phase-shifting circuits P11 to Pnm via source lines Sp1 to Spm.

[0078] In some embodiments, the first terminals of transistors Mg1 to Mgm are grounded. The second terminals of transistors Mg1 to Mgm are electrically coupled to auxiliary source lines Ss1 to Ssm, respectively, and the gate terminals of transistors Mg1 to Mgm are electrically connected to the gate drive circuit 420 via wire Gg to receive the control signal SCg provided by the gate drive circuit 420.

[0079] In some embodiments, auxiliary source lines Ss1 to Ssm are electrically coupled to corresponding phase-shifting circuits P11 to Pnm. Specifically, auxiliary source line Ss1 is electrically coupled to phase-shifting circuits P11 to Pn1, auxiliary source line Ss2 is electrically coupled to phase-shifting circuits P12 to Pn2, and so on, with auxiliary source line Ssm being electrically coupled to phase-shifting circuits P1m to Pnm.

[0080] In some embodiments, the first ends of transistors Ms1 to Msm are electrically coupled to auxiliary source lines Ss1 to Ssm, the second ends of transistors Ms1 to Msm are electrically coupled to source drive circuit 430, and the gate ends of transistors Ms1 to Msm are electrically connected to gate drive circuit 420 via wire Gs to receive control signal SCs provided by gate drive circuit 420.

[0081] Please see Figure 4 as well as Figure 5 , Figure 5 This is a schematic diagram of a phase-shifting circuit Pij according to some embodiments of the present disclosure. In some embodiments, Figure 4 Each of the phase-shifting circuits P11 to Pnm can be generated by... Figure 5 The phase-shifting circuit Pij is implemented, where "i" is a variable in the range of 1 to n, and "j" is a variable in the range of 1 to m. In some embodiments, the phase-shifting circuit Pij represents the phase-shifting circuit located in the i-th column and j-th row. Figure 5As shown, the phase-shifting circuit Pij is electrically coupled to the gate line Gi, the source line Spj, and the auxiliary source line Ssj, and the auxiliary source line Ssj is electrically coupled to the transistor Mgj and the transistor Msj, where "i" and "j" are integers greater than or equal to 1.

[0082] The phase-shifting circuit Pij includes a storage capacitor CS, a phase modulation electrode Ep, and a transistor T1. Architecturally, the first terminal of transistor T1 is electrically coupled to the source line Spj, and the gate terminal of transistor T1 is electrically coupled to the gate line Gi. The gate terminal of transistor T1 is used to receive the control signal SCi transmitted by the gate line Gi.

[0083] The second terminal of transistor T1 is electrically coupled to the first terminal of storage capacitor CS and phase modulation electrode Ep. In some embodiments, node N1 is located at the connection point of the second terminal of transistor T1, the first terminal of storage capacitor CS, and phase modulation electrode Ep. A liquid crystal LC is formed between the phase modulation electrode Ep and the common electrode Ec to form a liquid crystal capacitor CL, wherein the common electrode Ec is grounded. In some embodiments, the common electrode Ec corresponds to Figure 1B as well as Figure 2 The common electrode 114 in the middle portion, and the liquid crystal LC corresponding to Figure 1B as well as Figure 2 The middle section of the LCD 116.

[0084] The first terminal of the storage capacitor CS is electrically coupled to the second terminal of transistor T1, and the second terminal of the storage capacitor CS is electrically coupled to the auxiliary source line Ssj. The auxiliary source line Ssj is electrically coupled to the first transistor Mgj and transistor Msj.

[0085] The first terminal of transistor Mgj is grounded, the gate terminal of transistor Mgj is used to receive the control signal SCg, and the second terminal of transistor Mgj is electrically coupled to the auxiliary source line Ssj. In some embodiments, Figure 5 The control signal SCg corresponds to Figure 4 The control signal SCg in the middle.

[0086] The first terminal of transistor Msj is electrically coupled to the auxiliary source line Ssj, the gate terminal of transistor Msj receives the control signal SCs, and the second terminal of transistor Msj is electrically coupled to the source drive circuit 430. In some embodiments, Figure 5 The control signal SCs corresponds to Figure 4 The control signals SCs in the system.

[0087] For a better understanding, please refer to the following: Figure 5 , Figure 6 as well as Figures 7A to 7D . Figure 6 Provided in accordance with some embodiments of this disclosure Figure 5The timing diagram shows the signal, voltage, and potential changes of the nodes in the phase-shifting circuit Pij. Figure 7A as well as Figure 7B According to some embodiments of this disclosure Figure 5 A schematic diagram of the phase-shifting circuit Pij during the setting period of the positive half-cycle Cp1 and during the positive voltage period. Figure 7C as well as Figure 7D According to some embodiments of this disclosure Figure 5 A schematic diagram of the phase-shifting circuit Pij during the setting period of the negative half-cycle Cn1 and during the negative voltage period.

[0088] like Figure 6 As shown, one cycle C1 in the control timing of the phase-shifting circuit Pij can be divided into two half-cycles, namely the positive half-cycle Cp1 and the negative half-cycle Cn1. The positive half-cycle Cp1 has two periods, namely the setting period Psa1 and the positive voltage period Ppv1. The negative half-cycle Cn1 has two periods, namely the setting period Psb1 and the negative voltage period Pnv1. In some embodiments, the setting periods Psa1 and Psb1 can be understood as the data setting period and / or the scan period. In some embodiments, the positive voltage period Ppv1 refers to the period during which the potential of the phase modulation electrode Ep is controlled at 0 volts and / or a positive voltage, and the negative voltage period Pnv1 refers to the period during which the potential of the phase modulation electrode Ep is controlled at 0 volts and / or a negative voltage.

[0089] In some embodiments, the duration of the positive half-cycle Cp1 and the negative half-cycle Cn1 in the control timing of the phase-shifting circuit Pij is 1 ms, wherein the duration of the setting period Psa1 of the positive half-cycle Cp1 and the setting period Psb1 of the negative half-cycle Cn1 is 180 μs, and the duration of the positive voltage period Ppv1 of the positive half-cycle Cp1 and the negative voltage period Pnv1 of the negative half-cycle Cn1 is 820 μs. In some instances, the duration of the positive voltage period Ppv1 and the negative voltage period Pnv1 is longer than the duration of the setting periods Psa1 and Psb1. Furthermore, the setting period Psa1 can be implemented with the duration of Psb1, the positive voltage period Ppv1, and the negative voltage period Pnv1, and can be implemented with other suitable durations, which are not limited to this disclosure.

[0090] Specifically, the control signal SCg has a low logic level during the setting period Psa1 of the positive half-cycle Cp1 and Psb1 of the setting period Cn1 of the negative half-cycle. Furthermore, the control signal SCg has a high logic level during the positive voltage period Ppv1 of the positive half-cycle Cp1 and the negative voltage period Pnv1 of the negative half-cycle Cn1. The control signal SCs has a high logic level during the setting period Psa1 of the positive half-cycle Cp1 and Psb1 of the setting period Cn1 of the negative half-cycle. Furthermore, the control signal SCs has a low logic level during the positive voltage period Ppv1 of the positive half-cycle Cp1 and the negative voltage period Pnv1 of the negative half-cycle Cn1. In some embodiments, the control signal SCi can be understood from the scan signal.

[0091] In some embodiments, the voltages Vai and Vbi provided by the source drive circuit 430 are greater than or equal to 0 volts. In some embodiments, the voltages provided by the source drive circuit 430 are in the range of 0 volts and positive values. It is worth noting that the pulse width (e.g., 15 μs) corresponding to the voltages Vai and Vbi provided by the source drive circuit 430 is longer than the pulse width (e.g., 10 μs) of the control signal Sci, and the pulses corresponding to the voltages Vai and Vbi overlap with the pulse of the control signal Sci on the time axis.

[0092] like Figure 7A As shown, during the setting period Psa1 of the positive half-cycle Cp1, transistor Msj is turned on because the control signal SCs has a high logic level. On the other hand, transistor Mgj is turned off because the control signal SCg has a low logic level. During the setting period Psa1, the reference voltage provided by the source drive circuit 430 is transmitted to the second terminal of the storage capacitor CS via transistor Msj and auxiliary source line Ssj. During the period of setting the reference voltage to the second terminal of the storage capacitor CS, transistor T1 is turned on according to the control signal SCi to transmit the voltage Vai provided by the source drive circuit 430 to the first terminal of the storage capacitor CS via source line Spj and transistor T1.

[0093] In some embodiments, the reference voltage may be implemented as 0 volts. In some embodiments, the reference voltage may be implemented as other values ​​less than or equal to voltage Vai, which is not a limitation of this disclosure. In other words, while the reference voltage provided by the source drive circuit 430 is transmitted to the second terminal of the storage capacitor CS, the potential of the first terminal of the storage capacitor CS (i.e., the potential of node N1) is set at voltage Vai, wherein voltage Vai is greater than or equal to 0 volts. Figure 6 Examples are shown where the voltage Vai is greater than 0 volts.

[0094] like Figure 7BAs shown, during the positive voltage period Ppv1 of the positive half-cycle Cp1, transistor Msj is turned off because the control signal SCs has a low logic level. On the other hand, transistor Mgj is turned on because the control signal SCg has a high logic level. During the positive voltage period Ppv1, transistor Mgj is turned on and grounds the second terminal of the storage capacitor CS. At this time, since transistor T1 turns off the path between the first terminal of the storage capacitor CS and the source line Spj, the potential of the first terminal of the storage capacitor CS (i.e., the potential of node N1) remains at voltage Vai. Therefore, the potential of the phase modulation electrode Ep is also voltage Vai, thereby controlling the alignment of the liquid crystal based on voltage Vai.

[0095] like Figure 7C As shown, during the setting period of Cn1 in Psb1, transistor Msj is turned on because the control signal SCs has a high logic level. On the other hand, transistor Mgj is turned off because the control signal SCg has a low logic level. During the setting period of Psb1, the voltage Vbi provided by the source drive circuit 430 is transmitted to the second terminal of the storage capacitor CS via transistor Msj and auxiliary source line Ssj, wherein the voltage Vbi is greater than or equal to 0 volts. Figure 6 An example is shown where the voltage Vbi is greater than 0 volts. During the period when the voltage Vbi is set to the second terminal of the storage capacitor CS, transistor T1 is turned on according to the control signal SCi to transfer the reference voltage (e.g., a 0-volt reference voltage) provided by the source drive circuit 430 via the source line Spj and transistor T1 to the first terminal of the storage capacitor CS. In other words, while the voltage Vbi provided by the source drive circuit 430 is transferred to the second terminal of the storage capacitor CS, the potential of the first terminal of the storage capacitor CS (i.e., the potential of node N1) is set to 0 volts, so that the potential of the first terminal of the storage capacitor CS is less than or equal to the potential of its second terminal.

[0096] like Figure 7D As shown, during the negative voltage period Pnv1 of the negative half-cycle Cn1, transistor Msj is turned off because the control signal SCs has a low logic level. On the other hand, transistor Mgj is turned on because the control signal SCg has a high logic level. During the negative voltage period Pnv1, transistor Mgj is turned on and grounds the second terminal of the storage capacitor CS. Since transistor T1 turns off the path between the first terminal of the storage capacitor CS and the source line Spj, the voltage change of the second terminal of the storage capacitor CS from voltage Vbi to ground potential (e.g., (0-Vbi) volts) is capacitively coupled to the first terminal of the storage capacitor CS. At this time, the potential of the first terminal of the storage capacitor CS (i.e., the potential of node N1) is represented by the voltage Vpi in the following formula.

[0097]

[0098] In the above formula, the capacitance value of the storage capacitor CS is expressed as C. S This indicates that the capacitance value of the liquid crystal capacitor CL is expressed in terms of C. L Therefore, during the negative voltage period Pnv1, the potential of the phase modulation electrode Ep is also a voltage Vpi less than or equal to 0 volts. Figure 6 (An example is shown where the voltage Vpi is less than 0 volts), and the liquid crystal alignment is controlled based on a voltage less than or equal to the voltage Vpi, thereby providing negative half-cycle operation, and thus avoiding liquid crystal inertial deformation based on a voltage greater than and / or equal to 0 volts provided by the source drive circuit 430.

[0099] Continuing, the next cycle C2 has a positive half-cycle Cp2 and a negative half-cycle Cn2. The positive half-cycle Cp2 has two periods, namely a set period Psa2 and a positive voltage period Ppv2. The negative half-cycle Cn2 has two periods, namely a set period Psb2 and a negative voltage period Pnv2.

[0100] During the setting period Psa2 of the positive half-cycle Cp2, the source drive circuit 430 transmits a voltage Vai' to node N1 via the source line Spi, and controls the potential of node N1 to be controlled at voltage Vai' and maintain it until the positive voltage period Ppv2 of the positive half-cycle Cp2. During the setting period Psb2 of the negative half-cycle Cn2, the source drive circuit 430 transmits a reference voltage (e.g., 0 volts) to node N1 via the source line Spi, and transmits a voltage Vbi' to the second terminal of the storage capacitor CS via the auxiliary source line Spi.

[0101] During the negative voltage period Pnv2 of the negative half-cycle Cn2, the second terminal of the storage capacitor CS is grounded, and the voltage change at the second terminal of the storage capacitor CS from the voltage Vbi' to the ground potential (e.g., (0-Vbi') volts) is capacitively coupled to the first terminal of the storage capacitor CS. At this time, the potential of the first terminal of the storage capacitor CS (i.e., the potential of node N1) is represented by the voltage Vpi' in the following formula.

[0102]

[0103] Thus, during the negative voltage period Pnv2, the potential of the phase modulation electrode Ep is also less than or equal to a voltage Vpi' of 0 volts, and based on a voltage Vpi' of less than or equal to 0 volts ( Figure 6 (Example shown: voltage Vpi' less than 0 volts) controls the alignment of the liquid crystal, thereby providing negative half-cycle operation, and thus avoiding inertial deformation of the liquid crystal based on a voltage greater than and / or equal to 0 volts provided by the source drive circuit 430.

[0104] The detailed operation of the phase-shifting circuit Pij in period C2 is similar to that in period C1, and will not be repeated here.

[0105] Please see Figure 8 , Figure 8 This is a schematic diagram of a phase control array 118 according to some embodiments of the present disclosure. In some embodiments, the phase control array 118 includes phase shifting circuits P11-P31 and P12-P32, which correspond to... Figure 4 The phase-shifting circuits P11 to Pn2. For example... Figure 8 As shown, phase shift circuits P11 to P31 are arranged in the first to third columns of the array, respectively. Phase shift circuits P11 to P31 each include transistors T11 to T31, storage capacitors CS11 to CS31, and phase modulation electrodes EP11 to EP31.

[0106] Specifically, the first terminals of transistors T11 to T31 are electrically coupled to the source line Sp1, and the gate terminals of transistors T11 to T31 are electrically coupled to gate lines G1 to G3, respectively, and receive the control signal SC1 via gate lines G1 to G3. The second terminals of transistors T11 to T31 are electrically coupled to the first terminals of storage capacitors CS11 to CS31 and phase modulation electrodes Ep11 to Ep31, respectively. The phase modulation electrodes Ep11 to Ep13 and the common electrodes Ec11 to Ec31 form liquid crystal capacitors CL11 to CL13. In some embodiments, the common electrodes Ec11 to Ec31 correspond to... Figure 1B as well as Figure 2 Part of the CCP electrode 114.

[0107] Similarly, phase-shifting circuits P12 to P32 are arranged in the first to third columns of the array, respectively. Each phase-shifting circuit includes transistors T12 to T32, storage capacitors CS12 to CS32, and phase modulation electrodes EP12 to EP32. Specifically, the first terminals of transistors T12 to T32 are electrically coupled to the source line Sp2, and the gate terminals of transistors T12 to T32 are electrically coupled to gate lines G1 to G3, respectively, and receive the control signal SC1 via gate lines G1 to G3.

[0108] The second terminals of transistors T12-T32 are electrically coupled to the first terminals of storage capacitors CS12-CS32 and phase modulation electrodes Ep12-Ep32, respectively. In some embodiments, nodes N12-N32 are located at the connection points between the phase modulation electrodes Ep12-Ep32 and the first terminals of the corresponding storage capacitors CS12-CS32. The phase modulation electrodes Ep12-Ep32 and the common electrodes Ec12-Ec32 form liquid crystal capacitors CL12-CL32. In some embodiments, the common electrodes Ec12-Ec32 correspond to... Figure 1B as well as Figure 2The portion of the common electrode 114. The connection relationship of the components in the phase shift circuits P12 to P32 is similar to that of the components in the phase shift circuits P11 to P31, and will not be described again here.

[0109] Please see Figure 4 , Figure 8 as well as Figure 9 , Figure 9 Provided in accordance with some embodiments of this disclosure Figure 8 The timing diagram shows the signal, voltage, and node potential changes of the phase-shifting circuits P11 to P31 in the phase control array 118. (See diagram for example.) Figure 9 As shown, one cycle of the control timing of the phase control array 118 can be divided into two half-cycles, namely the positive half-cycle Cp1 and the negative half-cycle Cn1. The positive half-cycle Cp1 has two periods, namely the setting period Psa1 and the positive voltage period Ppv1. The negative half-cycle Cn1 has two periods, namely the setting period Psb1 and the negative voltage period Pnv1.

[0110] During the setting period Psa1 of the positive half-cycle Cp1, transistors T11 to T31 are turned on in a column sequence according to control signals SC1 to SC3, thereby transmitting voltages Va1 to Va3 to the first terminals of storage capacitors CS11 to CS31 via the source line Sp1 in the column sequence. At this time, transistor Mg1 is turned off according to control signal SCg, and transistor Ms1 is turned on according to control signal SCs to transmit the reference voltage (e.g., 0 volts) provided by the source drive circuit 430 to the second terminals of storage capacitors CS11 to CS31.

[0111] During the positive voltage period Ppv1 of the positive half-cycle Cp1, transistors T11 to T31 are turned off according to control signals SC1 to SC3. At this time, transistor Ms1 is turned off according to control signal SCs, and transistor Mg1 is turned on according to control signal SCg to ground the second terminals of storage capacitors CS11 to CS31. Thus, the phase-shifting circuits P11 to P31 control the orientation of the liquid crystal based on the voltages Va1 to Va3 of the phase modulation electrodes Ep11 to Ep31, thereby modulating the direction and field pattern of the electromagnetic wave.

[0112] During the setting period of the negative half-cycle Cn1, Psb1, transistors T11 to T31 are turned on in a column sequence according to control signals SC1 to SC3, thereby transmitting a reference voltage (e.g., 0 volts) to the first terminal of storage capacitors CS11 to CS31 in the column sequence via source line Sp1. At this time, transistor Mg1 is turned off according to control signal SCg, and transistor Ms1 is turned on according to control signal SCs, so as to transmit the voltages Vb1 to Vb3 provided by the source drive circuit 430 to the second terminal of storage capacitors CS11 to CS31 via source line Ss1, thereby setting the voltage difference across storage capacitors CS11 to CS31 at (0-Vb1) volts, (0-Vb2) volts, and (0-Vb3) volts, respectively.

[0113] During the negative voltage period Pnv1 of the negative half-cycle Cn1, transistors T11 to T31 are turned off according to control signals SC1 to SC3. At this time, transistor Ms1 is turned off according to control signal SCs, and transistor Mg1 is turned on according to control signal SCg to ground the second terminals of storage capacitors CS11 to CS31. The voltage differences (0-Vb1), (0-Vb2), and (0-Vb3) between the second terminals of storage capacitors CS11 to CS31 from voltages Vb1 to Vb3 to the ground potential are capacitively coupled to the first terminals of storage capacitors CS11 to CS31. At this time, the voltages Vp1 to Vp3 at the first terminals of storage capacitors CS11 to CS31 (i.e., nodes N11 to N31) can be expressed by the following formula.

[0114]

[0115]

[0116]

[0117] In the above formula, since voltage Vb2 is taken as 0 volts, voltage Vp2 is equal to 0. Thus, during the negative voltage period Pnv1, the potentials of the phase modulation electrodes Ep11 to Ep31 are also voltages Vp1 to Vp3 less than or equal to 0 volts, and the liquid crystal alignment is controlled based on voltages Vp1 to Vp3 less than or equal to these voltages, thereby providing negative half-cycle operation. In some embodiments, since the source drive circuit 430 provides voltages Vb1 to Vb3 greater than or equal to 0 volts during the negative half-cycle Cn1 (…),… Figure 9 (An example is shown where voltages Vb1 and Vb3 are greater than 0 volts and voltage Vb2 is equal to 0 volts). The output of the source drive circuit 430 may not cover the range of negative voltage values.

[0118] Thus, during the positive voltage period Ppv1, the potentials of the phase modulation electrodes Ep11 to Ep31 are manipulated to positive voltage and / or ground voltage, and during the negative voltage period Pnv1, the potentials of the phase modulation electrodes Ep11 to Ep31 are manipulated to negative voltage and / or ground voltage through capacitive coupling effect, thereby avoiding liquid crystal inertial deformation.

[0119] In the positive half-cycle Cp2 of the next cycle, the source drive circuit 430 sequentially sets the voltages Va1' to Va3' to the first terminals of the storage capacitors CS11 to CS31, and continuously controls the potential of the first terminals of the storage capacitors CS11 to CS31 at the voltages Va1' to Va3'.

[0120] During the setting period of the negative half-cycle Cn2, Psb2, the source drive circuit 430 sequentially sets voltages Vb1' to Vb3' to the second terminals of storage capacitors CS11 to CS31, so that during the negative voltage period, Pnv2, based on the voltage drop at the second terminals of storage capacitors CS11 to CS31, causes the first terminals of storage capacitors CS11 to CS31 to have voltages Vp1' to Vp3' less than or equal to 0 volts. Figure 9 Examples are shown where voltages Vp1' and Vp3' are less than 0 volts and voltage Vp2' is equal to 0 volts.

[0121] The operation of the set periods Psa2 and Ppv2 in the positive half-cycle Cp2, and the set periods Psb2 and Pnv2 in the negative half-cycle Cn2, is similar to the operation of the set periods Psa1 and Ppv2 in the positive half-cycle Cp1, and the set periods Psb2 and Pnv2 in the negative half-cycle Cn2, and will not be elaborated further here. Figure 8 The operation of the phase shifting circuits P12 to P32 located in the second row of the phase control array 118 is similar to that of the phase shifting circuits P11 to P31 located in the first row of the phase control array 118, and will not be described again here.

[0122] Please refer to Figure 1. Figure 5 as well as Figure 10 , Figure 10 This is a cross-sectional view of a portion of the antenna device 100 of FIG1 according to some embodiments of the present disclosure. Figure 10 As shown, transistor T1 is formed on substrate 112b and faces liquid crystal layer 116. Common electrode 114 is formed on substrate 112t and faces liquid crystal layer 116. Liquid crystal layer 116 is located between substrate 112b and substrate 112t. A phase modulation electrode EP electrically coupled to the second terminal of transistor T1 and a portion of common electrode 114 form liquid crystal capacitor CL.

[0123] In some embodiments, a common electrode 114 is formed on a first side of a substrate 112t, and an adhesive BA is used to attach the first side of a feed plate 120 to a second side of the substrate 112t. In some embodiments, a microstrip feed line 122 is formed on the first side of the feed plate 120. Thus, the microstrip feed line 122 and the common electrode 114 form a microstrip antenna.

[0124] In summary, the liquid crystal phase shifter 110 and the feed board 120 of the antenna device 100 can reduce the manufacturing cost of conventional array antennas and the use of high-frequency transmission printed circuit boards. Furthermore, the common electrode 114 of the liquid crystal phase shifter 110 and the microstrip feed line 122 of the feed board 120 constitute a microstrip antenna, which can reduce size and manufacturing cost. Moreover, through the circuit architecture and control signal configuration of the antenna device 100 disclosed herein, positive and negative half-cycle operation can be provided without changing the voltage range of the source drive circuit 430, thereby avoiding liquid crystal inertial deformation.

[0125] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. A liquid crystal phase shifter, comprising: A first transistor, wherein a first terminal is electrically coupled to a source line, and a gate terminal is used to receive a first control signal; A storage capacitor, the first terminal of which is electrically coupled to the second terminal of the first transistor, and the second terminal of which is electrically coupled to an auxiliary source line; A phase modulation electrode is electrically coupled to the second terminal of the first transistor; and A common electrode is formed with the phase modulation electrode to form a liquid crystal capacitor, and the common electrode is used to receive a ground voltage, wherein the liquid crystal phase shifter is attached to a feed board, and wherein the common electrode of the liquid crystal phase shifter is used to form a microstrip antenna with a microstrip feed line of the feed board.

2. The liquid crystal phase shifter as described in claim 1, further comprising: A second transistor, the first terminal of which is used to receive the ground voltage, the second terminal of which is electrically coupled to the auxiliary source line, and the gate terminal of which is used to receive a second control signal; One source drive circuit; and A third transistor, the first terminal of which is electrically coupled to the auxiliary source line, the second terminal of which is electrically coupled to the source drive circuit, and the gate terminal of which is used to receive a third control signal.

3. The liquid crystal phase shifter as described in claim 2, wherein: During a first setting period of a positive half-cycle, the third transistor is turned on according to the third control signal to transmit a reference voltage provided by the source drive circuit to the second terminal of the storage capacitor via the third transistor and the auxiliary source line. During the period when the reference voltage is set to the second terminal of the storage capacitor, the first transistor is turned on according to the first control signal to transmit a first voltage provided by the source drive circuit to the first terminal of the storage capacitor via the source line and the first transistor. as well as During a second setting period of a negative half-cycle, the third transistor is turned on according to the third control signal to transmit a second voltage provided by the source drive circuit to the second terminal of the storage capacitor via the third transistor and the auxiliary source line. During the period when the second voltage is set to the second terminal of the storage capacitor, the first transistor is turned on according to the first control signal to transmit the reference voltage provided by the source drive circuit to the first terminal of the storage capacitor via the source line and the first transistor.

4. The liquid crystal phase shifter of claim 3, wherein the first voltage and the second voltage provided by the source driving circuit are greater than or equal to the reference voltage, and wherein the reference voltage is 0 volts.

5. The liquid crystal phase shifter of claim 3, wherein during a positive voltage period of the positive half-cycle and during a negative voltage period of the negative half-cycle, the first transistor is turned off according to the first control signal, the third transistor is turned off according to the third control signal, and the second transistor is turned on according to the second control signal to transmit the ground voltage to the second terminal of the storage capacitor, and wherein during the negative voltage period of the negative half-cycle, a voltage change from the second voltage to the ground voltage at the second terminal of the storage capacitor is capacitively coupled to the first terminal of the storage capacitor.

6. A liquid crystal phase shifter, comprising: A phase control array, comprising: Multiple first phase-shifting circuits are arranged in multiple columns of an array. These first phase-shifting circuits include multiple first transistors, multiple first storage capacitors, and multiple first phase modulation electrodes electrically coupled to first terminals of the first storage capacitors. A first source line is electrically coupled to the first terminal of the first transistors, wherein the second terminals of the first transistors are electrically coupled to the first terminals of the first storage capacitors respectively. as well as A first auxiliary source line is electrically coupled to the second terminal of the first storage capacitors; as well as A common electrode is formed with the first phase modulation electrodes to form a plurality of first liquid crystal capacitors, wherein the common electrode is used to receive a ground voltage.

7. The liquid crystal phase shifter of claim 6, wherein the gate terminals of the first transistors are respectively used to receive a plurality of first control signals, wherein the phase control array further comprises: A second transistor, wherein a first terminal is used to receive the ground voltage, a second terminal is electrically coupled to the first auxiliary source line, and a gate terminal is used to receive a second control signal. One source drive circuit; and A third transistor, the first terminal of which is electrically coupled to the first auxiliary source line, the second terminal of which is electrically coupled to the source drive circuit, and the gate terminal of which is used to receive a third control signal.

8. The liquid crystal phase shifter of claim 7, wherein the phase control array further comprises: Multiple second phase-shifting circuits are arranged in the columns of the array, wherein each second phase-shifting circuit includes multiple fourth transistors, multiple second storage capacitors, and multiple second phase modulation electrodes electrically coupled to the first terminals of the second storage capacitors, wherein the common electrode and the second phase modulation electrodes form multiple second liquid crystal capacitors, and wherein the gate terminals of the fourth transistors are respectively used to receive the first control signals. A second source line is electrically coupled to the first terminal of these fourth transistors; A second auxiliary source line is electrically coupled to the second terminal of the second storage capacitors, and the source drive circuit is electrically coupled to the second source line and the second auxiliary source line.

9. An antenna device comprising: A power supply board, comprising: A circuit board; A microstrip feeder; and A ground plane, wherein the ground plane and the microstrip feed line are disposed on opposite sides of the circuit board; and The liquid crystal phase shifter according to claim 6 is attached to the feed board and covers a portion of the microstrip feed line, wherein the liquid crystal phase shifter comprises: First substrate; A phase control array is formed on the first substrate; One liquid crystal layer; A second substrate; and A common electrode is formed on the second substrate, wherein the liquid crystal layer is disposed between the phase control array and the common electrode, wherein the common electrode is electrically coupled to the ground layer, and wherein the common electrode of the liquid crystal phase shifter is used to form a microstrip antenna with a microstrip feed line of the feed board.

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