A negative pressure wide frequency band high PSRR low dropout linear voltage regulator

Abstract

The present application belongs to the technical field of power management chip in analog integrated circuit, in particular to a low-dropout linear regulator with negative voltage wideband high PSRR, comprising: by making the power loop and the output voltage reference loop into cascade, the output pole of the error operational amplifier in the output voltage reference loop is pushed to high frequency, and a step-down regulator is added in the front-stage bias, the former realizes wideband high PSRR, and the latter further increases PSRR, the effects of the two are superimposed, good PSRR and its wideband performance are realized, and making the power loop and the output voltage reference loop into cascade also realizes the target of high DC PSRR in the full load range, the present application does not need complex compensation technology, the technology can be used in low-dropout linear regulator, and good wideband high power suppression application is realized.

Description

Technical Field

[0001] This invention belongs to the field of power management chip technology in analog integrated circuits, and specifically relates to a low dropout linear regulator with negative voltage wideband and high PSRR. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in portable electronic devices, wearable applications, and system-on-a-chip (SoC) applications due to their excellent regulation performance and small size. Traditional negative pressure LDOs are shown in the attached diagram. Figure 1 As shown, to achieve good PSRR (Power Supply Rejection Ratio) performance, the open-loop gain of the error op-amp in the power regulation loop is usually greatly increased. However, increasing the gain of the error op-amp will cause a decrease in loop stability. At this time, the circuit needs to enhance the dominant pole at the cost of bandwidth or use more complex compensation techniques to improve stability. At the same time, for excellent LDOs, the bandwidth of the load range is crucial. However, under heavy full load, the output pole is located at a high frequency. At this time, the dominant pole of the power loop is located at the output of the error op-amp. The circuit's PSRR performance deteriorates first, and the high PSRR bandwidth is narrow. That is, the left zero point at the same position as the output pole of the error op-amp first appears in the circuit's PSR transfer function. The output pole of the error op-amp in the transfer function will be pushed to a higher frequency point by the negative feedback power loop (frequency point increases by 1+A). LOOP (Times). In other words, the attenuation of the gain of the error op-amp in the power loop has the primary dominant effect on PSRR. In addition, traditional negative voltage LDOs will experience a decrease in PSRR performance as the load increases, due to the increase in the drive bias current of the power transistor and the decrease in loop gain. Summary of the Invention

[0003] To address the problems existing in the background technology, this invention provides a low-dropout linear regulator with a negative voltage wideband and high PSRR. By cascading the power loop and the output voltage reference loop, the output pole of the error operational amplifier in the output voltage reference loop is pushed to a high frequency. Simultaneously, a buck regulator is added to the pre-stage bias, achieving good PSRR and wideband performance without the need for complex compensation techniques. This technology can be used in low-dropout linear regulators to achieve good wideband high power supply rejection applications. The regulator includes: a buck regulator REG, a low-voltage bandgap reference, error operational amplifiers EA0 and EA1, and a load resistor analog R. OUT MOSFET MPA, MOSFET MP2, resistor RF1, resistor RF2, resistor RREG, resistor Rref, capacitor CREG, capacitor Cref, capacitor CA, and capacitor CL;

[0004] The power input terminal of the buck regulator REG, the power input terminal of the error operational amplifier EA1, the source of MPA, the source of MP2, and the VIN terminal are connected by wires; the internal power output terminal of the buck regulator REG, one end of the capacitor CREG, one end of the resistor RREG, the power input terminal of the low-voltage bandgap reference, and the internal power input terminal of the error operational amplifier EA1 are connected by wires; the enable input terminal and the EN terminal of the low-voltage bandgap reference are connected by wires.

[0005] The reference output terminal of the low-voltage bandgap reference, one end of the resistor Rref, the enable input terminal of the buck regulator REG, one end of the capacitor Cref, and the negative input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA1 and the gate of the MPA are connected by a wire; the drain of the MPA, one end of the resistor RF1, one end of the capacitor CA, and the negative input terminal of the error operational amplifier EA0 are connected by a wire; the other end of the resistor RF1, one end of the resistor RF2, and the positive input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA0 and the gate of the MP2 are connected by a wire; the drain of the MP2, the positive input terminal of the error operational amplifier EA0, and the load resistor analog R... OUT One end of the capacitor, one end of capacitor CL, and VOUT are connected by a wire;

[0006] The other ends of resistor Rref, capacitor Cref, resistor RF2, capacitor CREG, resistor RREG, capacitor CL, capacitor CA, and the load resistor simulating R OUT The other end is grounded.

[0007] Preferably, the MOS transistors MPA and MP2 are N-channel MOS transistors.

[0008] Preferably, the load resistance simulates R. OUT include:

[0009] Current source IBIAS, resistor RB1, MOSFET MB1, MOSFET MB2, MOSFET MB3, MOSFET MB4 and resistor RL;

[0010] The positive terminal of current source IBIAS and the VIN terminal are connected by a wire; the negative terminal of current source IBIAS, one end of resistor RB1, the gate of MB1 and the gate of MB4 are connected by a wire; the other end of resistor RB1, the drain of MB1, the gate of MB2 and the gate of MB3 are connected by a wire; the source of MB1 and the drain of MB2 are connected by a wire; the source of MB2, the source of MB3 and one end of resistor RL are grounded; the drain of MB3 and the source of MB4 are connected by a wire; the drain of MB4, the other end of resistor RL and the VOUT terminal are connected by a wire.

[0011] Preferably, MOSFETs MB1, MB2, MB3 and MB4 are P-channel MOSFETs.

[0012] Preferably, the error operational amplifier EA0 includes: resistors R1, R2, Rb, Rg, and Rf; capacitors Cc and Cf; MOSFETs MP1, Mg, and Mf; and the error operational amplifier EAP.

[0013] One end of resistor R1, one end of resistor R2, and VOUT terminal are connected by a wire; the other end of resistor R1, one end of capacitor Cc, and the drain of MP1 are connected by a wire; the other end of resistor R2, the other end of capacitor Cc, and the negative input terminal of error operational amplifier EAP are connected by a wire; the gate of MP1, the drain of Mg, one end of resistor Rg, and the gate of MP2 are connected by a wire; the source of MP1 and one end of resistor Rb are connected by a wire; the other end of resistor Rb, the other end of resistor Rg, and VIN terminal are connected by a wire; the source of Mg and the source of Mf are grounded; the drain of Mf and one end of capacitor Cf are connected by a wire; the other end of capacitor Cf, the gate of Mf, and one end of resistor Rf are connected by a wire; the gate of Mg, the other end of resistor Rf, and the output terminal of error operational amplifier EAP are connected by a wire; the positive input terminal and VA terminal of error operational amplifier EAP are connected by a wire.

[0014] Preferably, MOS transistor MP1 is an N-channel MOS transistor; MOS transistors Mg and Mf are P-channel MOS transistors.

[0015] Preferably, the error operational amplifier EA1 includes: a current source ISS, resistors REA1, REA2, REA3, REA4, REA5, REAC, capacitor CEAC, and MOSFETs MEA1 to MEA10;

[0016] The negative terminal of current source ISS, one end of resistor REA1, one end of resistor REA2, one end of resistor REA3, and one end of resistor REAC are grounded;

[0017] The positive terminal of the current source ISS, one end of resistor REA5, the gate of MEA2, and the gate of MEA4 are connected by a wire; the other end of resistor REA5, the drain of MEA2, the gate of MEA1, and the gate of MEA3 are connected by a wire; the source of MEA2 and the drain of MEA1 are connected by a wire; the source of MEA4 and the drain of MEA3 are connected by a wire; the source of MEA3, the source of MEA1, and the internal power input terminal of EA1 are connected by a wire.

[0018] The other end of resistor REA1 is connected to the source of MEA7 via a wire; the other end of resistor REA2 is connected to the source of MEA8 via a wire; the gate of MEA7, the gate of MEA8, the drain of MEA7, and the drain of MEA5 are connected via a wire; the other end of resistor REAC is connected to one end of capacitor CEAC via a wire; the other end of resistor REA3 is connected to the source of MEA9 via a wire; the gate of MEA9, the other end of capacitor CEAC, the drain of MEA8, and the drain of MEA6 are connected via a wire; the gate of MEA5 is connected to the negative input terminal of EA1 via a wire; the gate of MEA6 is connected to the positive input terminal of EA1 via a wire; the source of MEA5, the source of MEA6, and the drain of MEA4 are connected via a wire; the drain of MEA9 is connected to one end of resistor REA4 via a wire; the other end of resistor REA4, the drain of MEA10, the gate of MEA10, and the output terminal of EA1 are connected via a wire; the source of MEA10 and the power input terminal of EA1 are connected via a wire.

[0019] Preferably, MOSFETs MEA1 to MEA6 and MEA10 are N-channel MOSFETs; MOSFETs MEA7 to MEA9 are P-channel MOSFETs.

[0020] Preferably, the buck regulator REG includes: resistor Rr1, resistor Rr2, current source IB1, error operational amplifier AREG, MOSFET Mr1, MOSFET Mr2, MOSFET MRP1 and MOSFET MRP2;

[0021] The negative terminal of current source IB1 and one end of resistor Rr1 are grounded; the other end of resistor Rr1, one end of resistor Rr2, and the positive input terminal of error operational amplifier AREG are connected by a wire; the negative input terminal of error operational amplifier AREG is connected to the enable input terminal of buck regulator REG; the other end of resistor Rr2, the drain of MRP1, and the internal power output terminal of buck regulator REG are connected by a wire; the gate of MRP1, the gate of MRP2, the drain of MRP2, the output terminal of error operational amplifier AREG, and the drain of Mr2 are connected by a wire; the source of MRP1, the source of MRP2, the source of Mr2, the source of Mr1, and the power input terminal of buck regulator REG are connected by a wire; the gate of Mr2, the gate of Mr1, the drain of Mr1, and the positive terminal of current source IB1 are connected by a wire.

[0022] Preferably, MOSFETs Mr1, Mr2, MRP1, and MRP2 are N-channel MOSFETs.

[0023] The present invention has at least the following beneficial effects

[0024] The negative voltage LDO of this invention cascades the power loop and the output voltage reference loop, pushes the output pole of the error operational amplifier in the output voltage reference loop to a high frequency, and adds a buck regulator in the pre-stage bias. The former achieves wideband high PSRR, while the latter further increases PSRR. The combined effect of the two achieves good wideband high power supply rejection performance. At the same time, cascading the power loop and the output voltage reference loop also achieves the goal of high DC PSRR across the entire load range. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the traditional negative pressure LDO principle;

[0026] Figure 2 This is a schematic diagram of the negative pressure wideband high PSRR LDO proposed in this invention;

[0027] Figure 3 This is a schematic diagram of the LDO power loop proposed in this invention;

[0028] Figure 4 This is a schematic diagram of the LDO voltage reference loop EA1 proposed in this invention;

[0029] Figure 5 The schematic diagram of the LDO step-down regulator REG proposed in this invention;

[0030] Figure 6 A simulation diagram of a traditional negative pressure LDO PSR@500mA;

[0031] Figure 7 This is a simulation diagram of the negative pressure LDO PSR@500mA proposed in this invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0033] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0035] Please see Figure 1 , Figure 1 The main structure of a traditional negative voltage LDO consists of a low-voltage bandgap reference, an error operational amplifier EA1, and a power transistor M. PA , resistive feedback network and output capacitor C L Composition, resistance R L Used to simulate the output load. The equivalent output of the low-voltage bandgap reference is a capacitor C. ref With a resistor R ref Let the DC gain of the internal negative feedback loop of the low-voltage bandgap reference be A. loop,ref The secondary pole is p ref The power transistor's transconductance gain is g mp,ref The gain PSR from the power supply to the low-voltage reference output is... ref for:

[0036]

[0037] because have

[0038]

[0039] Because the output poles of low-voltage bandgap references are often filtered for noise, their frequencies are much lower than those of the secondary poles. In this case, the loop is approximately single-stage, and the reference's PSR... ref exist The frequency point becomes better when it turns downward.

[0040] For the output, the gain path obtained from the power supply includes the power transistor M. PA The error op-amp EA1 bias and the low-voltage reference input at the differential terminal of the op-amp. The power supply gain of the power transistor path is:

[0041]

[0042] A loop,MPA =BA EA1 g mpA R OUT (4)

[0043]

[0044] R OUT =R L / / r ds,MPA / / (R F1 +R F2 (6)

[0045] Among them, g mpA With r ds,MPA These are power transistors M and M respectively. PA transconductance and channel modulation resistance, p EA1 A EA1 For the output poles and gain of the power loop error op-amp EA1, R F1 R F2 For the feedback resistor, A loop,MPA This represents the DC gain of the power loop.

[0046] The total gain from power supply to output is PSR. OUT for:

[0047]

[0048] Among them, PSR AE1 Let M be the power supply gain of the single-module unit buffer of the error op-amp EA1. From equation (6), it can be seen that the bias of the error op-amp EA1 and the power supply rejection of the low-voltage reference input at the differential terminal of the op-amp gradually improve with the effect of the power loop poles. As long as its DC PSRR is high enough, it will not affect the wide bandwidth of high PSRR. Therefore, the power supply gain path that restricts the high PSRR of the wide bandwidth is the power transistor M. PA At this point, the total gain from power supply to output, PSR, is... OUT Simplified to

[0049]

[0050] For power loops, the output poles increase in frequency with increasing load, especially under heavy full load. To ensure loop stability, the output pole of the error op-amp in the power loop is usually designated as the dominant pole or a strong secondary pole to prevent a sharp deterioration in stability due to increased bandwidth. Under heavy full load... When, then equation (8) can be simplified to

[0051]

[0052] At this time, PSR OUT In the transfer function, p appears first. EA1 The left zero at the frequency point, the original loop's main pole p EA1 Due to the negative feedback of this loop, it decays to a higher frequency (1+A).loop,MPA )p EA1 Then PSR OUT The frequency band begins to deteriorate from the left zero point, and the high PSRR frequency band is restricted.

[0053] When the intermediate load, When the output pole is equivalent to the output pole of the error op-amp, then equation (8) can be simplified to:

[0054]

[0055] At this time, PSR OUT In the transfer function, p still appears first. EA1 The left zero at the frequency point, followed by the appearance of a conjugate complex pole, still retains the original loop's dominant pole p. EA1 (or The frequency decays to higher frequencies due to the negative feedback of this loop. or Then PSR OUT It still starts to deteriorate from the left zero point, and the high PSRR band is restricted.

[0056] As the load continues to lighten, and PSR OUT In the transfer function, p still appears first. EA1 The left zero at the frequency point, and then the pole appears again, still retaining the original loop's main pole p. EA1 (or The PSR attenuates to higher frequencies due to the negative feedback of this loop, while... OUT It still starts to deteriorate from the left zero point, and the high PSRR band is still constrained.

[0057] In summary, in the traditional negative-voltage LDO output power gain PSR transfer function, because the output pole of the error op-amp in the power loop is relatively low-frequency, the left zero point (at the same frequency as the error op-amp output pole) in its transfer function will appear before the dominant pole attenuated by the power negative feedback loop. Therefore, the output PSR begins to deteriorate at the error op-amp output pole, ultimately making it difficult to achieve a wide bandwidth for high PSRR.

[0058] To address the aforementioned problems, this invention cascades the power loop and the output voltage reference loop, pushing the output pole of the error operational amplifier in the output voltage reference loop to a high frequency, with the loop output serving as a constant low-frequency dominant pole. A unit-buffered power loop is then cascaded in the next stage, and a buck regulator is added to the pre-stage bias, as shown in the attached diagram. Figure 2 As shown.

[0059] Please see Figure 2This invention provides a low-dropout linear regulator with negative voltage, wide bandwidth, and high PSRR, comprising: a buck regulator REG, a low-voltage bandgap reference, an error operational amplifier EA0, an error operational amplifier EA1, and a load resistor analog R. OUT MOSFET MPA, MOSFET MP2, resistor RF1, resistor RF2, resistor RREG, resistor Rref, capacitor CREG, capacitor Cref, capacitor CA, and capacitor CL;

[0060] The power input terminal of the buck regulator REG, the power input terminal of the error operational amplifier EA1, the source of MPA, the source of MP2, and the VIN terminal are connected by wires; the internal power output terminal of the buck regulator REG, one end of the capacitor CREG, one end of the resistor RREG, the power input terminal of the low-voltage bandgap reference, and the internal power input terminal of the error operational amplifier EA1 are connected by wires; the enable input terminal and the EN terminal of the low-voltage bandgap reference are connected by wires.

[0061] The reference output terminal of the low-voltage bandgap reference, one end of the resistor Rref, the enable input terminal of the buck regulator REG, one end of the capacitor Cref, and the negative input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA1 and the gate of the MPA are connected by a wire; the drain of the MPA, one end of the resistor RF1, one end of the capacitor CA, and the negative input terminal of the error operational amplifier EA0 are connected by a wire; the other end of the resistor RF1, one end of the resistor RF2, and the positive input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA0 and the gate of the MP2 are connected by a wire; the drain of the MP2, the positive input terminal of the error operational amplifier EA0, and the load resistor analog R... OUT One end of the capacitor, one end of capacitor CL, and VOUT are connected by a wire;

[0062] The other ends of resistor Rref, capacitor Cref, resistor RF2, capacitor CREG, resistor RREG, capacitor CL, capacitor CA, and the load resistor simulating R OUT The other end is grounded.

[0063] Preferably, the MOS transistors MPA and MP2 are N-channel MOS transistors.

[0064] Please see Figure 3 In the specific circuit of the power loop of the present invention, preferably, the load resistor simulates R. OUT include:

[0065] Current source IBIAS, resistor RB1, MOSFET MB1, MOSFET MB2, MOSFET MB3, MOSFET MB4 and resistor RL;

[0066] The positive terminal of current source IBIAS and the VIN terminal are connected by a wire; the negative terminal of current source IBIAS, one end of resistor RB1, the gate of MB1 and the gate of MB4 are connected by a wire; the other end of resistor RB1, the drain of MB1, the gate of MB2 and the gate of MB3 are connected by a wire; the source of MB1 and the drain of MB2 are connected by a wire; the source of MB2, the source of MB3 and one end of resistor RL are grounded; the drain of MB3 and the source of MB4 are connected by a wire; the drain of MB4, the other end of resistor RL and the VOUT terminal are connected by a wire.

[0067] Preferably, MOSFETs MB1, MB2, MB3 and MB4 are P-channel MOSFETs.

[0068] Preferably, the error operational amplifier EA0 includes: resistors R1, R2, Rb, Rg, and Rf; capacitors Cc and Cf; MOSFETs MP1, Mg, and Mf; and the error operational amplifier EAP.

[0069] One end of resistor R1, one end of resistor R2, and VOUT terminal are connected by a wire; the other end of resistor R1, one end of capacitor Cc, and the drain of MP1 are connected by a wire; the other end of resistor R2, the other end of capacitor Cc, and the negative input terminal of error operational amplifier EAP are connected by a wire; the gate of MP1, the drain of Mg, one end of resistor Rg, and the gate of MP2 are connected by a wire; the source of MP1 and one end of resistor Rb are connected by a wire; the other end of resistor Rb, the other end of resistor Rg, and VIN terminal are connected by a wire; the source of Mg and the source of Mf are grounded; the drain of Mf and one end of capacitor Cf are connected by a wire; the other end of capacitor Cf, the gate of Mf, and one end of resistor Rf are connected by a wire; the gate of Mg, the other end of resistor Rf, and the output terminal of error operational amplifier EAP are connected by a wire; the positive input terminal and VA terminal of error operational amplifier EAP are connected by a wire.

[0070] In this embodiment, the no-load bias module ensures normal output even when no load is connected, and is equivalent to the internal minimum load. To avoid affecting the output impedance and quiescent current, the bias current value should be set to a small value. Power transistor M P2 The number of M P1 K times, its function is to connect the pseudo-ESR resistor R2 with the output load capacitor C L The resulting left zero point is increased by a factor of K. This improves phase margin by relatively sacrificing bandwidth, avoiding the influence of high-frequency poles in the bandwidth area. This left zero is used to compensate for higher-frequency poles in or within the bandwidth area. Meanwhile, M... f C f R fGenerates a left zero and a lower frequency pole (EA) that follow the load current. P Output pole, EA P The power loop error op-amp EA1 is a rail-to-rail op-amp, i.e.:

[0071]

[0072] The resulting left zero can compensate for a low-frequency secondary pole in the bandwidth: that is, under light load, the dominant pole is on the output, EA. P Left zero compensation EA on the output P The effect of the output secondary pole; under heavy load, the dominant pole is at EA. P In terms of output, EA P The secondary pole (output pole) in the left-zero compensation loop at the output end is a follower compensation. Cc is a feedforward capacitor used to generate the left zero of the pseudo-ESR resistor R2 and the output capacitor. Cc itself introduces a pair of zero-pole pairs, which cancel each other out. The left zero generated by the pseudo-ESR resistor R2 is used to compensate for high-frequency poles in the bandwidth of the loop. Its compensation core is EA. P The output follows the left zero, which can compensate for the influence of the loop's secondary pole. Simultaneously, by introducing a feedforward pseudo-ESR left zero, the influence of higher-frequency poles in the bandwidth can be compensated, and the Q value can also be optimized, thus providing EA. P The design of the top left zero point of the output provides more space.

[0073] Preferably, MOS transistor MP1 is an N-channel MOS transistor; MOS transistors Mg and Mf are P-channel MOS transistors.

[0074] Please see Figure 4 The present invention provides a specific circuit for the voltage reference loop EA1. Preferably, the error operational amplifier EA1 includes: a current source ISS, resistors REA1, REA2, REA3, REA4, REA5, REAC, capacitor CEAC, and MOSFETs MEA1 to MEA10.

[0075] The negative terminal of current source ISS, one end of resistor REA1, one end of resistor REA2, one end of resistor REA3, and one end of resistor REAC are grounded;

[0076] The positive terminal of the current source ISS, one end of resistor REA5, the gate of MEA2, and the gate of MEA4 are connected by a wire; the other end of resistor REA5, the drain of MEA2, the gate of MEA1, and the gate of MEA3 are connected by a wire; the source of MEA2 and the drain of MEA1 are connected by a wire; the source of MEA4 and the drain of MEA3 are connected by a wire; the source of MEA3, the source of MEA1, and the internal power input terminal of EA1 are connected by a wire.

[0077] The other end of resistor REA1 is connected to the source of MEA7 via a wire; the other end of resistor REA2 is connected to the source of MEA8 via a wire; the gate of MEA7, the gate of MEA8, the drain of MEA7, and the drain of MEA5 are connected via a wire; the other end of resistor REAC is connected to one end of capacitor CEAC via a wire; the other end of resistor REA3 is connected to the source of MEA9 via a wire; the gate of MEA9, the other end of capacitor CEAC, the drain of MEA8, and the drain of MEA6 are connected via a wire; the gate of MEA5 is connected to the negative input terminal of EA1 via a wire; the gate of MEA6 is connected to the positive input terminal of EA1 via a wire; the source of MEA5, the source of MEA6, and the drain of MEA4 are connected via a wire; the drain of MEA9 is connected to one end of resistor REA4 via a wire; the other end of resistor REA4, the drain of MEA10, the gate of MEA10, and the output terminal of EA1 are connected via a wire; the source of MEA10 and the power input terminal of EA1 are connected via a wire.

[0078] Preferably, MOSFETs MEA1 to MEA6 and MEA10 are N-channel MOSFETs; MOSFETs MEA7 to MEA9 are P-channel MOSFETs.

[0079] In this embodiment, the operational amplifier's tail current adopts a common-source, common-gate structure to improve the efficiency due to V. REG Contribution to power supply suppression, R EAC C EAC The generated left zero is used to compensate for high-frequency poles. This frequency should not be set too low, otherwise it will generate even lower-frequency parasitic poles, which is detrimental to wideband high PSRR designs. Simultaneously, adding a buffer stage pushes the first-stage pole of the op-amp to a higher frequency, thus reducing the required driving frequency (M). EA9 The gate capacitor; the low-resistance diode connection of the current mirror in the buffer stage also pushes the regulating transistor M further away. PA The gate pole. To make V A Since the output pole is at a low frequency, the buffer stage transistor is designed as an inverting ratio transistor to increase the output impedance. Because the buffer stage is directly connected to the power input, V needs to be increased. EA1OUT Point to M EA9 The impedance to ground in the direction of R, i.e., the introduction of R EA3 R EA4 Using M EA9 Source-series negative feedback is used to increase impedance, i.e., R 等效 =R EA4 +g mEA9 r EA9 R EA3 Then V IN To V A Buffer stage transconductance gain (V A (Base loop feedback open loop) Easy to know V EA1OUT Point to M EA9 The greater the equivalent impedance to ground in the direction, the greater the impedance from the buffer stage to V. A The better the transconductance power supply suppression.

[0080] Please see Figure 5 Preferably, the buck regulator REG includes: resistor Rr1, resistor Rr2, current source IB1, error operational amplifier AREG, MOSFET Mr1, MOSFET Mr2, MOSFET MRP1 and MOSFET MRP2;

[0081] The negative terminal of current source IB1 and one end of resistor Rr1 are grounded; the other end of resistor Rr1, one end of resistor Rr2, and the positive input terminal of error operational amplifier AREG are connected by a wire; the negative input terminal of error operational amplifier AREG is connected to the enable input terminal of buck regulator REG; the other end of resistor Rr2, the drain of MRP1, and the internal power output terminal of buck regulator REG are connected by a wire; the gate of MRP1, the gate of MRP2, the drain of MRP2, the output terminal of error operational amplifier AREG, and the drain of Mr2 are connected by a wire; the source of MRP1, the source of MRP2, the source of Mr2, the source of Mr1, and the power input terminal of buck regulator REG are connected by a wire; the gate of Mr2, the gate of Mr1, the drain of Mr1, and the positive terminal of current source IB1 are connected by a wire.

[0082] In this embodiment, the design concept is the same as that of the voltage reference loop EA1 module. Both introduce an intermediate buffer stage on the first stage output of the internal operational amplifier to push the output pole of the first stage of the operational amplifier to a high frequency, so that the output pole of the module is the low-frequency dominant pole and is a single-stage point approximation, in order to prevent the module from damaging the high PSRR band.

[0083] Preferably, MOSFETs Mr1, Mr2, MRP1, and MRP2 are N-channel MOSFETs.

[0084] The step-down regulator added in this invention has an equivalent output of a capacitor C. REG With a resistor R REG Let the DC gain of the internal negative feedback loop of the buck regulator be A. loop,REG The secondary pole is p REG The power transistor's transconductance gain is g mp,REG ,because The gain PSR from the power supply to the buck regulator output is... REG for

[0085]

[0086] Because the output pole of a buck regulator is often filtered for noise, its frequency is much lower than that of the secondary pole. In this case, the single-stage point of the loop is approximately equal to the output PSR of the regulator. REG exist The frequency point becomes better when it turns downward.

[0087] Then the power supply to output voltage reference loop outputs V A gain PSR VA for

[0088]

[0089] R OUT1 =r ds,MPA / / (R F1 +R F2 (13)

[0090] A loop,MPA1 =BA EA1 g mpA R OUT1 (14)

[0091] Where C A The output voltage reference V A The output capacitor.

[0092] The buck regulator module further improves the power supply rejection ratio (PSR) of the error op-amp EA1 bias and the low-voltage reference input at the op-amp differential, especially reducing their contribution to the output PSR at low frequencies, meaning that it still has...

[0093]

[0094] At this time, the output voltage reference V A The output impedance is constant: R OUT1 =r ds,MPA / / (R F1 +R F2 Since it is independent of the load, the output voltage reference V A The pole is always the low-frequency dominant pole, and the output pole p of the error op-amp EA1 is also set to the low-frequency dominant pole. EA1 Set at high frequency, i.e. Then there is

[0095]

[0096] Output voltage reference loop V A The output frequency is always far lower than the output subpole p of the error op-amp EA1. EA1 At this point, the loop is approximated as a single-stage point, and the output voltage reference V A PSR VA exist The frequency point becomes better when it turns downward.

[0097] A power loop with a unit buffer is cascaded in subsequent stages to drive the load. Let g mp2 With r ds,MP2 These are the power transistors M and M respectively. P2 transconductance and channel modulation resistance, p EA0 A EA0 Let EA0 be the output pole and gain of the power loop error op-amp. Then the total power-to-output gain PSR is... OUT for

[0098]

[0099] As can be seen from equation (17), the negative voltage LDO of the present invention has a total gain PSR from power supply to output. OUT In the transfer function, the poles always appear first, and are independent of the load. This means that the power supply rejection of the output can be improved first over a large full load range, i.e., wide bandwidth high PSRR, without having to make a trade-off between stability and wide bandwidth high PSRR.

[0100] Please see Figure 6 The simulation results show the PSR of a traditional LDO with a 500mA load at three temperatures: -55℃, 25℃, and 125℃. The simulations cover the PSR at different frequency points. Figure 7 The simulation diagrams show the PSR of the LDO proposed in this invention under three temperature conditions: -60℃, 25℃, and 130℃, with a 500mA load. The simulations show the PSR at different frequency points. Therefore, the negative voltage wideband high PSRR low dropout linear regulator of this invention utilizes a cascaded power loop and an output voltage reference loop. The output pole of the error operational amplifier in the output voltage reference loop is pushed to a high frequency, and the loop output serves as a constant low-frequency dominant pole. A power loop with a unit buffer is then cascaded in the next stage, and a buck regulator is added in the pre-stage bias. This achieves good PSRR and wideband performance without the need for complex stability compensation techniques, and can be applied to LDO applications with a large load range.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A low-dropout linear regulator with negative voltage wideband and high PSRR, characterized in that, include: The components include: buck regulator REG, low-voltage bandgap reference, error op-amp EA0, error op-amp EA1, load resistor analog ROUT, MOSFET MPA, MOSFET MP2, resistor RF1, resistor RF2, resistor RREG, resistor Rref, capacitor CREG, capacitor Cref, capacitor CA, and capacitor CL. The power input terminal of the buck regulator REG, the power input terminal of the error operational amplifier EA1, the source of MPA, the source of MP2, and the VIN terminal are connected by wires; the internal power output terminal of the buck regulator REG, one end of the capacitor CREG, one end of the resistor RREG, the power input terminal of the low-voltage bandgap reference, and the internal power input terminal of the error operational amplifier EA1 are connected by wires; the enable input terminal and the EN terminal of the low-voltage bandgap reference are connected by wires. The reference output terminal of the low-voltage bandgap reference, one end of the resistor Rref, the enable input terminal of the buck regulator REG, one end of the capacitor Cref, and the negative input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA1 and the gate of the MPA are connected by a wire; the drain of the MPA, one end of the resistor RF1, one end of the capacitor CA, and the negative input terminal of the error operational amplifier EA0 are connected by a wire; the other end of the resistor RF1, one end of the resistor RF2, and the positive input terminal of the error operational amplifier EA1 are connected by a wire; the output terminal of the error operational amplifier EA0 and the gate of the MP2 are connected by a wire; the drain of the MP2, the positive input terminal of the error operational amplifier EA0, one end of the load resistor analog ROUT, one end of the capacitor CL, and the VOUT terminal are connected by a wire. The other end of resistor Rref, capacitor Cref, resistor RF2, capacitor CREG, resistor RREG, capacitor CL, capacitor CA, and the other end of the load resistor analog ROUT are grounded; The buck regulator REG includes: resistor Rr1, resistor Rr2, current source IB1, error operational amplifier AREG, MOSFET Mr1, MOSFET Mr2, MOSFET MRP1 and MOSFET MRP2; The negative terminal of current source IB1 and one end of resistor Rr1 are grounded; the other end of resistor Rr1, one end of resistor Rr2, and the positive input terminal of error operational amplifier AREG are connected by a wire; the negative input terminal of error operational amplifier AREG is connected to the enable input terminal of buck regulator REG. The other end of resistor Rr2, the drain of MRP1, and the internal power output terminal of buck regulator REG are connected by wires; the gate of MRP1, the gate of MRP2, the drain of MRP2, the output terminal of error operational amplifier AREG, and the drain of Mr2 are connected by wires; the source of MRP1, the source of MRP2, the source of Mr2, the source of Mr1, and the power input terminal of buck regulator REG are connected by wires; the gate of Mr2, the gate of Mr1, the drain of Mr1, and the positive terminal of current source IB1 are connected by wires.

2. The low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 1, characterized in that, The MOSFETs MPA and MP2 are N-channel MOSFETs.

3. The low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 1, characterized in that, The load resistance simulated ROUT includes: Current source IBIAS, resistor RB1, MOSFET MB1, MOSFET MB2, MOSFET MB3, MOSFET MB4 and resistor RL; The positive terminal of current source IBIAS and the VIN terminal are connected by a wire; the negative terminal of current source IBIAS, one end of resistor RB1, the gate of MB1 and the gate of MB4 are connected by a wire; the other end of resistor RB1, the drain of MB1, the gate of MB2 and the gate of MB3 are connected by a wire; the source of MB1 and the drain of MB2 are connected by a wire; the source of MB2, the source of MB3 and one end of resistor RL are grounded; the drain of MB3 and the source of MB4 are connected by a wire; the drain of MB4, the other end of resistor RL and the VOUT terminal are connected by a wire.

4. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 3, characterized in that, MOSFETs MB1, MB2, MB3, and MB4 are P-channel MOSFETs.

5. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 1, characterized in that, The error operational amplifier EA0 includes: resistors R1, R2, Rb, Rg, and Rf; capacitors Cc and Cf; MOSFETs MP1, Mg, and Mf; and the error operational amplifier EAP. One end of resistor R1, one end of resistor R2, and VOUT terminal are connected by a wire; the other end of resistor R1, one end of capacitor Cc, and the drain of MP1 are connected by a wire; the other end of resistor R2, the other end of capacitor Cc, and the negative input terminal of error operational amplifier EAP are connected by a wire; the gate of MP1, the drain of Mg, one end of resistor Rg, and the gate of MP2 are connected by a wire; the source of MP1 and one end of resistor Rb are connected by a wire; the other end of resistor Rb, the other end of resistor Rg, and VIN terminal are connected by a wire; the source of Mg and the source of Mf are grounded; the drain of Mf and one end of capacitor Cf are connected by a wire; the other end of capacitor Cf, the gate of Mf, and one end of resistor Rf are connected by a wire; the gate of Mg, the other end of resistor Rf, and the output terminal of error operational amplifier EAP are connected by a wire; the positive input terminal and VA terminal of error operational amplifier EAP are connected by a wire.

6. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 5, characterized in that, MOSFET MP1 is an N-channel MOSFET; MOSFETs Mg and Mf are P-channel MOSFETs.

7. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 1, characterized in that, The error operational amplifier EA1 includes: current source ISS, resistor REA1, resistor REA2, resistor REA3, resistor REA4, resistor REA5, resistor REAC, capacitor CEAC, and MOSFETs MEA1~MEA10; The negative terminal of current source ISS, one end of resistor REA1, one end of resistor REA2, one end of resistor REA3, and one end of resistor REAC are grounded; The positive terminal of the current source ISS, one end of resistor REA5, the gate of MEA2, and the gate of MEA4 are connected by a wire; the other end of resistor REA5, the drain of MEA2, the gate of MEA1, and the gate of MEA3 are connected by a wire; the source of MEA2 and the drain of MEA1 are connected by a wire; the source of MEA4 and the drain of MEA3 are connected by a wire; the source of MEA3, the source of MEA1, and the internal power input terminal of EA1 are connected by a wire. The other end of resistor REA1 is connected to the source of MEA7 via a wire; the other end of resistor REA2 is connected to the source of MEA8 via a wire; the gate of MEA7, the gate of MEA8, the drain of MEA7, and the drain of MEA5 are connected via a wire; the other end of resistor REAC is connected to one end of capacitor CEAC via a wire; the other end of resistor REA3 is connected to the source of MEA9 via a wire; the gate of MEA9, the other end of capacitor CEAC, the drain of MEA8, and the drain of MEA6 are connected via a wire; the gate of MEA5 is connected to the negative input terminal of EA1 via a wire; the gate of MEA6 is connected to the positive input terminal of EA1 via a wire; the source of MEA5, the source of MEA6, and the drain of MEA4 are connected via a wire; the drain of MEA9 is connected to one end of resistor REA4 via a wire; the other end of resistor REA4, the drain of MEA10, the gate of MEA10, and the output terminal of EA1 are connected via a wire; the source of MEA10 and the power input terminal of EA1 are connected via a wire.

8. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 7, characterized in that, MOSFETs MEA1~MEA6 and MEA10 are N-channel MOSFETs; MOSFETs MEA7~MEA9 are P-channel MOSFETs.

9. A low-dropout linear regulator with negative voltage wideband and high PSRR according to claim 1, characterized in that, MOSFETs Mr1, Mr2, MRP1, and MRP2 are N-channel MOSFETs.

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