Clock management circuit and clock management method

Abstract

A clock management circuit and method for managing an operating clock of a computing circuit that changes a state signal in response to an interrupt signal. The clock management circuit includes a delay circuit for delaying a wake-up interrupt signal to generate a delayed wake-up interrupt signal, and a clock control circuit coupled to the delay circuit for generating the operating clock in response to a reference clock, generating the wake-up interrupt signal in response to the state signal, and adjusting a frequency of the operating clock in response to the delayed wake-up interrupt signal.

Description

Technical Field

[0001] This invention relates to clock management, and more particularly to clock management circuits and clock management methods for high-speed circuits. Background Technology

[0002] Generally, due to clock gating, computing circuits consume less power in the idle state than in the active state. When a computing circuit switches from the idle state to the active state, i.e., when it is woken up, the opening of the clock gating causes a momentary power drain, often resulting in a momentary current surge. This causes a drop in the supply voltage (IR drop) on the printed circuit board (PCB). When the IR drop exceeds the tolerance limit, the computing circuit will exhibit unexpected behavior, leading to circuit malfunction. While capacitors can be added to the PCB to stabilize the supply voltage, this increases cost. Therefore, this disclosure proposes a circuit design to mitigate current surges (i.e., reduce supply voltage drop).

[0003] The aforementioned computing circuits include, for example, high-speed circuits such as the central processing unit (CPU), the CPU core, microcontrollers, and microprocessors. The operating state can also be referred to as the full-speed state. The idle state can also be referred to as the stationary state or the no-load state. Summary of the Invention

[0004] In view of the shortcomings of the prior art, one object of the present invention is to provide a clock management circuit and a clock management method to improve the shortcomings of the prior art.

[0005] An embodiment of the present invention provides a clock management circuit for managing an operating clock of a computing circuit, the computing circuit changing the level of a status signal according to an interrupt signal. The clock management circuit includes: a delay circuit for delaying a wake-up interrupt signal to generate a delayed wake-up interrupt signal; and a clock control circuit coupled to the delay circuit for generating the operating clock according to a reference clock, generating the wake-up interrupt signal according to the status signal, and adjusting the frequency of the operating clock according to the delayed wake-up interrupt signal.

[0006] Another embodiment of the present invention provides a clock management method for managing an operating clock of a computing circuit, the computing circuit changing the level of a status signal according to an interrupt signal, the clock management method comprising: generating the operating clock according to a reference clock; generating a wake-up interrupt signal according to the status signal; delaying the wake-up interrupt signal to generate a delayed wake-up interrupt signal; and adjusting the frequency of the operating clock according to the delayed wake-up interrupt signal.

[0007] The technical means embodied in the embodiments of the present invention can improve at least one of the shortcomings of the prior art. Therefore, the present invention can reduce current surges compared to the prior art.

[0008] The features, implementation, and technical effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a functional block diagram of an embodiment of the clock management circuit of the present invention;

[0010] Figure 2 A functional block diagram showing an embodiment of the clock control circuit;

[0011] Figure 3 This is a flowchart of an embodiment of the clock management method of the present invention;

[0012] Figure 4 It is an example of the timing of multiple clocks and signals;

[0013] Figure 5 A circuit diagram of an embodiment of a frequency divider and wake-up control circuit and a gate control pulse generator;

[0014] Figure 6 This illustrates an example of the frequency-division finite state machine of the present invention;

[0015] Figure 7 An example of waking up the finite state machine according to the present invention is shown; and

[0016] Figures 8A to 8C This is a flowchart of an embodiment of the clock management method of the present invention.

[0017] Symbol Explanation

[0018] 110: Calculation circuit

[0019] 120: Clock Management Circuit

[0020] 122: Delay Circuit

[0021] 124: Clock control circuit

[0022] 130: Interrupt control circuit

[0023] CPU_clk_src: Reference clock

[0024] CPU_clk: Operating clock

[0025] CPU_intr, intr0, intr1: Interrupt signals

[0026] CPU_sleep: Status signal

[0027] CPU_w_intr: Wake-up interrupt signal

[0028] dly_CPU_w_intr: Delayed wake-up interrupt signal

[0029] 210: Synchronizer

[0030] 220: Frequency division and wake-up control circuit

[0031] 230: Gate control pulse generator

[0032] 240: Clock gate circuit

[0033] div_sel: Divisor selection signal

[0034] div_st: Frequency divider signal

[0035] icg_en: gate control signal

[0036] STG1, STG2, STG3, STG4, STGM: Stages

[0037] PI1, PI2, PI3: Waiting time

[0038] 510: Frequency-divided finite state machine

[0039] 520: Wake up the finite state machine

[0040] sleep_ps,intr_ps,event_ps,wakeup_ps,div_st_nxt,wakeup_st,wakeup_st_nxt,st_chg_ps: signal

[0041] S610, S620, S630, S640, S710, S720, S730, S740, S750: Status

[0042] S310, S320, S330, S340, S350, S360, S370, S810, S820, S830, S840, S850, S860, S870, S875, S880, S890: Steps Detailed Implementation

[0043] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0044] The disclosure of this invention includes a clock management circuit and a clock management method. Since some components of the clock management circuit of this invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention. Furthermore, some or all of the processes of the clock management method of this invention may be in the form of software and / or firmware, and can be executed by the clock management circuit of this invention or its equivalent. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on the steps rather than the hardware.

[0045] In the following description, a high level represents active, and a low level represents inactive. Enabling / de-assertifying a signal means raising / lowering its level. However, this is merely an implementation or illustrative example and is not intended to limit the invention. In other words, in different implementations, a high level (e.g., logic 1) may represent inactive, and a low level (e.g., logic 0) may represent active. Enabling / de-assertifying a signal means lowering / raising its level. A level transition (change) or logic level transition (change) represents a signal changing from enabled (i.e., active, functioning) to deactivated (i.e., inactive, functioning), or vice versa.

[0046] Figure 1This is a functional block diagram of an embodiment of the clock management circuit 120 of the present invention. The clock management circuit 120 includes a delay circuit 122 and a clock control circuit 124. The clock management circuit 120 receives a reference clock CPU_clk_src and provides an operation clock CPU_clk to the computing circuit 110. The computing circuit 110 operates in an idle state or an operating state according to the operation clock CPU_clk and the interrupt signal CPU_intr. The computing circuit 110 uses the enable state signal CPU_sleep to transition itself from an operating state to an idle state or from an idle state to an operating state. The computing circuit 110 can change the level of the state signal CPU_sleep according to the interrupt signal CPU_intr. The interrupt control circuit 130 is used to control the interrupt signals. As shown, the interrupt control circuit 130 receives interrupt signals intr0, intr1, and a wake-up interrupt signal CPU_w_intr, and transmits the interrupt signal CPU_intr to the computing circuit 110 and the wake-up interrupt signal CPU_w_intr to the clock management circuit 120. The delay circuit 122 generates a delayed wake-up interrupt signal dly_CPU_w_intr by delaying the wake-up interrupt signal CPU_w_intr. The clock control circuit 124 also adjusts the operating clock CPU_clk based on the delayed wake-up interrupt signal dly_CPU_w_intr.

[0047] Figure 2 A functional block diagram of one embodiment of the clock control circuit 124 is shown. The clock control circuit 124 includes multiple synchronizers 210, frequency divider and wake-up control circuit 220, gate pulse generator 230, and clock gate circuit 240.

[0048] The function of synchronizer 210 is to synchronize the divisor selection signal div_sel, the status signal CPU_sleep, and the delayed wake-up interrupt signal dly_CPU_w_intr to prevent insufficient timing margin; however, if the three belong to the same clock domain, synchronizer 210 can be omitted.

[0049] The frequency division and wake-up control circuit 220 receives the reference clock CPU_clk_src, the divisor selection signal div_sel, the status signal CPU_sleep, and the delayed wake-up interrupt signal dly_CPU_w_intr. The frequency division and wake-up control circuit 220 generates or modifies the frequency division signal div_st based on the status signal CPU_sleep and the delayed wake-up interrupt signal dly_CPU_w_intr, and generates or enables the wake-up interrupt signal CPU_w_intr based on the status signal CPU_sleep and the delayed wake-up interrupt signal dly_CPU_w_intr.

[0050] The gate control pulse generator 230 generates a gate control signal icg_en based on the frequency divider signal div_st. More specifically, the gate control pulse generator 230 adjusts the frequency of the gate control signal icg_en based on the frequency divider signal div_st.

[0051] The clock gate control circuit 240 gates the reference clock CPU_clk_src according to the gate control signal icg_en to generate the operating clock CPU_clk. The clock gate control circuit 240 is well known to those skilled in the art, and therefore will not be described in detail.

[0052] Figure 3 This is a flowchart of an embodiment of the clock management method of the present invention. Figure 4 This is an example of the timing sequence for the reference clock CPU_clk_src, the status signal CPU_sleep, the operation clock CPU_clk, the gate signal icg_en, the wake-up interrupt signal CPU_w_intr, and the delayed wake-up interrupt signal dly_CPU_w_intr. The following is in conjunction with... Figure 3 and Figure 4 This will explain the operating principle of the clock control circuit 124. Figure 3 The process includes the following steps.

[0053] Step S310: Calculate that the operating frequency of the calculation circuit 110, representing the operating clock CPU_clk, is the full clock frequency when the circuit is in operation. For example... Figure 4 The symbol "1" is before it.

[0054] Step S320: The calculation circuit 110 is in an idle state. In this step, the clock control circuit 124 reduces the clock frequency of the operating clock CPU_clk. For example, in Figure 4 When the status signal CPU_sleep at the symbol "1" becomes valid, the computing circuit 110 operates at a lower clock frequency (below the full clock frequency of stage STG4) in stages STG1, STG2 and STG3.

[0055] Step S330: The computing circuit 110 is woken up, that is, the status signal CPU_sleep becomes invalid, and the clock control circuit 124 enables the wake-up interrupt signal CPU_w_intr. For example, in Figure 4 The status signal CPU_sleep at symbol "2" becomes invalid, while the wake-up interrupt signal CPU_w_intr at symbol "3" becomes valid.

[0056] Step S340: The clock control circuit 124 waits for the delayed wake-up interrupt signal dly_CPU_w_intr, that is, the clock control circuit 124 waits for the delayed wake-up interrupt signal dly_CPU_w_intr to become valid (equivalent to receiving the delayed wake-up interrupt signal dly_CPU_w_intr). For example, this step can correspond to Figure 4 The waiting time PI1 between the symbol “3” and the symbol “4”, the waiting time PI2 between the symbol “5” and the symbol “6”, and the waiting time PI3 between the symbol “7” and the symbol “8”.

[0057] Step S350: The clock control circuit 124 determines whether the computing circuit has returned to the idle state, that is, whether the status signal CPU_sleep has become valid (equivalent to receiving the status signal CPU_sleep). If the result of step S350 is yes, then return to step S320; if no, then proceed to step S360.

[0058] Step S360: Clock control circuit 124 determines whether the finite state machine (FSM) is in its last stage (or state). The finite state machine is part of the frequency division and wake-up control circuit 220, which will be described in detail below. In some embodiments, the finite state machine uses the signal div_st_nxt to indicate its next state. This step can be determined based on the signal div_st_nxt. If the result of step S360 is yes, proceed to step S370; if no, return to step S320. Figure 4 In the example, stage STG3 is the last stage (or state); therefore, at symbols “4” and “6”, the judgment result of step S360 is negative, while at symbol “8”, the judgment result of step S360 is positive.

[0059] Step S370: The clock control circuit 124 adjusts the frequency of the operating clock CPU_clk to the full clock frequency (i.e., puts the computing circuit 110 into operation), and then the process returns to step S310. Figure 4 As shown, after the symbol "8", the clock control circuit 124 adjusts the frequency of the operating clock CPU_clk to the full clock frequency, so that the computing circuit 110 operates in the working state (i.e., stage STG4).

[0060] like Figure 3 and Figure 4 As shown, after the computing circuit 110 is woken up (step S330), the clock control circuit 124 will not immediately change the operating clock CPU_clk from the lowest clock frequency (e.g., Figure 4 The STG1 stage in the middle is adjusted to the full clock frequency (e.g., STG1). Figure 4 In step S360 (STG4), instead of using the frequency divider finite state machine (step S360), the operating clock CPU_clk is kept at a lower clock frequency (i.e., below the full clock frequency, for example...). Figure 4 The process involves a period of time (specifically, the waiting time PI2 and waiting time PI3).

[0061] Furthermore, if the status signal CPU_sleep becomes valid in stage STG2 or stage STG3 (i.e., the result of step S350 is yes), the frequency divider finite state machine of the clock control circuit 124 returns to stage STG1 instead of proceeding to the next stage (stage STG3 or stage STG4) so ​​that the calculation circuit 110 operates in an idle state again.

[0062] Figure 4 The waiting times PI1, PI2, and PI3 are adjustable; for example, they can be adjusted by setting the delay circuit 122 via software.

[0063] Please note that the clock control circuit 124 (more specifically, a frequency-divided finite state machine) can have M states (M is an integer greater than 2). Figure 4 In this example, M = 4 (i.e., stages STG1, STG2, STG3, and STG4). M can be set using the aforementioned divisor selection signal div_sel. Each state corresponds to a different operating clock frequency, CPU_clk.

[0064] As described above, the clock management circuit 120 can gradually increase the clock frequency of the operating clock CPU_clk (instead of jumping from the lowest frequency (e.g., stage STG1) to the highest frequency (e.g., stage STGM)) to reduce current surges (i.e., avoid large voltage drops).

[0065] Figure 5 This is a circuit diagram of one embodiment of the frequency divider and wake-up control circuit 220 and the gate pulse generator 230. The frequency divider and wake-up control circuit 220 includes circuitry other than the gate pulse generator 230, namely, the frequency divider and wake-up control circuit 220 includes a frequency divider finite state machine 510, a wake-up finite state machine 520, multiple logic gates, and multiple flip-flops.

[0066] The signal sleep_ps is related to the state of the status signal CPU_sleep. More specifically, a logic 1 in sleep_ps indicates that the status signal CPU_sleep has changed from invalid to valid.

[0067] The signal intr_ps is related to the state of the delayed wake-up interrupt signal dly_CPU_w_intr. More specifically, intr_ps being logic 1 indicates that the delayed wake-up interrupt signal dly_CPU_w_intr has changed from invalid to valid.

[0068] The state of the event_ps signal is related to the states of the sleep_ps and intr_ps signals. More specifically, the event_ps signal is logic 1 when the status signal CPU_sleep changes from invalid to valid or when the delayed wake-up interrupt signal dly_CPU_w_intr changes from invalid to valid.

[0069] The wakeup_ps signal is related to the state of the CPU_sleep status signal. More specifically, a logic 1 for the wakeup_ps signal indicates that the CPU_sleep status signal has changed from invalid to invalid.

[0070] The signal div_st_nxt is used to indicate the next state of the frequency divider finite state machine 510. For example, in Figure 4 In this example, the signal div_st_nxt indicates stage STG1, stage STG2, stage STG3, or stage STG4. The state of the frequency divider finite state machine 510 will be determined below. Figure 6 Detailed explanation.

[0071] The signals wakeup_st and wakeup_st_nxt are used to indicate the current state and the next state of the finite state machine 520, respectively. The wakeup_st signal will only activate when the event_ps, wakeup_ps, or st_chg_ps signals are logic 1. Figure 7 The condition jumps to the next state. The state that wakes up the finite state machine 520 will be in conjunction with the following... Figure 7 Detailed explanation.

[0072] The signal st_chg_ps is used to indicate the state change that wakes up the finite state machine 520.

[0073] The circuitry of the gate pulse generator 230 is well-known to those skilled in the art and will not be described in detail here. Figure 5 In the example, the circuit of the gate pulse generator 230 corresponds to four states in the frequency divider finite state machine 510 (stage STG1, stage STG2, stage STG3, and stage STG4, such as...). Figure 6 (As shown in the example).

[0074] Figure 6 This illustrates an example of the frequency divider finite state machine 510 of the present invention. In this example, the frequency divider finite state machine 510 includes four states: state S610 corresponds to... Figure 4 The STG4 stage (the divide-by-frequency signal div_st indicates that the frequency of the gate control signal icg_en (i.e., the frequency of the operating clock CPU_clk) is the full clock frequency); state S620 corresponds to... Figure 4 The stage STG1 (the frequency divide signal div_st indicates that the frequency of the gate control signal icg_en is one-quarter of the full clock frequency); state S630 corresponds to... Figure 4 The stage STG2 (the frequency divider signal div_st indicates that the frequency of the gate control signal icg_en is two-quarters of the full clock frequency); and state S640 corresponds to... Figure 4 The STG3 stage (the frequency divide signal div_st indicates that the frequency of the gate control signal icg_en is three-quarters of the full clock frequency).

[0075] like Figure 6 As shown, when the frequency divider finite state machine 510 is in state S610 and the signal sleep_ps is logic 1, the frequency divider finite state machine 510 enters state S620. When the frequency divider finite state machine 510 is in state S620, the signal event_ps is logic 1 and the state signal CPU_sleep is logic 0, the frequency divider finite state machine 510 enters state S630. When the frequency divider finite state machine 510 is in state S630, the signal event_ps is logic 1 and the state signal CPU_sleep is logic 0, the frequency divider finite state machine 510 enters state S640. When the frequency divider finite state machine 510 is in state S640, the signal event_ps is logic 1 and the state signal CPU_sleep is logic 0, the frequency divider finite state machine 510 enters state S610. When the frequency divider finite state machine 510 is in state S630, and the signal event_ps is logic 1 and the state signal CPU_sleep is logic 1, the frequency divider finite state machine 510 enters state S620. When the frequency divider finite state machine 510 is in state S640, and the signal event_ps is logic 1 and the state signal CPU_sleep is logic 1, the frequency divider finite state machine 510 enters state S620.

[0076] Figure 7 This illustrates an example of waking up the finite state machine 520 of the present invention. The finite state machine 520 includes the following five states.

[0077] State S710: Idle state. This state corresponds to the computing circuit 110 being in an active state (i.e., operating at a full clock frequency). When the finite state machine 520 is woken up in state S710 and the signal sleep_ps is logic 1 (e.g., corresponding to...), Figure 4 The symbol "1" is used to wake up the finite state machine 520 and enter state S720.

[0078] State S720: Sleep state. This state corresponds to the computing circuit 110 being in an idle state (i.e., operating at 1 / M of the full clock frequency). The finite state machine 520 is woken up in state S720 when the wakeup_ps signal is logic 1 (e.g., corresponding to...). Figure 4 The symbol “2”) wakes up the finite state machine 520 and enters state S730.

[0079] State S730: Wake-up state. In this state, the wake-up finite state machine 520 enables the wake-up interrupt signal CPU_w_intr (e.g., corresponding to...) via the control signals wakeup_st and wakeup_st_nxt. Figure 4 The symbol "3", "5" or "7"). When the finite state machine 520 is woken up in state S730 and the signal intr_ps is logic 1 (e.g., corresponding to...). Figure 4 The symbol “4”, “6” or “8” is used to wake up finite state machine 520 and enter state S740; when finite state machine 520 is woken up in state S730 and the signal sleep_ps is logic 1 (representing that frequency divider finite state machine 510 changes from state S640 to state S620 or from state S630 to state S620), finite state machine 520 is woken up and enters state S720.

[0080] State S740: Determine the state. Wake up finite state machine 520 to determine if the next state of frequency divider finite state machine 510 is a state that provides a complete clock frequency (e.g., ...). Figure 6 State S610). If it is (i.e., corresponding to the computing circuit 110 about to return to the working state to operate at the full clock frequency), then the finite state machine 520 is woken up to return to state S710 (e.g., corresponding to the state S610). Figure 4 The symbol "8"); if not (for example, corresponding to Figure 4 If the symbol "4" or "6" is used, the finite state machine 520 is awakened and enters state S750.

[0081] State S750: Waiting state. The finite state machine 520 is woken up to wait for the frequency divider finite state machine 510 to change state (i.e., the frequency divider signal div_st and the signal div_st_nxt are changed). When the finite state machine 520 enters state S750, the signal st_chg_ps will be logic 1. At this time, the following operations are performed according to the signal sleep_ps. If the signal sleep_ps is logic 1, it means that the computing circuit 110 needs to enter the idle state again, and the frequency divider finite state machine 510 changes from state S640 to state S620 or from state S630 to state S620; if the signal sleep_ps is logic 0, it means that the computing circuit 110 needs to be woken up continuously, and the frequency divider finite state machine 510 changes from state S620 to state S630 or from state S630 to state S640. The logic 1 of the signal st_chg_ps can correspond to... Figure 4 The descending edge between the symbols “4” and “5” or between the symbols “6” and “7”.

[0082] Those skilled in this art can... Figure 6 and Figure 7 The description explains that logic gates and / or transistors are used to implement the frequency divider finite state machine 510 and the wake-up finite state machine 520.

[0083] In summary, the present invention provides multiple stages for the operating clock CPU_clk, with each stage generating a different clock frequency. Therefore, during the process of the computing circuit 110 returning from an idle state to an operating state, its operating clock CPU_clk gradually returns from the lowest clock frequency to the full clock frequency, thereby reducing current surges.

[0084] In addition to the aforementioned clock management circuit, the present invention also discloses a clock management method. This method is executed by the aforementioned clock management circuit 120 or its equivalent. Figures 8A to 8C The flowchart of one embodiment of this method includes the following steps.

[0085] Step S810: Generate the operating clock CPU_clk based on the reference clock CPU_clk_src. In some embodiments, this step may be performed by the clock control circuit 124; more specifically, it may be performed by the clock gate circuit 240.

[0086] Step S820: Generate a wake-up interrupt signal CPU_w_intr based on the status signal CPU_sleep. In some embodiments, this step can be performed by the clock control circuit 124; more specifically, it can be performed by the frequency division and wake-up control circuit 220. This step can correspond to... Figure 7 The state transition from state S720 to state S730.

[0087] Step S830: Delay the wake-up interrupt signal CPU_w_intr to generate a delayed wake-up interrupt signal dly_CPU_w_intr. In some embodiments, this step may be performed by the delay circuit 122.

[0088] Step S840: Adjust the frequency of the operating clock CPU_clk according to the delayed wake-up interrupt signal dly_CPU_w_intr. In some embodiments, this step can be performed by the clock control circuit 124. This step can correspond to... Figure 6 The state transition from state S620 to state S640.

[0089] Step S850: When the level of the status signal CPU_sleep changes, the frequency of the operating clock CPU_clk is controlled to a first frequency. In some embodiments, this step can be performed by the clock control circuit 124. This step can correspond to... Figure 6 State S610 to State S620 Figure 7 State S710 to State S720 and Figure 4 The symbol "1". The first frequency is, for example, the frequency of stage STG1.

[0090] Step S860: When the level of the delayed wake-up interrupt signal dly_CPU_w_intr changes, the frequency of the operating clock CPU_clk is controlled to a second frequency. The second frequency is greater than the first frequency. In some embodiments, this step can be performed by the clock control circuit 124. This step can correspond to... Figure 6 State S620 to State S630 and Figure 4 The symbol "4", "6" or "8". The second frequency is, for example, the frequency of stage STG2 or stage STG3.

[0091] Step S870: Generate or change the frequency divider signal div_st based on the divisor selection signal div_sel and the delayed wake-up interrupt signal dly_CPU_w_intr. In some embodiments, this step can be performed by the clock control circuit 124; more specifically, it can be performed by the frequency divider and wake-up control circuit 220. This step can correspond to... Figure 6 The state transition from state S620 to state S640, wherein the divisor selection signal div_sel can determine M( Figure 6 In the example, M=4).

[0092] Step S875: In response to the level change of the delayed wake-up interrupt signal dly_CPU_w_intr, change the frequency divider signal div_st. This step is a sub-step of step S870. The frequency divider finite state machine 510 determines the frequency divider signal div_st based on the delayed wake-up interrupt signal dly_CPU_w_intr. Figure 6 The state (i.e., the control frequency divider signal div_st corresponds to 1 / M, 2 / M, ...).

[0093] Step S880: Generate a gate control signal icg_en based on the frequency divider signal div_st. In some embodiments, this step can be performed by a gate control pulse generator 230, one embodiment of which is as follows: Figure 5 As shown.

[0094] Step S890: Gated the reference clock CPU_clk_src according to the gating signal to generate the operating clock CPU_clk. In some embodiments, this step may be performed by the clock gating circuit 240.

[0095] Since those skilled in the art can understand the implementation details and variations of the method invention disclosed herein through the disclosure of the device invention, repeated descriptions are omitted here to avoid redundancy, without affecting the disclosure requirements and implementability of the method invention. Please note that the shapes, sizes, and proportions of the elements in the foregoing figures are merely illustrative and intended for those skilled in the art to understand the invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the foregoing flowchart can be adjusted according to actual operation, and they may even be performed simultaneously or partially simultaneously.

[0096] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

Claims

1. A clock management circuit for managing an operating clock of a computing circuit, the computing circuit changing the level of a status signal according to an interrupt signal, the clock management circuit comprising: A delay circuit is used to delay a wake-up interrupt signal to generate a delayed wake-up interrupt signal; and A clock control circuit, coupled to the delay circuit, is used to generate the operating clock according to a reference clock, generate the wake-up interrupt signal according to the status signal, and adjust the frequency of the operating clock according to the delayed wake-up interrupt signal.

2. The clock management circuit as described in claim 1, wherein, The clock management circuit can control the frequency of the operating clock to a first frequency, a second frequency, or a third frequency. The first frequency is a minimum operating frequency of the computing circuit, the third frequency is a maximum operating frequency of the computing circuit, and the second frequency is between the first frequency and the third frequency. The clock control circuit responds to the level change of the status signal and controls the frequency of the operating clock to the first frequency. The clock control circuit also responds to the level change of the delayed wake-up interrupt signal and controls the frequency of the operating clock to the second frequency.

3. The clock management circuit as described in claim 2, wherein, The delay circuit delays the wake-up interrupt signal by a waiting time to generate the delayed wake-up interrupt signal, and the waiting time can be adjusted by software settings.

4. The clock management circuit as described in claim 3, wherein, The clock control circuit includes: A frequency divider and wake-up control circuit is used to generate the wake-up interrupt signal based on the status signal, and to generate a frequency divider signal based on a divisor selection signal and the delayed wake-up interrupt signal. A gate pulse generator, coupled to the frequency divider and wake-up control circuit, is used to generate a gate signal based on the frequency divider signal; and A clock gate control circuit, coupled to the gate control pulse generator, is used to gate the reference clock according to the gate control signal to generate the operating clock.

5. The clock management circuit as described in claim 4, wherein, The frequency divider and wake-up control circuit responds to the level change of the wake-up interrupt signal after the delay by changing the frequency divider signal.

6. A clock management method for managing an operating clock of a computing circuit, the computing circuit changing the level of a status signal according to an interrupt signal, the clock management method comprising: The operating clock is generated based on a reference clock; A wake-up interrupt signal is generated based on the status signal; Delay the wake-up interrupt signal to generate a delayed wake-up interrupt signal; and The frequency of the operation clock is adjusted based on the delayed wake-up interrupt signal.

7. The clock management method as described in claim 6, wherein, The clock management method can control the frequency of the operating clock to a first frequency, a second frequency, or a third frequency, wherein the first frequency is a minimum operating frequency of the computing circuit, the third frequency is a maximum operating frequency of the computing circuit, and the second frequency is between the first frequency and the third frequency. The method further includes: When the level of the status signal changes, the frequency of the operating clock is controlled to the first frequency; and When the level of the delayed wake-up interrupt signal changes, the frequency of the operation clock is controlled to the second frequency.

8. The clock management method as described in claim 7, wherein, The step of delaying the wake-up interrupt signal to generate the delayed wake-up interrupt signal is to delay the wake-up interrupt signal by a waiting time, which can be adjusted by software settings.

9. The clock management method as described in claim 7, further comprising: A frequency divider signal is generated based on a divisor selection signal and the delayed wake-up interrupt signal. A gate control signal is generated based on the frequency divider signal; and The reference clock is gated according to the gate control signal to generate the operating clock.

10. The clock management method as described in claim 9, wherein, The step of generating the frequency divider signal based on the divisor selection signal and the delayed wake-up interrupt signal includes: The frequency divider signal is changed in response to the level change of the wake-up interrupt signal after the delay.

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